Integral University, Lucknow

Question Bank

Course Code : EC-209 Credits : 4 Date :19-12-2016

Course Name : Digital Electronics
Units to be covered in First Mid-Sem Exam :1,2 Second Mid-Sem Exam : 3,4
Difficulty Index: ‘easy’ (A); ‘moderate’ (B); ‘difficult’ (C)
Unit Q. Question Max. Difficulty
1 No. marks Index
1. . Convert The SOP to POS form 1 A
A.
B.
C.
D.
2. Determine the values of A, B, C, and D that make the sum 1 A
term equal to zero.
A. A = 1, B = 0, C = 0, D = 0
B. A = 1, B = 0, C = 1, D = 0
C. A = 0, B = 1, C = 0, D = 0
D. A = 1, B = 0, C = 1, D = 1
3. Derive the Boolean expression for the logic circuit shown below: 1 A
UNIT-1

A.

B.

C.

D.
4. From the truth table below, determine the standard SOP expression. 1 B

A.
B.
 C.
D.
5. One of De Morgan's theorems states that . Simply stated, this 1 B
means that logically there is no difference between:
A. a NOR and an AND gate with inverted inputs
B. a NAND and an OR gate with inverted inputs
C. an AND and a NOR gate with inverted inputs
D a NOR and a NAND gate with inverted inputs
6. 1 B
AC + ABC = AC
A. True
B. False
7. When grouping cells within a K-map, the cells must be combined in groups 1 B
of ________.
A. 2s
B. 1, 2, 4, 8, etc.
C. 4s
D 3s
8. Use Boolean algebra to find the most simplified SOP expression 1 C
for F = ABD + CD + ACD + ABC + ABCD.
A. F = ABD + ABC + CD
B. F = CD + AD
C. F = BC + AB
D. F = AC + AD
9. 1 C
The NAND or NOR gates are referred to as "universal" gates because either:
A. can be found in almost all digital circuits
B. can be used to build all the other types of gates
C. are used in all countries of the world
D. were the first gates to be integrated
10. Derive the Boolean expression for the logic circuit shown below: 1 C

A.
B.
C.
D.
11. The Boolean expression C + CD is equal to ________. 2 A
A. C
 B. D
C. C + D
D 1
12. The standard SOP form of the expression is ________. 2 A
A.
B
C.
D.
13. Which of the following is true for a 5-variable Karnaugh map? 2 B
A There is no such thing.
B. It can be used only with the aid of a computer.
C. It is made up of two 4-variable Karnaugh maps.
D. It is made up of a 2-variable and a 3-variable Karnaugh
14. In Boolean algebra, the word "literal" means ________. 2 B
A. a product term
B. all the variables in a Boolean expression
C. the inverse function
D. a variable or its complement
15. The distributive law of Boolean algebra is ……….. 2 C
A. (A + B) + C = A + (B + C)
B. A(B + C) = AB + AC
C. A + (B + C) = AB + AC
D. A(BC) = (AB) + C
16. ………..expresses the commutative law of multiplication 2 C
A. A + B = B + A
B. AB = B + A
C. AB = BA
AB = A × B
17. The expression W(X + YZ) can be converted to SOP form by applying ……. 2 A
law?
A. associative law
B commutative law
C. distributive law
D. none of the above
18. The truth table for the SOP expression has ………. input 2 B
combinations?
A. 1
B. 2
C. 4
 D. 8
19. …………………….., statement below best describes a Karnaugh map? 2 B
A. A Karnaugh map can be used to replace Boolean rules.
The Karnaugh map eliminates the need for using NAND and NOR
B.
gates.
C. Variable complements can be eliminated by using Karnaugh maps.
Karnaugh maps provide a cookbook approach to simplifying Boolean
D.
expressions.
20. The Boolean expression can be reduced to ________. 2 C
A
B
C.
D.
21. Write excess 3 code for 1011 2 A
22. Write down the binary equivalent of 34.50 2 A
23. Convert 101101 to hexadecimal equivalent 2 B
24. Find the gray code for 111001 2 B
25. Add +21 and -10 using 2s compliment method 2 C
26. Write hexadecimal equivalent of 10010 2 C
27. Write down the POS form of S=ABC+AC+AB 4 A
28. Explain odd and even parity codes 4 A
29. Distinguish between 1s and 2s compliment by an example 4 B
30. Apply DeMorgan's theorem to the expression and simplify 4 B
31. Write the canonical form for the following expression: 4 C
F(A,B,C)=AC+B+BC
32. What is the significance of minimization techniques in digital electronics 4 C
33. Using K Map, find the expression for the following: 8 A
F(A,B,C,D,E)=∑(0,1,2,8,10,12,15,18,25,29).Also realize the final expression
using the gates.
34. Develop a logic circuit, using only NAND gates, to implement a circuit to 8 A
meet the requirements of the truth table shown below.
A B Y(output)
000
011
101
111
35. Show how to create an exclusive-OR gate using only 2-input NAND 8 B
gates.
36. Y(A,B,C,D)= ∑ m(0,1,3,7,8,9,11,15).Find the expression using Tabulation 8 B
Method
37. g (A, B, C, D, E, F) = (A E) + (B D E) + (B C E F).Implement the following 8 B
by using only NOR gates
38. Encode the following binary bits into 7 bit hamming codes: 1000,0101,1011 8 B
39. Subtract the following decimal numbers using 9’s complement method: 19- 8 C
12,39-15
40. Simplify the following logic expressions: 8 C
A+AB+ABC,BCD+AC
Unit Q. Max. Difficulty
2 No. marks Index
1. Which statement below best describes a Karnaugh map? 1 A
A. A Karnaugh map can be used to replace Boolean rules.
The Karnaugh map eliminates the need for using NAND and NOR
B.
gates.
C. Variable complements can be eliminated by using Karnaugh maps.
Karnaugh maps provide a visual approach to simplifying Boolean
D.
expressions.
2. 1 A
The simplest equation
which implements the
K-map shown below
is:

A.
B.
UNIT-2

C.
D.
3. Quine Mc Cluskey method is used for: 1 A
A) Minimization of expression
B) Expansion Of Expression
C) Representation of expression
D) None of the above
4. Which of the following is a universal gate: 1 B
A)AND
B) OR
C)NOT
D)NAND
5. K MAP can be used to find the : 1 B
A) POS and SOP form both
B) SOP form only
C) POS form only
D) D0 None of the above

6. How many Half adders are required to make a full adder: 1 B

A)1
B)2
C)3
D)4
7. When grouping cells within a K-map, the cells must be combined in groups 1 B
of ________.
 A. 2s
B. 1, 2, 4, 8, etc.
C. 4s
D 3s
8. Prime implicant chart is constructed in 1 C
A) Quine Mc Cluskey Method
B) K Map
C) Boolean simplification method
D) D) none of the above
9. Multiplexing refers to 1 C
A)Many to one
B) One to many
C)same input same output
D) None of the above
10. Derive the Boolean expression for the logic circuit shown below: 1 C

A.
B.
C.
D.
11. Demultiplexer and Decoder are same: 2 A
A) True
B) False

12. The concept of augend and addend is there in ________. 2 A

A. Adder
B Subtractor
C. Multiplier
D. Comparator
13. Comparator circuit has _______ 2 B
A) Not gate
B) NOR gate
C) None of the above
14. In K map don’t care conditions may be used for ________. 2 B
A. Forming pairs ,quads and octets
B. Forming pairs only
C. For representation only
D. None of the above
15. Comparator circuit is an example of_________ 2 C
A. Combinational circuit
B. Sequential circuit
 C. None of the above

16. Parallel adder is used where 2 C

A. Fast addition is required
B. Slow and gradual process of addition is required
C. None of the above

17. Controlled inverter has its utility in __________ 2 A

A) Parallel adder and subtractor
B) Encoder
C) Decoder
D) Multiplier
18. 2 B
19. …………………….., statement below best describes a Karnaugh map? 2 B
A. A Karnaugh map can be used to replace Boolean rules.
The Karnaugh map eliminates the need for using NAND and NOR
B.
gates.
C. Variable complements can be eliminated by using Karnaugh maps.
Karnaugh maps provide a cookbook approach to simplifying Boolean
D.
expressions.
20. The concept of minuend and subtrahend is there in 2 C
A) Adder
B) Subtractor
C) Multiplier
D) Comparator
21. Using K-map method, obtain the minimal SOP expression of the following 2 A
function:
Y= Σm( 0,2,3,6,7,8,10,11,12,15)
22. The POS form of expression Z=ABC+AB is. 2 A
23. Write the truth table and expression for half adder circuit. 2 B
24. Write the truth table for half subtractor 2 B
25. Which gate is used as controlled inverter 2 C
26. Write the truth table for full adder 2 C
27. F(A,B,C)=∑(1,4,6)+∑d(2,5) 4 A
28. Define encoder and decoder 4 A
29. Explain the working of 1 bit magnitude comparator 4 B
30. Explain the significance of K Map briefly for minimization of function. 4 B
31. Write short note on parallel adder 4 C
32. Write short note on half subtractor 4 C
33. Using K Map, find the expression for the following: 8 A
F(A,B,C,D,E)=∑(0,1,2,8,10,12,15,18,25,29).Also realize the final expression
using the gates.
34. Draw the truth table for full subtractor and realize the expression of 8 A
difference using NAND gates only
35. 8 B
36. Y(A,B,C,D)= ∑ m(0,1,3,7,8,9,11,15).Find the expression using Tabulation 8 B
Method
37. g (A, B, C, D, E, F) = (A E) + (B D E) + (B C E F).Implement the following 8 B
by using only NOR gates
 38. Encode the following binary bits into 7 bit hamming codes: 1000,0101,1011 8 B
39. Subtract the following decimal numbers using 9’s complement method: 19- 8 C
12,39-15
40. Simplify the following logic expressions: 8 C
A+AB+ABC,BCD+AC

Unit Q. Question Max. Difficulty

3 No. marks Index
1. How is a J-K flip-flop made to toggle? 1 A
A. J = 0, K = 0

B. J = 1, K = 0

C. J = 0, K = 1

D. J = 1, K = 1
2. How many flip-flops are required to produce a divide-by-128 device? 1 A
A. 1

B. 4

C. 6

D. 7
3. Flip Flop is 1 A
A. Combinational Circuit
B. Sequential Circuit
C. Analog Circuit
UNIT-3

D. None Of the above

4. 1 B
Which of the following is correct for a gated D flip-flop?
A. The output toggles if one of the inputs is held HIGH.

B. Only one of the inputs can be HIGH at a time.

C. The output complement follows the input when enabled.

D. Q output follows the input D when the enable is HIGH.

5. With regard to a D latch, ________. 1 B
A. the Q output follows the D input when EN is LOW

B. the Q output is opposite the D input when EN is LOW

C. the Q output follows the D input when EN is HIGH

D. the Q output is HIGH regardless of EN's input state

6. A J-K flip-flop is in a "no change" condition when ________. 1 B
A. J = 1, K = 1

B. J = 1, K = 0
 C. J = 0, K = 1

D. J = 0, K = 0
7. Race around condition is : 1 B
A. An advantage
B. A disadvantage
8. Race around condition occurs in 1 C
A. JK flip flop
B. T flip flop
C. D flip flop
D. SR flipflop
9. Registers can: 1 C
A. Only shift data
B. Only store data
C. Can do both
D. None of the above

10. Flip flops can be used as frequency dividers. 1 C

A. True
B. False
11. For J=K=1 the output of a J K flip flop will ………… 2 A
12. Assume an latch, made from cross-coupled NAND gates, has a 0 on 2 A
both inputs. The outputs will be ________.
13. When the output of the NOR gate S-R flip-flop is in the HOLD state (no 2 B
change), the inputs are ________.
14. Maximum number that a MOD-6 counter will count will be ________ 2 B
15. Ascending order counting is done by _______counter 2 C
16. MOD-10 counter is also known as _______counter 2 C
17. _______flip flop copies the input when the clock pulse is applied 2 A
18. SR flipflop has _______number of forbidden state 2 B
19. Race around condition occurs in _________flip flop 2 B
20. ______ triggered flip flop changes its state during transition of edge of the 2 C
clock pulse
21. What is the basic difference between flip flop and latch 2 A
22. Write three uses of flip flops 2 A
23. Write down the PS-NS table for SR flipflop 2 B
24. Write down the excitation table of D flip flop 2 B
25. What is a latch 2 C
26. How many states can be counted by MOD-5 counter 2 C
27. Write a short note on sequential circuit 4 A
28. Write a short note on SR flip flop 4 A
29. Draw the diagram of SR flip flop using NAND gates 4 B
30. Draw the diagram of JK flip flop using SR flip flop 4 B
31. Draw the diagram of master slave JK flip flop using only NAND gates 4 C
32. Draw MOD 3 counter using JK flip flop 4 C
33. Convert SR flip flop to JK flip flop 8 A
34. Convert SR flip flop to D flip flop 8 A
35. Explain in detail about the working of master slave flip flop and how it 8 B
eliminates race around condition
 36. Write short note on triggering and its types 8 B
37. Design MOD-6 counter using JK flip flop 8 B
38. Explain the working of UP/DOWN counter with proper diagram 8 B
39. Write short note on ring counter 8 C
40. Explain shift right and shift left operation of registers with proper diagram 8 C

Unit Q. Question Max. Difficulty

4 No. marks Index

1. Which of the following statements are true? 1 A

A. Asynchronous events do not occur at the same time.

B. Asynchronous events are controlled by a clock.

C. Synchronous events do not need a clock to control them.

D. Only asynchronous events need a control

2. Asynchronous circuits are : 1 A
A. Faster than synchronous circuits
B. Slower than synchronous circuits
C. None of the above
3. State reduction in asynchronous circuits helps in : 1 A
A. Lesser propagation delay
B. Less circuit complexity
C. Both of the above
D. None of the above

4. The propagation delay in asynchronous circuit is: 1 B

UNIT-4

A. Less than synchronous cicuit

B. More than synchronous circuit
5. SR latch consists of 1 B

A. 1 input
B. 2 inputs
C. 3 inputs
D. 4 inputs

6. Outputs of SR latch are 1 B

A. x and y
B. a and b
C. s and r
D. q and q'

7. First step of analysis procedure of SR latch is to 1 B

A. label inputs
 B. label outputs
C. label states
D. label tables

8. Table that is not a part of asynchronous analysis procedure 1 C

A. transition table
B. state table
C. flow table
D. excitation table

9. Stable condition in transition table is given by expression 1 C

A. Y=x
B. X=x
C. Y=y
D. X=y

10. Making of transition table consists of 1 C

A. 2 steps
B. 4 steps
C. 5 steps
D. 6 steps

11. Present states of asynchronous circuits are also called _________ 2 A

12. Primitive flow table for gated latch, for each state has_________ 2 A
13. Complexity of asynchronous circuits is involved in timing problems 2 B
of______
14. NAND latches work when both the inputs are__________ 2 B
15. Effect of change of input to more than one state is called_________ 2 C
16. Naming states is done in __________ 2 C
17. Analysis procedure is to obtain______ 2 A
18. Transition table gives values of_________ 2 B
19. Table having one state in each row is called________ 2 B
20. State reduction table reduces the repetitive______states 2 C
21. What is asynchronous circuit in general 2 A
22. What is reduction table used for 2 A
23. What is a primitive table in context to design of asynchronous circuits 2 B
24. Write down the type of hazards 2 B
25. What are glitches 2 C
26. How can an asynchronous circuit converted to synchronous circuit 2 C
27. What is an essential hazard 4 A
28. What is hazard is asynchronous circuit 4 A
29. What are hazard free digital circuits 4 B
30. Define cycle in asynchronous circuits 4 B
31. How a hazard can be removed using SR latch 4 C
32. Define Stuck at 0 and stuck at 1 hazards with proper diagram 4 C
33. 8 A

For a given diagram draw its state table

34. For a given state diagram, draw the state table, reduce it and draw the reduced 8 A

state diagram.
35. 8 B

For the following table

draw a sequential circuit using D flip flop
36. Obtain static hazard free asynchronous circuit for the following switching 8 B
function
F= Σ(0,2,4,5,8,10,14)
37. Explain and classify counters 8 B
38. For a given state diagram, draw the sequential circuit using JK flip Flop 8 B

39. Explain how a hazard free circuit can be made by using K map technique 8 C
40. Write short notes on 8 C
a) Race free assignments
b) Pulse mode circuits
Unit Q. Question Max. Difficulty
5 No. marks Index

1. How many address bits are needed to select all memory locations in the 2118 1 A
16K × 1 RAM?
A. 8

B. 10

C. 14

D. 16

2. What is the meaning of RAM, and what is its primary role? 1 A

Readily Available Memory; it is the first level of memory used by the
A.
computer in all of its operations.

Random Access Memory; it is memory that can be reached by any

B.
sub- system within a computer, and at any time.

Random Access Memory; it is the memory used for short-term

UNIT-5

C.
temporary data storage within the computer.

Resettable Automatic Memory; it is memory that can be used and then

D.
automatically reset, or cleared, after being read from or written to.

3. The storage element for a static RAM is the ________. 1 A

A. diode

B. resistor

C. capacitor

D. flip-flop

4. In a DRAM, what is the state of R/W during a read operation? 1 B

A. Low

B. High
 C. Hi-Z

D. None of the above

5. Select the statement that best describes Read-Only Memory (ROM). 1 B

nonvolatile, used to store information that changes during system
A.
operation

nonvolatile, used to store information that does not change during

B.
system operation

volatile, used to store information that changes during system

C.
operation

volatile, used to store information that does not change during system
D.
operation

6. How many 2K × 8 ROM chips would be required to build a 16K × 8 1 B

memory system?
A. 2

B. 4

C. 8

D. 16

7. What is the maximum time required before a dynamic RAM must be 1 B

refreshed?
A. 2 ms

B. 4 ms

C. 8 ms

D. 10 ms

8. Which of the following best describes random-access memory (RAM)? 1 C

A. a type of memory in which access time depends on memory location

a type of memory that can be written to only once but can be read
B.
from an infinite number of times
 a type of memory in which access time is the same for each memory
C.
location

D. mass memory

9. Why are ROMs called nonvolatile memory? 1 C

A. They lose memory when power is removed.

B. They do not lose memory when power is removed.

10. Secondary memory is 1 C

A. Inside the computer
B. Outside the computer
11. A CD-ROM is a form of read-only memory in which data are stored as - 2 A
_______
12. PAL has only______ gates as programmable gates 2 A
13. In PLA ________ gates are programmable 2 B
14. Both PLA and PAL are made of ____gates 2 B
15. FPGA stands for_________ 2 C
16. EPROM stands for_________ 2 C
17. Programming is done using UV rays in _________ 2 A
18. ________RAM needs to be refreshed periodically 2 B
19. _______is a non volatile memory 2 B
20. BJTs diodes and ______can be used to form memory circuits 2 C
21. Define memory cell and memory word. 2 A
22. What is a ROM? 2 A
23. Classify the memory devices 2 B
24. What is meant by PSRAM? 2 B
25. Define address, byte, and access time 2 C
26. What are the features of FPGA? 2 C
27. Explain the difference between primary and secondary memories 4 A
28. What are the advantages of an EEPROM over an EPROM? 4 A
29. How does a static RAM cell differ from a dynamic RAM cell? 4 B
30. Explain FPGA with architecture. 4 B
31. Describe and compare sequential access memories, random access memories 4 C
and read only memories
32. What is a PLD? What do a dot and an x represent on a PLD diagram? 4 C
33. Explain the steps involved in programming of FPGA. 8 A
34. Design following functions using PLA: 8 A
F1= Σ(0,1,2,3,5,6)
F2=Σ( 4,5,6,7,)
35. Design following functions using PAL: 8 B
A1= Σ( 1,5,9,10,13,)
A2=Σ(8,9,10,11,13,15)
36. Design using PAL 8 B
A1= ABC+AC+𝐴𝐵 ̅̅̅̅ 𝐶
A2=AC+ 𝐴̅𝐶 + 𝐴𝐵
37. Design using PLA 8 B
F1= 𝐴̅𝐵𝐶 + 𝐴̅𝐵𝐶̅ + 𝐴̅𝐵̅ 𝐶̅
F2= AC+ 𝐴̅𝐶 + 𝐴𝐵𝐶
38. Design using FPGA 8 B
 F=Σ (0,1,3,5,7) with LUT, Circuit block, Input / output pads
39. Write short notes on PLD’s. 8 C
40. Tabulate a truth table for an 8×4 ROM that implements the following four 8 C
Boolean functions:
A(x,y,z)= Σ (1,2,4,6)
B(x,y,z)=Σ( 0,1,6,7)
C(x,y,z)=Σ(2,6)
D(x,y,z)=Σ(1,2,3,5,7)

Answer Key

Q. No. UNIT 1 UNIT 2 UNIT 3 UNIT 4 UNIT 5

1. B B D A C
2. B B D A C
3. C A B C D
4. D D D B B
5. A A C B B
6. A B D D C
7. B B B B A
8. A A A D C
9. B A C C B
10. C C A D B
11. A B toggle Secondary Pits
variables
12. B A Q=1,Q’=1 1 row AND
13. C C S=R=0 Feedback path AND,OR
14. D A 5 1 AND,OR
15. B A UP Race condition Field
programmable
gate array
16. C A Johnson Flow table Erasable
PROM
17. C A D table EEPROM
18. B B 1 Output/y DRAM
19. D D JK Primitive flow ROM
table
20. D B Edge output MOS