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Lecture 2:
Reflections
Prof Eric Bogatin, Dean, Signal Integrity Academy
Teledyne LeCroy www.beTheSignal.com, eric@beTheSignal.com
Adjunct Prof, ECEE Dept CU, Boulder
And
Prof Melinda Piket-May
Assoc. Prof, ECEE Dept, CU, Boulder
Spring 2016 Feb 2016

ECEN 5224 High Speed Digital Design

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Topic Schedule
1. Jan 19: Intro and the 5 most important principles
2. Jan 26: reflections, driver models, power dissipation
3. Feb 2: routing topologies, eyes and terminations
4. Feb 9: cross talk, guard traces, ground bounce
5. Feb 16: Differential pairs
6. Feb 23: via to via cross talk and cavities
7. Mar 2: S-parameters
8. Mar 9: Attenuation and loss, serial links
9. Mar 16: HFSS intro
10. Mar 23 current distributions
11. Mar 30: spring break
12. April 6: signal and return path discontinuities
13. April 13: vias
14. April 20 measurement and simulation
15. April 27: project presentations
16. May 5: reading day, no class
17. May 9: final exam are the projects (due April 27)

ECEN 5224 High Speed Digital Design

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Reading Assignment #2, due before Feb 2, 2018

• Read: Chapters 8 in the text book

• Sign into the SI Academy and view the videos:
 EPSI, section 4

• Problem set:
 Characterize two driver models: 74AC11, TDR, IDT 74FCT
 Build a transmission line circuit. How long can it be without termination?
 Engineer five different termination schemes and optimize each one. Do some have
advantages?
 Calculate the power dissipation in each approach, assuming driver output resistance is 0.

ECEN 5224 High Speed Digital Design

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Essential Principle #3: Signals see an

instantaneous impedance
ALL Signals ALWAYS propagate
The edge has a spatial extent, where the dV/dt, dI/dt is
The edge sees an instantaneous impedance

Vsignal
V Frozen in time

Signal path
Vin V
Return path GROUND

The dV/dt
The dI/dt V
Z
I
ECEN 5224 High Speed Digital Design
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Electrical Model of a Lossless Transmission Line

   
Telegraphers’ equation V x, t   L Ix, t  Ix, t   C V x, t 
x t x t

2 1 2 2 1 2
Wave equation V x, t   V x, t  Ix, t   Ix, t 
t 2
LC x 2 t 2
LC x 2

L 1
derive Z0  v
C LC
ECEN 5224 High Speed Digital Design

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What is the Impedance of a Transmission Line?

Voltage applied
Z
Current through

C = C L x

I I = Qt Q = CV,
x
C every t = v
vCL  x V
x V I = Qt = x = vCLV

V V 1
instantaneous impedance of the transmission line Z  
I vCL V vCL
The characteristic impedance of a transmission line:
The one value of instantaneous impedance in a uniform transmission line
ECEN 5224 High Speed Digital Design
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Essential Principle # 4: The Return Current is Just

as Important as the Signal Current

signal

+++ +++

= I
displacement
current
--- +++

The current loop has two directions associated with it:

1. A direction of propagation
2. A direction of circulation

They are independent!

ECEN 5224 High Speed Digital Design

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Current Flow in a Transmission Line

ECEN 5224 High Speed Digital Design

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ECEN 5224 High Speed Digital Design

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Current Distributions
50 Ohm microstrip, FR4
t = 3 mils

1 MHz

10 MHz

100 MHz

ECEN 5224 High Speed Digital Design

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An Ideal Transmission Line Model

• Ideal lossless transmission line

 Characteristic impedance, Zo
 Time delay, TD
 Accounts for reflection noise, time delays
• The input impedance of a transmission line
For t < 2 x TD
Vunloaded Rsource

=
Rsource Z0
Z0 Z0 Vlaunched  Vunloaded
Z 0  R source

• What’s missing?
 Coupled transmission lines (diff pairs, multiple lines)
 Lossy transmission lines (impact on rise time degradation)

ECEN 5224 High Speed Digital Design

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Distinction between Signals and Voltages

• Do not confuse the “signal” that propagates with the

“voltage” that is measured at one node
 One has a direction of propagation
 One is a scalar and is the sum of signals propagating in both
directions

• Looking at a voltage at a node, you cannot tell what

direction it is propagating
 If you only learn signal integrity from looking at scope traces you
will screw up your engineering intuition!
 Always think of the signals when viewing scope voltage traces

ECEN 5224 High Speed Digital Design

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HyperLynx: Driving a Transmission line

• Driver models: (look at both rising and falling edge)

• Driving a transmission line

ECEN 5224 High Speed Digital Design

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Why are there reflections?

 If the instantaneous impedance changes some of the
signal reflects

Most important distinction: signals are dynamic! don’t confuse the signal that
propagates with the measured voltage at a node

Read this post: https://bethesignal.com/wp/2015/02/feature-2015-feb-why-are-there-reflections/

ECEN 5224 High Speed Digital Design

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Exercise The Essential Principles:

Reflections at an Open or Short

Vincident = 1 v Vincident = 1 v
Vmeasured = 2 v Vmeasured = 0
Vreflected = 1 v Vreflected = -1 v
Z1 Z2 = open Z1 Z2 = short

Vr   Z1 Vr 0  Z1
  rho   1   rho    1
Vi   Z1 Vi 0  Z1

Iincident(cw) Iincident(cw)

Ireflected(ccw) Ireflected(cw)
Net current is 0- it’s an open! Net current is twice- they add

ECEN 5224 High Speed Digital Design

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Essential Principle# 5: Signals Will Reflect

Whenever The Instantaneous Impedance Changes

If the instantaneous impedance changes,

some of the signal reflects.

50 75
Vt 2 x Z2
If the instantaneous impedance is constant,
the signal continues undistorted.
Vincident Vtransmitted t 
Vi Z 2  Z1
Vr Z 2  Z1
Vreflected   rho  
Vi Z 2  Z1

Multiple sources of impedance discontinuities will

Ringing is caused by multiple reflections from
impedance discontinuities at both ends of a line create reflections that can rattle around and can
dramatically distort the signal

ECEN 5224 High Speed Digital Design

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Predicting Reflection Noise

 = -0.67
TD = 1 nsec =1

50  
10 

Received signal with RT << TD

Reflection noise within 1 unit interval
1v 0.84 v
Reflection noise from 1 bit
leaking into other bits
0.84 v

-0.56 v Inter-Symbol Interference (ISI)

-0.56 v Single Bit Response (SBR)

Circuit simulation is critical to evaluate acceptable

0.38 v designs: SPICE, QUCS, HyperLynx…
Rules of thumb, approximations are not good enough.
0.38 v ALL the details matter, some more than others
ECEN 5224 High Speed Digital Design

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Practice Safe Simulation

Rule #9: Never do a measurement or

simulation without first anticipating what
you expect to see.
If you are wrong, there is a reason- either the set up is
wrong or your intuition is wrong. Either way, by
exploring the difference, you will learn something
If you are right, you get a nice warm feeling that you
understand what is going on.

Corollary to rule #9:

There are so many ways of screwing up a measurement or
simulation, you can never do too many consistency checks

ECEN 5224 High Speed Digital Design

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Dynamic Simulation of Reflected Signals

Download this free animation tool from

www.beTheSignal.com

VRPW-30-16: Yoshi’s Animations of

Reflections

ECEN 5224 High Speed Digital Design

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Acceptable Performance:
Noise Margins
U1.1 TL1 U2.1
VOH VIH Margin VIL VOL Margin
TTL [5volt] 2.4V 2.0V 400mV 0.8v 0.5v 300mV
50.0 ohms
ELB_10_Ohms_0p...
500.000 ps
ELB_10_Ohms_0p...
FCT [5volt] 2.5V 2.0V 500mV 0.8v 0.5v 300mV
Simple

BTL [5 volt] 2.1V 1.62V 480mV 1.47v 1.1v 370mV

VOHmin GTL [5 volt] 1.5V 1.05V 450mV 0.95v 0.55v 400mV
Noise margin, hi
CMOS [5 volt] 4.9V 3.85V 1050mV 1.35v 0.1 1340mV
VIHmin
LVTTL [3volt] 2.4V 2.0V 400mV 0.8v 0.4v 400mV
LVCMOS [3 volt] 2.8V 2.0V 800mV 0.8v 0.2v 600mV

VILmax CMOS [2.5V] 2.0V 1.7V 300mV 0.7v 0.4v 300mV

Noise margin, lo CMOS [1.8V] 1.35V 1.1V 250mV 0.66v 0.45v 210mV
VOLmax
For 5 V CMOS, noise margin-hi/lo ~ 1/5 ~ 20%
For 2.5 V CMOS, noise margin-hi/lo ~ 0.3/2 ~ 15%
For 1.8 V CMOS, noise margin-hi/lo ~ 0.25/1.35 ~ 18%
Typical noise margin for single-ended CMOS technology ~ 15% of signal swing
Noise budget allocation: ~ 1/3 to reflection noise, ~1/3 to xtk, ~1/3 to PDN noise
ECEN 5224 High Speed Digital Design
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Acceptable Performance:
Timing Margin for “Valid” Level
tset-up ~ thold ~ (0.05 nsec and 0.125 nsec for 800 Mbps DDR2)
2.0
Set-up Hold
1.5 time time
data Data @RX must
1.0 be “valid” within
setup and hold
Voltage

0.5
interval
0.0

-0.5 clock
Clock to data
-1.0 skew, jitter,
decrease timing
-1.5 margins on both
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 sides
time, nsec
At 1 Gbps, UI = 1 nsec, time when level needs to be valid: ~ 40% of UI
jitter can be ~30% on each edge
ECEN 5224 High Speed Digital Design

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The Eye Diagram:

The Most Important FINAL Metric of Performance

Take every 2 bits,

A Pseudo Random Bit Sequence (PRBS)
Align synchronous with the clock
(all possible combinations of bit patterns)
Superimpose: The Eye Diagram

data mask

1 unit interval
clock
If ALL RX voltage is outside the mask, bit
error rate will be acceptable

A synchronous clock If any signal “violates” the mask, there

2 bits per clock (double data rate) may be a bit error
Data read edge-triggered
Vertical collapse: noise margin (noise)
Horizontal collapse: timing margin (jitter)

ECEN 5224 High Speed Digital Design

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Turn root cause into best design practices

• Reflections can cause signal distortion and collapse of the eye.

• If the root cause of reflections is changes in the instantaneous
impedance, what general guideline do we follow to eliminate reflection
noise?
 Keep the instantaneous impedance the signal sees constant

• Four typical situations to engineer:

1. Problem: non-uniformity of the transmission lines
 Solution: use controlled impedance lines
2. Problem: the ends of the lines U1.1 TL1 U2.1

 Solution: use a termination strategy

3. Problem: routing topology

 Solution: use a linear route, keep branches short

4. Problem: discontinuities
 Solution: keep them short, match to line impedance

ECEN 5224 High Speed Digital Design

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Practical Design Guideline:

1. Use Controlled Impedance Lines
• Example: four different uniform segments: 40  - 60 

ISI

• Solution: Adjust cross section of each segment to hit

target impedance (use 2D field solver)

ECEN 5224 High Speed Digital Design

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Practical Design Guideline:

Two General Termination Strategies

No termination Far end parallel Source series termination

termination Rsource = Z0 - Zdriver
Or to Vcc
Rterm = Z0
@RX

Shelf at input to the line

Probed 2 inches
from RX

For point to point, all have equivalent signal quality

ECEN 5224 High Speed Digital Design

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Two Important Properties of EVERY Driver:

Rise Time, Output Impedance

10-90 Rise Time

Output impedance

Vsource

Rload = 15 Ω Rsource
Rload
Vout  Vsource
Rsource  Rload
Rload

When Vout = ½ Vsource,

Rsource = Rload

ECEN 5224 High Speed Digital Design

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Decision #1: Received Signal Swing

Due to Finite Output Impedance

Loosing voltage noise margin

Drop ~ output impedance of driver

How to modify far end termination to

provide voltage offset?

ECEN 5224 High Speed Digital Design

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Demo

• Setup, power supply V1 to 0.9

v, V2 to 1.8 v
• Create circuits
 Far end to gnd,
 Far end to V2
 Far end to V1

• Look at the clock signals

• Create eyes for PRBS signals

ECEN 5224 High Speed Digital Design

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Three Other Variations of Far End Termination

Requires Vtt VRM

RT = Z0

RC termination
Rterm = Z0
C ~ 1-100 nF
Far End Thevenin Vtt Termination
Termination
R1 || R2 = RT = Z0

For point to point, all have equivalent signal

quality.

Key feature of these approaches: centers

signal about ½ Vcc

How do we decide which ones to use, when?

ECEN 5224 High Speed Digital Design

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Decision #2: Power Consumption

1  Vlo 2 Vhi2  1 2
• Power is consumed in resistors: P     P 
2
Ilo R  Ihi2R 
2 R R 

Current from driver

Can be very low power dissipation.

If you live for low power, source series
termination should be your first choice

1  02 3.32 
Power consumed by far end termination (50% duty cycle) = P      100mW
2  50 50 

Much less power if << 50% duty cycle, or >> 50% duty cycle and Vcc termination

ECEN 5224 High Speed Digital Design

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Power Consumed in Other Far End

Terminations

R = 100Ω R = 50Ω

R = 100Ω

1   21 3.3   1 3.3  
2 2

1  V V 
2 2 P    2   50mW
P   lo  hi  2  50 50 
2 R R   

1  3.3 2 3.32 
P      100mW
2  100 100 

Vtt termination consumes half the power as Thevenin far end!

(another reason it is preferred- what is the “cost”?)
ECEN 5224 High Speed Digital Design

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Power Consumed in RC

Voltage across
capacitor “charges up”

Signal not centered

@RX initially

1  Vlo 2 Vhi2 
P    
2 R R 
A few time constants later ~
initially 50 x 10 nF ~ 1000 nsec
1   21 3.3   1 3.3  
2 2

P    2   50mW
2  50 50 
 

Power consumed in RC
termination is ½ as much as
far-end single-resistor

ECEN 5224 High Speed Digital Design

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Limitation with RC Termination

• Power dissipation advantage for 50% duty cycle
 Less advantage with non 50% duty cycles

• Some data dependent jitter

 Most suitable for clocks: with 50% duty cycle
 Will have a turn on time for centered signal @RX
 Might be ok for other data nets if jitter is acceptable (need to do PRBS simulation)

700 Mbps PRBS pattern

Vtt termination RC termination

ECEN 5224 High Speed Digital Design

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Which Termination to Use?

• Often times many “correct” answers
• If power is most important
 source series termination
• If a clock net, lowest power, and minimum complexity:
 RC termination
• If low duty cycle control line, mostly lo or mostly hi, lowest power if:
 Far end termination to Vss or Vcc
• For reduced ground bounce @termination:
 Provide connection to each plane used in the return path
• Good balance between: lower power, higher noise margin, higher bandwidth,
but higher cost:
 Far end Vtt termination

• …but for the highest data rate:

 It’s the routing topology that sets the maximum supported data rate, not the termination strategy

 You cannot “terminate away” reflections from poor routing topologies

ECEN 5224 High Speed Digital Design

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Problem Set #2

 Characterize two driver models: 74AC11, TDR, IDT 74FCT

 Pick one of the drivers: Build a transmission line circuit. How long
can it be without termination?
 Engineer the five different termination schemes and optimize each
one. Do some have advantages?
 Calculate the average power dissipation in each approach,
assuming driver output resistance is 0.

ECEN 5224 High Speed Digital Design

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ECEN 5224 High Speed Digital Design