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Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics available options

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6

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Monday, February 28, 2011

Basic of Timing Analysis in Physical Design

Vls

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Lots of people asked me to share my experience over timing analysis. Even though, a lot of material is already present but still it looks to me that
things are not in a systematic way. I try my best to put things in a simple and understandable language or say way and wish it helps everyone
(beginner and professional).
Please let me know in case I have missed any topic or concept. It’s difficult to put everything in a single post, so be ready for series of articles :)
on Timing analysis.

What is Timing Analysis??

Before we start anything, it's important to know "what exactly we mean by Timing Analysis". Why it's so important these days?

There are a couple of reasons for performing timing analysis.

Timing Constraints
We want to verify whether our circuit meet all its timing requirements
VLSI EXPE
There are 3 types of design constraints
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timing, Bridging G
power, Acdamia a

area.
During designing there is a trade-offs between speed, area, power, and runtime according to the constraints set by the
designer. However, a chip must meet the timing constraints to operate at the intended clock rate, so timing is the most 319 fo

important design constraint.

Operating Evniroment:
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We want to make sure that circuit is properly designed and can work properly for all combinations of components over the
entire specified operating environment. "Every Time".
5,549,85
Component Selection: Timing analysis can also help with component selection.
An example: You are trying to determine the speed of the memory device which can be use with a microprocessor.
Using a memory device that is too slow, may not work in the circuit (or would degrade the performance by
introducing wait states) and
Using one that is too fast will likely cost more than it needs to.
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So, I say Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces Posts
are met. Typically, this means that you are trying to meet all set-up, hold, and pulse-width times requirement.
Comments

Note: Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing!
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Types of Timing Analysis:
"Timing Paths
Timing Analys
There are 2 type of Timing Analysis
basic (Part 1)
Static Timing Analysis
Basic of Timin
Checks static delay requirements of the circuit without any input or output vectors. Analysis in Ph
Design
 Dynamic Timing Analysis.
"Setup and H
verifies functionality of the design by applying input vectors and checking for correct output vectors : Static Timing
(STA) basic (

Basic Of Timing Analysis: "Examples Of

and Hold time
The basis of all timing analysis is the "Clock" and "Sequential component" (Flip-flop, Latches). Following are few of the things related to clock and Timing Analys
basic (Part 3c
flip-flop which we usually want to take care during Timing analysis.
"Setup and H
Clock related: Violation" : St
Timing Analys
It must be well understood parametrically and glitch-free. basic (Part 3b
Timing analysis must ensure that any clocks that are generated by the logic are clean, are of bounded period and duty cycle, and of a
known phase relationship to other clock signals of interest. Delay - "Wire
Model" : Stati
The clock must, for both high and low phases, meet the minimum pulse width requirements. Analysis (STA
Certain circuits, such as PLLs, may have other requirements such as maximum jitter. As the clock speeds increase, jitter becomes an (Part 4c)
increasingly important parameter.
Delay - "Inter
When "passing" data from one clock edge to the other, ensure that the worst-case duty cycle is used for the calculation. Remember: A Delay Models
frequent source of error is the analyst assuming that every clock will have a 50% duty cycle. Timing Analys
basic (Part 4b
Flip-Flop related:
"Time Borrow
Make sure that all parameters of flip-flops always met. The only exception is when synchronizers are used to synchronize
Static Timing
asynchronous signals (STA) basic (
For asynchronous presets and clears, there are two basic parameters (Recovery and Removal) must be met.
10 Ways to fix
All setup and hold times are met for the earliest/latest arrival times for the clock. and HOLD vio
Setup times are generally calculated by designers and suitable margins can be demonstrated under test. Hold times, however, are Static Timing
frequently not calculated by designers. (STA) Basic (

When passing data from one clock domain to another, ensure that there is either known phase relationships which will guarantee 5 Steps to Cr
meeting setup and hold times or that the circuits are properly synchronized Interview

Now, let's talk about Each type of Timing analysis One by one in the series of articles.
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Khadar October 15, 2012 at 3:02 PM

Really great job!!! very helpful
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