Design of a ternary static memory cell using carbon nanotube-based transistors

K. You, K. Nepal
Department of Electrical Engineering, Bucknell University, Lewisburg, PA 17837, USA
E-mail: ky004@bucknell.edu; kn010@bucknell.edu

Published in Micro & Nano Letters; Received on 4th April 2011; Revised on 4th May 2011

In this Letter, the authors investigate the use of carbon nanotube-based field effect transistors (CNTFET) for the design of a ternary static
random access memory (SRAM). The authors consider two designs – one using 8 transistors and the other using 14 transistors. Using
circuit simulation models for CNTFETs, the authors show that both designs produce a functional ternary SRAM cell. The authors also
measure the delay and power of the read-and-write operation of the ternary SRAM created using both models and show that the delays are
comparable.

1. Introduction
1.1. Carbon nanotubes: The quest to find an alternative to silicon
technology has spurred a great deal of research into non-silicon
materials and circuit structures. Among the many devices, the excel-
lent electrical properties of the carbon nanotube has made it a poss-
ible contender since its discovery in the early 1990s [1, 2]. Tans
et al. [3, 4] configured carbon nanotubes to behave as a channel
where the movement of the majority carriers could be controlled
by an electric field giving rise to the carbon nanotube field effect
transistors (CNTFETs). Similar to the silicon FETs, both P-type
and N-type FETs can be created by doping the channel with a
P- or N-type material or by controlling the Schottky barriers at the
the metal-nanotube contacts [4]. To create a CNTFET, a number
of tubes are placed or grown on an oxide layer over a silicon substrate
as shown in Fig. 1. The width of the channel depends on the number
of tubes used and their pitch while the length depends on the length
of the tubes directly under the metal gate. A metal contact is placed at
the gate, source and drain to form the FET.
The fabrication process can yield either a metallic or semicon-
ducting tube depending on the angle of the arrangement of
carbon atoms along the tube. This angle of arrangement is referred
to as the chirality vector (n1 , n2). The chirality vector determines the
diameter, the threshold voltage (VTH) and dictates whether the tube
will behave as a metallic or a semiconducting tube. The diameter of
the tube is given in terms of the carbon –carbon bond length
(aC−C = 1.42 Ȧ) and the chirality vectors (n1 , n2)
√ 
3aC−C
dtube = (n21 + n1 n2 + n22 ) (1)
p
The threshold voltage is defined in terms of the tube diameter, dtube ,
and indirectly in terms of the chirality vectors and can be approxi-
mated as
aC−C
VTH ≃ 3.0333 V (2)
dtube
1.2. Ternary logic: A n-variable ternary valued function f (x1 , . . . , xn)
is a mapping f: S n  S, with the variable xi taking values from the
set S ¼ {0, 1, 2}. Other numerical conventions exist for ternary
logic (see [5, 6] for more details). For this Letter, the three distinct
logic levels {0}, {1} and {2} in a ternary circuit correspond to
voltage levels ground (GND), half-of supply (VDD/2) and supply
(VDD). Similar to the universal set {AND, OR, NOT} in binary
logic, a complete ternary logic set involves a set of literal
operators(aX a), the inverse, the minimum (MIN) and maximum
(MAX) functions.
Logically thinking of systems allowing multiple logic values is
naturally more complex. However, when the complexity of a
system and its cost is concerned, it has been shown mathematically
that for a minimum cost, the ideal radix of a number system should
be equal to e(2.71828) [5] (i.e. three-valued logic system). It has
also been shown that numerous mathematical functions can be oper-
ated with fewer operations in ternary logic leading to an overall
advantage over binary logic in terms of area, delay and power [7].
However, the added complexity during fabrication and the overall
unfamiliarity with multi-valued algebra has kept ternary compu-
tation a relatively smaller field. Researchers have successfully
designed different current and voltage mode multi-valued circuits
using CMOS technologies [8, 9]. Different works have also
looked at creating a much simpler design style and tried to reduce
the added complexity during manufacturing [7] to increase the
overall attractiveness of the ternary design.
1.3. CNTFETs for ternary logic: New nanomaterials provide a new
opportunity for multi-valued computation. A number of researchers
have proposed the CNTFET as a foundation for ternary/multi-
valued computing [10– 14]. Raychowdhury and Roy [10] proposed
the use of carbon nanotubes fabricated with different chiral vector
and large resistors to create a resistor-CNTFET circuit structure
for multi-valued computation. The design of circuits proposed in
[13] was similar in concept to [10]. O’Connor et al. [11] also
exploited the geometry-dependent threshold voltages to create
multi-valued logic and Lin et al. [12] proposed a resistor-less
design by using similar multi-threshold CNTFETs. Nepal [14]
showed that dynamic ternary logic can be implemented in
CNTFET devices using multiple voltage rails while using the
same diameter tubes in the CNTFET.

1.4. Multi-valued memory design: Research on multi-valued

memory using CMOS as well as novel technologies has been
going on for quite some time now. Gulak [15] described the
working principle of different memory systems (DRAM, ROM,
Figure 1 A CNTFET structure Flash etc.) and showed how CMOS technology could be used to
a Cross-section build different kinds of multiple-valued memory systems. In [16],
b Top view the authors showed that a four-level static CMOS memory cell

Micro & Nano Letters, 2011, Vol. 6, Iss. 6, pp. 381 –385 381
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can be designed efficiently and its performance can be as good as or
even better than the conventional binary memory. In terms of novel
materials, Manikas and Teeters [17] proposed a multi-valued logic
memory system by using nano-scale electrochemical cells placed in
a crossbar array. Other multi-valued memories using spin valves
[18] and single-electron transistors have also been proposed [19].
In the case of CNTFETs, the design of a binary static random
access memory (SRAM) cell was described in [20]. Lin et al.
[20] showed that the noise margin of the CNTFET SRAM cell
was almost double that of the 32 nm CMOS design while
the power consumption was reduced in half. In this Letter, we use
CNTFETs with different diameters (and hence different
threshold voltages) to design a memory element for multi-valued
computation. We show two design of a SRAM cell based on the
six-transistor ternary inverter proposed by Lin et al. [12] and our
design of a three-transistor ternary inverter based on multiple
supply voltages. We show that the SRAM created using either of
these techniques’ functions correctly during the read-and-write
operations.
2. Ternary inverter – design and simulation: Ternary inverters
come in three different varieties: simple ternary inverter (STI),
negative ternary inverter (NTI) and the positive ternary inverter.
The NTI and the PTI are skewed binary inverters and do not have
an output stage of logic {1} (i.e. VDD/2). The truth-table for the
three flavours is shown in Table 1.
The STI is the primary building block for the proposed SRAM
design because of its ability to produce a logic {1} at the output.
In this Letter we consider two different design of the STI – the
first design is based on the work of Lin et al. [12] and the second
is our design based on multiple voltages. The circuit schematic of
these two STI designs is shown in Fig. 2.
The six-transistor design from [12] is shown in Fig. 2a. The
threshold voltages of the six transistors are P1 ¼ 20.289 V,
P2 ¼ 20.559 V, P3 ¼ 20.428 V, N1 ¼ 0.289 V, N2 ¼ 0.559 V
and N3 ¼ 0.428 V. These threshold voltages allow the transistors
to switch at different input voltages and produce the three required
logic values at the output. Readers are referred to [12] for more
details about the circuit structure. The three-transistor design
shown in Fig. 2b uses two power supplies, a regular supply
voltage (VDD) and a lower-supply voltage (VDDL). The lower-
supply voltage VDDL is equal to VDD/2. For this design, the
Table 1 Truth table of ternary inverters
H STI NTI PTI
0 2 2 2
1 1 0 2
2 0 0 0
Figure 2 Ternary inverter designs
a Six-transistor (6-T STI) design [12]
b Three-transistor (3-T STI) multi-voltage design
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PFET (P1) is created using 8 tubes with a threshold voltage of
20.591 V; the NFET (N1) using 20 tubes with a threshold of
0.591 V. A third NFET (N2) with threshold 0.5 V and two tubes
is connected between voltage rail VDDL and the output is gated
by VDD causing the transistor to always be ON. This always-ON
transistor in effect acts as a pull-up to logic level {1} and allows a
dc path to exist when either N1 or P1 is also ON. To minimise
the fight, N2 transistor is made weaker by using less tubes, lower
pitch to minimise current and increasing the length to 64 nm [21].
To observe the DC and transient behaviour of the circuit and to
verify the functionality, we use the SPICE model from [22] with
a high-supply voltage (VDD) of 0.9 V, a low-supply voltage
(VDDL) of 0.45 V and gate length of 32 nm. Figs. 3 and 4 show
the results of the transient and DC simulation of the ternary inverters.
Both simulations compare the result of the three-transistor design to
the design of the inverter from [12].
Based on the simulation, we see that the both designs
function well as a ternary inverter. The three-transistor design has
trouble settling all the way to 0 V. Instead the logic low for the
three-transistor design is at 19 mV. This is expected because transis-
tor N2 is constantly ON and weekly pulling the OUT node to
VDDL. When the input IN is at logic {0}, this does not pose a
problem but when input is at logic {2}, a fight exists at node
OUT between transistor N1 and N2. Since N1 is stronger (it is com-
posed of more tubes), N1 wins the fight and pulls the node to logic
{0}. This fight is also visible in the transfer characteristic curve of
Fig. 4.
Fabricated carbon nanotube transistors can deviate from the
threshold voltages and diameters specified earlier. Our analysis
Figure 3 Transient simulation of the ternary inverter
V(OUT) is the output of the three-transistor ternary inverter (3-T STI) and
V(OUTM) is the output of the six-transistor inverter (6-T STI) from [12]
Figure 4 DC simulation of the ternary inverter
V(OUT) is the output of the three-transistor ternary inverter (3-T STI) and
V(OUTM) is the output of the six-transistor inverter (6-T STI) from [12]
Micro & Nano Letters, 2011, Vol. 6, Iss. 6, pp. 381 –385
doi: 10.1049/mnl.2011.0168
using SPICE shows that the deviation of +10% can be tolerated.
However, depending on the increase or decrease of the threshold,
the logic margin of one of the logic level suffers by about 80 mV
as the deviation becomes larger.
3. Ternary SRAM – design and simulation: We propose that a
ternary SRAM may be constructed using the same architecture of
a binary 6-T SRAM cell. By cross-coupling two STIs for the data
storage element and adding two access transistors gated by a word-
line WL, the SRAM cell is created as shown in Fig. 5. The STI is
either replaced with the six-transistor design of Lin et al. [12] or the
three-transistor design. Access transistors NA1 and NA2 allow the
logic value at the tritline (TRIT and TRIT_B) to be either written
to the SRAM at nodes Q, Q_B or read from the SRAM to appropri-
ate sense amplifiers. Note that tritlines are the ternary analogue of
bitlines.
Similar to the binary SRAM, the ternary SRAM operation con-
sists of a precharge and the read/write phase. During the precharge
phase, the tritlines are pulled to logic {2} while the wordline
remains low. During the read/write phase, the precharge circuit is
disconnected and the wordline is asserted to either write to or
read from the cell. To read the value stored in the SRAM cell, the
tritlines are precharged and left floating at logic {2}. The wordline
is then asserted and the logic levels stored in Q and Q_B then
Figure 5 Ternary SRAM design
STI is from designs shown in Fig. 2
Figure 6 Read (a) and write (b) operation of logic {2}, {1} and {0}, respectively, using the 3-T STI
Micro & Nano Letters, 2011, Vol. 6, Iss. 6, pp. 381 –385
doi: 10.1049/mnl.2011.0168
settle the tritlines (TRIT and TRIT_B) to the stored values
through the access transistors. Fig. 6a shows the results of the
SPICE simulation of the read operation of logic {2}, {1} and {0},
respectively, for an SRAM cell created using the 3-T STI design.
For clarity, the figure shows a zoomed in snapshot of timeframe
210 to 290 ps. In each of the three sub-plots, the wordline is
asserted at 250 ps.
For writing a particular value into the memory, the tritline driver
drives TRIT and its complement TRIT_B and the desired logic level
is passed onto the storage nodes Q and Q_B through the access tran-
sistors. Fig. 6b shows the results of the SPICE simulation of the
write operation of logic {2}, {1} and {0}, respectively, for an
SRAM cell created using the 3-T STI design. From the Figure, it
is clear that the storage nodes Q and Q_B settle to the correct
values after the wordline is asserted at 250 ps. It is also evident
that the storage of a logic {1} takes longer than the storage of the
other two logic levels. Using the 6-T STI design, the transient simu-
lation plots for both the read-and-write operation plots are similar to
the ones shown in Fig. 6.
Next we compare the read-and-write times of the two designs.
The times shown in Table 2 are extracted from numerous SPICE
simulations for the SRAM cell. Based on the delays shown in
Table 2, writing a {1} in a 3-T STI-based SRAM has the highest
delay of 6.50 ps. The N2 transistor in the 3-T STI is primarily
responsible to bring the output node to the {1} state. To reduce
fight between the transistors during the {2} and {0} states, N2 is
sized to be weak compared to both the P1 and N1 transistors
shown in Fig. 2b. When a {1} needs to be written on the SRAM,
the weak current drive of N2 causes the overall write time of
the node to increase. Since reading a {1} involves passing the
value of node Q (Q_B) to TRIT (TRIT_B) via the access transis-
tors NA1 (NA2) of Fig. 5, no fight is involved and the read time is
the same as reading a {1} in the 6-T STI-based SRAM design.
This is also the reason why we see that the read times in both
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Table 2 Read/write delay and power and area. As explained earlier, the delay for both designs are
comparable.
Logic Read time Write time Read power Write power
(ps) (ps) (uw) (uw)
4. Conclusions: This Letter presented the design of a multi-valued
memory structure based on the carbon nanotube FETs. Using two
3-T STI {0} 1.69 2.83 2.47 2.58
design approaches for a ternary inverter and SPICE models for
{1} 1.60 6.50 0.03 1.49
{2} 1.69 2.83 2.47 2.58
the CNTFETs, we showed that both designs can be used to
6-T STI {0} 1.69 3.44 0.24 0.44
produce a functionally correct circuit. We also showed that while
{1} 1.60 2.65 1.96 1.14 both designs were good in terms of delay, designers can choose
{2} 1.69 3.44 0.24 0.44 between one or the other to trade-off between power and area.
The authors are currently working on the extension of this ternary
memory cell to produce larger memory arrays and to design a
multi-valued content addressable memory.
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