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Abstract— With the emergence of nonplanar CMOS devices turn on the device, providing maximum gate drive. In the IG
at the 22-nm node and beyond, it is highly likely that mode of operation, the two gates are electrically independent.
multigate device adoption will occur in a high-performance The back-gate bias can be used to alter the threshold voltage
process technology, owing to the increased performance and
area benefits. In this paper, for the first time, we evaluate (Vth ) of the front gate, thereby controlling the OFF-current
symmetric (Symm- G ) and asymmetric (Asymm- G ) gate- (IOFF ) of the device [2]. IOFF in SG-mode devices is generally
workfunction FinFETs head to head in a high-performance much higher than in IG-mode devices [with the back gate held
process, using technology computer-aided design 3-D device sim- above (below) the rail for p-type (n-type)], and, because of the
ulations. We demonstrate that Asymm- G shorted-gate (a-SG) fixed Vth , it cannot be altered electrically. The Vth is typically
n/p-FinFETs, which use both workfunctions corresponding to
typical high-performance metal-gate n/p-FinFETs, are promis- controlled by directly setting the gate workfunction. If the front
ing, as they can yield over two orders of magnitude lower and back gates have the same (different) workfunctions, they
leakage without excessive degradation in ON-state current, in are referred to as Symm-G (Asymm-G ) FinFETs. While
comparison to Symm- G shorted-gate (SG) FinFETs, placing IG-mode devices provide the advantage of controlling the
them in a better position than back-gate biased independent- device Vth , and hence delay/leakage, they lead to a complicated
gate (IG) FinFETs for leakage reduction. Thereafter, we explore
the design space of FinFET logic gates, latches, and flip-flops, transistor layout strategy. This is due to the fact that multifin
for optimal tradeoffs in leakage versus delay and temperature, IG-mode FinFETs need larger spacing between the source and
using mixed-mode 2-D device simulations. Elementary logic drain regions, as well as larger fin pitch in order to land
gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using a contact to the back gate in comparison to corresponding
Asymm- G SG-mode FinFETs appear to be located optimally multifin SG-mode FinFETs with compact layouts. The major
in the leakage–delay spectrum, in comparison to the most versa-
tile configurations possible by mixing corresponding Symm- G contributions of this paper are as follows.
SG- and IG-mode FinFETs. Latches and flip-flops, however, 1) We evaluate Symm-G and Asymm-G FinFET
require an astute combination of Symm- G and Asymm- G devices head to head in a high-performance process
FinFETs to optimize leakage, delay, and setup time simultane- using 3-D device simulations in Sentaurus technology
ously.
computer-aided design (TCAD) [3].
Index Terms— Device simulation, FinFETs, flip-flops, leakage 2) We examine the effect of physical device parameters on
power, logic gate, multigate device. ON -current (ION ), OFF -current (IOFF ), and gate work-
function fluctuations (which are likely to be the largest
I. I NTRODUCTION
sources of Vth variation [4]) on FinFET leakage via
TABLE I X
X
FinFET D EVICE PARAMETERS
DRAIN DRAIN
Parameters Y
Y
L GF , L GB (nm) 25
Effective TOXF , TOXB (nm) 1
TSI (nm) 10
FRONT GATE
BACK GATE
FRONT GATE
BACK GATE
HFIN (nm) 50
HGF , HGB (nm) 20
L SPF , L SPB (nm) 20
L UN (nm) 10
NBODY (cm−3 ) 1015
GF , GB (eV) Gn : 4.4, Gp : 4.8
NSD (cm−3 ) 1020
VDD (V) 1 SOURCE SOURCE
VHIGH (V) 1.2
VLOW (V) −0.2
(a) (b)
Φ =Φ =4.4eV ΦGF=ΦGB=4.8eV
GF GB
BACK GATE
FRONT GATE
FRONT GATE
BACK GATE
(a) (b) (c) (d)
X
X
Φ =4.4eV ΦGB=4.4eV
GB
DRAIN
DRAIN
Y
Y
Φ =4.8eV
GF Φ
FRONT GATE
BACK GATE
FRONT GATE
BACK GATE
=4.8eV
GF
(a) (b)
X
X
SOURCE SOURCE DRAIN
DRAIN
Y Y
(a) (b)
BACK GATE
FRONT GATE
BACK GATE
SOURCE SOURCE
(a) (b)
Z Z
FRONT GATE (Φ = 4.8eV)
X X
(c) (d)
G
Z Z
−2 −5
10 x 10 SG−mode
68% I reduction w.r.t SG−mode 14
ON a−SG−mode
IG−mode
−4
10 12
10
−6
10
ION (A)
IDS (A)
8
−8
26% ION reduction w.r.t SG−mode
10
6
a−SG−mode (V =V )
GBS GFS
−10 415X
10 IG−mode (V = −0.2V) 4
GBS
15X
SG−mode (VGBS = VGFS)
−12
2
10 0.02 0.022 0.024 0.026 0.028 0.03
0 0.2 0.4 0.6 0.8 1 LG (μm)
V (V)
GFS
(a)
Fig. 8. IDS versus VGFS for an a-SG-mode n-FinFET (VDS = 1 V), with x 10
−4
−2
10 1.2
88% ION reduction w.r.t SG−mode
1
−4
41% ION reduction w.r.t SG−mode
10
(A)
0.8
ON
−6
10 0.6
I
(A)
0.4
DS
SG−mode
I
−8
10
0.2 a−SG−mode
IG−mode
SG−mode (VGBS = VGFS)
−10
10 0
IG−mode (V = 0.2V) 175X 0.006 0.008 0.01 0.012 0.014
GBS
a−SG−mode (V =V T (μm)
GBS GFS SI
5X
−12
10 (b)
−1 −0.8 −0.6 −0.4 −0.2 0 −5
V (V) x 10
GFS 16 SG−mode
a−SG−mode
Fig. 9. IDS versus VGFS for an a-SG-mode p-FinFET (|VDS | = 1 V), with 14 IG−mode
corresponding curves for SG-mode and IG-mode p-FinFETs.
12
[Fig. 7(b) and (d)], the energy bands bend strongly near the
ION (A)
10
front-gate side (as GF = 4.8 eV), thereby raising the barrier
for electrons. The electrostatic potential/electron density dis- 8
tributions are qualitatively identical to those observed in the
Symm-G IG-mode FinFETs in the OFF state in Fig. 5(b) and 6
(d), respectively. Therefore, Asymm-G FinFETs combine the
advantages offered by Symm-G SG- and IG-mode FinFETs. 4
Fig. 8 quantifies the above, showing that Symm-G SG-
2
mode (IG-mode) n-FinFETs have 415× (15×) higher leakage 4 6 8 10 12
current compared to a-SG-mode devices at 300 K. Fig. 9 shows LUN (μm) −3
x 10
that Symm-G SG-mode (IG-mode) p-FinFETs have 175× (c)
(5×) higher leakage than a-SG-mode p-FinFETs.
Fig. 10. (a) ION versus L G . (b) ION versus TSI . (c) ION versus L UN .
ION characteristics versus variations in L G , TSI , and L UN .
B. Effect of Device Parameter Variations
We also investigated the effect of variations in the para- almost linearly with an increase in L G . ION increases linearly
meters L G , TSI and L UN on ION and IOFF . Fig. 10(a) shows with an increase in TSI in Fig. 10(b), with higher slopes
that in SG/a-SG-mode and IG-mode FinFETs, ION decreases for SG/IG-mode FETs in comparison to a-SG-mode FETs.
1980 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013
Fig. 10(c) shows that ION in SG-mode FETs is very sensitive 0.02
to reduction in L UN , followed by IG-mode FETs, while
a-SG-mode FETs are relatively immune to changes in L UN . 0
/1 nA)
IOFF , on the other hand, is greatly affected by all three
parameters. Fig. 11(a) shows that IOFF in SG/IG-mode devices
has an exp(k/L G ) dependence, while a-SG-mode FETs show −0.02
OFF
a stronger exp(k1 /L G + k2 L G ) dependence, where k, k1 ,
(I
10
and k2 are constants. Fig. 11(b) shows that IOFF has an −0.04
LG log
exp(k1 /L G + k2 L G ) dependence in all cases, with different
values for k1 and k2 for each device. IOFF appears to roughly SG−mode
have an exp(k1 L 2UN + k2 L UN ) dependence on L UN in all cases −0.06
a−SG−mode
in Fig. 11(c). IG−mode
−0.08
0.02 0.022 0.024 0.026 0.028 0.03
C. Effect of Gate-Workfunction Fluctuations L (μm)
G
Since metal-gate FET Vth s are linearly dependent on (a)
the gate workfunction, we studied the effect of work- 0.015
function fluctuations on IOFF (or ILEAK ) in n-FinFETs. SG−mode
In [4], gate workfunction variation is shown to be the 0.01 a−SG−mode
major contribution to Vth variation in comparison to L G
1 SG−mode
D. Effect of Temperature on Leakage a−SG−mode
0.5 IG−mode
Fig. 13 suggests that the ILEAK advantage in topologies
having SG- and IG-mode FinFETs would reduce relative to
(IOFF/1 nA)
0
those of only SG-mode FinFETs with an increase in tem-
perature. Also, a-SG-mode devices have two (one) orders of −0.5
magnitude lower IOFF than Symm-G SG-mode (IG-mode)
FinFETs. −1
10
log
−1.5
IV. S YMMETRIC -G AND A SYMMETRIC -G FinFET
L OGIC G ATES −2
A significant problem with logic circuits implemented in
high-performance process technologies is the relatively high −2.5
4 6 8 10 12
leakage current that is concomitant with the high ON-state LUN (μm) −3
x 10
current. Hence, circuit topologies with low leakage that do (c)
not compromise on performance constitute the optimal design
points. In this section, we explore the design space of Symm- Fig. 11. (a) IOFF versus L G . (b) IOFF versus TSI . (c) IOFF versus L UN .
G FinFET INV and NAND2 gates in detail to determine the IOFF characteristics versus variations in L G , TSI , and L UN .
most versatile topologies that can arise by mixing Symm-G
SG- and IG-mode FinFETs.
in practical timeframes. Also, transient simulations, which
are necessary to capture logic element delays, are extremely
A. 3-D Versus 2-D Device Simulation cumbersome to perform via 3-D device simulation on account
Owing to the prohibitively high computational costs of which device simulations on a 2-D structure (corresponding
involved in single-FET 3-D transport simulations, mixed- to a slice of the 3-D FinFET device) are used hereafter.
mode 3-D device simulations for FinFET circuits is intractable Since 2-D simulations do not fully capture all physical effects
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1981
0.6
33%
0.4
DS, 3D
0.2
a−SG
)/I
24% −4.3%
DS, 3D
IG 0
SG 4.5%
−I
−0.2
−11.2%
DS, 2D
−0.4
SG−mode
(I
−0.6 IG−mode
a−SG−mode
−0.8
0 0.2 0.4 0.6 0.8 1
VGFS (V)
Fig. 14. Fractional error in IDS versus VGFS for 2-D/3-D device simulations.
Fig. 12. ILEAK distribution for a-SG/SG/IG-mode n-FinFETs under gate
workfunction fluctuations. σG = 50 meV.
−7
10
−8
10
104X
−9
8X
10
IOFF (A)
Fig. 16. INV layouts. (a) SG (size X2). (b) LP (size X1). (c) IGn (size X1).
(d) IGp (size X1).
(a) (b) (c)
Fig. 19. NAND 2 layouts. (a) SG (size X2). (b) LP (size X1). (c) XT2
(size X1).
Fig. 17. NAND 2 gates. (a) SG. (b) LP. (c) MT.
TABLE II
S TANDARD C ELL FinFET INV C HARACTERISTICS , VLOW = −0.2 V AND
VHIGH = 1.2 V
TABLE III
S TANDARD C ELL FinFET NAND 2 C HARACTERISTICS
1.2 1.2
1 1
0.8
0.8
Voltage (V)
Voltage (V)
0.6
0.6 VA, VB
V ,V
A B
VOUT, Toggle A VOUT, Toggle A
0.4
0.4 V , Toggle B
VOUT, Toggle B OUT
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
−0.2
0 1 2 3 4 5 6
−0.2 Time (s) x 10
−10
0 1 2 3 4 5 6
(b)
Time (s) −10
x 10
(b)
Fig. 24. XT2-NAND2 transient charactertistics. Input rise time has been
increased from 10 to 50 ps to improve visibility. (a) Node voltages, and
Fig. 23. SG- NAND2 transient charactertistics. Input rise time has been (b) VG F S on FInFET NA.
increased from 10 to 50 ps to improve visibility. (a) Node voltages, and
(b) VG F S on FInFET NA.
Fig. 25 shows the leakage–delay characteristics of the Next, we investigate simple latches and flip-flops that lever-
Asymm-G gates compared to their corresponding Symm- age combinations of Symm-G and Asymm-G FinFETs,
G SG-mode counterparts as well as IGn-INV and using insights from earlier sections. We modified four tem-
XT2-NAND2 gates, which were the best Symm-G gates. plate configurations, namely, the brute-force transmission gate
a-SG-INV gates are 60% slower than their SG-INV coun- [TGL, Fig. 26(b)] and half-swing clocked FinFET latches
terparts, with average leakage that is 238× lower, while [HSL, Figs. 27 and 28], and the corresponding flip-flops
a-SG-NAND2 gates are 65% slower than SG-NAND2 gates, [TGF, Fig. 27 and HSF, Fig. 28], in order to demonstrate the
with 235× lower leakage. (a-SG- NOR2, a-SG-XOR2, and importance of choosing the appropriate kinds of FinFETs to
a-SG-XNOR2) gates had (234×, 206×, and 234×) lower optimize leakage, propagation delay, and setup time.
average leakage compared to (SG-NOR2, SG-XOR2, and SG- Tables IV and V show the various possible cases of interest
XNOR2) with (34%, 20%, and 10%) higher delay, respectively. for TGL, TGF, HSL, and HSF using SG-, a-SG-, and IG-mode
The NAND2S gate, which introduces a Symm-G SG-mode FinFETs along with their fin counts. TGL1 and TGF1 have
n-FinFET to reduce delay, has SG- NAND2-like leakage for the only SG-mode FinFETs, which necessitates a larger I 1 gate in
“10” vector, thereby increasing overall average ILEAK . From order to overcome I 3 and force the data into the cross-coupled
Fig. 25, it is also clear that the best IG-mode configurations inverter configuration. TGL2 and TGF2 employ a-SG-mode
such as IGn-INV and XT2-NAND2 are not as well placed as FinFETs to implement a weaker I 3 gate, hence, permitting a
their a-SG-mode counterparts in the leakage–delay spectrum. smaller I 1 gate. By replacing I 1/I 2 with a-SG-mode FinFETs
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1985
−12 TABLE IV
x 10
14 TG L ATCH AND F LIP -F LOP C ASES , xPyN = x-fin p-FinFET, y-fin
SG−XOR2 n-FinFET, T2 = SG(1P1N)
a−SG−XOR2
12
Case I 1/I 2 I3 T1 I4 I5 I6
a−SG−NOR2
Average FO4 delay (s)
TGL1 SG SG SG - - -
10
XT2−NAND2 4P2N/2P1N 1P1N 2P2N - - -
a−SG−NAND2S SG−NOR2 TGL2 SG a-SG SG - - -
8 a−SG−NAND2
TGL3 a-SG a-SG SG - - -
IGn−INV
SG−NAND2 TGL4 SG IG SG - - -
6 2P1N/2P1N 1P1N 1P1N - - -
a−SG−XNOR2
TGF1 SG SG SG SG SG SG
4 SG−XNOR2
a−SG−INV 4P2N/2P1N 1P1N 2P2N 1P1N 1P1N 2P1N
SG−INV
TGF2 SG a-SG SG SG a-SG SG
2 −11 −10 −9 −8 TGF3 a-SG a-SG SG a-SG a-SG a-SG
10 10 10 10
Average I (A) TGF4 SG IG SG IG IG SG
LEAK
2P1N/2P1N 1P1N 1P1N 1P1N 1P1N 2P1N
Fig. 25. Leakage–delay spectrum for Asymm-G FinFET logic gates.
TABLE V −9
x 10 HSF1
HS L ATCH AND F LIP -F LOP C ASES , xPyN = x-fin p-FinFET, y-fin 8 HSF5
n-FinFET, N1/N3/N7 = SG(2N), I5 = SG(2P1N)
7
Case I 1/I 2 N 2/N 4 I 3/I 4 N 5/N 6
HSL1 SG SG - - 6
HSL2 SG a-SG - - TGF1 HSF2 HSF4 HSF6
HSL3 a-SG SG - -
HSL5 IG SG - -
4
HSL6 IG a-SG - - TGF2
1P1N/1P1N 2N/2N - - HSF3
3
HSF1 SG SG SG SG
HSF2 SG a-SG SG a-SG
HSF3 a-SG a-SG a-SG a-SG 2
1
5
HSL2
0.5
HSL5
4
TGL1
(A)
HSL6 0
LEAK
1 2 3 4 5 6 7 8 9 10
3 HSL3
Average I
−11
x 10 mode FinFET configuration, owing to the large I 1 data-
6
forcing inverter. (TGF2, TGF3) and (HSF3, HSF4) have
TGF4
considerably larger setup times, as they employ weaker
5 TGF3 a-SG-mode FinFETs. Similar trends were also observed for
TGF1 HSF5 HSF6 latches.
In summary, (TGF3, HSF3), which are implemented using
Average propagation delay (s)
HSF3 HSF4
4 a combination of a-SG-mode and SG-mode FinFETs, have the
best tradeoffs in leakage, delay, and setup time for (TG, HS)
HSF1 HSF2
TGF2
flip-flop configurations.
3
VI. C ONCLUSION
Unlike prior fragmented approaches to FinFET
2 logic/sequential circuit design, in this paper, we evaluated
Symm-G SG/IG-mode FinFETs and Asymm-G SG-mode
FinFETs head to head in a high-performance process. We
1 also investigated the design space of logic gates, latches, and
flip-flops employing them in a unified manner, which resulted
in the following key insights.
0 1) Asymm-G SG-mode FinFETs with high-performance
1 2 3 4 5 6 7 8 9 10
targets provide very steep subthreshold slopes, ultralow
Fig. 32. Average propagation delay for FinFET flip-flops. off-currents, and reasonably high ON-currents in
comparison to Symm-G SG/IG-mode FinFETs, and
−11
3.5
x 10 maintain their advantage at high temperature. This sug-
HSF3 gests that they could be widely used (in combination
HSF4 with Symm-G SG-mode FinFETs when necessary)
3 in off-critical paths, with the same layout as Symm-
G SG-mode devices and without the routing and
TGF2 HSF2
2.5 HSF1 process-related problems of integrating IG-mode back-
TGF3 HSF6
HSF5 gate biased devices.
Setup time (s)
0
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1 2 3 4 5 6 7 8 9 10
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[7] A. Muttreja, N. Agarwal, and N. K. Jha, “CMOS logic design with Niraj K. Jha (S’85–M’85–SM’93–F’98) received
independent gate FinFETs,” in Proc. Int. Conf. Comput. Design, Oct. the B.Tech. degree in electronics and electrical com-
2007, pp. 560–567. munication engineering from the Indian Institute of
[8] M. Rostami and K. Mohanram, “Dual-Vth independent-gate FinFETs for Technology, Kharagpur, India, in 1981, the M.S.
low power logic circuits,” IEEE Trans. Comput.-Aided Design, vol. 30, degree in electrical engineering from State Univer-
no. 3, pp. 337–349, Mar. 2011. sity of New York at Stony Brook, Stony Brook,
[9] A. Datta, A. Goel, R. T. Cakici, H. Mahmoodi, D. Lakshmanan, and in 1982, and the Ph.D. degree in electrical engi-
K. Roy, “Modeling and circuit synthesis for independently controlled neering from the University of Illinois at Urbana-
double gate FinFET devices,” IEEE Trans. Comput.-Aided Design, Champaign, Urbana, in 1985.
vol. 26, no. 11, pp. 1957–1966, Nov. 2007. He is a Professor of electrical engineering with
Princeton University, Princeton, NJ. He has co-
[10] S. A. Tawfik and V. Kursun, “Low-power and compact sequential circuits
authored or co-edited five books titled the Testing and Reliable Design of
with independent-gate FinFETs,” IEEE Trans. Electron Devices, vol. 55,
CMOS Circuits (Kluwer, 1990), High-Level Power Analysis and Optimization
no. 1, pp. 60–70, Jan. 2008.
(Kluwer, 1998), Testing of Digital Systems (Cambridge University Press,
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gate biased FinFET latches and flip-flops under process variations,” in versity Press, 2009), and Nanoelectronic Circuit Design (Springer, 2010).
Proc. Int. Symp. Qual. Electron. Design, Mar. 2008, pp. 311–316. He has authored 12 book chapters. He has authored or co-authored more
[12] J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, than 390 technical papers. He has co-authored 14 award-winning papers. He
H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. holds 13 U.S. patents. He has given several keynote speeches in the area of
Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. nanoelectronic design and test. His current research interests include FinFETs,
E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, low power hardware/software design, computer-aided design of integrated
M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate and circuits and systems, digital system testing, and secure computing.
CMOS-compatible Vt asymmetric-gate FinFET devices,” in Proc. Int. Dr. Jha is a fellow of ACM. He has served as the Editor-in-Chief of the IEEE
Electron. Device Meeting, 2001, pp. 19.5.1–19.5.4. T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS
[13] L. Mathew, M. Sadd, B. E. White, A. Vandooren, S. Dakshina-Murthy, and an Associate Editor of the IEEE T RANSACTIONS ON C IRCUITS
J. Cobb, T. Stephens, R. Mora, D. Pham, J. Conner, T. White, Z. Shi, A. AND S YSTEMS –I: R EGULAR PAPERS and the IEEE T RANSACTIONS ON
V.-Y. Thean, A. Barr, M. Zavala, J. Schaeffer, M. J. Rendon, D. Sing, C IRCUITS AND S YSTEMS –II: E XPRESS B RIEFS , the IEEE T RANSACTIONS
M. Orlowski, B.-Y. Nguyen, and J. Mogab, “FinFET with isolated n+ ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS
and p+ gate regions strapped with metal and polysilicon,” in Proc. Int. the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI)
SOI Conf., Nov. 2003, pp. 109–110. S YSTEMS , and the Journal of Electronic Testing: Theory and Applications.
[14] A. N. Bhoj and N. K. Jha, “Design of ultra-low-leakage logic gates and He is currently serving as an Associate Editor of the IEEE T RANSACTIONS
flip-flops in high-performance FinFET technology,” in Proc. Int. Symp. ON C OMPUTERS , the Journal of Low Power Electronics, and the Journal
Qual. Electron. Design, Mar. 2011, pp. 1–8. of Nanotechnology. He has served as the Program Chairman of the 1992
[15] A. N. Bhoj and N. K. Jha, “Gated-diode FinFET DRAMs: Device and Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004
circuit design considerations,” ACM J. Emerg. Technol. Comput. Syst., International Conference on Embedded and Ubiquitous Computing, and the
vol. 6, no. 4, pp. 12:1–12:32, 2010. 2010 International Conference on VLSI Design. He has served as the Director
of the Center for Embedded System-on-a-Chip Design funded by the New
[16] D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, “Molybdenum gate
Jersey Commission on Science and Technology. He is a recipient of the
technology for ultrathin-body MOSFETs and FinFETs,” IEEE Trans.
AT&T Foundation Award and NEC Preceptorship Award for research excel-
Electron Devices, vol. 51, no. 12, pp. 1989–1996, Dec. 2004.
lence, the NCR Award for Teaching Excellence, and the Princeton University
[17] J. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Graduate Mentoring Award. He was a recipient of the Best Paper Award
Springer-Verlag, 2008. at ICCD’93, FTCS’97, ICVLSID’98, DAC’99, PDCS’02, ICVLSID’03,
[18] M. Alioto, “Comparative evaluation of layout density in 3T, 4T, and MT CODES’06, ICCD’09, and CLOUD’10. His paper was selected for “The
FinFET standard cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Best of ICCAD: A Collection of the Best IEEE International Conference
Syst., vol. 19, no. 5, pp. 751–762, May 2011. on Computer-Aided Design papers of the past 20 years,” two papers by IEEE
Micro Magazine as one of the top picks from the 2005 and 2007 Computer
Architecture Conferences, and two others as being among the most influential
papers of the last ten years at the IEEE Design Automation and Test in Europe
Conference. He has co-authored six other papers that have been nominated
Ajay N. Bhoj (S’07) received the B.Tech. degree for Best Paper Awards.
from the Indian Institute of Technology, Chennai,
India, in 2007, and the M.A. degree from Princeton
University, Princeton, NJ, in 2009, where he is
currently pursuing the Ph.D. degree, all in electrical
engineering.
His current research interests include interesting
problems in device modeling, simulation of multi-
gate transistors, SRAM/eDRAMs as well as low
power digital circuit design, and computer architec-
ture/VLSI implementations of architectural ideas.