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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

11, NOVEMBER 2013 1975

Design of Logic Gates and Flip-Flops in


High-performance FinFET Technology
Ajay N. Bhoj, Student Member, IEEE, and Niraj K. Jha, Fellow, IEEE

Abstract— With the emergence of nonplanar CMOS devices turn on the device, providing maximum gate drive. In the IG
at the 22-nm node and beyond, it is highly likely that mode of operation, the two gates are electrically independent.
multigate device adoption will occur in a high-performance The back-gate bias can be used to alter the threshold voltage
process technology, owing to the increased performance and
area benefits. In this paper, for the first time, we evaluate (Vth ) of the front gate, thereby controlling the OFF-current
symmetric (Symm- G ) and asymmetric (Asymm- G ) gate- (IOFF ) of the device [2]. IOFF in SG-mode devices is generally
workfunction FinFETs head to head in a high-performance much higher than in IG-mode devices [with the back gate held
process, using technology computer-aided design 3-D device sim- above (below) the rail for p-type (n-type)], and, because of the
ulations. We demonstrate that Asymm- G shorted-gate (a-SG) fixed Vth , it cannot be altered electrically. The Vth is typically
n/p-FinFETs, which use both workfunctions corresponding to
typical high-performance metal-gate n/p-FinFETs, are promis- controlled by directly setting the gate workfunction. If the front
ing, as they can yield over two orders of magnitude lower and back gates have the same (different) workfunctions, they
leakage without excessive degradation in ON-state current, in are referred to as Symm-G (Asymm-G ) FinFETs. While
comparison to Symm- G shorted-gate (SG) FinFETs, placing IG-mode devices provide the advantage of controlling the
them in a better position than back-gate biased independent- device Vth , and hence delay/leakage, they lead to a complicated
gate (IG) FinFETs for leakage reduction. Thereafter, we explore
the design space of FinFET logic gates, latches, and flip-flops, transistor layout strategy. This is due to the fact that multifin
for optimal tradeoffs in leakage versus delay and temperature, IG-mode FinFETs need larger spacing between the source and
using mixed-mode 2-D device simulations. Elementary logic drain regions, as well as larger fin pitch in order to land
gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using a contact to the back gate in comparison to corresponding
Asymm- G SG-mode FinFETs appear to be located optimally multifin SG-mode FinFETs with compact layouts. The major
in the leakage–delay spectrum, in comparison to the most versa-
tile configurations possible by mixing corresponding Symm- G contributions of this paper are as follows.
SG- and IG-mode FinFETs. Latches and flip-flops, however, 1) We evaluate Symm-G and Asymm-G FinFET
require an astute combination of Symm- G and Asymm- G devices head to head in a high-performance process
FinFETs to optimize leakage, delay, and setup time simultane- using 3-D device simulations in Sentaurus technology
ously.
computer-aided design (TCAD) [3].
Index Terms— Device simulation, FinFETs, flip-flops, leakage 2) We examine the effect of physical device parameters on
power, logic gate, multigate device. ON -current (ION ), OFF -current (IOFF ), and gate work-
function fluctuations (which are likely to be the largest
I. I NTRODUCTION
sources of Vth variation [4]) on FinFET leakage via

P LANAR transistor scaling in deep-submicrometer CMOS


technology has approached its limits at sub-22-nm nodes,
owing to very poor electrostatic integrity, which is manifested
quasi-Monte Carlo 3-D device simulations.
3) We comprehensively probe the design space of Symm-
G and Asymm-G FinFET logic gates and flip-
as degraded short-channel behavior and high leakage current. flops along various electrical characteristic dimensions
Multigate field-effect transistors (FETs) overcome these prob- (leakage, delay) and layout complexity/area by suitably
lems because of tighter control of the channel potential by mixing SG/a-SG/IG-mode FinFETs, using mixed-mode
multiple gates wrapped around the body. Amongst multigate 2-D device simulations.
FETs, FinFETs/-FETs have emerged as the best candidate 4) For the first time, we also demonstrate that the most
structures from a fabrication perspective [1]. versatile Symm-G topologies fail to approach the
The FinFET device structure consists of a silicon fin leakage–delay tradeoffs enjoyed by logic elements based
surrounded by shorted or independent gates on either side on Asymm-G SG-mode FinFETs. This suggests that
of the fin, typically on a silicon-on-insulator substrate. In the it is more practical to use Asymm-G FinFETs for
SG mode of operation, the two gates are biased together to ultralow-leakage designs in a high-performance FinFET
Manuscript received May 14, 2012; revised August 14, 2012; accepted technology rather than integrate Symm-G IG-mode
October 23, 2012. Date of publication January 17, 2013; date of current FinFETs (which have high area/process overheads and
version September 23, 2013. This work was supported by SRC under Contract introduce additional CAD/layout design/testing costs),
2010-HJ-2079.
The authors are with the Department of Electrical Engineering, Prince- or add a third gate workfunction to the process (which
ton University, Princeton, NJ 08544 USA (e-mail: abhoj@princeton.edu; dramatically exacerbates yield control issues and process
jha@princeton.edu). cost).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. The rest of this paper is organized as follows. In Section II,
Digital Object Identifier 10.1109/TVLSI.2012.2227850 we review related work. In Section III, we evaluate key
1063-8210 © 2013 IEEE
1976 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

metrics of Symm-G and Asymm-G FinFETs via 3-D/2-D


device transport simulations. Thereafter, we employ mixed-
mode 2-D device simulations in subsequent sections, owing
to the rapid increase in computational complexity/time of
3-D device simulations. In Section IV, we characterize var-
ious plausible Symm-G and Asymm-G FinFET inverter GATE
SOURCE
(INV) and two-input NAND (NAND2) logic gates in detail
to determine the most versatile configurations with respect
to the electrical characteristics. In Section V, we examine
tradeoffs in designing basic latch and flip-flop topologies using
various combinations of Symm-G SG/IG-mode and Asymm-
G SG-mode FinFETs, using insights from Sections III
and IV. Finally, we conclude in Section VI.
DRAIN
Z
II. R ELATED W ORK Y X
Circuit design based on low-leakage multigate
FETs/FinFETs has garnered significant attention over
the past decade, owing to the explosive increase in leakage Fig. 1. SG-mode 3-D FinFET structure simulated in Sentaurus TCAD.
power consumption in planar FETs at lower technology
nodes. Low-power multigate circuit design has been explored
from a device-circuit viewpoint in [5] and [6]. In [7]–[9], logic
styles leveraging the SG and IG modes of FinFET operation
have been investigated. FinFET latches and flip-flops have
been studied in [10] and [11]. Owing to its small dimensions,
a FinFET is likely to suffer from the effects of process and
temperature variations. In gate workfunction variation is
shown to be the most important contributor to the variation in
Vth for metal-gate FinFETs. FinFETs with asymmetric gate
workfunctions in the form of n+/p+ polysilicon gates have
been engineered and investigated in [12] and [13].
Since multigate adoption is likely to be driven by per-
formance/area benefits, in this paper, we comprehensively
characterize Symm-G and Asymm-G FinFETs in a high-
performance process. We also investigate various possible
configurations of logic gates and flip-flops employing such Fig. 2. 2-D (X-Y ) cross-section of an n-FinFET simulated in Sentaurus
FinFETs through mixed-mode device simulation (taking into TCAD.
account the effect of temperature) from a digital circuit
designer’s perspective. Preliminary results dealing with the
latter were presented in [14]. front- and back-gate spacer thicknesses, gate-drain/source
underlap, body doping, front- and back-gate workfunctions,
source/drain doping, and the operating voltage, respectively.
III. S YMMETRIC -G AND A SYMMETRIC -G
The Vth of FinFETs is typically tuned by directly adjusting
FinFET D EVICES
the workfunction of the gate material [16]. The workfunc-
In this section, we evaluate Symm-G and Asymm- tions for n-FinFET (GF = GB = Gn = 4.4 eV) and
G FinFETs head to head in a high-performance p-FinFET (GF = GB = Gp = 4.8 eV) devices were
process. Owing to the absence of a suitable platform chosen corresponding to high-performance logic requirements
for multigate circuit design exploration, we use FinE3- [17] and yield low-Vth devices whose symbols are shown in
D, an extension of FinE [15]. We utilized the FinFET Fig. 3.
device structure shown in Fig. 1 for 3-D device transport
simulations in Sentaurus TCAD [3]. Also, a 2-D
(X-Y ) cross-section of the device structure in Fig. 1 as A. ION and IOFF Characteristics
shown in Fig. 2, was employed for mixed-mode device- We revisit the physics of SG- and IG-mode FinFET devices,
circuit simulations. In Table I, the parameters for a typical to better appreciate the limitations of Symm-G devices
n/p-FinFET device are listed, where L GF , L GB , TOXF , TOXB , and the advantages of Asymm-G FinFETs. Accounting for
TSI , HFIN , HGF , HGB, L SPF , L SPB , L UN , NBODY , GF , temperature effects, we performed hydrodynamic mixed-mode
GB , NSD , and VDD are the physical front- and back-gate 3-D device simulations on carefully defined meshes (for excel-
lengths, front- and back-gate effective oxide thicknesses, lent convergence) and invoked the density gradient model for
fin thickness, fin height, front- and back-gate thicknesses, incorporating quantum effects in a thin fin. We ignored the
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1977

TABLE I X
X
FinFET D EVICE PARAMETERS
DRAIN DRAIN
Parameters Y
Y
L GF , L GB (nm) 25
Effective TOXF , TOXB (nm) 1
TSI (nm) 10

FRONT GATE

BACK GATE

FRONT GATE

BACK GATE
HFIN (nm) 50
HGF , HGB (nm) 20
L SPF , L SPB (nm) 20
L UN (nm) 10
NBODY (cm−3 ) 1015
GF , GB (eV) Gn : 4.4, Gp : 4.8
NSD (cm−3 ) 1020
VDD (V) 1 SOURCE SOURCE
VHIGH (V) 1.2
VLOW (V) −0.2
(a) (b)

Φ =Φ =4.4eV ΦGF=ΦGB=4.8eV
GF GB

BACK GATE
FRONT GATE
FRONT GATE

BACK GATE
(a) (b) (c) (d)

Fig. 3. Symm-G FinFET symbols. (a) SG-mode n-type. (b) IG-mode


n-type. (c) SG-mode p-type. (d) IG-mode p-type.

effects of gate tunneling currents due to the undoped fin, and


used an effective oxide thickness that can easily be realized Z Z
using thicker high-k dielectrics to suppress gate leakage.
Fig. 4(a) and (b) show the electrostatic potential in the
fin region (X–Y plane) of an SG-mode n-FinFET under
X X
ON -state (VGFS = VGBS = 1 V, VDS = 1 V) and OFF -state
(c) (d)
(VGFS = VGBS = 0 V, VDS = 1 V) conditions. In the ON
state, both gates contribute to band-bending such that inverted Fig. 4. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential.
regions [Fig. 4(c)] form beside both gates (and move toward (c) ON-state electron density. (d) OFF-state electron density. Electrostatic
the fin center as TSI decreases, due to increased quantum potential and electron density distributions within the fin region of an
SG-mode n-FinFET for ON-state (VGFS = VGBS = 1 V, VDS = 1 V) and
confinement), leading to high drain current. In the OFF state, OFF-state (VGFS = VGBS = 0 V, VDS = 1 V) conditions.
the fin center is most susceptible to leakage [Fig. 4(d)], as the
barrier height for electrons is higher for paths closer to either
gate.
In Figs. 5(a)–(d), the electrostatic potential and electron Next, we introduce Asymm-G FinFETs and demon-
density in an IG-mode n-FinFET is shown with VGBS = strate that they possess steep subthreshold characteristics
−0.2 V. The bias on the back gate causes an inverted region to that can be employed in the design of ultralow-leakage
form predominantly near the front gate, which contributes to logic circuits in high-performance process technologies, thus
the drain current in the ON state [Fig. 5(a) and (c)], and leads reducing the need for Symm-G IG-mode FinFET-based
to leakage paths beside the front gate in the OFF state [Fig. 5(b) back-gate biasing schemes. Asymm-G FinFETs can be
and (d)]. The peak electron density in the OFF state (which is formed by adjusting the workfunctions on each side of
tunable using VGBS ) is over an order of magnitude smaller in the SG-mode FinFET using selective implantation for the
the IG mode in comparison to the SG mode, indicating that IG- gate-stack. This has been demonstrated for n+ /p+ polysili-
mode FinFETs have lower leakage. This suggests that using con gates using large-angle tilt implants [12], [13]. If the
IG-mode FinFETs (with a strong reverse bias on the back choice of front/back-gate workfunctions is identical to that
gate) can considerably reduce leakage by up to two orders of high-performance n/p-FinFET metal-gate workfunctions,
of magnitude in FinFET standard cells in high-performance as shown in Fig. 6, it would be favorable from a fabrica-
processes. tion perspective. All Asymm-G FinFETs, n- or p-channel,
1978 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

X
X
Φ =4.4eV ΦGB=4.4eV
GB
DRAIN
DRAIN

Y
Y

Φ =4.8eV
GF Φ
FRONT GATE

BACK GATE

FRONT GATE

BACK GATE
=4.8eV
GF
(a) (b)

Fig. 6. Asymm-G FinFET symbols. (a) a-SG-mode n-type. (b) a-SG-mode


p-type.

X
X
SOURCE SOURCE DRAIN
DRAIN

Y Y
(a) (b)

FRONT GATE (ΦG = 4.8eV)

BACK GATE (ΦG = 4.4eV)

FRONT GATE (ΦG = 4.8eV)

BACK GATE (ΦG = 4.4eV)


FRONT GATE

BACK GATE
FRONT GATE

BACK GATE

SOURCE SOURCE

(a) (b)

Z Z
FRONT GATE (Φ = 4.8eV)

FRONT GATE (ΦG = 4.8eV)

BACK GATE (ΦG = 4.4eV)


BACK GATE (Φ = 4.4eV)

X X
(c) (d)
G

Fig. 5. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential.


(c) ON-state electron density. (d) OFF-state electron density. Electrostatic
potential and electron density distributions within the fin region of an IG-
mode n-FinFET for ON-state (VGFS = 1 V, VGBS = −0.2 V, VDS = 1 V)
and OFF-state (VGFS = 0 V, VGBS = −0.2 V, VDS = 1 V) conditions.

Z Z

would have both workfunctions on either side of the fin,


without the need for complicating the process with a
third gate workfunction exclusively for high-Vth devices, X X
(c) (d)
and high-performance SG-mode Symm-G n/p-FinFETs
would be fabricated along with them using the same gate Fig. 7. (a) ON-state electrostatic potential. (b) OFF-state electrostatic potential.
workfunctions. In Fig. 6, both n-FinFETs and p-FinFETs (c) ON-state electron density. (d) OFF-state electron density. Electrostatic
have 4.4/4.8 eV workfunctions, with the source/drain doping potential and electron density distributions within the fin region of an
a-SG-mode n-FinFET for ON-state (VGFS = VGBS = 1 V, VDS = 1 V)
determining the type of majority charge carrier conduction and OFF-state (VGFS = VGBS = 0 V, VDS = 1 V) conditions.
during the ON state. Since the asymmetric-workfunction gates
are shorted, they are referred to as “a-SG-mode” FinFETs.
From Fig. 7(a), we see that, during the ON state (VGFS = Symm-G SG-mode n-FinFET [Fig. 4(a)], resulting in a
VGBS = 1 V, VDS = 1 V), the electrostatic potential dis- reasonably high drain current. This is also indicated by the
tribution in an a-SG-mode n-FinFET approaches that of a volume inversion in the fin [Fig. 7(c)]. In the OFF state
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1979

−2 −5
10 x 10 SG−mode
68% I reduction w.r.t SG−mode 14
ON a−SG−mode
IG−mode
−4
10 12

10
−6
10

ION (A)
IDS (A)

8
−8
26% ION reduction w.r.t SG−mode
10
6
a−SG−mode (V =V )
GBS GFS
−10 415X
10 IG−mode (V = −0.2V) 4
GBS
15X
SG−mode (VGBS = VGFS)
−12
2
10 0.02 0.022 0.024 0.026 0.028 0.03
0 0.2 0.4 0.6 0.8 1 LG (μm)
V (V)
GFS
(a)
Fig. 8. IDS versus VGFS for an a-SG-mode n-FinFET (VDS = 1 V), with x 10
−4

corresponding curves for SG-mode and IG-mode n-FinFETs. 1.4

−2
10 1.2
88% ION reduction w.r.t SG−mode
1
−4
41% ION reduction w.r.t SG−mode
10
(A)
0.8
ON

−6
10 0.6
I
(A)

0.4
DS

SG−mode
I

−8
10
0.2 a−SG−mode
IG−mode
SG−mode (VGBS = VGFS)
−10
10 0
IG−mode (V = 0.2V) 175X 0.006 0.008 0.01 0.012 0.014
GBS
a−SG−mode (V =V T (μm)
GBS GFS SI
5X
−12
10 (b)
−1 −0.8 −0.6 −0.4 −0.2 0 −5
V (V) x 10
GFS 16 SG−mode
a−SG−mode
Fig. 9. IDS versus VGFS for an a-SG-mode p-FinFET (|VDS | = 1 V), with 14 IG−mode
corresponding curves for SG-mode and IG-mode p-FinFETs.
12

[Fig. 7(b) and (d)], the energy bands bend strongly near the
ION (A)

10
front-gate side (as GF = 4.8 eV), thereby raising the barrier
for electrons. The electrostatic potential/electron density dis- 8
tributions are qualitatively identical to those observed in the
Symm-G IG-mode FinFETs in the OFF state in Fig. 5(b) and 6
(d), respectively. Therefore, Asymm-G FinFETs combine the
advantages offered by Symm-G SG- and IG-mode FinFETs. 4
Fig. 8 quantifies the above, showing that Symm-G SG-
2
mode (IG-mode) n-FinFETs have 415× (15×) higher leakage 4 6 8 10 12
current compared to a-SG-mode devices at 300 K. Fig. 9 shows LUN (μm) −3
x 10
that Symm-G SG-mode (IG-mode) p-FinFETs have 175× (c)
(5×) higher leakage than a-SG-mode p-FinFETs.
Fig. 10. (a) ION versus L G . (b) ION versus TSI . (c) ION versus L UN .
ION characteristics versus variations in L G , TSI , and L UN .
B. Effect of Device Parameter Variations
We also investigated the effect of variations in the para- almost linearly with an increase in L G . ION increases linearly
meters L G , TSI and L UN on ION and IOFF . Fig. 10(a) shows with an increase in TSI in Fig. 10(b), with higher slopes
that in SG/a-SG-mode and IG-mode FinFETs, ION decreases for SG/IG-mode FETs in comparison to a-SG-mode FETs.
1980 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

Fig. 10(c) shows that ION in SG-mode FETs is very sensitive 0.02
to reduction in L UN , followed by IG-mode FETs, while
a-SG-mode FETs are relatively immune to changes in L UN . 0

/1 nA)
IOFF , on the other hand, is greatly affected by all three
parameters. Fig. 11(a) shows that IOFF in SG/IG-mode devices
has an exp(k/L G ) dependence, while a-SG-mode FETs show −0.02

OFF
a stronger exp(k1 /L G + k2 L G ) dependence, where k, k1 ,

(I
10
and k2 are constants. Fig. 11(b) shows that IOFF has an −0.04

LG log
exp(k1 /L G + k2 L G ) dependence in all cases, with different
values for k1 and k2 for each device. IOFF appears to roughly SG−mode
have an exp(k1 L 2UN + k2 L UN ) dependence on L UN in all cases −0.06
a−SG−mode
in Fig. 11(c). IG−mode
−0.08
0.02 0.022 0.024 0.026 0.028 0.03
C. Effect of Gate-Workfunction Fluctuations L (μm)
G
Since metal-gate FET Vth s are linearly dependent on (a)
the gate workfunction, we studied the effect of work- 0.015
function fluctuations on IOFF (or ILEAK ) in n-FinFETs. SG−mode
In [4], gate workfunction variation is shown to be the 0.01 a−SG−mode
major contribution to Vth variation in comparison to L G

TSI log10 (IOFF/1 nA)


IG−mode
and TSI , which have minor contributions. Using a quasi- 0.005
Monte Carlo (QMC) sample generator, we performed QMC
0
3-D device simulations, varying G for SG/a-SG/IG-mode
n-FinFETs with σG = 50 meV, and limited the total sample −0.005
count to 100 on account of the prohibitively large runtimes
for 3-D device simulation. Fig. 12 shows the ILEAK distribu- −0.01
tions, with a-SG-mode devices maintaining lower/comparable
spreads with respect to SG/IG-mode FinFETs. The above −0.015
investigation into parametric dependences with respect to
−0.02
L G , TSI , and L UN and variation analysis based on gate- 0.006 0.008 0.01 0.012 0.014
workfunction fluctuations suggest that a-SG-mode FinFETs T (μm)
SI
are likely to be very robust to process variations. (b)

1 SG−mode
D. Effect of Temperature on Leakage a−SG−mode
0.5 IG−mode
Fig. 13 suggests that the ILEAK advantage in topologies
having SG- and IG-mode FinFETs would reduce relative to
(IOFF/1 nA)

0
those of only SG-mode FinFETs with an increase in tem-
perature. Also, a-SG-mode devices have two (one) orders of −0.5
magnitude lower IOFF than Symm-G SG-mode (IG-mode)
FinFETs. −1
10
log

−1.5
IV. S YMMETRIC -G AND A SYMMETRIC -G FinFET
L OGIC G ATES −2
A significant problem with logic circuits implemented in
high-performance process technologies is the relatively high −2.5
4 6 8 10 12
leakage current that is concomitant with the high ON-state LUN (μm) −3
x 10
current. Hence, circuit topologies with low leakage that do (c)
not compromise on performance constitute the optimal design
points. In this section, we explore the design space of Symm- Fig. 11. (a) IOFF versus L G . (b) IOFF versus TSI . (c) IOFF versus L UN .
G FinFET INV and NAND2 gates in detail to determine the IOFF characteristics versus variations in L G , TSI , and L UN .
most versatile topologies that can arise by mixing Symm-G
SG- and IG-mode FinFETs.
in practical timeframes. Also, transient simulations, which
are necessary to capture logic element delays, are extremely
A. 3-D Versus 2-D Device Simulation cumbersome to perform via 3-D device simulation on account
Owing to the prohibitively high computational costs of which device simulations on a 2-D structure (corresponding
involved in single-FET 3-D transport simulations, mixed- to a slice of the 3-D FinFET device) are used hereafter.
mode 3-D device simulations for FinFET circuits is intractable Since 2-D simulations do not fully capture all physical effects
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1981

0.6
33%
0.4

DS, 3D
0.2
a−SG

)/I
24% −4.3%

DS, 3D
IG 0
SG 4.5%

−I
−0.2
−11.2%

DS, 2D
−0.4
SG−mode

(I
−0.6 IG−mode
a−SG−mode
−0.8
0 0.2 0.4 0.6 0.8 1
VGFS (V)

Fig. 14. Fractional error in IDS versus VGFS for 2-D/3-D device simulations.
Fig. 12. ILEAK distribution for a-SG/SG/IG-mode n-FinFETs under gate
workfunction fluctuations. σG = 50 meV.

−7
10

−8
10
104X

−9
8X
10
IOFF (A)

(a) (b) (c) (d)


640X
−10
10 Fig. 15. INV gates. (a) SG. (b) LP. (c) IGn. (d) IGp.

−11 a−SG−mode n/p-FinFETs with a highly compact layout, as shown in


10
SG−mode
18X
Fig. 16(a). In the LP-INV configuration [Fig. 15(b)], the back
IG−mode (VGBS = −0.2V)
gate of PA (NA) in the pull-up (pull-down) network is biased
−12
10
280 300 320 340 360 380 400
to VHIGH (VLOW ), necessitating a complex layout [Fig. 16(b)]
Temperature (K) with 36% larger area than size X2 SG-INV, while IGn-INV
[Fig. 16(c)] and IGp-INV [Fig. 16(d)] occupy the same area
Fig. 13. IOFF versus temperature for an a-SG-mode n-FinFET, with as LP-INV, owing to the multifin IG-mode FinFET back-gate
corresponding curves for SG-mode and IG-mode n-FinFETs.
contacts. Amongst NAND2 gates [Figs. 17 and 18], while SG-
NAND 2 has the most compact layout [Fig. 19(a)], LP- NAND 2
[Fig. 19(b)] occupies 27% more area than size X2 SG- NAND2,
(e.g., corner effect [17]) on carrier transport, we computed with a staggered pull-up network of parallel FinFETs, and
the error percentage from the drain currents, (I D S,2- D − shared back-gate contacts for the series pull-down FinFETs.
I D S,3-D )/I D S,3-D versus VGFS from 2-D/3-D device simula- Mixed-terminal (MT-) NAND2 [18] is identical to LP-NAND2
tions [Fig. 14]. In general, 2-D device simulation overpredicts in area, with NB in SG mode [Fig. 17(c)]. IG- and IG2-
IOFF and underestimates ION with respect to corresponding NAND 2 combine the parallel FinFETs of the pull-up network
3-D simulations. Also, a-SG-mode devices have relatively into a single p-FinFET, whereby the layout area is the same as
large differences between 2-D and 3-D simulations in the SG-NAND2. XT-NAND2 is a variant of MT-NAND2, with both
subthreshold regime, in comparison to SG/IG-mode devices. FinFETs of the pull-down network in SG mode and identical
However, IOFF and ION predictions are marginally different layout area (not shown). XT2- NAND2 is also a variant of
(within 33% for IOFF and 11.2% for ION ), suggesting that MT-NAND2, with both parallel FinFETs of the pull-up network
reasonably accurate comparisons can be made with mixed- in SG mode, which enables a compact layout [Fig. 19] with
mode 2-D device circuit simulations. the same area as SG-NAND2.
Fig. 20(a) and (b) show Asymm-G -based SG-mode
FinFET INV and NAND2 gates. (Note that any Symm-G -
B. Symm-G and Asymm-G Logic Gates based FinFET logic gate schematic/layout can be converted
Fig. 15 shows four possible INV configurations with to the corresponding Asymm-G version by replacing the
SG/IG-mode FinFETs: SG-, low-power (LP-) [7], IGn-, and devices with no layout overheads.) For generalized pull-up
IGp-INV. The SG-INV configuration has only SG-mode and pull-down networks, it is possible to mix Asymm-G
1982 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

(a) (b) (c) (d)

Fig. 16. INV layouts. (a) SG (size X2). (b) LP (size X1). (c) IGn (size X1).
(d) IGp (size X1).
(a) (b) (c)

Fig. 19. NAND 2 layouts. (a) SG (size X2). (b) LP (size X1). (c) XT2
(size X1).

(a) (b) (c)

Fig. 17. NAND 2 gates. (a) SG. (b) LP. (c) MT.

(a) (b) (c)

Fig. 20. Asymm-G SG-mode FinFET gates. (a) a-SG-INV.


(b) a-SG-NAND2. (c) a-SG-NAND2S.

TABLE II
S TANDARD C ELL FinFET INV C HARACTERISTICS , VLOW = −0.2 V AND
VHIGH = 1.2 V

Topology SG LP IGn IGp


Area (w.r.t to SG) 1 1.36 1.36 1.36
Avg. ILEAK (nA) 2.51 0.12 0.33 2.31
(a) (b)
t p (ps) 3.31 12.15 5.55 9.66

C. Leakage–Delay Characteristics: Symm-G Logic


Table II and Fig. 21 show the leakage–delay characteristics
of the Symm-G FinFET INV standard cells. The leakage
current ILEAK is an average over all input vectors, and delay
t p is the fanout-of-four (FO4) delay. All comparisons below
are drawn with respect to SG-INV (size X2), as it is the largest
SG-INV that can be accommodated for the chosen standard
cell height.
(c) (d) In Fig. 21, VHIGH and VLOW are varied (if permitted by
the topology), in order to sweep the design space. SG-INV
Fig. 18. NAND 2 gates. (a) IG. (b) IG2. (c) XT. (d) XT2.
(size X2) has the smallest delay t p = 3.31 ps, with the
largest average ILEAK [SG-INV (size X1) was found to have
t p = 5.75 ps]. LP-INV shows over an order of magnitude
FinFETs for leakage reduction with Symm-G FinFETs for reduction in mean ILEAK with a 267% (111%) increase in t p
speed. This strategy was applied to the NAND2 gate to yield with respect to SG-INV size X2 (size X1). From Fig. 21, it
the NAND2S gate shown in Fig. 20(c). is clear that the dominant factor affecting t p , for the current
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1983

Fig. 22. Leakage–delay spectrum for FinFET NAND2 configurations.


Fig. 21. Leakage–delay spectrum for FinFET INV configurations.

TABLE III
S TANDARD C ELL FinFET NAND 2 C HARACTERISTICS

Topology SG LP MT IG IG2 XT XT2


Area (w.r.t to SG) 1 1.27 1.27 1 1 1.27 1 to higher falling delay, t p H L , (owing to a slower pull-
Avg. ILEAK (nA) 2.76 0.15 1.05 2.76 1.16 2.72 1.16 down stack). However, decreasing VLOW enables over 50%
t p (Toggle A) (ps) 5.47 22.60 20.80 8.77 11.40 17.50 8.04 reduction in average ILEAK . XT2-NAND2 presents a similar
t p (Toggle B) (ps) 5.07 22.82 19.66 8.56 10.26 18.17 7.01 tradeoff in average ILEAK reduction, with the benefit of lower
t p (Toggle AB) (ps) 4.41 15.33 13.66 4.41 6.85 10.50 6.85 t p L H , owing to a fast parallel SG-mode pull-up. Overall,
XT2-NAND2 lies closest to SG- NAND2 in the leakage–delay
spectrum, offering the best way to leverage back-gate biasing
choice of Gn and Gp , is VHIGH . For IGp-INV, lowering to reduce average ILEAK without a significant degradation in
VHIGH increases t p and only marginally reduces average delay.
ILEAK . For LP-INV, varying VLOW (with VHIGH = 1.2 V) We see from Table III that, unlike traditional planar
presents a lower slope on the leakage–delay plot in comparison bulk CMOS NAND2 gates, t p (Toggle A) ≥ t p (Toggle B)
to varying VHIGH (with VLOW = −0.2 V), which reaffirms for many of the FinFET logic styles [e.g., Figs. 23(a) and
the above. IGn-INV appears to provide the best leakage– 24(a)]. This is dependent on the input slew rate, intermediate
delay tradeoff, with upto an order of magnitude reduction in node capacitance (CINT )/node voltage (VINT ) of the pull-
average ILEAK at the cost of 66% increase in t p with respect down stack, output load capacitance (COUT ), and modes of
to SG-INV (size X2) and marginally better t p than SG-INV FinFET operation in the logic gate. In Figs. 23(a) and 24(a),
(size X1). the transient behavior of SG-NAND2 is shown, with VGFS
Table III and Fig. 22 show the leakage–delay spectrum for across FinFET NA rising slightly faster for the Toggle B
the various FinFET NAND2 gates. All comparisons below are condition in comparison to Toggle A. Hence, t p (Toggle A) >
drawn with respect to SG-NAND2 (size X2), as it is the largest t p (Toggle B). This is exacerbated in XT2- NAND2 [Fig. 24(a)
SG-NAND2 that can be accommodated in the chosen standard and (b)], as VINT does not rise to VDD when VOUT =
cell height. In Fig. 22, LP-NAND2 (VLOW = −0.2 V, VHIGH = V A = VDD , owing to the IG-mode FinFET NA, which loses
1.2 V) shows over an order of magnitude reduction in mean gate drive very quickly when VINT increases, and VGFS is
cell leakage with around 4× higher t p in comparison to SG- nonzero in the dc condition. The latter, along with the fact
NAND 2. Varying VHIGH presents a steep slope in the leakage– that CINT  COUT (CINT mainly consists of source/drain–
delay plot for our choice of Gp and Gn , suggesting that body depletion capacitances which are negligible in Fin-
pull-up FinFETs should be in SG mode. This is also seen for FETs), helps VGFS develop very quickly across NA in the
XT-NAND2 and MT-NAND2 gates, where varying VHIGH could Toggle B condition in comparison to Toggle A [Fig. 24(b)].
only increase delay and does not decrease the average ILEAK . From the above analysis, introducing a single IG-mode
IG-NAND2 does not gain in average ILEAK in spite of com- n-FinFET in the pull-down series stack with only SG-mode
bining the parallel pull-up FinFETs into a single p-FinFET. p-FinFETs in the pull-up network, as with XT2-NAND2,
Instead, the rising delay, t p L H , degrades for IG-NAND2, which appears to be the best method to leverage the leakage–delay
increases t p . IG2-NAND2 has a larger t p compared to tradeoff using back-gate biasing in high-performance Symm-
IG-NAND2 over the entire spectrum of VLOW variation due G FinFET standard cells.
1984 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

1.2 1.2

1 1

0.8
0.8

Voltage (V)
Voltage (V)

0.6
0.6 VA, VB
V ,V
A B
VOUT, Toggle A VOUT, Toggle A
0.4
0.4 V , Toggle B
VOUT, Toggle B OUT

0.2 VINT, Toggle A


VINT, Toggle A
0.2 V , Toggle B
VINT, Toggle B INT
0
0
−0.2
0 1 2 3 4 5 6
−0.2 Time (s) x 10
−10
0 1 2 3 4 5 6
Time (s) −10 (a)
x 10
(a) 1.2
1.2 Toggle A, B=1
1 Toggle B, A=1
Toggle A, B=1

VGFS (V), FinFET NA


1 Toggle B, A=1 0.8
VGFS, FinFET NA

0.8
0.6

0.6
0.4

0.4
0.2

0.2
0

0
−0.2
0 1 2 3 4 5 6
−0.2 Time (s) x 10
−10
0 1 2 3 4 5 6
(b)
Time (s) −10
x 10
(b)
Fig. 24. XT2-NAND2 transient charactertistics. Input rise time has been
increased from 10 to 50 ps to improve visibility. (a) Node voltages, and
Fig. 23. SG- NAND2 transient charactertistics. Input rise time has been (b) VG F S on FInFET NA.
increased from 10 to 50 ps to improve visibility. (a) Node voltages, and
(b) VG F S on FInFET NA.

V. S YMMETRIC -G AND A SYMMETRIC -G FinFET


D. Leakage–Delay Characteristics: Asymm-G Logic L ATCHES AND F LIP - FLOPS

Fig. 25 shows the leakage–delay characteristics of the Next, we investigate simple latches and flip-flops that lever-
Asymm-G gates compared to their corresponding Symm- age combinations of Symm-G and Asymm-G FinFETs,
G SG-mode counterparts as well as IGn-INV and using insights from earlier sections. We modified four tem-
XT2-NAND2 gates, which were the best Symm-G gates. plate configurations, namely, the brute-force transmission gate
a-SG-INV gates are 60% slower than their SG-INV coun- [TGL, Fig. 26(b)] and half-swing clocked FinFET latches
terparts, with average leakage that is 238× lower, while [HSL, Figs. 27 and 28], and the corresponding flip-flops
a-SG-NAND2 gates are 65% slower than SG-NAND2 gates, [TGF, Fig. 27 and HSF, Fig. 28], in order to demonstrate the
with 235× lower leakage. (a-SG- NOR2, a-SG-XOR2, and importance of choosing the appropriate kinds of FinFETs to
a-SG-XNOR2) gates had (234×, 206×, and 234×) lower optimize leakage, propagation delay, and setup time.
average leakage compared to (SG-NOR2, SG-XOR2, and SG- Tables IV and V show the various possible cases of interest
XNOR2) with (34%, 20%, and 10%) higher delay, respectively. for TGL, TGF, HSL, and HSF using SG-, a-SG-, and IG-mode
The NAND2S gate, which introduces a Symm-G SG-mode FinFETs along with their fin counts. TGL1 and TGF1 have
n-FinFET to reduce delay, has SG- NAND2-like leakage for the only SG-mode FinFETs, which necessitates a larger I 1 gate in
“10” vector, thereby increasing overall average ILEAK . From order to overcome I 3 and force the data into the cross-coupled
Fig. 25, it is also clear that the best IG-mode configurations inverter configuration. TGL2 and TGF2 employ a-SG-mode
such as IGn-INV and XT2-NAND2 are not as well placed as FinFETs to implement a weaker I 3 gate, hence, permitting a
their a-SG-mode counterparts in the leakage–delay spectrum. smaller I 1 gate. By replacing I 1/I 2 with a-SG-mode FinFETs
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1985

−12 TABLE IV
x 10
14 TG L ATCH AND F LIP -F LOP C ASES , xPyN = x-fin p-FinFET, y-fin
SG−XOR2 n-FinFET, T2 = SG(1P1N)
a−SG−XOR2
12
Case I 1/I 2 I3 T1 I4 I5 I6
a−SG−NOR2
Average FO4 delay (s)

TGL1 SG SG SG - - -
10
XT2−NAND2 4P2N/2P1N 1P1N 2P2N - - -
a−SG−NAND2S SG−NOR2 TGL2 SG a-SG SG - - -
8 a−SG−NAND2
TGL3 a-SG a-SG SG - - -
IGn−INV
SG−NAND2 TGL4 SG IG SG - - -
6 2P1N/2P1N 1P1N 1P1N - - -
a−SG−XNOR2
TGF1 SG SG SG SG SG SG
4 SG−XNOR2
a−SG−INV 4P2N/2P1N 1P1N 2P2N 1P1N 1P1N 2P1N
SG−INV
TGF2 SG a-SG SG SG a-SG SG
2 −11 −10 −9 −8 TGF3 a-SG a-SG SG a-SG a-SG a-SG
10 10 10 10
Average I (A) TGF4 SG IG SG IG IG SG
LEAK
2P1N/2P1N 1P1N 1P1N 1P1N 1P1N 2P1N
Fig. 25. Leakage–delay spectrum for Asymm-G FinFET logic gates.

For the HS latches and flip-flops, HSL1 and HSF1 constitute


the base cases with only SG-mode FinFETs. A half-swing
clock is employed, which toggles between 0 and VDD /2,
thereby reducing dynamic clock power dissipation consider-
ably. However, the switched clock load capacitance doubles,
as N1–N7 are sized-up to two fins to be able to flip the
cross-coupled inverters. Therefore, the effective clock power
dissipation is halved with respect to TG configurations using
(a) (b)
T 1/T 2 gates with single-fin FinFETs. (HSL2, HSL3, HSL4)
Fig. 26. FinFET latch templates. (a) TG latch (TGL). (b) HS latch (HSL). and (HSF2, HSF3, HSF4) introduce a-SG-mode FinFETs at
all possible locations except N1, N3, and N7, which are
driven by the half-swing clock. HSL5 and HSF5 use IG-
mode FinFETs (with n-FinFET back gate tied to ground and
p-FinFET back gate tied to VDD ) for I 1/I 2 and I 3/I 4. This
carries over to HSL6 and HSF6 as well, but N2/N4/N5/N6
are a-SG-mode FinFETs. With respect to layout area, all
Fig. 27. TG flip-flop (TGF).
versions of TGL occupy the same area with standard cell
height consisting of four fins for the p-FinFETs and two fins
for the n-FinFETs. The same is true for all versions of TGF,
HSL, and HSF.
Both TGFs and HSFs are negative edge-triggered, for TGL
and TGF configurations, when the clock is high, data value D
is forced into I 2/I 3 through T 1, while T 2 is off and I 4/I 5
are in the hold mode. When the clock goes low, T 1 shuts off
and T 2 forces the value at the output of I 2 into I 4/I 5 for
TGF. In HSL (HSF) configurations, when both clock and D
are high, Q B (I N B) is pulled low, forcing Q (I N) high. For
HSF, when the clock goes low, N7 is active, and depending
on the polarity of I N and I N B, Q is pulled either low or
high.
Fig. 28. HS flip-flop (HSF). Table VI shows the hold static noise margins of the
cross-coupled inverter pairs used in Tables IV and V. a-SG
(1P1N) outperforms the rest of the configurations, including
as well, TGL3 and TGF3 push the limits of operation. TGL4 IG (1P1N), suggesting that a-SG-mode FinFETs are ideal for
and TGF4 use IG-mode FinFETs (with n-FinFET back gate keeper inverters in latches/flip-flops as well.
tied to ground and p-FinFET back gate tied to VDD ) to Quasistationary/dc simulations were used to measure
weaken I 3. average leakage over all possible legal combinations of
1986 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2013

TABLE V −9
x 10 HSF1
HS L ATCH AND F LIP -F LOP C ASES , xPyN = x-fin p-FinFET, y-fin 8 HSF5
n-FinFET, N1/N3/N7 = SG(2N), I5 = SG(2P1N)
7
Case I 1/I 2 N 2/N 4 I 3/I 4 N 5/N 6
HSL1 SG SG - - 6
HSL2 SG a-SG - - TGF1 HSF2 HSF4 HSF6
HSL3 a-SG SG - -

Average ILEAK (A)


5
HSL4 a-SG a-SG - - TGF4

HSL5 IG SG - -
4
HSL6 IG a-SG - - TGF2
1P1N/1P1N 2N/2N - - HSF3
3
HSF1 SG SG SG SG
HSF2 SG a-SG SG a-SG
HSF3 a-SG a-SG a-SG a-SG 2

HSF4 a-SG SG a-SG SG


HSF5 IG SG IG SG 1 TGF3
HSF6 IG a-SG IG a-SG
1P1N/1P1N 2N/2N 1P1N/1P1N 2N/2N 0
1 2 3 4 5 6 7 8 9 10

TABLE VI Fig. 30. Average ILEAK for FinFET flip-flops.


H OLD S TATIC N OISE M ARGINS , xPyN = x-fin p-FinFET, y-fin n-FinFET
−11

INV1 INV2 SNM (mV) 3.5 x 10


TGL3
(SG, 2P1N) (SG, 1P1N) 310 HSL4 HSL5 HSL6
(SG, 1P1N) (SG, 1P1N) 315 HSL3
3
(SG, 2P1N) (IG, 1P1N) 325
(a-SG, 2P1N) (SG, 1P1N) 320
Average propagation delay (s)

(a-SG, 2P1N) (a-SG, 1P1N) 375 2.5


TGL2
(a-SG, 1P1N) (a-SG, 1P1N) 400
(IG, 1P1N) (IG, 1P1N) 375 2
TGL1
−9 TGL4 HSL2
x 10 HSL1 1.5 HSL1
6

1
5
HSL2

0.5
HSL5
4
TGL1
(A)

HSL6 0
LEAK

1 2 3 4 5 6 7 8 9 10
3 HSL3
Average I

TGL4 Fig. 31. Average propagation delay for FinFET latches.


HSL4
TGL2
2
lower leakage compared to HSL1. From Fig. 30, TGF3 and
HSF3 can be seen to follow similar trends. The introduction
1
TGL3
of IG-mode FinFETs results in a marginal reduction in
average leakage in (TGL4, TGF4), (HSL5, HSF5), and
(HSL6, HSF6).
0
1 2 3 4 5 6 7 8 9 10 Propagation delay was averaged for 1 → 0 as well
as 0 → 1 transitions, assuming an output load of four
Fig. 29. Average ILEAK for FinFET latches. size-X1 SG-INVs for both latches and flip-flops. From Fig. 31,
TGL3 can be seen to have nearly 2× larger delay compared
to TGL1 owing to the weaker a-SG-mode FinFETs. Similar
input/output vectors and internal states. From Fig. 29, TGL3, observations hold good for (HSL1, HSL2) and (HSL3–HSL6).
which employs a-SG-mode FinFETs (except for T 1), can be However, from Fig. 32, TGF3 and TGF1 can be seen to have
seen to have over 10× lower leakage than TGL1. Similarly, almost identical delays. This is due to the fact that forcing
HSL4, with mostly a-SG-mode FinFETs, has nearly 3× data into I 4/I 5 in TGF1, when the clock is low, is harder
BHOJ AND JHA: LOGIC GATES AND FLIP-FLOPS DESIGN IN HIGH-PERFORMANCE FinFET TECHNOLOGY 1987

−11
x 10 mode FinFET configuration, owing to the large I 1 data-
6
forcing inverter. (TGF2, TGF3) and (HSF3, HSF4) have
TGF4
considerably larger setup times, as they employ weaker
5 TGF3 a-SG-mode FinFETs. Similar trends were also observed for
TGF1 HSF5 HSF6 latches.
In summary, (TGF3, HSF3), which are implemented using
Average propagation delay (s)

HSF3 HSF4
4 a combination of a-SG-mode and SG-mode FinFETs, have the
best tradeoffs in leakage, delay, and setup time for (TG, HS)
HSF1 HSF2
TGF2
flip-flop configurations.
3
VI. C ONCLUSION
Unlike prior fragmented approaches to FinFET
2 logic/sequential circuit design, in this paper, we evaluated
Symm-G SG/IG-mode FinFETs and Asymm-G SG-mode
FinFETs head to head in a high-performance process. We
1 also investigated the design space of logic gates, latches, and
flip-flops employing them in a unified manner, which resulted
in the following key insights.
0 1) Asymm-G SG-mode FinFETs with high-performance
1 2 3 4 5 6 7 8 9 10
targets provide very steep subthreshold slopes, ultralow
Fig. 32. Average propagation delay for FinFET flip-flops. off-currents, and reasonably high ON-currents in
comparison to Symm-G SG/IG-mode FinFETs, and
−11

3.5
x 10 maintain their advantage at high temperature. This sug-
HSF3 gests that they could be widely used (in combination
HSF4 with Symm-G SG-mode FinFETs when necessary)
3 in off-critical paths, with the same layout as Symm-
G SG-mode devices and without the routing and
TGF2 HSF2
2.5 HSF1 process-related problems of integrating IG-mode back-
TGF3 HSF6
HSF5 gate biased devices.
Setup time (s)

2) While it is possible to trade off leakage versus delay


2
TGF1 TGF4 using IG-mode FinFETs, indiscriminate use of back-
gate biasing could impact area, performance, and leak-
1.5 age, as IG-mode devices need extra area to land
back-gate contacts and have degraded subthreshold
1 slopes. In this regard, using a single IG-mode device
at the top of a series stack is sufficient to reduce
leakage considerably without too much degradation
0.5
in delay.

0
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[9] A. Datta, A. Goel, R. T. Cakici, H. Mahmoodi, D. Lakshmanan, and in 1982, and the Ph.D. degree in electrical engi-
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Princeton University, Princeton, NJ. He has co-
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Proc. Int. Symp. Qual. Electron. Design, Mar. 2008, pp. 311–316. He has authored 12 book chapters. He has authored or co-authored more
[12] J. Kedzierski, D. M. Fried, E. J. Nowak, T. Kanarsky, J. H. Rankin, than 390 technical papers. He has co-authored 14 award-winning papers. He
H. Hanafi, W. Natzle, D. Boyd, Y. Zhang, R. A. Roy, J. Newbury, C. holds 13 U.S. patents. He has given several keynote speeches in the area of
Yu, Q. Yang, P. Saunders, C. P. Willets, A. Johnson, S. P. Cole, H. nanoelectronic design and test. His current research interests include FinFETs,
E. Young, N. Carpenter, D. Rakowski, B. A. Rainey, P. E. Cottrell, low power hardware/software design, computer-aided design of integrated
M. Ieong, and H.-S. P. Wong, “High-performance symmetric-gate and circuits and systems, digital system testing, and secure computing.
CMOS-compatible Vt asymmetric-gate FinFET devices,” in Proc. Int. Dr. Jha is a fellow of ACM. He has served as the Editor-in-Chief of the IEEE
Electron. Device Meeting, 2001, pp. 19.5.1–19.5.4. T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI) S YSTEMS
[13] L. Mathew, M. Sadd, B. E. White, A. Vandooren, S. Dakshina-Murthy, and an Associate Editor of the IEEE T RANSACTIONS ON C IRCUITS
J. Cobb, T. Stephens, R. Mora, D. Pham, J. Conner, T. White, Z. Shi, A. AND S YSTEMS –I: R EGULAR PAPERS and the IEEE T RANSACTIONS ON
V.-Y. Thean, A. Barr, M. Zavala, J. Schaeffer, M. J. Rendon, D. Sing, C IRCUITS AND S YSTEMS –II: E XPRESS B RIEFS , the IEEE T RANSACTIONS
M. Orlowski, B.-Y. Nguyen, and J. Mogab, “FinFET with isolated n+ ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS
and p+ gate regions strapped with metal and polysilicon,” in Proc. Int. the IEEE T RANSACTIONS ON V ERY L ARGE S CALE I NTEGRATION (VLSI)
SOI Conf., Nov. 2003, pp. 109–110. S YSTEMS , and the Journal of Electronic Testing: Theory and Applications.
[14] A. N. Bhoj and N. K. Jha, “Design of ultra-low-leakage logic gates and He is currently serving as an Associate Editor of the IEEE T RANSACTIONS
flip-flops in high-performance FinFET technology,” in Proc. Int. Symp. ON C OMPUTERS , the Journal of Low Power Electronics, and the Journal
Qual. Electron. Design, Mar. 2011, pp. 1–8. of Nanotechnology. He has served as the Program Chairman of the 1992
[15] A. N. Bhoj and N. K. Jha, “Gated-diode FinFET DRAMs: Device and Workshop on Fault-Tolerant Parallel and Distributed Systems, the 2004
circuit design considerations,” ACM J. Emerg. Technol. Comput. Syst., International Conference on Embedded and Ubiquitous Computing, and the
vol. 6, no. 4, pp. 12:1–12:32, 2010. 2010 International Conference on VLSI Design. He has served as the Director
of the Center for Embedded System-on-a-Chip Design funded by the New
[16] D. Ha, H. Takeuchi, Y.-K. Choi, and T.-J. King, “Molybdenum gate
Jersey Commission on Science and Technology. He is a recipient of the
technology for ultrathin-body MOSFETs and FinFETs,” IEEE Trans.
AT&T Foundation Award and NEC Preceptorship Award for research excel-
Electron Devices, vol. 51, no. 12, pp. 1989–1996, Dec. 2004.
lence, the NCR Award for Teaching Excellence, and the Princeton University
[17] J. Colinge, FinFETs and Other Multi-Gate Transistors. New York: Graduate Mentoring Award. He was a recipient of the Best Paper Award
Springer-Verlag, 2008. at ICCD’93, FTCS’97, ICVLSID’98, DAC’99, PDCS’02, ICVLSID’03,
[18] M. Alioto, “Comparative evaluation of layout density in 3T, 4T, and MT CODES’06, ICCD’09, and CLOUD’10. His paper was selected for “The
FinFET standard cells,” IEEE Trans. Very Large Scale Integr. (VLSI) Best of ICCAD: A Collection of the Best IEEE International Conference
Syst., vol. 19, no. 5, pp. 751–762, May 2011. on Computer-Aided Design papers of the past 20 years,” two papers by IEEE
Micro Magazine as one of the top picks from the 2005 and 2007 Computer
Architecture Conferences, and two others as being among the most influential
papers of the last ten years at the IEEE Design Automation and Test in Europe
Conference. He has co-authored six other papers that have been nominated
Ajay N. Bhoj (S’07) received the B.Tech. degree for Best Paper Awards.
from the Indian Institute of Technology, Chennai,
India, in 2007, and the M.A. degree from Princeton
University, Princeton, NJ, in 2009, where he is
currently pursuing the Ph.D. degree, all in electrical
engineering.
His current research interests include interesting
problems in device modeling, simulation of multi-
gate transistors, SRAM/eDRAMs as well as low
power digital circuit design, and computer architec-
ture/VLSI implementations of architectural ideas.

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