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Construct a Common Emitter BJT amplifier using voltage divider bias and determine the
frequency response. Calculate the bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
2. Construct a Common Collector BJT amplifier using voltage divider bias and determine the frequency
response. Calculate the bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
3. Construct a Common Source FET amplifier and determine the frequency response.
Calculate the bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
4. Construct a Darlington amplifier using BJT and determine the frequency response.
Calculate the bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
5. Construct a Differential amplifier using BJT and determine the common mode gain,
differential mode gain and CMRR. (100)
7. Construct a Cascode amplifier and determine the frequency response. Calculate the bandwidth from
the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
8. Construct a Cascade amplifier and determine the frequency response. Calculate the bandwidth from
the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
9. Construct a Single stage amplifier and determine the frequency response. Calculate the
bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
10. Construct a multistage amplifier and determine the frequency response. Calculate the
bandwidth from the obtained frequency response. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
12. Design and implement Excess-3 to BCD code converter using logic gates and verify its
truth table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
13. Design and implement binary to gray code converter and gray to binary code converter
using logic gates and verify its truth table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
14. Design and implement 4-bit binary Adder / Subtractor using IC 7483. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
17. Design and implement 4x1 multiplexer and 1x4 de-multiplexer using logic gates and verify its truth
table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
18. Design and construct a 4 – bit binary ripple counter and verify its truth table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
19. Design and construct a 4 – bit mod-10 ripple counter and verify its truth table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
20. Construct a 3-bit synchronous up / down counter and verify its truth table. (100)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)
22. (i) Design and implement binary to gray code converter using logic gates and verify
its truth table. (50)
(ii) Design and implement gray to binary code converter using logic gates and verify
its truth table. (50)
Aim & Circuit Theory &
Design & Output Record Viva Total
Identification Diagram Procedure
verification (30) (10) (10) (100)
(10) (30) (10)