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Technology Chapter, SCV
REV A
Background on FOWLP
Benefits
Conventional fan-out
o WLCSP-type packaging for chips with high
IO count
o Excellent electrical properties and performance
o Smallest possible package form factor
o No custom substrate required First Generation eWLB
o Multi-chip and SIP applications
Challenges
Reliability, Yield, Cost
Brunnbauer, M. et. al., “Embedded Wafer Level Ball Grid Array (eWLB),”
Electronics Packaging Technology Conference 8th Proceedings, Dec. 2006.
www.cpmt.org/scv/ 1
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
www.cpmt.org/scv/ 2
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Package
Wafer Prep Panelization Fan-out
Finishing
Cu Stud Pattern and Die Attach to Carrier Polymer Coat, Panel Backgrind
Plate Pattern, Cure
Molding Backside Laminate
Backgrind RDL Pattern and
Carrier Removal Plate Laser Mark, Saw,
Singulation TnR
Panel Top Grind Polymer Coat,
Pattern, Cure
Die Location Meas.
UBM Pattern and
Plate
` `
Molding
Carrier Removal
MT
www.cpmt.org/scv/ 3
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Carrier Removal
Backgrind
Singulation
Chips placed face-up on release tape & carrier
Die Attach
Pl
Placement t accuracy can affect
ff t overlay,
l yield
i ld
Molding
Serial process -> significant costs
Carrier Removal
www.cpmt.org/scv/ 4
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Panelization – Molding
Cu Stud Pattern and
Plate
Requirements:
Backgrind
High silica filled mold compound
Singulation
No surface voids or incomplete molding
Die Attach to Carrier
Good adhesion of die to release tape
Molding
Carrier Removal
www.cpmt.org/scv/ 5
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Panelization – Molding
Carrier Removal
www.cpmt.org/scv/ 6
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Adaptive Patterning
www.cpmt.org/scv/ 7
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Adaptive Routing
Dynamically adapts Via1 and a portion of RDL pattern of each
individual package to align to the true position of each die
Via2, UBM and BGA pattern fixed with respect to package edge
1) C
Create
t a nominal
i l ffan- 2) O
Omitit a smallll portion
ti off th
the 3) C
Complete
l t th
the d
design
i
out RDL design RDL design near the die pads after measuring the true
(prestratum) position of each chip
www.cpmt.org/scv/ 8
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Adaptive Alignment
Entire RDL layer and Via1 shift to match die shift; misalignment is
effectively moved to the UBM stack
Via2, UBM and BGA patterns remain fixed with respect to package edge
Adaptive Alignment
Via2 slightly undersized;
via2 and bump Via1 and RDL patterns
locations held constant adapted for die shift
X spacing
Y spacing
p g
www.cpmt.org/scv/ 9
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
www.cpmt.org/scv/ 10
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Fan-out
Polymer Coat, Conventional build-up: polymer 1, RDL, polymer 2,
Pattern, Cure
UBM layers + ball drop and reflow
RDL Pattern and
Plate
Unique Adaptive Patterning design files facilitate good
overlay to chips and Cu studs
Polymer
o y e Coat,
Pattern, Cure Planar mold surface supports high density RDL wiring
UBM Pattern and Mold layer provides good inductor performance
Plate
Package Finishing
Panel Backgrind
Package finishing used to complete part
Backside Laminate
Optional backside laminate for fully encased structure
Laser Mark, Saw,
TnR
Semiconductor device
Mold compound
PCB
www.cpmt.org/scv/ 11
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
TC Results
www.cpmt.org/scv/ 12
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Initial production
300mm round
Summary
Advantages of chips face-up approach with Adaptive Patterning:
1) Low contact resistance to Al pads
2) Low chip attach costs
3) High
g yyields through
g mold and Via1 overlay
y
4) Tight ground rules
5) Fully protected die edge
6) Planar surface for fine pitch RDL
7) Good RF performance
8) Robust BLR
Challenges:
Minimizing wafer prep costs
Control of grind tolerances
www.cpmt.org/scv/ 13
Components, Packaging and Manufacturing October 14, 2015
Technology Chapter, SCV
Thank You
www.cpmt.org/scv/ 14