Homework Assignment 1, Due September 17th, 11:59 PM

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(1.a) Write two different Verilog descriptions at the gate level and dataflow level for Module g1 and
Module g2.
Module g1 Module g2
x3 x3
x2 y1
x2 y
x1 x1
x0 y0 x0

(1.b) Write a Verilog module at the structural level for the following Module g3. Verify your Module g3
design using a testbench and show the output waveforms for the following test vectors.
Module g3
a x3 x3 y z
abcdef = 000000 y1 x2
b x2 (Module g2)
abcdef = 111111 c x1 (Module g1) x1
abcdef = 010101 d x0 y2 x0
abcdef = 101010 e
f

(2) Write Verilog module(s) for a two-bit arithmetic logic unit (ALU). The ALU receives two inputs A and B,
each two bits (A=a1a0 and B=b1b0) and performs logical operations (AND, OR, XOR, NOT, shift left logical,
shift right logical) and unsigned addition and multiplication. The ALU multiplexes only one result from one
of the logical operations or arithmetic operations to the output. Write a testbench for your design. Verify
each operation of your ALU using the following test vectors.

a = 2’b00; b = 2’b00;
a = 2’b11; b = 2’b11;
a = 2’b01; b = 2’b10;

Submit the output waveform in addition to your source codes for the design and your testbench. Use
decimal representation for the signal values on your output waveform.

(3) The following block diagram shows an n-bit ripple carry adder implemented using n full-adders. Design
a four-bit ripple carry adder that receives two values “a” and “b”, each four bits, and generates a five-bit
output in Verilog HDL. Describe the adder at two different levels: gate-level and dataflow level. Write a
testbench for your adder and on the simulation output waveform show the value of “a” and “b” and the
two outputs “sumG” and “sumD”, which are the outputs of the gate-level and dataflow level descriptions,
respectively.

Verify your outputs using the following test vectors. Submit the output waveforms in addition to your
source codes for the design and your testbench.

These notes are copyrighted and are strictly for 2017 courses at SDSU. No part of this publication may be reproduced, distributed,
or transmitted.
a = 4’b0000; b = 4’b0000;
a = 4’b1111; b = 4’b1111;
a = 4’b1110; b = 4’b0111;
a = 4’b1010; b = 4’b0101;
a = 4’b0011; b = 4’b1100;
a = 4’b1010; b = 4’b0110;
a = 4’b1111; b = 4’b0001;
a = 4’b0000; b = 4’b1111;
a = 4’b0000; b = 4’b0001;

These notes are copyrighted and are strictly for 2017 courses at SDSU. No part of this publication may be reproduced, distributed,
or transmitted.