Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲 H83

1099-0062/2009/13共3兲/H83/4/$28.00 © The Electrochemical Society

Nonvolatile Memories with Dual-Layer Nanocrystalline ZnO

Embedded Zr-Doped HfO2 High-k Dielectric
Chen-Han Lin and Yue Kuo*,z
Thin Film Nano and Microelectronics Research Laboratory, Texas A&M University, College Station,
Texas 77843-3122, USA

Metal-oxide-semiconductor memory capacitors composed of dual-layer nanocrystalline ZnO embedded zirconium-doped hafnium
oxide high-k film were fabricated, characterized, and compared with those with the single-layer nanocrystalline ZnO embedded
sample. Distinct layers of discretely dispersed nanocrystalline dots embedded in the amorphous high-k matrix were observed. The
nanocrystalline ZnO dots trap many electrons. The dual-layer sample not only drastically increases the charge storage density but
also improves the charge trapping speed due to the coulomb blockade effect. This is a potentially important gate dielectric
structure for high density, high speed nonvolatile memories.
© 2009 The Electrochemical Society. 关DOI: 10.1149/1.3276055兴 All rights reserved.

Manuscript submitted October 5, 2009; revised manuscript received November 25, 2009. Published December 31, 2009. This was
paper 762 presented at the San Francisco, California, Meeting of the Society, May 24–29, 2009.

Recently, there have been reports on replacing the thermally Experimental

grown SiO2 with a high-k dielectric material as the tunnel and con-
trol dielectric layers in the floating-gate memory device to improve
the programming efficiency and charge retention time.1,2 In addition,
there are reports that the continuous polycrystalline silicon film in
the floating-gate dielectric could be replaced with nanocrystalline
silicon 共nc-Si兲 dots to minimize the charge loss due to the defective
thin tunnel dielectric layer.3,4 Among many high-k materials,
hafnium oxide 共HfO2兲 is promising for the gate dielectric applica-
tion due to its relatively large bandgap, good thermal stability, etc.5,6
Furthermore, the doped high-k thin film has many advantages over
the undoped high-k thin film, such as a higher amorphous-to-
polycrystalline transformation temperature, a thinner interface layer
共IL兲, a lower interface state density, and a larger breakdown
voltage.7-9 The zirconium-doped HfO2 共ZrHfO兲 high-k dielectric has
been prepared into sub-1-nm equivalent oxide thickness 共EOT兲 with
good dielectric properties.10 The electron barrier height between
ZrHfO and Si is lower than that between SiO2 and Si, i.e., 1.5 eV vs
3.5 eV, which favors the high data writing speed.1 Based on the
same EOT, the ZrHfO high-k film is a better tunnel dielectric than
SiO2 with respect to charge retention because the former has a
thicker physical thickness than the latter. For example, the nc-Si
embedded ZrHfO memory has a retention time greater than
10 years.2
In this study, the authors investigated the memory function of the
dual-layer nanocrystalline zinc oxide 共nc-ZnO兲 embedded ZrHfO
high-k dielectric capacitor. Because ZnO is a wide bandgap
共⬃3.3 eV兲 semiconductor with a large work function
共⬃4.5 eV兲,11,12 judged from the energy band diagram, it can en-
hance the charge trapping and retention capabilities when embedded
in the high-k film.13 ZnO can be prepared into the nanocrystalline
form for various electronic and optoelectronic applications.14,15 The
sputtered ZnO film is an n-type semiconductor containing many
defects, such as Zn interstitial 共Zni兲 and oxygen vacancy 共VO兲,
which may work as deep trapping sites, i.e., below the conduction
bandedge.16-18 Because there is a large conduction band offset be-
tween nc-ZnO and ZrHfO, i.e., ⬃2 eV, the nc-ZnO embedded
high-k dielectric could have a long charge retention time. Therefore,
this kind of film is potentially important for nonvolatile memory
applications. In principle, two nc-ZnO layers could trap more
charges than one nc-ZnO layer in the same dielectric film. However,
a floating-gate memory device composed of two layers of nc-ZnO
embedded in the high-k dielectric film has never been fabricated and
studied.
* Electrochemical Society Fellow.
z
E-mail: yuekuo@tamu.edu
Metal-oxide-semiconductor 共MOS兲 capacitors with single- and
dual-layer ZnO embedded ZrHfO gate dielectrics were prepared on
the p-type Si 共phosphorus doped at 1015 cm−3兲 wafer. All thin-film
layers were sequentially sputter deposited in a one-pump-down pro-
cess without breaking the vacuum. The ZrHfO layer was sputtered
from a Zr/Hf 共12/88 wt % 兲 target and the ZnO layer was sputtered
from a Zn target, both in a 1:1 Ar/O2 ambient at 60 W. For the
single-layer embedded structure, the ZrHfO 共tunnel
dielectric兲/ZnO/ZrHfO 共control dielectric兲 stack was deposited for
2/3/10 min, separately. For the dual-layer embedded structure, the
ZrHfO 共tunnel dielectric兲/ZnO/ZrHfO/ZnO/ZrHfO 共control dielec-
tric兲 stack was deposited for 2/3/5/3/5 min, separately. The post-
deposition annealing step was carried out with a rapid thermal an-
nealing 共RTA兲 process at 800°C under pure N2 ambient for 1 min.
The control sample, i.e., containing only ZrHfO gate dielectric with-
out any embedded layer, was also prepared under the same sputter-
ing 共for 12 min兲 and RTA conditions as those in preparing the ZnO
embedded samples. Aluminum 共Al兲 was sputter deposited and pat-
terned as the gate electrode and the back ohmic contact layer. The
complete capacitor was annealed at 300°C for 5 min under forming
gas 共10:90 H2 /N2兲. The dielectric stack was examined with a high
resolution transmission electron microscope 共TEM兲 共JEOL 2010兲.
Charge trapping characteristics were investigated using capacitance–
voltage 共C-V兲 measurements 共Agilent 4284A Precision LCR meter兲.
The flatband voltage 共VFB兲 of the capacitor was extracted from the
C-V curve using the NCSU CVC program.19
Results and Discussion
The cross-sectional TEM micrograph of the control sample is
shown in Fig. 1a. The ZrHfO film is amorphous. It contains two
amorphous ILs formed at the ZrHfO/Si 共IL1 ⬃ 3.5 nm兲 and
ZrHfO/Al 共IL2 ⬃ 1.8 nm兲 contacts. The former has a hafnium
silicate-like structure20 and the latter has an aluminum oxide-like
structure. Figure 1b shows the top-view TEM micrograph of the
single-layer nc-ZnO embedded ZrHfO film. The grain size of the
nanodot is 3–8 nm, and the two-dimensional spatial density is about
1.43 ⫻ 1012 cm−2. The nanodots are crystalline ZnO with 共100兲 ori-
entation detected by X-ray diffraction 共XRD兲, as shown in Fig. 1c.
The absence of crystalline ZrHfO peaks in the XRD pattern indi-
cates that the ZrHfO part is amorphous, which is consistent with the
TEM result shown in Fig. 1a. Figure 1d and e shows the cross-
sectional TEM micrographs of the single- and dual-layer ZnO em-
bedded ZrHfO stacks without the top Al gate layer, respectively. In
the single-layer embedded sample, discrete nanodots, as highlighted
in circles, are dispersed in the amorphous ZrHfO matrix. In the
dual-layer embedded sample, two layers of discrete nanodots are
observed, which is critical to memory functions such as charge leak-

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 H84 Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲
ing and retention characteristics.21 Assuming that the density of the
nc-ZnO dots in the cross-sectional view is proportional to that in the
top view, the density of the dual-layer nc-ZnO sample is about
2.38 ⫻ 1012 cm−2. The 3.7 nm thick amorphous hafnium silicate IL
formed between ZrHfO and Si has a low electron barrier height to
Si.22 Separately, the top amorphous Al2O3 IL has a large energy
barrier, i.e., ⬃2.9 eV, which makes it difficult to inject electrons
from the gate electrode to the dielectric layer or to leak electrons
from the trapped nc-ZnO site in the dielectric layer to the gate elec-
trode. The insets in Fig. 1d and e show that the nanodots in both
single- and dual-layer embedded samples have periodic lattice
fringes spacing about 0.28 nm, which corresponds to the ZnO共100兲
layer.
Figure 2 shows C-V curves of 共a兲 single- and 共b兲 dual-layer nc-
ZnO embedded samples before 共fresh兲 and after being stressed for
10 ms with a constant gate voltage 共Vg兲 of −8 or +8 V. The C-V
curves were measured at 1 MHz over a small voltage range, i.e.,
−2 to 1 V, so that the amount of charges introduced from the mea-
surement process is negligible. The −8 V stress condition induced a
hole-rich accumulation layer and the +8 V stress condition induced
an electron-rich inversion layer near the Si/high-k interface. Charges
that obtained enough energy could be injected into the gate dielec-
tric layer. The shift of the VFB of the sample’s C-V curve, i.e.,
⌬VFB = VFB共after stress兲 − VFB共fresh兲, represents the amount of
charges trapped due to the gate stress process. Because the control
sample has a negligible C-V shift under either a +8 or −8 V stress
condition, as shown in the inset of Fig. 2a, the contribution of the
ZrHfO part of the embedded sample to the total charge trapping is
minimum. Figure 2a and b shows that after a +8 V stress, the C-V
curve shifts to the positive direction in both single- and dual-layer
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Figure 1. 共a兲 Cross-sectional TEM micro-
graph of control sample. 共b兲 Top-view
TEM micrograph and 共c兲 XRD pattern of
the single-layer nc-ZnO embedded ZrHfO
film. Cross-sectional TEM micrographs of
共d兲 single- and 共e兲 dual-layer nc-ZnO em-
bedded ZrHfO stacks.
embedded samples, i.e., ⌬VFB = 0.43 and 0.98 V, separately, which
corresponds to electron trapping densities 共Qe’s兲 of 1.34 ⫻ 1012 and
3.06 ⫻ 1012 cm−2, separately. The latter is comparable to that of the
dual-layer nc-Si embedded SiO2 capacitor.23 Judging from the Qe of
the single-layer embedded sample and the nc-ZnO density, in aver-
age, each nc-ZnO dot stores about one electron, which is in the same
order of magnitude as that of nc-Si in SiO2.24,25 The increase in the
charge trapping density from the addition of the second embedded
layer is consistent with the increase in the number of the nc-ZnO
dots in the dielectric structure. Figure 2a also shows that after a
−8 V stress, the C-V curve of the single-layer embedded sample
slightly shifts to the negative direction, i.e., ⌬VFB = −0.15 V, which
indicates the trap of a small amount of holes. It is not contributed by
the ZrHfO part of the film, as shown in the inset of Fig. 2a. The low
hole trapping capability is probably related to nc-ZnO properties.
Defects, such as Zni and VO, in nc-ZnO are sub-conduction-band
trapping centers for electrons instead of holes.16-18 Therefore, only a
small portion of the injected holes were retained at the nc-ZnO site.
For the dual-layer embedded sample, the negative shift of the C-V
curve after a −8 V stress is negligible, as shown in Fig. 2b. Because
the dual-layer embedded sample has a thinner top control dielectric
layer than the single-layer embedded sample, as shown in Fig. 1a
and b, it may be easier to inject electrons from the Al electrode to
the dielectric film or to detrap holes from the nc-ZnO sites to the Al
electrode under the strong gate bias condition. However, more stud-
ies are required to verify the exact mechanism.
Figure 3 shows the C-V hysteresis curves of the control sample
and the two nc-ZnO embedded samples with the gate being swept
from −2 to + 8 V 共forward兲 and then back to −2 V 共backward兲.
The control sample shows very small C-V hysteresis corresponding
Figure 2. C-V curves of 共a兲 single- and
共b兲 dual-layer nc-ZnO embedded samples
stressed at −8 and +8 V for 10 ms. C-V
curve of control sample is shown in the
inset of 共a兲.
 Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲
Figure 3. C-V hysteresis curves of control, single-, and dual-layer nc-ZnO
embedded samples measured at 1 MHz.
to the negligible charge trapping capability of the ZrHfO film. Both
nc-ZnO embedded samples show counterclockwise hysteresis,
which is contributed by the large positive gate voltage, i.e., +8 V, at
the end of the forward sweeping condition. Electron trapping densi-
ties 共Qe’s兲 of 1.47 ⫻ 1012 and 3.06 ⫻ 1012 cm−2 were obtained for
the single- and dual-layer embedded samples, separately. This is
consistent with the result of Fig. 2 that the dual-layer embedded
sample traps much more electrons than the single-layer embedded
sample does under the +8 V stress condition. Separately, it was
observed that the memory window was enlarged with the increase in
the forward direction voltage. For example, for the dual-layer em-
bedded sample, the memory window ⌬VFB was increased from
0.12 V to 0.42 and 0.98 V when the end of the forward gate voltage
was increased from +4 V to +6 and +8 V, separately. Under the
same gate bias condition, for the single-layer embedded sample, the
corresponding ⌬VFB’s were 0.12, 0.3, and 0.47 V, separately. The
magnitude of the memory window difference between the dual- and
single-layer embedded samples increases with the increase in the
gate sweep voltage. The high positive gate voltage enhances the
formation of an electron-rich inversion layer and promotes electron
injection into the dielectric layer. Figure 3 demonstrates that there
are two major factors affecting the charge storage capability of the
nc-ZnO embedded device: 共i兲 the supply of energetic electrons from
the substrate and 共ii兲 the density of the embedded nc-ZnO dots in the
dielectric layer.
Figure 4 shows the shift of VFB of the nc-ZnO embedded sample
after Vg = +8 V bias 共with respect to the fresh device兲 as a function
of the stress time. For the single-layer embedded sample, the mag-
nitude of the VFB shift monotonically increases with the stress time,
which is similar to other nonvolatile memory devices, e.g., nc-
tungsten embedded in HfAlO and nc-ruthenium oxide embedded in
Figure 4. Shifts of VFB 共with respect to fresh device兲 of single- and dual-
layer nc-ZnO embedded samples vs gate stress time at Vg = +8 V.
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H85
ZrHfO.26,27 This kind of relationship implies that some of the
trapped charges were probably lost to the gate electrode during gate
stress.28 In addition, electrons injected from the substrate may not be
completely retained by the nc-ZnO dots in the single-layer embed-
ded sample. In the dual-layer embedded sample, the loss of electrons
from the bottom nc-ZnO layer during gate stress could be reduced
because they have to overcome the coulomb blockade effect gener-
ated from electrons trapped in the top nc-ZnO layer before reaching
the gate electrode.29 Because the VFB shift of the dual-layer embed-
ded sample is much larger than that of the single-layer embedded
sample within a very short stress time, e.g., ⬍10 ms, the data writ-
ing speed is greatly improved with the addition of the extra nc-ZnO
layer. In addition, the VFB shift of the dual-layer embedded sample is
less dependent on the stress time than the single-layer embedded
sample is. This is probably due to the limited supply of electrons
from the substrate or the saturation of the nc-ZnO charge trapping
site within a short period of stress time.
Conclusion
MOS capacitors containing single- and dual-layer nc-ZnO em-
bedded amorphous ZrHfO high-k gate dielectric were fabricated.
Electrons instead of holes were trapped by the embedded nc-ZnO
dots, which is responsible for the large memory window of the de-
vice. The dual-layer embedded sample has many advantages over
the single-layer embedded sample with respect to the charge trap-
ping density and writing speed. The additional embedded layer hin-
dered the charge leakage to the gate electrode or to the substrate due
to the coulomb blockade effect. Charge trapping in the dual-layer
sample can be accomplished in a very short period of time. The
dual-layer nc-ZnO embedded high-k gate dielectric structure is
promising for future high density nonvolatile memories.
Acknowledgments
This work was supported by the NSF CMMI 0926379 project.
Chen-Han Lin acknowledges Applied Materials Inc. for providing a
graduate fellowship.
Texas A&M University assisted in meeting the publication costs of this
article.
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