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1.2 Dynamics of Exponentials in Circuits and Systems
Ahmad Bahai, Chief Technology Officer,
Texas Instruments, Santa Clara, CA
1.1 Introduction
Scaling of CMOS, the technology that has driven our industry for 45 years and
prompted unprecedented innovations in device, circuit, and manufacturing, is
coming to an end. There is no unanimous agreement as to precisely when this will
happen, or whether it has already happened, or what classes of products it will
impact first. However, there is no disagreement that the continued shrinking of
CMOS feature size will end at some point. And when this does occur, what will be
the consequences for our industry? Certainly, there will be changes in the way
products are developed and produced. This paper will address some of the most
important changes that we will see.
In spite of the slowing of CMOS scaling, an unprecedented revolution in electronics
is taking place. “Things” are getting smarter and more connected with more and
more semiconductor content. Smart personal electronics, autonomous systems,
and smart factories are prime examples. These impressive developments are being
fueled by many exponential improvements in communication-bandwidth efficiency,
continued reductions in manufacturing cost, innovative new manufacturing
technologies, and new design techniques. In a sense, the end of CMOS scaling is
enabling exciting opportunities for “multi-dimensional innovations” in circuits and
systems.
The continuing demand for higher performance will further tilt solutions toward
creative system and circuit technologies, such as innovative engineering of CMOS
nodes for RF and analog, MEMS-based sensors and timing references, III-V
devices, high-performance SiGe devices and Si photonics. These technologies will
not necessarily be monolithically integrated, but they will provide opportunities for
system repartitioning and new circuit topologies in applications such as sensor
nodes, high voltage power electronics, high-performance RF, and precision timing.
Market forces are also at work to change our industry. For the past 20 years, the
semiconductor industry has been dominated by personal electronic products. This
has resulted in an industry where huge volumes of a relatively small number of
products are provided using commodity CMOS. However, we are currently
witnessing the rapid growth and sophistication of electronics for automotive
transportation, industrial/building automation, and health care. The dynamics of
the automotive, industrial, and medical markets are quite different from the
dynamics of that for personal electronics. They will be served by a large number
of various semiconductor products provided to a large number of system
companies using innovative differentiated manufacturing technologies.
Examples of many complementary exponential technology trends and their impact
on design methodologies are presented below.
2.1 Industry in Transition: Ubiquitous Electronics
Semiconductor growth over the last several decades has been fueled by a small
number of dominant applications and markets. Emergence of PCs in the 1970s,
Internet and connected PC in the 1990s, and mobile phones in the past two decades
coincide with peaks in the semiconductor market. Moving forward, a more
diversified proliferation of technologies and products will contribute to the steady
growth of the semiconductor market for the foreseeable future. Everything around
us is getting smarter and more connected with new features and more electronics
content. As shown in Figure 1.2.1, the number of semiconductor devices per person
is rapidly growing. Personal Electronics continues to drive this growth, but new
markets are also accelerating overall growth.
The automotive industry has been a major driver of recent innovation in
semiconductor growth. There are more than 6,000 semiconductor devices in a
modern mid-range vehicle, and electronic content contributes to about a third of
the vehicle cost. This electronics includes: Advanced Driver-Assist Systems
(ADAS), infotainment cluster, body electronics, lighting and powertrain for Electric
Vehicles/Hybrid Electric Vehicles (EV/HEV). To meet the needs of ADAS, sensor
systems are being developed that include radar, LIDAR, optical cameras, time-of-
flight (TOF) imaging devices, and ultrasound modules. An example of a
14 • 2017 IEEE International Solid-State Circuits Conference
highly-integrated radar module, (fully integrated into a BGA package), is shown in
Figure 1.2.2. This radar module can provide high-resolution images, and has led
to many automotive applications.
Industrial Internet or Industry 4.0, promotes the concept of intelligent
manufacturing and relies on the deployment of a massive number of intelligent
sensors at industrial plants to improve efficiency and reliability. Extensive use of
smart devices in factory automation, process control, and building automation will
drive a significant growth of electronics in industrial applications.
Personal medicine represents a third emerging market. Medical electronics
promises to revolutionize the healthcare industry with low-cost deployment of non-
invasive and minimally-invasive biosensors for preventive care and treatment
procedures.
Slowdown in CMOS scaling has not reduced the appetite for more intelligent and
connected things around us: Many other exponential and nonlinear scaling trends,
some of which are highlighted in this paper, have been and will be at work to
continue the pace and support demand.
3.1 Scaling Is More than Moore’s Law!
Scaling is a critical step toward miniaturization on every front, as more electronics
are integrated into a smaller form factor at lower cost. Many innovations have
contributed to the confluence of multiple scaling trends enabling the amazing
journey of electronics miniaturization. Dennard exponential scaling of process
technology has been complemented with several other trends following
exponentials with variable rates or other nonlinear functions. These have collectively
contributed to the ubiquity of electronics. The future innovations in semiconductors
and circuits will be increasingly multi-dimensional.
3.1.1 Bandwidth Efficiency
Connectivity has played an enormous role in the proliferation of the semiconductor
industry. Connected PCs and mobile phones have been the two recent drivers of
semiconductor market growth. Connectivity, particularly embedded, is an
indispensable element of intelligent devices. Bandwidth efficiency of
communication systems has consistently improved over the past several decades,
just about doubling every 30 months.
The progress in communication-system design utilizing advanced variations in
OFDM-enhanced [1] deployment of massive MIMO and coding techniques have
realized near-theoretical capacity of modern communication systems. The
evolution to 5G is a continuation of exponential improvement in bandwidth
efficiency. One central mission for 5G is to carry more bits per second to more
users, more efficiently. This is clearly to address the insatiable demand for higher
data rates (exabytes/month), and support for a large number of connected devices.
In addition to extension of 4G LTE performance In addition to extending 4G LTE
capacity, 5G promises to support machine-type communication in industrial and
commercial applications, and in other wireless sensor networks. Therefore, low
latency, low power consumption, and extremely high reliability are among the key
5G attributes.
As shown in Figure 1.2.3, the bandwidth efficiency of different generations of
wireless cellular radio shows exponential improvement. Embedded-connectivity
solutions such as WiFi, BLE, ZigBee, and other proprietary standards have
experienced tremendous improvement in bandwidth and power efficiency. As
shown in Figure 1.2.4, the power efficiency of WiFi radio has improved significantly
over generations at a pace of 4× in 10 years. However, many of these improvements
happened at the same technology node due to architectural advancements.
3.1.2 Manufacturing Efficiency
Innovation in semiconductor manufacturing has shaped an unprecedented
inflation-defying industry. A combination of improvements in factory throughput,
higher yield, and larger wafer size has led to the cost-per-unit-area of silicon to
remain almost constant over the past three decades. Yield loss can occur during a
complex chain of manufacturing processes such as implantation, etching,
deposition, planarization, cleaning, or lithography, and yet the industry can offer a
very high overall yield. Mature technology nodes benefit from higher yield and a
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better cost structure, which make them even more desirable for analog
applications. As shown in Figure 1.2.5, the longevity of analog nodes spans
almost a decade, as manufacturing efficiency and challenges of porting analog
circuits motivate designers to park on a node and implement innovative
advanced circuit topologies on a mature technology. Transition to larger wafer
size will further enhance the efficiency of analog IC design.
3.1.3 Other Scaling Trends
Consistent scaling of CMOS technology has driven growth in the semiconductor
market over the past four decades. Reliance on the next CMOS technology node
to reduce the power, size, and cost is widespread across the industry.
Consequently, the slowdown in CMOS scaling has been cause for concern.
While,many promising innovations such as 3D structures are extending the
scaling trend, clearly the pace of scaling has subsided. However, many aspects
of IC design do not follow the CMOS scaling trends as tightly as digital ICs, so
they have not been impacted. In fact, the slowdown of scaling is opening up
opportunities for design innovation in more exciting ways. Analog, RF, power
management, precision circuits, and MEMS devices are some examples of
circuits and systems which will follow other exponential or nonlinear trends.
4.1 Power Management and Scaling
In general, power devices have not been the main beneficiary of CMOS scaling.
When the power solution is not dominated by digital content, scaling does not
necessarily benefit power-device performance. The performance of the power
device is mainly determined by its voltage requirement. As a result, many power-
device process improvements are made without shrinking feature size. Though
some power devices do benefit from the availability of new technologies, they
are driven by feature-size improvement such as advance lithography. Other
benefits come from improvements in power-device architecture, and from new
semiconductor materials.
However, power solutions see some adjacent benefits of scaling, but the
disruptive advances come from device architecture and new materials, such as
2D/vertical devices and wide-bandgap GaN. Additionally, power switches and
passive devices dominate die area. As a result, high-mask-count processes are
not cost-effective in power ICs and low-mask-count processes that are optimized
for power tend to have long lifespan of up to a decade or more, as opposed to
about two years for digitally-optimized processes.
In BCD (Bipolar-CMOS-DMOS) integrated power technologies, commonly used
for power management, the feature size is typically larger than the state-of-the-
art CMOS. High-voltage operation of LDMOS power transistors requires a large
drift region to withstand higher breakdown voltages. Low on-resistance and low
gate charge for low voltage operation, and low output capacitance for high
voltage are among the key figures of merit (FOM) of an LDMOS switch. Also,
higher switching speed is increasingly desirable, as it reduces the inductor size,
thus improving power density. Figure 1.2.6 highlights a few key attributes of
scaling and figures-of-merit for power devices. First, improvement in LDMOS
on-resistance, in many cases, is not necessarily related to scaling. Secondly, the
reduction in on-resistance for smaller power devices quickly diminishes for
higher voltages. For example, a typical 20V DMOS has experienced an
improvement of about 20% per year which is much slower than Moore’s Law
scaling. As we go to higher voltage DMOS, the improvement with scaling slows
further. A typical 50V DMOS has experienced an annual improvement of about
14-15%.
The “1D silicon limit” is more dominant for higher-voltage devices due to the
fact that the drift region is relatively larger than the rest of the device.  The
increase in Rsp with respect to breakdown voltage is a quadratic function of
breakdown voltage for a typical LDMOS with a uniform drift region. Interestingly,
within the vicinity of each node, many innovative device engineering techniques,
such as the split gate architecture used in discrete power devices, have managed
to improve the device performance significantly. Also, 2D structures like the
super-junction structures shown in Figure 1.2.7 has achieved much higher
breakdown voltages beyond and above quadratic limits of 1D structures, albeit
at higher cost.
There are other concerns which prevent aggressive scaling of process. Off-state
leakage of switches, which is more pronounced in the finer process nodes, is
ISSCC 2017 / February 6, 2017 / 9:20 AM
detrimental to efficiency of power devices and systems. Also, cost sensitivity of
power solutions (Rsp × wafer cost) is another incentive for power devices to avoid 1
leverage expensive technologies when digital content is not the defining factor.
Increasing the switching speed of power devices up to the range of tens of MHz
is desirable for achieving high-power density in AC/DC and DC/DC converters.
Since, as described earlier, CMOS scaling inherently compromises operational
voltage of the power MOSFET, alternative materials have been introduced to the
power-FET mix. III-V materials with large band gaps such as GaN and SiC provide
low on-resistance and the capability of higher-switching speeds in high-voltage
applications. At high voltages, GaN shows a substantial improvement over Si in
the important FOM of gate charge (QG × Rds(on). This is illustrated in Figure 1.2.8.
While the high cost of GaN is a barrier to widespread deployment at this time,
the cost is expected to be reduced through improvements in GaN-on-Si wafers
in 200mm manufacturing.
The competition between GaN, SiC. and Si power MOSFETs will continue, as
each technology will offer higher power density through creative device
engineering, and will define its region of competitive advantage.
4.1.2 Precision Circuits and Scaling
Analog circuits have benefited from many aspects of CMOS scaling, but unlike
digital circuits they have not been in the forefront of the trend.  
Analog blocks for low-signal-swing circuits shrink in area with process scaling.
However, mask-set cost, development cost, the need for high-voltage devices,
and specialty passive support have resulted in a significantly slower pace of
scaling for high-performance analog and power processes, as compared to
leading-edge CMOS digital processes.  The transition to the finer nodes for
analog blocks can usually be justified only when mask and wafer cost of the node
comes down. Also, the availability of integrated higher-voltage devices, or a much
higher gain heterojunction bipolar transistor (HBT) for high linearity, ultra-low
noise (Noise Figure) and high swing/precision circuits may compel transition of
analog to a new node.    As digital gates are more readily available and more
economical in finer analog nodes, architectures that use digital circuitry to tune
analog become more common place in standard analog products.
Many low-voltage high-speed analog and RF blocks have made the transition to
fine CMOS technologies. In some cases, such as large SoCs with massive digital
gate counts, the transition is inspired by the exponential die size reduction of
digital and the need for higher fT. Therefore, analog and RF designers have
deployed innovative circuit topologies to compensate for imperfection inherent
in the technology (mismatch, gain and noise issues). On the other hand, some
high-performance analog and RF circuits such as GSPS ADC and DACs and
mmWave RF continue to utilize fine CMOS processes, albeit a few generations
behind the leading digital node. In these cases, some enhancements to CMOS
such as improved matching, low Vt, low leakage, drain-extended CMOS (DEMOS)
for IO circuits, isolated transistors, and integrated passives optimized for analog
design, are added to a baseline digital process to enable aggressive analog/RF
integration.
An analog process typically offers a large number of key analog components and
interconnect options, which result in the optimum analog performance at the
lowest cost.  These analog processes enable innovative analog circuits and IP to
benefit from rich and precise device capabilities. Also, the customization of
analog IP to specific product domains, together with the capability of a highly-
tuned analog process, will allow for solutions that are not possible using an
advanced digital CMOS process. 
As shown in Figure 1.2.9 [2], the speed-resolution product of A/D converters
improves with process scaling but at a slower pace than the scaling of digital
circuits alone. Converters double every 3.5 to 4 years. Interestingly, the
improvement rate beyond 90nm is slowing down as the performance of high-
bandwidth converters is limited by clock jitter (Figure 1.2.10). Clearly,
innovations in clock references and new architectures will be critical for achieving
higher-performance data converters.
There are many examples of the exceptional capabilities of high-performance
analog processes that are not supported by standard digital CMOS. These include
ultra-low-noise audio DACs with high-voltage efficient Class-D drive, and gigabit
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ISSCC 2017 / SESSION 1 / PLENARY / 1.2
automotive/industrial Ethernet with robust ESD capability. Such optimized
analog processes are usually 5 to10 years behind the leading digital process.
This lagging trend will most likely further slow once 45nm or 28nm become main
stream for some future low-power analog processes. Innovative device
engineering for analog and RF at these nodes will be highly desirable for most
RF and analog applications. Also, integrating unique new devices will become
the new axis of expansion in such an analog domain. 
Digital CMOS is now widely available from foundries, and has led to the
standardization of CMOS technology which has become a commodity. For analog
and power circuits, however, specialized and differentiated process technologies
continue to provide a competitive advantage.
Alternative technologies such as SiGe BiCMOS offer many desirable advantages
with less aggressive scaling compared to CMOS. In particular, BiCMOS
technology can typically offer the same gain-bandwidth products as basic CMOS
two nodes beyond. High GBW, relatively higher supply voltage, and better noise
performance than CMOS technologies with comparable fT are critical in many
precision analog designs. BiCMOS technologies have also shown more
promising device interconnect properties for RF circuits than CMOS, as shown
in Figure 1.2.11 [3]. Precision amplifiers using bipolar transistors have
outperformed all-CMOS based designs.
Creative engineering of 45 to 28nm CMOS devices optimized for RF and precision
analog is very promising. Also, using high-density CMOS in conjunction with
high-performance HBT will offer a desirable combination of process technologies
optimized for analog design, with the availability of digital gates. However, many
process innovations are needed to keep complexity and cost down.
4.1.3 MEMS and Scaling
MEMS technology has its own miniaturization roadmap and challenges that are
quite different from CMOS scaling. The importance of MEMS as a critical part of
modern systems and circuit topologies is growing. High-performance MEMS
sensors have been deployed in a large number of personal electronics,
automotive, medical, and other applications with low power consumption. The
presence of MEMS sensors on the chip and in the system avails a wealth of
physical information such as orientation, and pressure in a highly-integrated and
affordable form factor. This has led to a big stride toward “Intelligent Things”.
MEMS resonators that are used as clock and frequency references and filters
have scaled down aggressively over past two decades. Quartz crystal oscillators
(XOs) still dominate today’s timing market due to their high Q and excellent
frequency stability over temperature. But, over the past decade, MEMS-resonator
timing solutions have become comparable in performance with XOs in many
applications. MEMS-based oscillators are now available with RMS jitter less than
1 pico-second (integrated from 12kHz to 20MHz) and consume less than 1mW
of power. Quartz crystal references of a similar performance, paired with a phase-
locked loop (PLL) circuit consume higher power and silicon area for on-chip
inductors used in the LC oscillator. While in the past, MEMS devices have been
considered useable only for research, the MEMS community has been
engineering these micro-resonators for both performance and production
manufacturability to compete with the already-matured quartz crystal technology.
Figure 1.2.12 shows exponential growth of the common FOM, frequency-Q
product, of various MEMS-resonator technologies over two decades. Recently,
the frequency-Q product of capacitive MEMS resonators has surpassed that of
typical quartz crystals. However, most commercial capacitive MEMS resonators
are operating in the tens-of-megahertz range and suffer from high motional
impedance. On the other hand, piezoelectric MEMS resonators (or commonly
called acoustic wave resonators) operating in the gigahertz range with low
motional impedance bring immediate benefits for modern systems requiring
high-performance (low RMS jitter) clocks. The performance of piezoelectric
MEMS technology is predicted to surpass quartz technology in the next few
years.
Another example of scaling in a more complex MEMS structure is reflected in
Digital Light Processor (DLP) devices. The complex structure of a massive
number of mirrors, up to eight million, on a single chip, has enabled a wide
spectrum of optical applications ranging from high-resolution projectors to
spectroscopy. As shown in Figure 1.2.13, the scaling of DLP devices will have a
16 • 2017 IEEE International Solid-State Circuits Conference
different pace from that of CMOS. This is due to the challenges of integrating a
large number of MEMS devices on the chip. Massive signal processing
requirements for DLP applications in video, imaging, and spectroscopy will rely
on co-packaged advance processors.
5.1 System in Package
Monolithic integration and System-on-Chip (SoC) trends have also been driving
CMOS scaling. Integration of massive digital cores with peripheral circuits has
prompted many innovative mixed-signal, RF, and power-circuit design topologies
on a single digital CMOS node. System-in-package (SiP) and 3D packaging are
growing alternative approaches for integration. They can accommodate multiple
process technologies and/or passives in a package, thus creating new virtual Si-
nodes. Integrating multiple dies, each of which are optimized for different
purposes, can offer higher performance than forcing all circuit components, if
at all possible, on a single chip. Additionally, the ability to integrate passives and
sensors can reduce the complexity demands on the circuits.
Creative variations of wafer-level packaging have been extensively used to offer
heterogeneous solutions in photonics, resonators, and precision applications.
Solutions such as, through-silicon via (TSV), wafer-to-wafer bonding, die-to-
wafer bonding, and fan-out wafer-level packaging (FOWLP) can accommodate
various integration levels such as 2D, 2.5D, and 3D (Figure 1.2.14). The prospect
of advantages in size, reliability, and efficiency of wafer-level packaging continues
to open more opportunities for the integration of multiple circuit blocks that are
optimized in various technologies in a single package.
SiP solutions can offer faster time-to-market and local optimization of system
blocks, with less investment. There have been many promising innovations to
reduce size and cost along with increased functionality and performance of SiP
solutions. Innovative die-stacking techniques such as TSV and wire-in-film, with
area efficiency of close to or even sometimes more than 100%, have been
demonstrated.
Many precision applications use SiP techniques, such as flip-chip integration to
deal with interface parasitic issues. Meanwhile, stacking in a 3D configuration is
becoming more compelling in power applications. But, innovative thermal
management within a 3D package is critical to avoid hot-spot issues that
complicate monolithic SoC approaches.
Increasing switching frequency of power devices, higher-bandwidth
requirements of interfaces, RF modules, and many other high-frequency
applications require careful design and parasitic management. Proper spacing
and layout of interconnected multi-chip and passives that can be addressed much
more efficiently by package-level integration are compelling reasons for SiP
solutions. SiP will increasingly be adopted to integrate heterogeneous
technologies.
6.1 Conclusion
Our industry is in a state of transition as the result of the confluence of two trends
– the first, technology driven, the second, market driven:
1. CMOS scaling is coming to an end! This is encouraging “multi-
dimensional innovations” in circuits and systems enabled by various scaling
trends (exponential and nonlinear) in CMOS device engineering for analog
circuits, new materials such as III-V, timing references, high-performance
SiGe devices, integrated sensors, and Si photonics.
2. Electronics is a critical element in many product areas: automotive,
industrial, and medical. In all of these, there is rapid growth in both volume
and sophistication. Demand for these products will result in an industry
where a very large number of semiconductor devices is provided to a large
number of customers using differentiated manufacturing technologies.
CMOS technology is here to stay! The challenge is to improve CMOS
performance beyond scaling. In this process, new materials, new system
partitioning, and new efficient SiP techniques will add more dimensions to
innovation in circuits and systems. Overall, progress is likely to continue to be
exponential as approximated by a series of nonlinear functions representing
improvements in various segments of technology.
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 ISSCC 2017 / February 6, 2017 / 9:20 AM

References:
[1] A. Bahai, et. Al. “Multicarrier Digital Communications-Theory and Application 1
of OFDM” 2nd edition, 2004, Springer.
[2] B. Murmann, "ADC Performance Survey 1997-2016," [Online]. Available:
http://web.stanford.edu/~murmann/adcsurvey.html.
[3] R. L. Schmid, A. Ç Ulusoy, S. Zeinolabedinzadeh and J. D. Cressler, "A
Comparison of the Degradation in RF Performance Due to Device Interconnects
in Advanced SiGe HBT and CMOS Technologies," in IEEE Transactions on
Electron Devices, vol. 62, no. 6, pp. 1803-1810, June 2015.

DIGEST OF TECHNICAL PAPERS • 17

ISSCC 2017 / SESSION 1 / PLENARY / 1.2

Figure 1.2.1: Semiconductor Market Growth. Figure 1.2.2: Radar system (RF+DSP) on a chip.

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18 • 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE

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Figure 1.2.7: GaN and silicon super-junction performance. Figure 1.2.8: Figure-of-Merit for GaN and Si power device.



Figure 1.2.9: Rate of improvement for data converters. Figure 1.2.10: Jitter-limited converter performance.
http://web.stanford.edu/~murmann/adcsurvey.html. http://web.stanford.edu/~murmann/adcsurvey.html.

Figure 1.2.11: fT comparison at top metal – J. Cressler (2015). Figure 1.2.12: Evolution of capacitive and piezo MEMS.

DIGEST OF TECHNICAL PAPERS • 19

ISSCC 2017 / SESSION 1 / PLENARY / 1.2 February 6, 2017 / 9:20 AM






Figure 1.2.13: Pixel count improvement in DLP. Figure 1.2.14: Integration options using wafer-level packaging.

20 • 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE