ISSCC 2017 / SESSION 5 / ANALOG TECHNIQUES / 5.
5.5 A Quadrature Relaxation Oscillator with a Process-
Induced Frequency-Error Compensation Loop
Jahyun Koo1, Kyoung-Sik Moon2, Byungsub Kim1, Hong-June Park1,
Jae-Yoon Sim1
1
Pohang University of Science and Technology, Pohang, Korea
2
Research Institute of Industrial Science & Technology, Pohang, Korea
With the emergence of wearable and implantable technologies, there has been
growing demand on development of key enabling circuits for ultra-low-power
sensor interface SoCs. As a reference-frequency generation block for clock
management of the overall system, the relaxation oscillator has been widely
adopted since it can provide a controllable and well-defined untrimmed frequency
with low-cost circuits. In the past decade, the major goal in the design of the
relaxation oscillators has been the improvement of phase-noise figure-of-merit
(FOM) closer to the fundamental limit of 169dBc/Hz [1]. There have been feedback
approaches to internally generate reference voltages for comparison, hence
compensating the comparator circuit delay [2-4]. Since the delay compensation
relies on the feedback operation, power consumption by analog circuits to meet
the required bandwidth of the feedback loop eventually limits FOM. Recently, a
swing-boosted differential scheme was proposed to reduce the effect of
comparator noise by boosting the signal slope at the comparator input,
demonstrating an FOM of over 160dBc/Hz [5]. However, the boosted voltage
swing can increase stress on the input transistors of the comparator. In addition,
a high-speed comparator is also needed to reduce the effect of the circuit delay
on the output frequency. While most of previous works achieved good FOMs with
MHz oscillators, implementation of low-frequency relaxation oscillators presents
additional challenges since it requires excessive area for RC and power
consumption by analog circuits with leakage not scaled down along with the
output frequency.
This work presents a low-power quadrature phase relaxation oscillator suitable
for low-frequency generation. The proposed quadrature generation enables a
switching scheme to compensate process-induced frequency error. It also
alleviates the speed requirement of analog circuits to reduce power consumption.
Figure 5.5.1 shows the concept of the proposed quadrature relaxation oscillator,
which consists of two identical RC networks. The RC network follows a typical
1st-order lowpass characteristic and drive voltages on Vo1 and Vo2. They are
controlled so that one of Vo1 and Vo2 stops transitioning while the other is being
charged or discharged with the RC time constant. The alternate transitions of Vo1
and Vo2 with charging or discharging determined by two SR latch outputs
guarantees a quadrature-phase relation. Each RC network has two comparators
with upper and lower references for limiting the voltage swing, i.e. refup1 and
refdn1 for Vo1, and refup2 and refdn2 for Vo2, respectively. The four reference
voltages are automatically generated by an error-sampling feedback loop to
compensate nonzero delays (td) and the effect of 1/f noise including offset of the
comparator circuits. The quadrature phase generation divides one clock period
into four transition sections, where each section holds the same RC dynamics. It
increases the transition slope at the time of flipping of the comparator output
compared with the conventional differential phase generation that divides one
clock period into two transition sections.
The quadrature phase generation requires twice the number of comparisons of
the differential phase generation. Assuming that both of the comparator noise
levels are dominated by the thermal noise and are not correlated, the use of twice
the number of comparisons causes a √2 times increase in timing jitter. However,
even considering the cost of increased comparator noise, the gain from the slope
elevation from quadrature phase generation can suppress the net effect of the
comparator noise. The quadrature phase generation also provides an inherently
safe large timing window in sampling Vo1 and Vo2 for the error estimation
process in the feedback loop, which relieves the speed requirement of analog
circuits and helps reduce power consumption.
Figure 5.5.2 shows the circuit diagram of the reference generator. A resistor string
provides Vup and Vdn, which define the target voltage swing on Vo1 and Vo2.
Since Vo1 and Vo2 are driven by the supply voltage with swing determined by a
portion of the same supply voltage, the period has strong immunity to supply-
voltage variation. For the generation of refup1 and refup2, sampled Vo1 and Vo2
94 • 2017 IEEE International Solid-State Circuits Conference
are compared with Vup. The voltage differences, Vo1 – Vup and Vo2 – Vup, drive
a current output with an open-loop transconductance amplifier, developing the
reference voltages refup1 and refup2, respectively. Updated refup1 and refup2
return with change of Vo1 and Vo2, which forms a discrete-time feedback loop
stabilizing refup1 and refup2. The refdn1 and refdn2 are generated in a similar
way by comparing Vo1 and Vo2 with Vdn, as indicated with brackets. The
transconductance amplifier is implemented with a folded-cascode amplifier. A
small sub-amplifier is also employed with a unity-gain feedback configuration to
define the voltage of the high-impedance output node of the folded-cascode
amplifier to be around the target before updating refup1 and refup2. A switching
scheme similar to chopping is applied to compensate the effect of offset of the
transconductance amplifier. With the proposed switching, if one of the voltage
swings on Vo1 and Vo2 increases due to an offset (Vos), the other decreases,
resulting in compensation of frequency error. Since the RC-shaped signal
transition can be approximated to be a straight line for a small period of time, the
switching can suppress more frequency error as the offset becomes smaller (Fig.
5.5.3).
It should be noted that the proposed frequency-error compensation switching
scheme is different from the conventional chopping which continually drives
alternating outputs to eliminate the comparison error on average. Thus, the
chopping induces serious noise of the chopping frequency which should be
filtered out. However, the filtering of the noise by a capacitor especially in a low-
frequency generation requires excessively large area, and remaining unfiltered
noise degrades jitter performance. The proposed switching does not drive
alternating outputs, so it does not induce the noise of the switching frequency on
refup1 and refup2. Instead, the frequency-error compensation loop eventually
stores the offset at refup1 and refup2 but with opposite polarity and compensates
the error by changing the voltage swings on Vo1 and Vo2.
The proposed relaxation oscillator was implemented in a 0.18μm CMOS process.
The active area is 0.058mm2. The oscillator consumes 21.3μW from a supply
voltage of 1.8V, while generating 444.9kHz. Figure 5.5.4 shows measured phase
noise. The corner frequency of 1/f noise is about 3kHz. By enabling the error-
compensation switching, the slope of the phase-noise plot becomes well-matched
to -20dB/dec, representing negligible remaining 1/f noise. The measured phase
noise is -65.29dBc/Hz at an offset frequency of 100Hz, showing an FOM of
155dBc/Hz. The compensation loop also reduces frequency error caused by
transistor parameter variations. Monte-Carlo simulation shows that the frequency-
error compensation scheme reduces the standard deviation of output frequency
from 4.03% to 0.136% (Fig. 5.5.5). Statistics of untrimmed output frequencies
were measured from 100 chips. The standard deviation was reduced from 1.69%
to 0.95%. The remaining deviation mainly comes from process variations on RC
since the compensation loop cannot eliminate process variations on RC. The rms
period jitter is measured to be 1.06ns, or 0.047% of the period. Accumulated jitter
stably increases with √N, revealing that thermal noise is the dominant noise
source with 1/f noise greatly suppressed. Figure 5.5.6 compares performance
with previous works. Our quadrature relaxation oscillator achieves better FOM
among previously reported oscillators having similar frequencies and comparable
performance with the state-of-the-art high-frequency oscillators. Figure 5.5.7
shows a die micrograph.
Acknowledgements:
This work was supported by IITP under grant No. R7117-16-0166.
References:
[1] P.F.J. Geraedts, et al., “A 90μW 12MHz Relaxation Oscillator with a -162dB
FOM,” ISSCC, pp. 348-349, Feb. 2008.
[2] Y. Tokunaga, et al., “An On-Chip CMOS Relaxation Oscillator with Power
Averaging Feedback Using a Reference Proportional to Supply Voltage,” ISSCC,
pp. 404-405, 2009.
[3] Y. Tokunaga, et al., “An Over 20,000 Quality Factor On-Chip Relaxation
Oscillator using Power Averaging Feedback with a Chopped Amplifier,” IEEE
Symp. VLSI Circuits, pp. 111-112, June 2010.
[4] Y. Cao, et al., “A 63,000 Q-Factor Relaxation Oscillator with Switched-
Capacitor Integrated Error Feedback,” ISSCC, pp. 186-187, Feb. 2013.
[5] J. Lee, et al., “A 1.4V 10.5MHz Swing-Boosted Differential Relaxation Oscillator
with 162.1dBc/Hz FOM and 9.86psrms Period Jitter in 0.18μm CMOS,” ISSCC, pp.
106-107, Feb. 2016.
978-1-5090-3758-2/17/$31.00 ©2017 IEEE
 ISSCC 2017 / February 6, 2017 / 3:15 PM

Figure 5.5.1: Core circuit diagram of the proposed quadrature relaxation

oscillator. Figure 5.5.2: Circuit diagram of the reference generator.

Figure 5.5.3: Frequency-error compensation of gm amplifier offset voltage. Figure 5.5.4: Measured phase noise.

Figure 5.5.5: Monte-Carlo simulation (256 hit), measured chip variation (100
samples), period jitter and accumulate jitter. Figure 5.5.6: Performance comparison.

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Figure 5.5.7: Die micrograph.

• 2017 IEEE International Solid-State Circuits Conference 978-1-5090-3758-2/17/$31.00 ©2017 IEEE