main

Set the clock to run at 40MhZ using the PLL and 16MHz external crystal

First disable interrupts

Init GPIO function

Init ineterrupts function
Init PWM function
Init SPI function

enable global interrupts

now initialize the Events and Services Framework and start it running
}

InitGPIO
{

Port B
Enable the clock to Port B

Wait till clock for Port B is ready

Set as digital
Set as outputs
Set as inputs

Port C
Enable the clock to Port C
Wait till clock for Port C is ready
Set as digital
Set as outputs
Set as inputs

Port D
Enable the clock to Port D
Wait till clock for Port B is ready
Set as digital
Set as outputs
Set as inputs
 Port E
Clock enable for Port E included within function
Init analog inputs for magnetic line following and Sharp sensor

InitInterrupts
{

WIDE TIMER 0A
start by enabling the clock to the timer (Wide Timer 0)

kill a few cycles to let the clock get going

make sure that timer (Timer A) is disabled before configuring

set it up in 32bit wide (individual, not concatenated) mode

the constant name derives from the 16/32 bit timer, but this is a 32/64
bit timer so we are setting the 32bit mode

we want to use the full 32 bit count, so initialize the Interval Load
register to 0xffff.ffff (its default value :-)

set up timer A in capture mode (TAMR=3, TAAMS = 0),

for edge time (TACMR = 1) and up-counting (TACDIR = 1)

To set the event to rising edge, we need to modify the TAEVENT bits
in GPTMCTL. Rising edge = 00, so we clear the TAEVENT bits

Now Set up the port to do the capture (clock was enabled earlier)
start by setting the alternate function for Port C bit 4 (WT0CCP0)

Then, map bit 4s alternate function to WT0CCP0

7 is the mux value to select WT0CCP0, 16 to shift it over to the
right nibble for bit 4 (4 bits/nibble * 4 bits)

Enable pin 4 on Port C for digital I/O

make pin 4 on Port C into an input

back to the timer to enable a local capture interrupt

HWREG(WTIMER0_BASE+TIMER_O_IMR) |= TIMER_IMR_CAEIM;
enable the Timer A in Wide Timer 0 interrupt in the NVIC
it is interrupt number 94 so appears in EN2 at bit 30

now kick the timer off by enabling it and enabling the timer to
stall while stopped by the debugger

WIDE TIMER 1A AND 1B

start by enabling the clock to the timer (Wide Timer 1)

kill a few cycles to let the clock get going

make sure that timer (Timer A) is disabled before configuring

set it up in 32bit wide (individual, not concatenated) mode

set up timer A in periodic mode so that it repeats the time-outs

set timeout to 100 seconds

enable a local timeout interrupt

enable the Timer A in Wide Timer 0 interrupt in the NVIC

it is interrupt number 96 so appears in EN3 at bit 0

now kick the timer off by enabling it and enabling the timer to
stall while stopped by the debugger

make sure that timer (Timer B) is disabled before configuring

we want to use the full 32 bit count, so initialize the Interval Load
register to 0xffff.ffff (its default value :-)

set up timer B in capture mode (TAMR=3, TAAMS = 0),

for edge time (TACMR = 1) and up-counting (TACDIR = 1)

To set the event to rising edge, we need to modify the TBEVENT bits
in GPTMCTL. Rising edge = 00, so we clear the TBEVENT bits

Now Set up the port to do the capture (clock was enabled earlier)
start by setting the alternate function for Port C bit 7 (WT1CCP1)

Then, map bit 7s alternate function to WT1CCP1

7 is the mux value to select WT1CCP1, 28 to shift it over to the
right nibble for bit 7 (4 bits/nibble * 7 bits)

Enable pin 7 on Port C for digital I/O

make pin 7 on Port C into an input

back to the timer to enable a local capture interrupt

HWREG(WTIMER1_BASE+TIMER_O_IMR) |= TIMER_IMR_CBEIM;

enable the Timer B in Wide Timer 1 interrupt in the NVIC

it is interrupt number 97 so appears in EN3 at bit 1

now kick the timer off by enabling it and enabling the timer to
stall while stopped by the debugger

WIDE TIMERS 3A AND 3B

start by enabling the clock to the timer (Wide Timer 3)

kill a few cycles to let the clock get going

make sure that timer (Timer A) is disabled before configuring

make sure that timer (Timer B) is disabled before configuring

set it up in 32bit wide (individual, not concatenated) mode

the constant name derives from the 16/32 bit timer, but this is a 32/64
bit timer so we are setting the 32bit mode

we want to use the full 32 bit count, so initialize the Interval Load
register to 0xffff.ffff (its default value :-)

we want to use the full 32 bit count, so initialize the Interval Load
register to 0xffff.ffff (its default value :-)

set up timer A in capture mode (TAMR=3, TAAMS = 0),

for edge time (TACMR = 1) and up-counting (TACDIR = 1)

set up timer B in capture mode (TAMR=3, TAAMS = 0),

for edge time (TACMR = 1) and up-counting (TACDIR = 1)

To set the event to rising edge, we need to modify the TAEVENT bits
in GPTMCTL. Rising edge = 00, so we clear the TAEVENT bits
 To set the event to rising edge, we need to modify the TBEVENT bits
in GPTMCTL. Rising edge = 00, so we clear the TBEVENT bits

Now Set up the port to do the capture (clock was enabled earlier)
start by setting the alternate function for Port D bit 2 (WT3CCP0)

Then, map bit 2s alternate function to WT3CCP0

7 is the mux value to select WT3CCP0, 8 to shift it over to the
right nibble for bit 2 (4 bits/nibble * 2 bits)

Enable pin 2 on Port D for digital I/O

make pin 2 on Port D into an input

Now Set up the port to do the capture (clock was enabled earlier)
start by setting the alternate function for Port D bit 3 (WT3CCP1)

Then, map bit 3s alternate function to WT3CCP1

7 is the mux value to select WT3CCP1, 12 to shift it over to the
right nibble for bit 3 (4 bits/nibble * 3 bits)
Enable pin 3 on Port D for digital I/O

make pin 3 on Port D into an input

back to the timer to enable a local capture interrupt

HWREG(WTIMER3_BASE+TIMER_O_IMR) |= TIMER_IMR_CAEIM;

back to the timer to enable a local capture interrupt

HWREG(WTIMER3_BASE+TIMER_O_IMR) |= TIMER_IMR_CBEIM;

enable the nvic interrupts

now kick the timer off by enabling it and enabling the timer to
stall while stopped by the debugger

now kick the timer off by enabling it and enabling the timer to
stall while stopped by the debugger
}

InitPWM
{
Enable the clock to Module 0 of PWM
Select the PWM clock as System Clock / 32
Wait until the clock has started

Disable PWM0 (PB6 and PB7) while initializing

program generators to go to 1 at rising compare A/B, 0 on falling compare A/B
Set period
Set value at which pin changes state
Enable PWM to motors in InitMotorService

Disable PWM1 (PB4 and PB5) while initializing

program generators to go to 1 at rising compare A/B, 0 on falling compare A/B
Set half the period (load = period/4/32 - adjusting for difference in clock to PWM and timers)
Set value at which pin changes state (50% duty cycle)
Enable PWM output (DONT ENABLE, WAIT FOR SM TO ENABLE IT)
HWREG(PWM0_BASE + PWM_O_ENABLE) |= (PWM_ENABLE_PWM3EN);

Disable PWM2 (PE4 and PE5) while initializing

program generators to go to 1 at rising compare A/B, 0 on falling compare A/B
Set period
Set value at which pin changes state
Enable PWM output for ball storage servo and flag servo

Disable PWM3 (PD0 and PD1) while initializing NOT USING PD1
program generators to go to 1 at rising compare A/B, 0 on falling compare A/B
Set period
Set value at which pin changes state
Set the Duty cycle on A by programming the compare value
to the required duty cycle of Period/2 - DesiredHighTime/2
Dont enable PWM output to flywheel (0V across leads when MOSFET is off)

Select alternate functions for PB6 and PB7 and PB4 and PB5
Map PWM to PB6 and PB7 and PB4 and PB5. 4 comes from Table 23-5 on Page 1351 of TIVA datasheet
Set PB6 and PB7 and PB4 and PB5 as digital
Set PB6 and PB7 and PB4 and PB5 as outputs

Select an alternate function for PD0 and PD1

Map PWM to PD0 and PD1. 4 comes from Table 23-5 on Page 1351 of TIVA datasheet
Set PD0 and PD1 as digital
Set PD0 and PD1 as output
 Select alternate functions for PE4 and PE5
Map PWM to PE4 and PE5. 4 comes from Table 23-5 on Page 1351 of TIVA datasheet
Set PE4 and PE5 as digital
Set PE4 and PE5 as outputs

Make all the enables locally synchronized

HWREG(PWM0_BASE + PWM_O_ENUPD) = ((PWM_ENUPD_ENUPD2_M &
PWM_ENUPD_ENUPD2_LSYNC) |
(PWM_ENUPD_ENUPD3_M & PWM_ENUPD_ENUPD3_LSYNC) | (PWM_ENUPD_ENUPD4_M &
PWM_ENUPD_ENUPD4_LSYNC) |
(PWM_ENUPD_ENUPD5_M & PWM_ENUPD_ENUPD5_LSYNC) | (PWM_ENUPD_ENUPD6_M &
PWM_ENUPD_ENUPD6_LSYNC) |
(PWM_ENUPD_ENUPD7_M & PWM_ENUPD_ENUPD7_LSYNC));
Set up+down count mode, enable PWM generator, and make generate update locally
synchronized to zero count
Set up+down count mode, enable PWM generator, and make generate update locally
synchronized to zero count
Set up+down count mode, enable PWM generator, and make generate update locally
synchronized to zero count
Set up+down count mode, enable PWM generator, and make generate update locally
synchronized to zero count

InitSPI
{
Enable the clock to the GPIO port A
Enable the clock to SSI module
Wait for the GPIO port to be ready
Program the GPIO to use the alternate functions on the SSI pins
Set mux position in GPIOPCTL to select the SSI use of the pins
Program the port lines for digital I/O
Program the required data directions on the port lines
If using SPI mode 3, program the pull-up on the clock line
Wait for the SSI0 to be ready
Make sure that the SSI is disabled before programming mode bits
Select master mode (MS) & TXRIS indicating End of Transmit (EOT)
Configure the SSI clock source to the system clock
Configure the clock pre-scaler: max frequency 961kHz
SSInClk = SysClk / (CPSDVSR *(1+SCR)), we want CPSDVSR*(1+SCR) > 2642 (CPSR = 54, SCR = 50)
Configure clock rate (SCR), phase & polarity (SPH, SPO), mode (FRF), data size (DSS)
 Locally enable interrupts (TXIM in SSIIM)
Make sure that the SSI is enabled for operation
}