Ec6612-Vlsi Design Lab Observation: Name Regno Class/Sem

EC6612-VLSI DESIGN
LAB OBSERVATION
NAME: ____________________________
REGNO :_____________________________
CLASS/SEM :____________________________
EC-6612 VLSI DESIGN LAB – RECORD 1

LIST OF EXPERIMENTS
LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS
1. HDL based design entry and simulation
a) Counters
b) State Machines
c) Adders
d) Multipliers
2. Synthesis, P&R and Post P&R simulation of the given components
a) Counters
b) State Machines
c) Adders
d) Multipliers
3. Critical paths and static timing analysis results to be identified.
4. Identify and verify possible conditions under which the blocks will fail to
work correctly.
5. Hardware fusing and testing of each of the blocks simulated in (I). Use of
either chip scope feature (Xilinx) or the signal tap feature (Altera) is a must.
Invoke the PLL and demonstrate the use of the PLL module for clock
generation in FPGAs
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR

GRAPHICS / EQUIVALENT)
6. Design and simulation of a simple 5 transistor differential amplifier. Measure

gain, ICMR, and CMRR
7. Layout generation, parasitic extraction and resimulation of the circuit
designed
a) Differential amplifier
8. Synthesis and Standard cell based design of a circuits simulated in 1(I)
above. Identification of critical paths, power consumption.
9. For expt (c) above, P&R, power and clock routing, and post P&R simulation
10. Analysis of results of static timing analysis.

SYLLABUS
EC6612 VLSI DESIGN LABORATORY
LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS.
1. HDL based design entry and simulation of simple counters, state machines,
adders (min 8 bit) and multipliers (4 bit min).
2. Synthesis, P&R and post P&R simulation of the components simulated in (I)
above. Critical paths and static timing analysis results to be identified. Identify and
verify possible conditions under which the blocks will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use of either
chipscope feature (Xilinx) or the signal tap feature (Altera) is a must. Invoke the
PLL and demonstrate the use of the PLL module for clock generation in FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR

GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier. Measure
gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and resimulation of the circuit designed in
(I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I) above.
Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R simulation.
8. Analysis of results of static timing analysis.

INDEX
NAME OF THE
EXP.NO DATE PAGE NO MARKS SIGNATURE
EXPERIMENT

Counter:
2-BIT
Truth Table:
2 Bit Counter
---------------------------------------------------
Clock Clear Output[2]
---------------------------------------------------
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 0 00
1 0 00
0 1 00
1 1 01
0 1 01
1 1 10
0 1 10
1 1 11
0 1 11
1 1 00
0 1 00
1 1 01
0 1 01
1 1 10
0 1 10
1 1 11
0 1 11
1 1 00
0 0 00
1 0 00
------------------------------------------------
Ex. No:1a IMPLEMENTATION OF COUNTERS
Date:
AIM:
To implement Counters using Verilog HDL
APPARATUS REQUIRED:
• PC with Windows XP.
• XILINX, ModelSim software.
PROCEDURE:
➢ Write and draw the Digital logic system.

➢ Write the Verilog code for above system.
➢ Enter the Verilog code in Xilinx software.
➢ Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
verify the output waveform as obtained.
Program:
COUNT2BIT
module Count2Bit(Clock, Clear, out);

input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
always@(posedge Clock, negedge Clear)
if((~Clear) || (out>=4))
out=2'b00;
else
out=out+1;
endmodule
UP/DOWN COUNTER:
module updown_counter (clk, reset, updown, q );

input clk;
input reset;
input updown;
output [3:0] q;
reg [3:0] q;
always @ (posedge reset or posedge clk)
begin
if(reset)
begin

q <= 4'b0;
end
else
Output Wave:
RIPPLE COUNTER LOGIC DIAGRAM:
Output Wave:

begin
if(updown)
begin
q <= q + 1'b1;
end
else
begin
q <= q - 1'b1;
end
end
end
endmodule
RIPPLE COUNTER:
module ripplecount(q, qb,data,clk,clr);

output [3:0] q,qb;
input clk,clr;
input data;
wire [2:0]t;
tff v0(q[0],qb[0],data,clock,clr);
and2g v1(w[0],q[0]);
tff v2(q[1]qb[1],q[0],clk,clr);
and2g v3(w[1],w[0],q[1]);
tff v2(q[2], qb[2],q[1],clk,clr);
and2g v4(w[2],q[2],w[1]);
endmodule

RESULT:
Thus the Verilog code for counter has been simulated and verified

STATE MACHINE DIAGRAM:
STATE MACHINE OUTPUT:

Ex. No:1b IMPLIMENTATION OF STATE MACHINE
Date:
AIM:
To implement state machine in Verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:

➢ Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and
Program:
State Machine:
module fsm( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin

end
2'b10:
begin
end
2'b11:
begin
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule

RESULT:
Thus the Verilog code for state machine has been simulated and verified
successfully
OUTPUT WAVEFORM (Half Adder):
OUTPUT WAVEFORM (Full Adder):
OUTPUT WAVE (addsub):

Ex. No: 1c HALF ADDER AND FULL ADDER
Date :
AIM:
To implement half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:
Hardware and software requirement:

➢ Xilinx (Alliance)/Xilinx ISE 10.1 software
➢ Personal Computer
PROCEDURE:

➢ Check the syntax and simulate the above verilog code using Xilinx and verify the output
waveform as obtained.
PROGRAM: HALF ADDER:
DATAFLOW MODELLING
module ha (a,b,s,c);
input a,b;
output s,c;
assign s = a^b;
assign c =a&b;
endmodule
BEHAVIOURAL MODELLING
module ha(a,b,s,c);
input a,b;
output s,c;
reg s,c;
always@(a or b)
begin
s =a^b;
c =a&b;
end
endmodule

STRUCTURAL MODELLING
module HalfAddr(sum, c_out, i1, i2);

output sum;
output c_out;
input i1;
input i2;
xor x1(sum,i1,i2);
and a1(c_out,i1,i2);
endmodule
PROGRAM: FULL ADDER:
DATAFLOW MODELLING:
module fa(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign sum = a^b^cin;
assign cout =(a&b)|(b&cin)|(cin&a);
endmodule
BEHAVIOURAL MODELLING:
input a,b,cin;
output sum,cout;
reg sum,cout;
always @(a or b or cin)
begin
sum =a^b^cin;
cout =(a&b)|(b&cin)|(cin&a);
end
endmodule
STRUCTURAL MODELLING:
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

8 bit ADDER:( STRUCTURAL MODELING)
module addsub(s,cout,a,b,m);
input [7:0] a,b;
input m;
output [7:0] s;
output cout;
wire [0:6]c;
wire [0:7]t;
xor2g x1(t[0],m,b[0]);
xor2g x2(t[1],m,b[1]);
xor2g x3(t[2],m,b[2]);
xor2g x4(t[3],m,b[3]);
xor2g x5(t[4],m,b[4]);
xor2g x6(t[5],m,b[5]);
xor2g x7(t[6],m,b[6]);
xor2g x8(t[7],m,b[7]);
fa x9(s[0],c[0],a[0],t[0],m);
fa x10(s[1],c[1],a[1],t[1],c[0]);
fa x11(s[2],c[2],a[2],t[2],c[1]);
fa x12(s[3],c[3],a[3],t[3],c[2]);
fa x13(s[4],c[4],a[4],t[4],c[3]);
fa x14(s[5],c[5],a[5],t[5],c[4]);
fa x15(s[6],c[6],a[6],t[6],c[5]);
fa x16(s[7],cout,a[7],t[7],c[6]);
endmodue
PARALLEL ADDER
module adder8 (a, b, cin, sum, cout);
input [7:0] a;
input [7:0] b;
inputcin;
output [7:0] sum;
outputcout;
wire [6:0] c
fulladd a1 (a[0], b[0], cin, sum[0], c[0]);
fulladd a2 (a[1], b[1], c[0], sum[1], c[1]);
fulladd a1 (a[7], b[7], c[6], sum[7], cout);
endmodule.
RESULT:
Thus the verilog code for half adder, full adder and parallel adder has been
simulated and verified successfully

4-Bit multiplier
MULTIPLIER OUTPUT:

Ex. No:1d DESIGN OF MULTIPLIERS
Date:
AIM:
To implement 4 bit multiplier using Verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:

Program:
Multiplier(Dataflow)
module mul4(a, b, result);
input [3:0] a;
input [3:0] b;
output [7:0] result;
wire [7:0] result;
assign result = a * b;
endmodule

Program:
Multiplier(Behavioral model)
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
RESULT:
Thus the verilog code for 4 bit multiplier has been simulated and verified.

2.STUDY OF SYNTHESIS TOOLS
THEORY:
Synthesis is the process of constructing a gate level netlist from a register-transfer
Level model of the circuit described in VHDL, Verilog, or mixed language designs.
The netlist files contain both logical design data and constraints.
XILINX SYNTHESIS TOOL enables us to study:
1) Utilization of LUTs & Slices
2) I/O Buffer assignment
3) RTL Schematic in gate level
4) Time delay between I/Os and path
PROCEDURE:
1. Start the Xilinx ISE by using start Program files  Xilinx ISE (8.1i)  project navigator
2. File New Project
3. Enter the Project Name and location then click next
4. Select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click next
and finish
7. Writing the behavioral Verilog Code in Verilog Editor.
8. Run the Check syntax  Process window synthesize double click check syntax and
remove errors, if present, with proper syntax & coding.
9. Synthesis your design, from the source window select, Synthesis/ implementation from the
window Now double click the Synthesis –XST
10. After the HDL synthesis phase of the synthesis process, you can display a schematic
representation of your synthesized source file. This schematic shows a representation of the
pre-optimized design in terms of generic symbols, such as adders, multipliers, counters, AND
gates, and OR gates double click View RTL Schematic
11. Double click the schematic to internal view
12. Double click outside the schematic to move one-level back
13. This schematic shows a representation of the design in terms of logic elements optimized to
the target device. For example, in terms of LUTs(Look Up Table), carry logic, I/O buffers, and
other technology-specific components
 Double click View Technology Schematic
14. Double click the schematic to inner view

15. Double click the LUT to inner view. This is Gate Level view of LUT, if you want see Truth
Table and K-Map for your design just click the respective tabs.
16. After finishing the synthesis, you can view number of Slices, LUT(Look Up
Table), I/Os are taken by your deign in Device using Design summary.

2(a) .PLACE AND ROUTE AND POST P&R FOR FPGA
THEORY:
• Back annotation is the translation of a routed or fitted design to a timing simulation netlist.
• To define the behavior of the FPGA, a hardware description language (HDL) or a schematic
design methods are used. Common HDLs are VHDL and Verilog. Then, using an electronic design
automation (EDA) tool, a technology-mapped netlist is generated.
• The netlist can then be fitted to the actual FPGA architecture using a process called place-and-
route, usually performed by the FPGA vendor’s proprietary place-and-route software.
• The user will validate the map, place and route results via timing analysis, simulation, and other
verification methodologies. Once the design and validation process is complete, the binary file generated is
used to (re)configure the FPGA.
• In an attempt to reduce the complexity of designing in HDLs, which have been compared to the
equivalent of assembly
• In a typical design flow, an FPGA application developer will simulate the design at multiple
stages throughout the design process.
• Initially the RTL description in VHDL or Verilog is simulated by creating test benches to
simulate the system and observe results.
• Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a
gate level description where simulation is repeated to confirm the synthesis proceeded without errors.
• Finally the design is laid out in the FPGA at which point propagation delays can be added and the
simulation run again with these values back-annotated onto the netlist.
• Place & Route, the process of optimization of logic cells for effective utilization of FPGA area
and the speed of operation, is used to modify and infer the following:
1) Re-assignment of Pins
2) Re-location of Slices
3) Run time minimization
PROCEDURE:
1. Start the Xilinx ISE by using startProgram files Xilinx ISE (8.1i) project navigator
2. File New Project3. Enter the Project Name and location then click next
4. Select the Device and other category and click next twice and finish
5. Click on the symbol of FPGA device and then right click click on new source
6. Select the Verilog Module and give the file name click next and define ports click next and
finish

7. Writing the behavioral Verilog Code in Verilog Editor
8. Run the Check syntax  Process window synthesize double click
check syntax
9. Synthesis your design, from the source window select, synthesis/implementation from the
window Now double click the
Synthesis -XST
10. After Synthesis you assign the Pin Value for your design so, double click the Assign
Package Pins
11. Enter the Pin value for your input and output signals. if you want see your Pin assignment in
FPGA zoom in Architecture View or Package View
12. You see the Pins in FPGA. Save file as XST Default click ok and close the window
13. Design Implementation begins with the mapping or fitting of a logical design file to a specific
device and is complete when the physical design is successfully routed and a bit stream is generated.
Double Click Implementation Design
14. After implementation you see Design Summary, you get the all details
about your design. If you want edit the place and route double click
View/Edit placed design
15. You see where your IOs are placed in FPGA. And zoom to view how Pins are placed in FPGA.
You can see where your pins are placed
16. Just double click View/Edit Routed Design to view interconnection wires and blocks
17. Click the pin to see where its placed in FPGA. And Zoom particular area
to see Place and Routing.
18. If you want to change the place of the design, click and trace to another slice.
See!!! You changed place and route of the design
19. Double click Back annotated Pin Location. Once back annotation is completed, constraint file
is generated.

Ex. No: 2a STUDY OF SYNTHESIS, P&R, POST P&R, STATIC
Date : TIMING/CRITICAL PATH FOR COUNTERS
AIM:
To simulate the synthesis for counters using verilog HDL.
APPARATUS REQUIRED:

➢ Spartan3 FPGA Trainer Kit.
➢ RS232 cable.
➢ 5V DC power cable.
PROCEDURE:
1. Start the Xilinx ISE by using start Program files  Xilinx ISE (10.1)  project
navigator
3. Before enter the Project Name,check location where you can save then click next
4. Select the Device and other category and click next twice and finish.
5. Open Design summary and select synthesis.
Program:
COUNT2BIT

input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
out=2'b00;
else
out=out+1;
endmodule

Counter P&R report
Design Summary Report:
Number of External IOBs 4 out of 158 2%
Number of External Input IOBs 2
Number of External Input IBUFs 2
Number of External Output IOBs 2
Number of External Bidir IOBs 0
Number of BUFGMUXs 1 out of 24 4%
Number of Slices 1 out of 4656 1%
Number of SLICEMs 0 out of 2328 0%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989697) REAL time: 3 secs
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 3 secs
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 3 secs
Phase 4.2.
Phase 4.2 (Checksum:26259fc) REAL time: 3 secs
Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 3 secs
Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 3 secs
Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs
Phase 8.8
Phase 8.8 (Checksum:98adef) REAL time: 5 secs
Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 5 secs
Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 5 secs
Phase 11.5
Phase 11.5 (Checksum:68e7775) REAL time: 5 secs
REAL time consumed by placer: 5 secs CPU time consumed by placer: 5

UP/DOWN COUNTER:

input clk;
input reset;
input updown;
output [3:0] q;
reg [3:0] q;
begin
if(reset)
begin
q <= 4'b0;
end
else
begin
if(updown)
begin
q <= q + 1'b1;
end
else
begin
q <= q - 1'b1;
end
end
end
endmodule
RIPPLE COUNTER:

output [3:0] q,qb;
input clk,clr;
input data;
wire [2:0]t;
and2g v1(w[0],q[0]);
and2g v3(w[1],w[0],q[1]);
and2g v4(w[2],q[2],w[1]);
endmodule

Writing design to file Count2Bit.ncd
Total REAL time to Placer completion: 6 secs
Total CPU time to Placer completion: 5 secs
Starting Router
Phase 1: 9 unrouted; REAL time: 9 secs
Phase 4: 0 unrouted; (221) REAL time: 9 secs
Total REAL time to Router completion: 9 secs
Total CPU time to Router completion: 8 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| Clock_BUFGP | BUFGMUX_X2Y10| No | 1 | 0.000 | 0.153 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
The Delay Summary Report
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
The AVERAGE CONNECTION DELAY for this design is: 0.411
The MAXIMUM PIN DELAY IS: 0.835
The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.441
Listing Pin Delays by value: (nsec)
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
8 0 0 0 0 0
Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Clo | SETUP | N/A| 1.767ns| N/A| 0
ck_BUFGP | HOLD | 1.132ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 8 secs
Peak Memory Usage: 134 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file Count2Bit.ncd
PAR done!
POST P&R REPORT FOR COUNTER
Command Line: netgen -intstyle ise -s 5 -pcf Count2Bit.pcf -sdf_anno true
-sdf_path netgen/par -insert_glbl true -insert_pp_buffers false -w -dir
netgen/par -ofmt verilog -sim Count2Bit.ncd Count2Bit_timesim.v
Read and Annotate design 'Count2Bit.ncd' ...
Loading device for application Rf_Device from file '3s500e.nph' in environment
C:\Xilinx92i.
"Count2Bit" is an NCD, version 3.1, device xc3s500e, package pq208, speed -5
Loading constraints from 'Count2Bit.pcf'...
The speed grade (-5) differs from the speed grade specified in the .ncd file
(-5).
The number of routable networks is 6
Flattening design ...
Processing design ...
Preping design's networks ...
Preping design's macros ...
Writing Verilog SDF file 'netgen\par\count2bit_timesim.sdf' ...
Writing Verilog netlist file 'C:\Xilinx92i\vh\netgen\par\Count2Bit_timesim.v'...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM simulation library for
correct compilation and simulation.
Number of warnings: 0
Total memory usage is 105828 kilobytes
STATIC TIMING ANALYSIS:
Release 9.2i Trace

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/2c/2c.ise -intstyle

ise -e 3 -s
5 -xml cntr cntr.ncd -o cntr.twr cntr.pcf
Design file: cntr.ncd

Physical constraint file: cntr.pcf
Device,speed: xc3s500e,-5 (PRODUCTION 1.26 2007-04-13)
Report level: error report
Environment Variable Effect

-------------------- ------
NONE No environment variables were set
INFO:Timing:2698 - No timing constraints found, doing default

enumeration.
INFO:Timing:2752 - To get complete path coverage, use the
unconstrained paths
option. All paths that are not constrained will be reported in
the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report
are based on
a 50 Ohm transmission line loading model. For the details of
this model,
and for more information on accounting for different loading
conditions,
please see the device datasheet.
Data Sheet report:

-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad

------------+------------+------------------+---
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
out<0> | 6.520(R)|clk_BUFGP | 0.000|
out<1> | 6.549(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 1.767| | | |
---------------+---------+---------+---------+---------+
Analysis completed Mon Apr 11 15:39:42 2016

--------------------------------------------------------------------
------------
RESULT:
Thus the Synthesis, P&R and post P&R, Static timing/ Critical path
simulation of counter was done successfully.

STATE MACHINE DIAGRAM:

Expt No:2b STUDY OF SYNTHESIS, P&R, POST P&R, STATIC TIMING/CRITICAL
PATH FOR STATE MACHINE
Date:
AIM:
To simulate the synthesis for statement using verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:

➢ Open Design summary and select synthesis.
Program:
State Machine:

output outp;
reg [1:0] state;

reg outp;

begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
end
2'b01:
begin
P&R REPORT:
Number of BUFGMUXs 1 out of 24 4%
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98969b) REAL time: 2 secs
Phase 2.7
Phase 3.31
Phase 4.2.
Phase 5.30
Phase 6.3
Phase 7.5
Phase 8.8
Phase 8.8 (Checksum:98cfaf) REAL time: 5 secs
Phase 9.5
Phase 10.18
Phase 11.5
REAL time consumed by placer: 5 secs
CPU time consumed by placer: 4 secs
end
2'b10:
begin
end
2'b11:
begin
end
endcase
end
end

begin
if( rst )
outp <= 0;
outp <= 1;
else outp <= 0;
end
endmodule

Writing design to file fsm.ncd
Starting Router
-------------------------------
-------------------------------
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X2Y10| No | 2 | 0.002 | 0.177 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
14 0 0 0 0 0

Timing Score: 0
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 2.610ns| N/A| 0
_BUFGP | HOLD | 1.279ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Writing design to file fsm.ncd
PAR done!
POST P&R REPORT:
Release 9.2i - netgen J.36
Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis
-ofmt verilog -sim fsm.ngc fsm_synthesis.v
Reading design 'fsm.ngc' ...
Writing Verilog netlist file 'C:\Xilinx92i\vh\netgen\synthesis\fsm_synthesis.v'...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
Release 9.2i Trace

C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/sm/sm.ise -intstyle

ise -e 3 -s
5 -xml fsm fsm.ncd -o fsm.twr fsm.pcf
Design file: fsm.ncd

Physical constraint file: fsm.pcf

-------------------- ------

enumeration.
unconstrained paths
the
are based on
this model,
conditions,
Data Sheet report:

-----------------
Setup/Hold to clock clk

------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
inp | 0.071(R)| 1.082(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+
Clock clk to Pad

------------+------------+------------------+--------+
| clk (edge) | | Clock |

Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
out | 5.629(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk

---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 2.610| | | |
---------------+---------+---------+---------+---------+
RESULT:
Thus the Synthesis, P&R and post P&R simulation of state machine circuits
and Critical paths/static timing analysis was done successfully

Expt. No:2c STUDY OF SYNTHESIS, P&R, POST P&R, STATIC
Date : TIMING/CRITICAL PATH FOR FOR HALF ADDER & FULL ADDER
AIM:
To simulate the synthesis for half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:

PROCEDURE:

➢ Check the syntax and simulate the above verilog code using Xilinx and verify the output
waveform as obtained.
DATAFLOW MODELLING
input a,b;
output s,c;
assign s = a^b;
assign c =a&b;
endmodule
module ha(a,b,s,c);
input a,b;
output s,c;
reg s,c;
always@(a or b)
begin
s =a^b;
c =a&b;
end
endmodule

HALF ADDER P&R REPORT:
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:98968e) REAL time: 2 secs
Phase 2.7
Phase 3.31
Phase 4.2
Phase 5.30
Phase 6.3
Phase 7.5
Phase 8.8.
Phase 8.8 (Checksum:989fdf) REAL time: 2 secs
Phase 9.5
Phase 10.18
Phase 11.5


output sum;
output c_out;
input i1;
input i2;
xor x1(sum,i1,i2);
endmodule
DATAFLOW MODELLING:
input a,b,cin;
output sum,cout;
endmodule
input a,b,cin;
output sum,cout;
reg sum,cout;
begin
sum =a^b^cin;
end
endmodule

input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule
Writing design to file ha.ncd
Starting Router
-------------------------------
-------------------------------
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
6 0 0 0 0 0
Timing Score: 0
Writing design to file ha.ncd
PAR done!
POST P&P REPORT:

-ofmt verilog -sim ha.ngc ha_synthesis.v
Reading design 'ha.ngc' ...
Writing Verilog netlist file 'C:\Xilinx92i\vh\netgen\synthesis\ha_synthesis.v'
FULL ADDER P&R REPORT:
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 2 secs
Phase 2.7

Phase 3.31
Phase 4.2
Phase 5.30
Phase 6.3
Phase 7.5
Phase 8.8.
Phase 8.8 (Checksum:98a57f) REAL time: 2 secs
Phase 9.5
Phase 10.18
Phase 11.5
Writing design to file fa.ncd
Starting Router
-------------------------------
-------------------------------
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
8 0 0 0 0 0
Timing Score: 0
Writing design to file fa.ncd
PAR done!
POST P&R REPORT:
-ofmt verilog -sim fa.ngc fa_synthesis.v
Reading design 'fa.ngc' ...
Writing Verilog netlist file 'C:\Xilinx92i\vh\netgen\synthesis\fa_synthesis.v'...

Release 9.2i Trace
C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/adr/adr.ise -intstyle

ise -e 3
-s 5 -xml addr addr.ncd -o addr.twr addr.pcf
Design file: addr.ncd

Physical constraint file: addr.pcf

-------------------- ------

enumeration.
unconstrained paths
the
are based on
this model,
conditions,
Data Sheet report:

-----------------
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a |c | 5.759|
a |s | 5.984|
b |c | 5.841|
b |s | 6.026|
---------------+---------------+---------+
Peak Memory Usage: 95
RESULT:
Thus the Synthesis, P&R and post P&R simulation of adder and Critical
paths/static timing analysis was done successful.

Expt No:2d STUDY OF SYNTHESIS, P&R, POST P&R, STATICTIMING/CRITICAL
Date: PATH FOR MULTIPLIERS
AIM:
To simulate the synthesis for multipliers using verilog HDL.
APPARATUS REQUIRED:
PROCEDURE:

Program:
Multiplier:
input [3:0] a;
input [3:0] b;
wire [7:0] result;
endmodule

P&R REPORT :
esign Summary Report:
Number of MULT18X18SIOs 1 out of 20 5%
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:9896b2) REAL time: 2 secs
Phase 2.7
Phase 3.31
Phase 4.2
Phase 5.30
Phase 6.3
Phase 7.5
Phase 8.8
Phase 8.8 (Checksum:99213f) REAL time: 2 secs
Phase 9.5
Phase 10.18
Phase 11.5
Writing design to file mul4.ncd
Starting Router
-------------------------------
-------------------------------
d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00
--------- --------- --------- --------- --------- ---------
7 8 1 0 0 0
Timing Score: 0
Writing design to file mul4.ncd
PAR done!

POST P&R REPORT :
-ofmt verilog -sim mul4.ngc mul4_synthesis.v
Reading design 'mul4.ngc' ...
Writing Verilog netlist file 'C:\Xilinx92i\vh\netgen\synthesis\mul4_synthesis.v'
STRATIC TIMING ANALYSIS:
Release 9.2i Trace

C:\Xilinx92i\bin\nt\trce.exe -ise C:/Xilinx92i/mul/mul.ise -intstyle

ise -e 3
-s 5 -xml mult mult.ncd -o mult.twr mult.pcf
Design file: mult.ncd

Physical constraint file: mult.pcf

-------------------- ------
--------------------------------------------------------------------
------------

enumeration.
unconstrained paths
the

are based on
this model,
conditions,
Data Sheet report:

-----------------
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a<0> |r<0> | 10.236|
a<0> |r<1> | 9.878|
a<0> |r<2> | 10.066|
a<0> |r<3> | 9.844|
a<0> |r<4> | 10.205|
a<0> |r<5> | 9.859|
a<0> |r<6> | 10.346|
a<0> |r<7> | 10.457|
a<1> |r<1> | 10.076|
a<1> |r<2> | 10.264|
a<1> |r<3> | 10.042|
a<1> |r<4> | 10.403|
a<1> |r<5> | 10.057|
a<1> |r<6> | 10.544|
a<1> |r<7> | 10.655|
a<2> |r<2> | 9.186|
a<2> |r<3> | 8.964|
a<2> |r<4> | 9.325|
a<2> |r<5> | 8.979|
a<2> |r<6> | 9.466|
a<2> |r<7> | 9.577|
a<3> |r<3> | 9.656|
a<3> |r<4> | 10.017|
a<3> |r<5> | 9.671|
a<3> |r<6> | 10.158|
a<3> |r<7> | 10.269|
b<0> |r<0> | 9.453|
b<0> |r<1> | 9.095|
b<0> |r<2> | 9.283|
b<0> |r<3> | 9.061|
b<0> |r<4> | 9.422|
b<0> |r<5> | 9.076|
b<0> |r<6> | 9.563|
b<0> |r<7> | 9.674|
b<1> |r<1> | 9.825|
b<1> |r<2> | 10.013|
b<1> |r<3> | 9.791|
b<1> |r<4> | 10.152|
b<1> |r<5> | 9.806|
b<1> |r<6> | 10.293|
b<1> |r<7> | 10.404|
b<2> |r<2> | 10.052|
b<2> |r<3> | 9.830|
b<2> |r<4> | 10.191|
b<2> |r<5> | 9.845|
b<2> |r<6> | 10.332|
b<2> |r<7> | 10.443|
b<3> |r<3> | 10.094|
b<3> |r<4> | 10.455|
b<3> |r<5> | 10.109|
b<3> |r<6> | 10.596|
b<3> |r<7> | 10.707|
---------------+---------------+---------+
RESULT:
Thus the Synthesis, P&R and post P&R simulation of multiplier and Critical
paths/static timing analysis was done successfully.

Expt. No:3a CLOCK GENERATION USING FPGAs FOR COUNTERS
Date :
AIM:
To implement clock generation using FPGAs for counters.
APPARATUS REQUIRED:

➢ RS232 cable.
PROCEDURE:
1. Start the Xilinx ISE by using start Program files  Xilinx ISE (10.1)  project
navigator
3. Before enter the Project Name,check location where you can save then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right click click on

6. Select the Verilog Module and give the file name click next and define ports click
next and finish.
7. Writing the behavioral Verilog Code in Verilog Editor.
8. Run the Check syntax  Process window synthesize double click check syntax
 and remove errors, if present, with proper syntax & coding.
9. Expand synthesize-XST -> (D) View technology Schematic then verify on design
process as correct or not, such as logical block, gate structures, truth table,K-map and
LUT’s block.
10. I/Os are taken by your deign in Device using Design summary.
Download Design to the FPGA:
11. Connect the 5V DC power cable to the power input on the FPGA.
12. Connect the download cable between the PC and FPGA.
13. Select Implementation from the drop-down list in the Sources window.
14. Select adder in the Sources window.
15. In the Process window, User constrains assign pin package double-click the
Configure Target Device process.
16. The Xilinx Web Talk Dialog box may open during this process. Click Decline. Impact
opens and the Configure Devices dialog box is displayed.
17. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
18. Verify that automatically connect to a cable and identify Boundary-Scan chain is
selected. Click Finish.
19. If you get a message saying that there are two devices found, click OK to continue.
The devices connected to the JTAG chain on the board will be detected and displayed
in the impact window.
20. The Assign New Configuration File dialog box appears. To assign a configuration file
to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.
21. If you get a Warning message, click OK.
22. Select Bypass to skip any remaining devices.
23. Right-click on the xc3s200 device image, and select Program... The Programming
Properties dialog box opens.
BACK ANNOTATION

PIN CONFIGURATION:
24. Click OK to program the device. When programming is complete, the Program
Succeeded message is displayed.

25. On the board click the PROG key to load the code to Spartan. Check the functionality
of the adder with the switches and LEDs.
Program:
COUNT2BIT

input Clock;
input Clear;
output [1:0] out;
reg [1:0]out;
out=2'b00;
else
out=out+1;
endmodule
UP/DOWN COUNTER:

input clk;
input reset;
input updown;
output [3:0] q;
reg [3:0] q;
begin
if(reset)
begin
q <= 4'b0;
end
else
begin
if(updown)
begin
q <= q + 1'b1;
end
else
begin
q <= q - 1'b1;
end
end
end
endmodule

PROM GENERATION FILE:
BOUNDRY SCAN:

RIPPLE COUNTER:

output [3:0] q,qb;
input clk,clr;
input data;
wire [2:0]t;
and2g v1(w[0],q[0]);
and2g v3(w[1],w[0],q[1]);
and2g v4(w[2],q[2],w[1]);
endmodule
RESULT:
Thus the clock generation of counters using FPGAs and hardware tested for
blocks was verified successfully.

Expt No:3b CLOCK GENERATION USING FPGAs FOR STATE MACHINE
Date:
AIM:
To implement state machine Verilog HDL.
APPARATUS REQUIRED:
Program:
State Machine:

output outp;
reg [1:0] state;
reg outp;
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
end
2'b01:
begin
end
2'b10:
begin
end
2'b11:
begin
end
endcase
end
end
begin
if( rst )
outp <= 0;
outp <= 1;
else outp <= 0;
end
endmodule

RESULT:
Thus the clock generation of state machine using FPGAs and hardware tested
for blocks was verified successfully.

Expt. No:3c CLOCK GENERATION USING FPGAs FOR HALF ADDER AND Date
: FULL ADDER
AIM:
To implement half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:

➢ RS232 cable.
DATAFLOW MODELLING
input a,b;
output s,c;
assign s = a^b;
assign c =a&b;
endmodule
module ha(a,b,s,c);
input a,b;
output s,c;
reg s,c;
always@(a or b)
begin
s =a^b;
c =a&b;
end
endmodule

output sum;
output c_out;
input i1;
input i2;
xor x1(sum,i1,i2);
endmodule
DATAFLOW MODELLING:
input a,b,cin;
output sum,cout;
endmodule
input a,b,cin;
output sum,cout;
reg sum,cout;
begin
sum =a^b^cin;
end
endmodule

input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
and n4(c2,s1,c_in);
or n5(c_out,c1,c2);
endmodule

RESULT:
Thus the clock generation of half adder, full adder using FPGAs and
hardware tested for blocks was verified successfully.

Ex. No:3d CLOCK GENERATION USING FPGAs FOR MULTIPLIERS
Date:
AIM:
To implement 4 bit multiplier using Verilog HDL.
APPARATUS REQUIRED:
➢ Spartan3E FPGA Trainer Kit.
➢ RS232 cable.
Program:
Multiplier:
input [3:0] a;
input [3:0] b;
wire [7:0] result;
endmodule

RESULT:
Thus the clock generation of multipliers using FPGAs and hardware tested
for blocks was verified successfully.
CIRCUIT DIAGRAM:
DIFFERENTIAL AMPLIFIER:
SCHEMATIC DIAGRAM:

Ex. No:5 DESIGN AND SIMULATION OF DIFFERENTIAL AMPLIFIER
Date:
AIM
To design and simulate the differential amplifier circuit and measure gain,ICMR,CMRR.
SOFTWARE USED
Tanner EDA Tools

(i) S-Edit
(ii) T-Edit
(iii) W-Edit
THEORY:
Differential amplifier:
A differential amplifier is a type of electronic amplifier that multiplies the difference

between two inputs by some constant factor (the differential gain). Many electronic devices use
differential amplifiers internally. The output of an ideal differential amplifier is given by:
Where Vin+ and Vin- are the input voltages and Ac is the differential gain. In practice,
however, the gain is not quite equal for the two inputs. This means that if Vin+ and Vin- are
equal, the output will not be zero, as it would be in the ideal case. A more realistic expression for
the output of a differential amplifier thus includes a second term.
Ac is called the common-mode gain of the amplifier. As differential amplifiers are often
used when it is desired to null out noise or bias-voltages that appear at both inputs, a low
common-mode gain is usually considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-mode
gain and common-mode gain, indicates the ability of the amplifier to accurately cancel voltages
that are common to both inputs. Common-mode rejection ratio (CMRR):

PROCEDURE:
1. Open a schematic editor(S-Edit) from the Tanner EDA Tools.

2. Select the required components from the symbol browser and design given circuit using S-
Edit.
3. Output waveform is viewed in the waveform viewer.
SIMULATION REPORT:
DIFFERENTIAL AMPLIFIER:
T-Spice - Tanner SPICE

Version 10.01
Network license from: LAB1-1

Product Release ID:
Copyright (c) 1993-2004 Tanner Research, Inc.
Parsing "C:\Documents and Settings\students\My Documents\Module0.sp"
Probing options:
probefilename = File0.dat
probesdbname = C:\Documents and Settings\students\My Documents\diffamp.sdb

probetopmodule = Module0
Device and node counts:
SCHEMATIC DIAGRAM:

MOSFETs - 4 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 3 Current sources - 1
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
Macro devices - 0 External C model instances - 0
Subcircuits - 0 Subcircuit instances - 0
Independent nodes - 7 Boundary nodes - 4
Total nodes - 11

SIMULATION RESULT
SIMULATION STATISTICS:
* DC operating point
* Total DC operating points =1
* Total Newton iterations = 35
* Total Current evaluations = 180
* Transient analysis
* Transient timesteps = 422

* Successful timesteps = 408
* Failed timesteps = 14
* Newton non-convergence failures = 14
* Delta voltage (dv) failures =0
* Newton iterations = 863
* Successful Newton iterations = 709

* Failed Newton iterations = 154
* Average Newton iterations/timestep = 2.045
* Average Newton iterations/success = 1.738
* Current evaluations = 2519
* Matrix statistics: OP TRAN
* Matrix factors 35 863
* Matrix solves 35 863

* Size 7 7
* Initial elements 23 27
* Final elements 25 27
* Fill-ins 2 0
* Initial density 48.92% 55.10%
* Final density 52.89% 55.10%

* Total current evaluations = 2699
* Total Newton iterations = 898
* Total matrix factorizations = 898

* Total matrix-vector solves = 898
* Total matrix solve time (seconds) = 0.015

* T-Spice process times
* Newton solver 0.03 seconds
* Current evaluations 0.02 seconds
* Jacobian construction 0.00 seconds
* Linear solver 0.01 seconds
Parsing 0.00 seconds

Setup 0.00 seconds
DC operating point 0.00 seconds
Transient Analysis 4.39 seconds
Overhead 8.11 seconds
-----------------------------------------
Total 12.50 seconds

Simulation completed

RESULT:
The design and simulation of Differential Amplifier has been performed using Tanner
EDA Tools and gain, ICMR, CMRR was measured.
LAYOUT DIAGRAM
STICK DIAGRAM

Ex. No: 6 LAYOUT DESIGN FOR CMOS INVERTER
Date:
Aim:
To draw the layout of a CMOS inverter and Differential amplifier using L-Edit of Tanner EDA
tools.
SOFTWARE USED
Tanner EDA Tools

L-Edit
DESCRIPTION
CMOS INVERTER
The NMOS transistor and the PMOS transistor form a typical complementary MOS
(CMOS) device. When a low voltage (0 V) is applied at the input, the top transistor (P-type) is
conducting (switch closed) while the bottom transistor behaves like an open circuit. Therefore, the
supply voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the
input, the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves
like an open circuit. Hence, the output voltage is low (0 V).
PROCEDURE
1. Open layout Editor (L-Edit) from Tanner EDA tools.

2. Select a New file and enter the File type and enter the cell name in the new cell section.
3. Making use of the pallets in L-edit draw the required layers for the Layout.
4. Each Layer should be based on the Lambda rules.
5. Check for DRC for any error at each level of Layer.

LAYOUT DIAGRAM
STICK DIAGRAM

DESIGN RULES:
Layer Rule Explanation Value / l

well (CWN, CWP) 1.1 minimum width 10
1.2 minimum space (different potential, a hot well) 9
1.3 minimum space (same potential) 0 or 6
1.4 minimum space (different well type) 0
active (CAA) 2.1/2.2 minimum width/space 3
2.3 source/drain active to well edge space 5
2.4 substrate/well contact active to well edge space 3
2.5 minimum space between active 0 or 4
poly (CPG) 3.1/3.2 minimum width/space 2
3.3 minimum gate extension of active 2
3.4 minimum active extension of poly 3
3.5 minimum field poly to active space 1
select (CSN, CSP) 4.1 minimum select spacing to channel of transistor 1 3
4.2 minimum select overlap of active 2
4.3 minimum select overlap of contact 1
4.4 minimum select width and spacing 2 2
active contact 6.1.a exact contact size 2¥2
6.2.a minimum active overlap 1.5
6.3.a minimum contact spacing 2
6.4.a minimum space to gate of transistor 2
L-EDIT DRC SUMMARY REPORT
EXECUTION SUMMARY
Execution Start Time

L-Edit Version
Rule Set Name MOSIS/HP 1.0U SCN3M, Tight
Metal
File name E:\Batch4\L-Edit 11.0\CMOS
Inverter.tdb
Cell Name Students
Computer Name LAB1-2
Memory used at start 11.3M

CIRCUIT DIAGRAM:
CMOS INVERTER:
Analog Simulation
Analog Simulation

10.5c Pad to Unrelated-Act Space (15um)
18.3 Active Overlap of well-Cap-Poly (Covered by Other rules)
18.4 PolyCnt to Well-Cap Active (Covered by other rules)
Acute Angles 0
All Angle Edges 0
Offgrid Disabled
Zero-Width wires 0
Polygons with over 199 Vertices 0
Wires with over 200 vertices 0
Self intersections 0
Wire Join/End styles 0
CELL WITH ERRORS FOUND:-
RESULTS SUMMARY
DRC Errors generated 0

CPU Time 00:00:11
Real Time 00:00:11
Input Object 30 (30)

Rules executed 80
Geometry Flags Executed 7
Disabled Rules 9
MOS LAYOUT
We use MICROWIND2 to draw the MOS layout and simulate its behavior. Go to the
directory in which the software has been copied (By default MICROWIND2). Double-click on the
MicroWind2 icon. The MICROWIND2 display window includes four main windows: the main
menu, the layout display window,the icon menu and the layer palette. The layout window features
a grid, scaled in lambda units. The lambda unit is fixed to half of the minimum available
lithography of the technology. The default technology is a CMOS 6-metal layers 0.25μm
technology, consequently lambda is 0.125 μm.
RESULT:
Thus the Layout design of a CMOS inverter and differential amplifier has been drawn and
checked for DRC using L-Edit of Tanner EDA Tools.
DIFFERENTIAL AMPLIFER:
OUTPUT OF POWER CONSUMPTION:

Ex. No: 7 LAYOUT DESIGN FOR
Date: DIFFERENTIAL AMPLIFIER AND UNIVERSAL GATES
Aim:
To identify the power consumption of Differential amplifier using L-Edit of Tanner EDA tools.
SOFTWARE USED
Tanner EDA Tools

L-Edit
PROCEDURE
1. Open layout Editor (L-Edit) from Tanner EDA tools.

2. Select a New file and enter the File type and enter the cell name in the new cell section.
3. Making use of the pallets in L-edit draw the required layers for the Layout.
4. Each Layer should be based on the Lambda rules.
5. Check for DRC for any error at each level of Layer.

L-Edit DRC Log:-
Running DRC Standard Rule Set
Rule Set Name MOSIS/HP 1.0U SCN3M, Tight Metal
Execution Start Time
INPUT LAYER SUMMARY
Layer Name Object Count Flattened

Active 4 4
Active Contact 6 6
Cap Well 0 0
Metal 1 12 12
Metal 1-Tight 0 0
Metal 2 0 0
Metal 2-Tight 0 0
Metal 3 0 0
N Select 2 2
N Well 1 1
Overglass 0 0
P Select 2 2
Pad Comment 0 0
Poly 3 3
Poly Contact 0 0
Resistor ID 0 0
Via 1 0 0
Via 2 0 0

RESULT:
Thus the Layout design of a differential amplifier has been drawn and checked for power
consumption using L-Edit of Tanner EDA Tools.

Ex. No: 8 IMPLEMENTATION OF FLIP FLOPS
Date:
AIM
To simulate the verilog coding for D,,T,JK and SR flip flops.
APPARATUS REQUIRED:
PROCEDURE:

➢ Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
Program:
D Flip-Flop
module DFF(Clock, Reset, d, q);

input Clock;
input Reset;
input d;
output q;
reg q;
always@(posedge clock or negedge reset)
if (~Reset) q=1'b0;
else
q=d;
endmodule
JK Flip-Flop
module JKFF(Clock, Reset, j, k, q);
input Clock;
input Reset;
input j;
input k;
output q;
reg q;
always@(posedge Clock, negedge Reset) if(~Reset)
q=0;
else
begin
case({j,k})
2'b00: q=q;
2'b01: q=0;
2'b10: q=1;
2'b11: q=~q;

endcase
end
endmodule
T- Flip-Flop
module TFF(Clock, Reset, t, q);

input Clock;
input Reset;
input t;
output q;
reg q;
always@(posedge Clock , negedge Reset)
if(~Reset)
q=0;
else if (t) q=~q;
else q=q;
endmodule
SR-Flip-Flop
module sr_flip_flop ( s ,r ,clk ,reset ,q ,qb ); wire clk ; else if (s==1 && r==1) begin
output q ; input reset ; wire reset; qb <= 1'bZ;
reg q ; always @ (posedge (clk)) end
begin end
output qb ; if (reset) begin end
reg qb ; q <= 0; qb <= 1; endmodule
input s ; end
wire s ; else begin
input r ; if (s!=r) begin
wire r ; q <= s;
input clk ; qb <= r;
wire reset ; end

RESULT:
Thus the verilog code for Flip-Flops has been simulated and verified.

Ec6612-Vlsi Design Lab Observation: Name Regno Class/Sem

Enviado por

Dados do documento

Título original

Direitos autorais

Formatos disponíveis

Compartilhar este documento

Compartilhar ou incorporar documento

Opções de compartilhamento

Você considera este documento útil?

Este conteúdo é inapropriado?

Direitos autorais:

Formatos disponíveis

Ec6612-Vlsi Design Lab Observation: Name Regno Class/Sem

Enviado por

Direitos autorais:

Formatos disponíveis

EC6612-VLSI DESIGN

EC-6612 VLSI DESIGN LAB – RECORD 1

IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR

6. Design and simulation of a simple 5 transistor differential amplifier. Measure

EC-6612 VLSI DESIGN LAB – RECORD 3

LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS.

IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR

EC-6612 VLSI DESIGN LAB – RECORD 5

EC-6612 VLSI DESIGN LAB – RECORD 7

➢ Write and draw the Digital logic system.

module Count2Bit(Clock, Clear, out);

module updown_counter (clk, reset, updown, q );

EC-6612 VLSI DESIGN LAB – RECORD 9

RIPPLE COUNTER LOGIC DIAGRAM:

EC-6612 VLSI DESIGN LAB – RECORD 10

module ripplecount(q, qb,data,clk,clr);

EC-6612 VLSI DESIGN LAB – RECORD 11

EC-6612 VLSI DESIGN LAB – RECORD 13

STATE MACHINE OUTPUT:

EC-6612 VLSI DESIGN LAB – RECORD 14

➢ Write and draw the Digital logic system.

module fsm( clk, rst, inp, outp);

EC-6612 VLSI DESIGN LAB – RECORD 15

EC-6612 VLSI DESIGN LAB – RECORD 16

OUTPUT WAVEFORM (Full Adder):

OUTPUT WAVE (addsub):

EC-6612 VLSI DESIGN LAB – RECORD 18

Hardware and software requirement:

➢ Write and draw the Digital logic system.

PROGRAM: HALF ADDER:

EC-6612 VLSI DESIGN LAB – RECORD 19

module HalfAddr(sum, c_out, i1, i2);

PROGRAM: FULL ADDER:

EC-6612 VLSI DESIGN LAB – RECORD 20

output [7:0] sum;

fulladd a1 (a[0], b[0], cin, sum[0], c[0]);

fulladd a2 (a[1], b[1], c[0], sum[1], c[1]);

fulladd a3 (a[2], b[2], c[1], sum[2], c[2]);

fulladd a4 (a[3], b[3], c[2], sum[3], c[3]);

fulladd a5 (a[4], b[4], c[3], sum[4], c[4]);

fulladd a6 (a[5], b[5], c[4], sum[5], c[5]);

fulladd a7 (a[6], b[6], c[5], sum[6], c[6]);

fulladd a1 (a[7], b[7], c[6], sum[7], cout);

EC-6612 VLSI DESIGN LAB – RECORD 22

EC-6612 VLSI DESIGN LAB – RECORD 23

➢ Write and draw the Digital logic system.

EC-6612 VLSI DESIGN LAB – RECORD 24

EC-6612 VLSI DESIGN LAB – RECORD 26

Synthesis is the process of constructing a gate level netlist from a register-transfer

XILINX SYNTHESIS TOOL enables us to study:

1) Utilization of LUTs & Slices

2) I/O Buffer assignment

3) RTL Schematic in gate level

4) Time delay between I/Os and path

14. Double click the schematic to inner view

EC-6612 VLSI DESIGN LAB – RECORD 28

3) Run time minimization

EC-6612 VLSI DESIGN LAB – RECORD 30

8. Run the Check syntax  Process window synthesize double click

View/Edit placed design

to see Place and Routing.

See!!! You changed place and route of the design

EC-6612 VLSI DESIGN LAB – RECORD 32