Enhanced VHDL for Better

Design and Verification

AVMS VI-03 Seminar
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Aldec Background
• Aldec was established in 1984 and is focused on delivering design
verification solutions to FPGA and ASIC designers.
• Direct Offices in: Europe, United States, China and Japan, all other
territories supported via local distributors.
• Aldec focus
 Verification Solutions
Mixed VHDL, Verilog, SystemVerilog, and SystemC
simulator
Assertions (PSL and SVA) and LINT Support
Graphical design creation and debugging tools
 Hardware-assisted Verification Solutions
Hardware acceleration and prototyping in FPGA‟s
Software-Hardware Co-verification for embedded CPUs

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Aldec Website
• www.aldec.com provides the following
resources:
 Access to Mixed Language Simulator for 20 day
evaluation at no cost
 Encrypted IP Cores for functional validation in Aldec
simulator
 Language Tutorials (VHDL and Verilog)
 Recorded AVMS (Aldec Verification Methodology Series)

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Agenda
• VHDL history
• What‟s new in the forthcoming standard?
• Enhanced packages & operators
• Enriched language Constructs
• VHPI & PSL
• Encryption/Decryption envelopes for IP
• Conclusion

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VHDL History
VHDL Timeline
2010
VHDL 2006 officialy released
by Accellera
IEEE started efforts for VHDL
2005
200X, 2003
Took over by Accellera, 2005
VHDL 2002 released
2000
Year

1995
VHDL 1993 released

1990

VHDL 1987 released

1985 Contract given to TI,IBM and

Intermetrics, 1983 VHDL version 7.2 released ,
1985
VHDL concepts discussed,
1981
1980
DoD launched VHSIC Project
Progress

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What’s new in the forthcoming

standard?
• Deals with the issues reported after VHDL 2002
• Unified multiple standards branching from the original standard
• Synthesizable Packages supporting fixed-point arithmetic
• Newly added language constructs and operators
• Interface between VHDL and C/C++ code has been introduced in
new standard
• Allowing better assertions support and safer design with PSL
subset
• Encryption/decryption for protecting Intellectual Property

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Enhanced Packages & Operators

• Commonly used Packages,
 STD_LOGIC_1164 from IEEE Std 1164-1993
 MATH_REAL and MATH_COMPLEX from IEEE Std 1076.2-1996
 NUMERIC_BIT and NUMERIC_STD from IEEE Std 1076.3-1997
Now within one, 1076 standard
• Also the functionality of STD_LOGIC_TEXTIO is included in
STD_LOGIC_1164
• Newly added Packages for arithmetic operation:
 NUMERIC_BIT_UNSIGNED
 NUMERIC_STD_UNSIGNED
Replaces Synopsys Packages std_logic_arith & std_logic_unsigned
• Also synthesizable fixed and floating point Packages are included:
 FIXED_GENERIC_PKG and FIXED_PKG
 FLOAT_GENERIC_PKG and FLOAT_PKG
• New Package ENV contains declarations that provide a VHDL interface
to the host environment
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Fixed and Floating type Packages

• Fixed Point Types:
 type ufixed is array (INTEGER range <>) of STD_LOGIC;
 type sfixed is array (INTEGER range <>) of STD_LOGIC;
• Fixed Point Format:
 constant A : ufixed(3 downto -3) := "0110100";

• Standard-compliant Floating Point Types:

 Float32 – 32-bit IEEE 754 single precision floating point
 Float64 – 64-bit IEEE 754 double precision floating point
 Float128 – 128-bit IEEE 854 extended precision floating point
• Floating point usage:
 use ieee.float_pkg.all;
variable x, y, z : float (5 downto -10);

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Package ENV
• New ENV Package providing interface to host environment
• It contains procedures STOP, FINISH and function
RESOLUTION_LIMIT

 package ENV is
procedure STOP ( STATUS: INTEGER );
procedure FINISH ( STATUS: INTEGER );
function RESOLUTION_LIMIT return DELAY_LENGTH;
end package ENV;

• Usage:
 use std.env.all ;
. . .
Test : process begin
. . .
Stop ;
end process Test

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Operators
• and, or, nand, nor, xor, and xnor can now be used as unary operators
 With reduction unary operator,
Vec_1 <= xor d_in ;
Without reduction unary operator,
Vec_1 <= d_in(7) xor d_in(6) xor d_in(5) xor
d_in(4) xor d_in(3) xor d_in(2) xor
d_in(1) xor d_in(0) ;
• Operators can now accept mixture of scalar and array operands, e.g.
MY_VEC xor MY_BIT to control polarity of the vector by one bit
 signal Sel : std_logic ;
signal X, Y : std_logic_vector(3 downto 0) ;
. . .
T <= (Y and Sel) ;
Value of Sel will be adjusted to form an array
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Operators (cont)
• Unary condition operator (??) allows conversion of logic values ('0', '1',
'H', etc.) to TRUE or FALSE value
 For example,
if (X='1' and Y='0') then
 Can be written as,
if ??(X and not Y) then

• New matching operators (?=, ?/=, ?<, ?<=, ?> and ?>=) have been
added
 For Example,
"1---" ?= "1001" yields '1'
• Logical shift and rotate operators were added to STD_LOGIC_1164
package
• Modulus and remainder can now be used for physical type operands
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Language Constructs-Types
• New functions MINIMUM, MAXIMUM, TO_STRING are available for
predefined scalar and array types
 function MINIMUM (L, R: T) return T;
function MAXIMUM (L, R: T) return T;
function TO_STRING (VALUE: T) return STRING;
• RISING_EDGE and FALLING_EDGE functions now work with BIT and
BOOLEAN
 function RISING_EDGE (signal S: BOOLEAN) return
BOOLEAN;
function FALLING_EDGE(signal S: BOOLEAN) return
BOOLEAN;
• Several new, predefined types were added:
 BOOLEAN_VECTOR, INTEGER_VECTOR, REAL_VECTOR,
TIME_VECTOR
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Language Constructs- Assignment

• Conditional assignments for signals and variables in sequential code
 Portion of the process code:
if (sig1 = '1') then
red_light <= FLASH ;
else
red_light <= IDLE ;
end if ;
Can be written as,
red_light <= FLASH when (sig1 = '1') else IDLE ;
Similar syntax works for variable assignment:
red_light_var := FLASH when (sig1 = '1') else IDLE ;

• Force and release assignments are possible now, affecting driving (out mode)
or effective (in mode) signal value:
 Sig1 <= force '1';
Port1 <= release out;
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Language Constructs- Case

• More expressions are static now (e.g. '0'&'1'&'0') making case
statement much easier to write in VHDL 2006
 case std_logic_vector'(A & B & C & D) is

• In addition to ordinary case statement, new matching case statement

is available now:
 It requires additional “?” symbols to signify that matching equality
operator is used for comparing case expression value with choices.
Ideal for description of priority encoders/decoders
case ? sel is
when "1--" => Z <= A;
when "01-" => Z <= B;
when "001" => Z <= C;
when others => Z <= '0';
end case ?;

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Language Constructs- Generate

• Enriched if/generate with elsif/else clauses and added case/generate to
forthcoming standard
 Improved if/generate statement
L2: if A1: max_latency < 10 generate
multiplier1: parallel_multiplier port map ( ... );
else A2: generate
multiplier1: sequential_multiplier port map ( ... );
end generate L2;
 Added case/generate statement
L1: case verify_mode generate
when V_rtl: all_rtl | cpu_rtl =>
CPU1: entity work.cpu(rtl) port map ( ... );
when V_bfm: others =>
CPU1: entity work.cpu(bfm) port map ( ... );
end generate L1;

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Language Constructs- Process

• Processes benefit from previously mentioned changes (more
assignment flavors, matching case, etc.)
• Now you can use all keyword in the sensitivity list of a process
describing combinatorial logic
Mux: process(all)
begin
case sel is
when "00" => d_out <= X ;
when "01" => d_out <= Y ;
when "10" => d_out <= Z ;
when others => d_out <='0';
end case ;
end process

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Language Constructs- Subprograms

• Both subprogram kinds (procedures and functions) support
generics. Generic declarations and generic maps can be
specified in subprogram header
• Uninstantiated subprogram cannot be called directly
-- Uninstantiated function:
function multiply_u generic (size : natural)
parameter (L,R : signed) return signed is

-- Generic-mapped function:
function multiply_gm generic (size : natural)
generic map (size => 16)
parameter (L,R : signed) return signed is

-- Instantiated function:
function multiply_i is new multiply_u
generic map (size => 16);

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Language Constructs- Subprograms

• Package declarations can also have package headers that deal
with generics, creating simple, uninstantiated or generic-
mapped packages
Example of a standard, uninstantiated package:

package fixed_generic_pkg is
generic (
-- Rounding routine to use in fixed point, fixed_round or fixed_truncate
fixed_round_style : fixed_round_style_type := fixed_round;
-- Overflow routine to use in fixed point, fixed_saturate or fixed_wrap
fixed_overflow_style : fixed_overflow_style_type :=
fixed_saturate;
-- Extra bits used in divide routines
fixed_guard_bits : NATURAL := 3;
-- If TRUE, then turn off warnings on "X" propagation
no_warning : BOOLEAN := false );
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VHDL Procedural Interface

• VHPI is an application-programming interface to VHDL tools that
allows access to a VHDL model from external programs
• VHPI consists of two aspects:
 An information model that represents the topology and state of a VHDL
model
 Library Information model
 Design hierarchy information model
 A number of functions that operate on the information model to access or
affect the state of the VHDL model
 Information access functions
 Property access functions
• VHPI callbacks: Mechanism to gain control during execution
 Enable state
 Disable state
 Mature state
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Property Specification Language

• VHDL uses simple subset of PSL – set of constructs that assume
linear time flow and can be simulated
• PSL extends the grammar of VHDL expressions to allow PSL
expressions, PSL built-in function calls, and PSL union expressions as
sub expressions
• PSL declaration can be placed in packages and declarative regions of
entity, architecture, and block
• PSL uses temporal logic to specify properties (sets of conditions that
span a period of time):
 “whenever REQ is activated, ACK follows within next three cycles”
is an example of property, which can be written in PSL as:
always (REQ -> next_e[1 to 3](ACK))

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IP Protection
• Protect tool directives allow encryption of portions in VHDL
descriptions
• Directives are used to form protection envelopes, which include
specification of cryptographic methods and keys to be used by a
tool
 `protect begin
 `protect end
 `protect encoding
 `protect viewport
• Different mechanism for the protection
 Simple protection envelopes
 Digital envelopes
 Digital signatures
• Decryption tool, after processing a decryption envelope shall
conform to standard restrictions
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Miscellaneous
• Hwrite, Hread, Owrite and Oread have been added
 Read and write for Hex and Octal array types is possible
• Signal expression can be placed within port maps
 port map ( X, Y and Z, D) ;
• Replication of „X‟ and „Z‟ is possible
 8X“ZZ" = “ZZZZZZZZ"
• Delimited comments are allowed:
/* C-Type delimited comment example */
• Context declaration allows you to bundle frequently used
library and use clauses
 context IEEE_STD_CONTEXT is
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
end context IEEE_STD_CONTEXT;

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Conclusion
• The new VHDL standard features presented here can be helpful
to design community in many different ways:
 Prioritized proposal and issues since 2002 have been addressed
 With improved construct support its easy to write better and compact
code
 Unification of the Packages leads towards simplified project
management
 VHPI will provide the better communication between different
application
 PSL subset will bring the reliability to the code
 Encryption will allow the authors to provide IP to the users in more
secured way
 Maintained VHDL nature, style and backward compatibility will help
users to adopt easily

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References
• www.accellera.org
• www.eda.org
• www.synthworks.com
• www.klabs.org

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