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0542F–PEEPR–2/09
2. Pin Configurations 2.2 32-lead Flatpack – Top View
A17
A14
WE
NC
NC
NC
NC
6
5
4
3
2
1
44
43
42
41
40
A12 7 39 A13
A7 8 38 A8
A6 9 37 A9
A5 10 36 A11
NC 11 35 NC
NC 12 34 NC
NC 13 33 NC
A4 14 32 NC
A3 15 31 OE
A2 16 30 A10
A1 17 29 CE
18
19
20
21
22
23
24
25
26
27
28
A0
I/O0
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
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0542F–PEEPR–2/09
AT28C040
3. Block Diagram
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
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0542F–PEEPR–2/09
5. Device Operation
5.1 Read
The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4 AT28C040
0542F–PEEPR–2/09
AT28C040
5
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6. DC and AC Operating Range
AT28C040-20 Operation
Read Program
Industrial -40°C - 85°C -40°C - 85°C
Operating Temperature (Case)
Extended -55°C - 125°C -40°C - 85°C
VCC Power Supply 5V ± 10% 5V ± 10%
7. Operating Modes
Mode CE OE WE I/O
Read VIL VIL VIH DOUT
Write(2) VIL VIH VIL DIN
Write Inhibit X X VIH
Write Inhibit X VIL X
Output Disable X VIH X High Z
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
8. DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN = 0V to VCC + 1V 10 µA
ILO Output Leakage Current VI/O = 0V to VCC 10 µA
ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 50 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 2.1 mA 0.45 V
VOH1 Output High Voltage IOH = -400 µA 2.4 V
VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V
6 AT28C040
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AT28C040
9. AC Read Characteristics
AT28C040-20
Symbol Parameter Min Max Units
tACC Address to Output Delay 200 ns
tCE(1) CE to Output Delay 200 ns
tOE(2) OE to Output Delay 0 55 ns
tDF(3)(4) CE or OE to Output Float 0 55 ns
tOH Output Hold from OE, CE or Address, whichever occurred first 0 ns
Notes: 1. CE May be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
tR, tF < 5 ns
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0542F–PEEPR–2/09
14. AC Write Characteristics
Symbol Parameter Min Max Units
tAS, tOES Address, OE Set-up Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Set-up Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE) 100 ns
tDS Data Set-up Time 50 ns
tDH, tOEH Data, OE Hold Time 0 ns
15.1 WE Controlled
15.2 CE Controlled
8 AT28C040
0542F–PEEPR–2/09
AT28C040
Notes: 1. A8 through A18 must specify the page address during each high to low transition of WE (or CE).
2. OE must be high only when WE and CE are both low.
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0542F–PEEPR–2/09
18. Software Data 19. Software Data
Protection Enable Algorithm(1) Protection Disable Algorithm(1)
LOAD DATA AA LOAD DATA AA
TO TO
ADDRESS 5555 ADDRESS 5555
Notes: 1. A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above.
2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must
be the same for each high to low transition of WE (or CE).
3. OE must be high only when WE and CE are both low.
10 AT28C040
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AT28C040
11
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25. Ordering Information
Package Type
32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
Options
Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
12 AT28C040
0542F–PEEPR–2/09
AT28C040
PIN #1 ID
9.40(0.370)
6.86(0.270)
0.51(0.020)
0.38(0.015)
21.08(0.830)
20.60(0.811)
1.27(0.050) BSC
3.05(0.120)
0.18(0.007) 2.49(0.098)
0.10(0.004)
10.36(0.408)
9.02(0.355) 1.14(0.045)
0.66(0.026)
1.83(0.072)
0.76(0.030)
10/21/03
TITLE DRAWING NO. REV.
2325 Orchard Parkway
32F, 32-lead, Non-windowed, Ceramic Bottom-brazed 32F B
R San Jose, CA 95131
Flat Package (FlatPack)
13
0542F–PEEPR–2/09
26.2 44L – LCC
2.74(0.108)
2.16(0.085)
16.81(0.662)
16.26(0.640)
2.03(0.080)
1.40(0.055)
PIN 1
1.40(0.055)
1.14(0.045) INDEX CORNER
2.41(0.095)
1.91(0.075)
0.635(0.025)
X 45˚
0.381(0.015)
0.305(0.012)
RADIUS
0.178(0.007)
12.70(0.500) BSC
0.737(0.029)
0.533(0.021)
2.16(0.085)
12.70(0.500) BSC 1.65(0.065)
04/11/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless 44L A
R San Jose, CA 95131 Chip Carrier (LCC)
14 AT28C040
0542F–PEEPR–2/09
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0542F–PEEPR–2/09