DELL D620 Schematics Document (UMA) - LA-2791

A B C D E
COMPAL CONFIDENTIAL
MODEL NAME : HAL00
1 1
PCB NO : LA-2791
COMPAL P/N : 45135631L01
Travis (UMA) Schematics Document 2
uFCPGA Mobile Yonah

Intel Calistoga + ICH7M
2006-01-20
3
REV : 1.0 (DELL: A00) 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Number Description
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
DAA0000040L PCB ZJX LA-2791 BOM NO. 45135631L01 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover Sheet
REV0 M/B UMA
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PCB P/N: DA800002L1L PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-2791 0.6
Date: Tuesday, February 07, 2006 Sheet 1 of 63

A B C D E
A B C D E
Compal confidential
Block Diagram
Model : HAL00
FAN Thermal Pentium-M

FAN1_VOUT GUARDIAN II Yonah-2M
page 18
1 EMC4000 uFCPGA CPU CPU ITP Port Clock Generator 1
+3.3V_SUS page 18 +1.05V_VCCP (1.05V) SLG84450VTR
+VCC_CORE 478pin page 7,8,9 +1.05V_VCCP page 7 +3.3V_RUN page6
H_A#(3..31) H_D#(0..63)
System Bus
FSB 533/667 MHz
RGB CRT CONN
+5V_RUN page 20 RGB INTEL Memory BUS DDRII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 ,8
LVDS CONN Calistoga (DDR2) +1.8V_SUS 533 / 667MHz
page 16,17
on M/B Board page 19 LVDS +1.5V_RUN
+0.9V_DDR_VTT
+1.8V_SUS
DVI DVI Bridge DVO 1466pin BGA +1.8V_SUS
+1.05V_VCCP (1.05V)
SI1362 page 19
+3.3V_RUN
TV +2.5V_RUN Smart Card
page 10,11,12,13,14,15
HUB USB[3]
OZ77C6 SLOT
+3.3V_RUN page 31
2 DMI USB[5,6] REAR USB Ports X2 USB4 on right side of 2
+1.5V_RUN connector, USB6 on left side

PCI BUS +3.3V_RUN 33MHz 100MHz +5V_SUS page 32
48MHz USB[3,4] SIDE USB Ports X2

DOCKING DOCKING CardBus IDSEL:AD17 INTEL +5V_SUS IO/B
PORT BUFFER OZ601 TQFP (PIRQC,D#,GNT#1,REQ#1)
ICH7-M
+3.3V_RUN
PAGE 36 +5VRUN PAGE 35 +3VRUN page 30 Azalia I/F USB0 on the top of connector,
+3.3V_SUS
USB[7] HUB USB[1] 652pin BGA ATA100 USB2 on the bottom
+1.5V_RUN
+3.3V_RUN/ +1.5V_RUN 100MHz PCI Express BUS
+1.05V_VCCP
page 21,22,23,24 SATA
SPI
+3VRUN USB[2]
Mini Card2 Mini Card 1 GIGA Enthernet 33MHz LPC BUS M DC
WLAN WWAN BCM5752 USB[1] +3.3V_SUS
+3.3V_RUN +3.3V_RUN +3VLAN page 33
+1.5VRUN page 34 +1.5VRUN page 34 page 28,29
3 3
HUB USB[1] Cable
SMSC SIO Azalia Codec
USB[0] HUB USB[2] S-HDD D Moudle
HUB USB[4] ECE5018 HUB USB[2] STAC9200
RJ45 +3.3V_RUN
RJ11
IO/B HUB USB[3] +5VHDD +5VMOD
+3VALW page 38 page 25 page 25 +VDDA page 26 IO/B
SPI
1.8V/0.9V 1.5V/1.05V Bluetooth
+3.3V_RUN page 33
MEC5004
+RTC_CELL
page 48 page 47
Power Sequence
+3.3V_ALW page 39
AMP & INT. INT MIC HeadPhone &
page 42
VCORE (IMVP-6) DC IN Speaker +5V_SUS MIC Jack
page 49 page 44 COM +5V_SUS page 27 +3.3V_RUNpage 27
page 37
Power On/Off Int.KBD & ST M25P80
+3.3V_ALW page 39
CHARGER BATT IN SW & LED Stick page 40
page 43
4
page 50 page 45 FIR 4
+3.3V_RUN page 37
Stick Touch Pad
BATT SELECT 3V/5V/15V DC/DC Interface DELL CONFIDENTIAL/PROPRIETARY
+5V_RUN page 33
page 51 page 46 page 41 Compal Electronics, Inc.
Title
Block Diagram
Size Document Number Rev
0.6
LA-2791
A B C D E
5 4 3 2 1
PCI TABLE
Ceramic Capacitors :
PCI DEVICE IDSEL REQ#/GNT# PIRQ
0.1U_0402_6.3VXX
Tolerance CARD BUS AD17 1 C
D D
Temperature Characteristics
Rated Voltage
Package Size
Value
PM TABLE
+5V_RUN
+3.3V_SRC +3.3V_RUN
Tantalum or Polymer Capacitors : power +5V_ALW

+15V_SUS
+5V_SUS
+3.3V_RUN_R
+1.8V_RUN
plane
+3.3V_ALW +3.3V_SUS +0.9V_DDR_VTT
10U_D2_10VX_R45 +1.8V_SUS +1.5V_RUN

+VCC_CORE
State
+1.05V_VCCP
C
Low ESR Mark : 45 m ohm +2.5V_RUN
C
Tolerance S0 ON ON ON
Rated Voltage S1 ON ON ON
Package Size S3 ON ON OFF
Value S5 S4/AC ON OFF OFF
S5 S4/AC don't exist OFF OFF OFF
Capacitor Spec Guide:

USB TABLE
Temperature Characteristics:
B
Symbol 0 1 2 3 4 5 6 7 USB PORT# DESTINATION USB HUB DESTINATION B
CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R
0 Mini 2(WLAN) 1 PC Card Bay

8 9 A B C D E F G
NPO COG X6S BJ CH CJ CK SH SJ

1 USB Hub (5018) 2 Mini 1(WWAN)
H I J K
2 D Moudle 3 Smart Card --> BIO
UJ UK SL X5S
3,4 SIDE 4 Blue tooth

Tolerance:
Symbol A B C D F G H J
5,6 REAR
CODE +-0.05PF +-0.1PF +-0.25PF +-0.5PF +-1PF +-2% +-3% +-5%
A K M N P Q V X Z 7 Docking A
+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20% NOTE1:

@XX : Depop component DELL CONFIDENTIAL/PROPRIETARY
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.6
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
ADAPTER
RUN_ON
+PWR_SRC FDS4435 +INV_PWR_SRC
BATTERY
ALWON
+5V_ALW
MAX8734 ALWON
ISL6260 ISL6227 MAX88550
C C
+3.3V_ALW
SUSPWROK_5V
RUN_ON
RUNPWROK
SUS_ON
SUS_ON
RUNPWROK
RUNPWROK
+5V_SUS +3.3V_SRC +VCC_CORE +1.5V_RUN +1.05V_VCCP +1.8V_SUS +0.9V_DDR_VTT
AUDIO_AVDD_ON
HDDC_EN#
ENAB_3VLAN
RUN_ON
RUN_ON
RUN_ON
B B
RUN_ON
(Option)
SI3456 SI3456 793475 PL8 SI4800 SI3456 SI4800 SI4800 SI3456

MODC_EN#
+VDDA +15V_SUS
+5V_SATA +5V_RUN +3.3V_RUN +3VLAN +3.3V_SUS +3.3V_RUN_R +1.8V_RUN
SI3456
L47
EMC4000
MOD
(+5VRUN)
A A
+2.5V_RUN
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
LA-2791
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS +3.3V_RUN
2.2K 2.2K 2.2K 2.2K
+3.3V_SUS
C22 ICH_SMBCLK CLK_SCLK 16
2N7002
D D
ICH7-M ICH_SMBDATA CLK GEN.

B22 CLK_SDATA 17
2N7002
32 30 C7 C8 32 30
SMBUS Address [D2]
+3.3V_ALW 5752M
WWAN WLAN 197
LOM
SMBUS Address [TBD] SMBUS Address [C8] SMBUS Address [TBD]
DIMM0
10K 10K
195
6 CLK_SMB 8 SMBUS Address [A0]
DAT_SMB +3.3V_ALW GUARDIAN 197

5 7 SMBUS Address [2F]
DIMM1
195
+3.3V_ALW
SMBUS Address [A2]
C C
8.2K 8.2K
10 DOCK_SMB_CLK 39
DOCK_SMB_DAT +3.3V_ALW DOCKING SMBUS Address [C4, 72, 70, 48]

9 40
SIO +3.3V_ALW
100
3
2'nd
4.7K 4.7K SMBUS Address [16]
4 BATTERY
SBAT_SMBCLK 100
112 6
Macallan IV SBAT_SMBDAT +3.3V_ALW INV Inverter

111 5
SMBUS Address [58]
B B
+3.3V_ALW
8.2K 8.2K
PBAT_SMBCLK 100
8 3
BATTERY
PBAT_SMBDAT +3.3V_ALW SMBUS Address [16]
7 4 CONN
100
9
10 CHARGER SMBUS Address [12]
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SMBUS TOPOLOGY
LA-2791
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +CK_VDD_MAIN CLK_CPU_ITP 2 1

D R369 49.9_0402_1%~D
+3.3V_RUN +CK_VDD_MAIN CLK_CPU_ITP#
1 2 2 1
2.2K_0402_5%~D
2.2K_0402_5%~D
1 L40 1 1 1 1 1 1 R377 49.9_0402_1%~D
1
1 BLM21PG600SN1D_0805~D CLK_MCH_BCLK 2 1
G 2 3 S C326 C402 C384 C58 C64 C389 C70 R349 49.9_0402_1%~D
R270
R275
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D CLK_MCH_BCLK# 2 1
0.1U_0402_16V4Z~D 2 2 2 2 2 2 R360 49.9_0402_1%~D
2 CLK_CPU_BCLK 2 1
2N7002
2
+CK_VDD_MAIN2 R322 49.9_0402_1%~D
ICH_SMBDATA CLK_SDATA CLK_CPU_BCLK# 2
S
23,28,34 ICH_SMBDATA 1 3 CLK_SDATA 16,17 1
R338 49.9_0402_1%~D
Q36 1 2 CLK_MCH_3GPLL 1 2
2N7002W-7-F_SOT323~D L32 1 1 1 R392 49.9_0402_1%~D
G
2
BLM21PG600SN1D_0805~D CLK_MCH_3GPLL# 1 2
D C308 C344 C330 R403 49.9_0402_1%~D D
+3.3V_RUN
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D CLK_PCIE_SATA 1 2
2 2 2 R381 49.9_0402_1%~D
2
CLK_PCIE_SATA# 1
G
2
Place near each pin R385 49.9_0402_1%~D
ICH_SMBCLK 1 3 CLK_SCLK CLK_PCIE_ICH 1 2
23,28,34 ICH_SMBCLK CLK_SCLK 16,17 W>40 mil R365 49.9_0402_1%~D
S
Q38 R401 CLK_PCIE_ICH# 1 2
0.047U_0402_16V4Z~D
2N7002W-7-F_SOT323~D +CK_VDD_A +CK_VDD_48 +CK_VDD_REF 2.2_0603_5%~D R374 49.9_0402_1%~D
0.047U_0402_16V4Z~D
1 2 +CK_VDD_A CLK_PCIE_LOM 1 2
1 1 1 1 1
Place near CK410+
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
R393 49.9_0402_1%~D
CLK_PCIE_LOM# 1
FSC FSB FSA CPU SRC PCI 2
C68
C61
C50
R399 49.9_0402_1%~D
2 2 2 2 2
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz DREFCLK 1 2
C51
C52
U16 R344 49.9_0402_1%~D
DREFCLK# 1 2
0 0 0 266 100 33.3 R355 49.9_0402_1%~D
1 7 DREF_SSCLK 1 2
VDDSRC VDDA R522 49.9_0402_1%~D
49 VDDSRC
0 0 1 133 100 33.3 54 8 DREF_SSCLK# 1 2
* 65
VDDSRC
VDDSRC
GNDA R523
CLK_PCIE_MINI2 1
49.9_0402_1%~D
2
0 1 0 200 100 33.3 NOTE: Place Decoupling as close as 25 H_STP_PCI# R544 49.9_0402_1%~D
PCI_SRC_STOP# H_STP_PCI# 23
30 CLK_PCIE_MINI2# 1 2
physically possilble to the VDD pins 36
VDDPCI
24 H_STP_CPU# R545 49.9_0402_1%~D
VDDPCI CPU_STOP# H_STP_CPU# 23
0 1 1 166 100 33.3 CLK_PCIE_MINI1 1 2
R274 12 R1641 49.9_0402_1%~D
C329 X2 1_0603_5%~D VDDCPU MCH_BCLK CLK_MCH_BCLK CLK_PCIE_MINI1# 1
CPUT1 11 1 2 CLK_MCH_BCLK 10 2
1 0 0 333 100 33.3 27P_0402_50V8J~D 14.31818MHz_20P_1BX14318CC1A~D 1 2 +CK_VDD_REF 18 R348 33_0402_5%~D R1642 49.9_0402_1%~D
VDDREF MCH_BCLK# CLK_MCH_BCLK#
2 1 CPUC1 10 1 2 CLK_MCH_BCLK# 10
1 2 +CK_VDD_48 40 R359 33_0402_5%~D
VDD48
1
1 0 1 100 100 33.3 R273
C 2.2_0603_5%~D CPU_BCLK CLK_CPU_BCLK C
CPUT0 14 1 2 CLK_CPU_BCLK 7
Place crystal within CLK_XTAL_IN 20 R321 33_0402_5%~D
C333 R32 X1 CPU_BCLK# 1 CLK_CPU_BCLK#
1 1 0 400 100 33.3 500 mils of CK410 13 2 CLK_CPU_BCLK# 7
2
27P_0402_50V8J~D 470_0402_5%~D CPUC0 R337 33_0402_5%~D
2 1 1 2 CLK_XTAL_OUT 19 X2 CPU_ITP CLK_CPU_ITP
1 1 1 Reserve CPUT_ITP/SRCT10 6 1 2 CLK_CPU_ITP 7
R368 33_0402_5%~D
CLK_ICH_48M 2 1 FSA 41 5 CPU_ITP# 1 2 CLK_CPU_ITP#
23 CLK_ICH_48M USB_48MHz/FSLA CPUC_ITP/SRCC10 CLK_CPU_ITP# 7
Table : ICS954305AK R298 12.1_0402_1%~D R376 33_0402_5%~D
CLK_SMC_48M 1 2 FSB 45
31 CLK_SMC_48M FSLB/TEST_MODE
R1589 12.1_0402_1%~D 3
FSC SRCT9
23 REF0/FSLC/TEST_SEL
CLK_PCI_5004 2 1 2
39 CLK_PCI_5004 SRCC9
CPU_BSEL CPU_BSEL2(FSC) CPU_BSEL1(FSB) R1619 12.1_0402_1%~D
CLK_PCI_5018 2 1 FCTSEL1 34 72
38 CLK_PCI_5018 PCICLK4/FCTSEL1 CLKREQ9#
R1438 12.1_0402_1%~D
CLK_PCI_LOM 2 1 PCI_LOM 33 70 PCIE_SATA 1 2 CLK_PCIE_SATA CLK_PCIE_SATA 22
28 CLK_PCI_LOM PCICLK3 SRCT8
133 0 0 R331 33_0402_5%~D R394 33_0402_5%~D
CLK_PCI_PCM 2 1 PCI_PCM 32 69 PCIE_SATA# 1 2 CLK_PCIE_SATA# CLK_PCIE_SATA# 22
30 CLK_PCI_PCM PCICLK2 SRCC8
R302 33_0402_5%~D R400 33_0402_5%~D
CLK_DOCKPCI_33M 2 1 DOCKPCI_33M 27 71 SATA_CLKREQ# 23
36 CLK_DOCKPCI_33M PCICLK1 CLKREQ8#
166 0 1 R294 33_0402_5%~D R292 1 2 10K_0402_5%~D +3.3V_RUN
SRCT7 66
CLK_ICH_14M 1 2 CLKREF 22
23 CLK_ICH_14M REF1
CLK_SIO_14M R266
1 2 12.1_0402_1%~D 67
38 CLK_SIO_14M SRCC7
R250 12.1_0402_1%~D
DREFCLK 1 2 DOT96 43 38
10 DREFCLK DOTT_96MHz/27MHz CLKREQ7#
R345 33_0402_5%~D
DREFCLK# 1 2 DOT96# 44 63 PCIE_ICH 1 2 CLK_PCIE_ICH
10 DREFCLK# DOTC_96MHz/27MHz(SS) SRCT6 CLK_PCIE_ICH 23
R356 33_0402_5%~D R366 33_0402_5%~D
R316 64 PCIE_ICH# 1 2 CLK_PCIE_ICH#
SRCC6 CLK_PCIE_ICH# 23
R1582 +3.3V_RUN 1 2 37 R375 33_0402_5%~D
B 33_0402_5%~D 10K_0402_5%~D ITP_EN/PCICLK_F0 B
CLKREQ6# 62 1 2 +3.3V_RUN
CLK_PCI_ICH 2 1 PCI_ICH @ R1761 10K_0402_5%~D
21 CLK_PCI_ICH
49 CLK_ENABLE# CLK_ENABLE# 39 60 MCH_3GPLL 1 2 CLK_MCH_3GPLL CLK_MCH_3GPLL 10
Vtt_PwrGd#/PD SRCT5 R397 33_0402_5%~D
61 MCH_3GPLL# 1 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL# 10
SRCC5
1 2 CLKIREF 9 IREF
R402 33_0402_5%~D
R362 475_0402_1%~D 29 CLK_3GPLLREQ# 10
CLKREQ5# R299 1 2 10K_0402_5%~D +3.3V_RUN
58 PCIE_LOM 1 2 CLK_PCIE_LOM CLK_PCIE_LOM 28
CLK_SCLK SRCT4 R1435 33_0402_5%~D
16 SMBCLK
59 PCIE_LOM# 1 2 CLK_PCIE_LOM# CLK_PCIE_LOM# 28
R531 SRCC4 R1436 33_0402_5%~D
CLKREQ4# 57 LOM_CLKREQ# 28
8.2K_0402_5%~D CLK_SDATA 17 1 2 +3.3V_RUN
SMBDAT R1762 10K_0402_5%~D
SRCT3 55
FSC 2 1 1 2 FSB 1 2
MCH_CLKSEL2 10 MCH_CLKSEL1 10
4 GNDSRC SRCC3 56
R330 R354
8 CPU_BSEL2 0_0402_5%~D 8 CPU_BSEL1 0_0402_5%~D 15 28
GNDCPU CLKREQ3#
21 52 PCIE_MINI2 1 2 CLK_PCIE_MINI2
GNDREF SRCT2 CLK_PCIE_MINI2 34
FCTSEL1 R1393 33_0402_5%~D
+3.3V_RUN 31 53 PCIE_MINI2# 1 2 CLK_PCIE_MINI2#
GNDPCI SRCC2 CLK_PCIE_MINI2# 34
1
R1394 33_0402_5%~D
R291 35 26 MINI2CLK_REQ# 34
GNDPCI CLKREQ2#
2
FCTSEL1 PIN43 PIN44 PIN47 PIN48 10K_0402_5%~D R1395 1 2 10K_0402_5%~D +3.3V_RUN

R271 42 50 PCIE_MINI1 1 2 CLK_PCIE_MINI1
10K_0402_5%~D GND48 SRCT1 R1638 33_0402_5%~D CLK_PCIE_MINI1 34
2
0 DOT96T DOT96C 96/100M_T 96/100M_C 68 51 PCIE_MINI1# 1 2 CLK_PCIE_MINI1#

* GNDSRC SRCC1 R1639 33_0402_5%~D CLK_PCIE_MINI1# 34
1
FSA 46 MINI1CLK_REQ# 34
CLKREQ1#
1 27M_out 27M SSout SRCT0 SRCC0 73 THRM_PAD 1 2 +3.3V_RUN
1
A DOT96_SSC R1640 1 10K_0402_5%~D A

74 THRM_PAD LCD100/96/SRC0_T 47 2 DREF_SSCLK 10
@ R278 75 R524 33_0402_5%~D
THRM_PAD DOT96_SSC#
10K_0402_5%~D 76 THRM_PAD LCD100/96/SRC0_C 48 1 2 DREF_SSCLK# 10
R525 33_0402_5%~D
2
Solder Thermal Pad to GND. Add min. 4 vias. SLG84450VTR_QFN72~D

BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock Generator
LA-2791
5 4 3 2 1
5 4 3 2 1
10 H_A#[3..31] H_D#[0..63] 10
JCPUA
+1.05V_VCCP
H_A#3 J4 E22 H_D#0
H_A#4 L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
H_A#5 H_D#2
29
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 1 1 JITP +3.3V_SUS
H_A#7 A6# D3# H_D#4 R367
M1 F23
29
A7# D4#
C71
C72
H_A#8 N2 G25 H_D#5 28 150_0402_1%~D
H_A#9 A8# D5# H_D#6 VTT1 ITP_DBRESET#
J1 A9# D6# E25 27 VTT0 1 2
D H_A#10 H_D#7 2 @ 2 @ D
N3 A10# D7# E23 26 VTAP
H_A#11 P5 K24 H_D#8 ITP_DBRESET# 25
H_A#12 A11# D8# H_D#9 DBR# +1.05V_VCCP
P2 A12# D9# G24 24 DBA#
H_A#13 L1 J24 H_D#10 ITP_BPM#0 23 R415
H_A#14 A13# D10# H_D#11 BPM0# 51_0402_5%~D
P4 A14# D11# J23 22 GND5
H_A#15 P1 H26 H_D#12 ITP_BPM#1 21 1 2 ITP_TDO
H_A#16 A15# D12# H_D#13 BPM1# R416
R1 A16# D13# F26 20 GND4
H_A#17 Y2 K22 H_D#14 ITP_BPM#2 19 51_0402_5%~D
H_A#18 A17# D14# H_D#15 BPM2# H_RESET#
U5 A18# D15# H25 18 GND3 1 2
H_A#19 R3 N22 H_D#16 ITP_BPM#3 17 R33
H_A#20 A19# D16# H_D#17 BPM3# 54.9_0402_1%~D
W6 A20# D17# K25 16 GND2
H_A#21 U4 P26 H_D#18 ITP_BPM#4 15 1 2 ITP_BPM#5
H_A#22 A21# D18# H_D#19 R424 BPM4#
Y5 A22# D19# R23 14 GND1
H_A#23 U2 L25 H_D#20 22.6_0402_1%~D ITP_BPM#5 13
H_A#24 A23# D20# H_D#21 H_RESET# 1 BPM5#
R4 A24# D21# L22 2 12 RESET#
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 ITP_TCK 11
H_A#26 A25# D22# H_D#23 FBO +1.05V_VCCP R387
T3 A26# D23# M23 10 GND0
H_A#27 W3 P25 H_D#24 R434 CLK_CPU_ITP 9 39.2_0402_1%~D
A27# D24# 6 CLK_CPU_ITP BCLKP
H_A#28 W5 P22 H_D#25 22.6_0402_1%~D CLK_CPU_ITP# 8 1 2 ITP_TMS
A28# D25# 6 CLK_CPU_ITP# BCLKN
H_A#29 Y4 P23 H_D#26 ITP_TDO 1 2 7 R417
H_A#30 A29# D26# H_D#27 TDO 150_0402_5%~D
W2 A30# D27# T24 6 NC2
H_A#31 Y1 R24 H_D#28 ITP_TCK 5 1 2 ITP_TDI
10 H_REQ#[0..4] A31# D28# H_D#29 TCK This shall place near CPU
D29# L26 4 NC1
H_REQ#0 K3 T25 H_D#30 ITP_TRST# 3 R391
H_REQ#1 REQ0# D30# H_D#31 ITP_TMS TRST# 680_0402_5%~D
H2 REQ1# D31# N24 2 TMS
H_REQ#2 K2 AA23 H_D#32 ITP_TDI 1 1 2 ITP_TRST#
H_REQ#3 REQ2# D32# H_D#33 TDI R436
J3 AB24
30
H_REQ#4 REQ3# D33# H_D#34 27.4_0402_1%~D
L5 REQ4# D34# V24
V26 H_D#35 @ MOLEX_52435-2891_28P~D 1 2 ITP_TCK
30
H_ADSTB#0 D35# H_D#36
10 H_ADSTB#0 L2 ADSTB0# D36# W25
H_ADSTB#1 V4 U23 H_D#37
10 H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK A22 D42# H_D#43
6 CLK_CPU_BCLK BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
6 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45
D45# H_D#46
D46# AC26
AA24 H_D#47
H_ADS# D47# H_D#48
10 H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49
10 H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
10 H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
10 H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52
10 H_DEFER# H_DRD Y# DEFER# D52# H_D#53
10 H_DRDY# F21 DRDY# D53# AC25
R422 H_HIT# G6 AD20 H_D#54
10 H_HIT# HIT# D54#
56_0402_5%~D H_HITM# E4 CONTROL AE22 H_D#55
10 H_HITM# HITM# D55#
1 2 H_IERR# D20 AF23 H_D#56
+1.05V_VCCP H_LOCK# IERR# D56# H_D#57
10 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
10 H_RESET# RESET# D58#
AD21 H_D#59
D59# H_D#60
10 H_RS#[0..2] D60# AE25
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63#
10 H_TRDY# G2 TRDY#
DINV0# J26 H_DINV#0 10

DINV1# M26 H_DINV#1 10
ITP_BPM#0 AD4 V23
BPM0# DINV2# H_DINV#2 10
ITP_BPM#1 AD3 AC20
BPM1# DINV3# H_DINV#3 10
ITP_BPM#2 AD1
B ITP_BPM#3 BPM2# B
AC4 BPM3# H_DSTBN#[0..3] 10
H23 H_DSTBN#0
ITP_DBRESET# DSTBN0# H_DSTBN#1
23,39 ITP_DBRESET# C20 DBR# DSTBN1# M24
H_DBSY# E1 W24 H_DSTBN#2
10 H_DBSY# DBSY# DSTBN2#
H_DPSLP# B5 AD23 H_DSTBN#3
22 H_DPSLP# DPSLP# DSTBN3# H_DSTBP#[0..3] 10
H_DPRSTP# E5 G22 H_DSTBP#0
22,49 H_DPRSTP# DPRSTP# DSTBP0#
H_DPWR# D24 N25 H_DSTBP#1
10 H_DPWR# ITP_BPM#4 DPWR# DSTBP1# H_DSTBP#2
AC2 PRDY# MISC DSTBP2# Y25
ITP_BPM#5 AC1 AE24 H_DSTBP#3
PREQ# DSTBP3#
38 CPU_PROCHOT# D21 PROCHOT#
Pop R1378 required by 22 H_PWRGOOD D6 PWRGOOD
H_CPUSLP# D7
Intel for B0 Yonah. 10,22 H_CPUSLP# SLP#
ITP_TCK AC5
R1387 @ ITP_TDI TCK H_A20M#
Backward compatible for AA6 TDI A20M# A6 H_A20M# 22
1K_0603_1%~D ITP_TDO AB3 A5 H_FERR#
A0 and A1 Yonah TDO FERR# H_FERR# 22
2 1 TEST1 C26 C4 H_IGNNE#
TEST1 IGNNE# H_IGNNE# 22
2 1 TEST2 D25 B3 H_INIT#
TEST2 INIT# H_INIT# 22
R1378 ITP_TMS AB5 C6 H_INTR
TMS LINT0 H_INTR 22
51_0603_1%~D ITP_TRST# AB6 B4 H_NMI
TRST# LINT1 H_NMI 22
LEGACY CPU
THERMAL
H_THERMDA A24 D5 H_STPCLK#
18 H_THERMDA H_THERMDC THERMDA DIODE STPCLK# H_SMI#
H_STPCLK# 22
18 H_THERMDC A25 THERMDC SMI# A3 H_SMI# 22
C7 THERMTRIP#
H_THERMTRIP#
18 H_THERMTRIP# TYCO_1-1674770-2_Yonah~D
H_THERMDA, H_THERMDC routing together.

Trace width / Spacing = 10 / 10 mil R398
A 56_0402_5%~D A
+1.05V_VCCP 1 2 H_THERMTRIP#
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Yonah in mFCPGA479
LA-2791
5 4 3 2 1
5 4 3 2 1
Length match within 25 mils

+VCC_CORE
JCPUB JCPUC
VCCSENSE AF7 AB26 AE18 K1

49 VCCSENSE VCCSENSE VSS VCC VSS
VSSSENSE AE7 AA25 AE17 J2
49 VSSSENSE VSSSENSE VSS VCC VSS
VSS AD25 AB15 VCC VSS M2
VSS AE26 AA15 VCC VSS N1
+1.5V_RUN B26 VCCA VSS AB23 AD15 VCC VSS T1
VSS AC24 AC15 VCC VSS R2
+1.05V_VCCP K6 VCCP VSS AF24 AF15 VCC VSS V2
D D
J6 VCCP VSS AE23 AE15 VCC VSS W1
M6 VCCP VSS AA22 AB14 VCC VSS A26
N6 AD22 AA13 D26
+1.05V_VCCP T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
R_A K21 VCCP VSS AB19 AF14 VCC VSS B24
1
0.01U_0402_16V7K~D
10U_0805_4VAM~D
J21 VCCP VSS AA19 AE13 VCC VSS A23
+VCC_CORE M21 AD19 AB12 D23
1 1 VCCP VSS VCC VSS
R140 R555 N21 AC19 AA12 E24
V_CPU_GTLREF VCCP VSS VCC YONAH VSS
C88
C87
1K_0402_1%~D 100_0402_1%~D T21 AF19 AD12 B21
VCCSENSE VCCP VSS VCC VSS
1 2 R21 AE19 AC12 C22
2
2 2 VCCP VSS VCC VSS

V21 VCCP VSS AB16 AF12 VCC VSS F22
R556 W21 AA16 AE12 E21
POWER, GROUNG, RESERVED SIGNALS AND NC

100_0402_1%~D VCCP VSS VCC VSS
R_B V6 VCCP VSS AD16 AB10 VCC VSS B19
1
1 2 VSSSENSE G21 AC16 AB9 A19

VCCP VSS VCC VSS
VSS AF16 AA10 VCC VSS D19
R147 AE16 AA9 C19
2K_0402_1%~D H_PSI# VSS VCC VSS
49 H_PSI# AE6 PSI# VSS AB13 AD10 VCC VSS F19
AA14 AD9 E19
2
VID0 VSS VCC VSS

49 VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
VID1 AF5 AC14 AC9 A16
49 VID1 VID1 VSS VCC VSS
VID2 AE5 AF13 AF10 D16
VID3 AF4 AE14 AF9 C16
Layout close CPU PIN AD26 Layout close CPU 49 VID3
VID4 AE3
VID3 VSS
AB11 AE10
VCC
POWER, GROUND VSS
F16
VID5
0.5 inch (max) 49 VID5
VID6
AF2
AE2
VID5 VSS AA11
AD11
AE9
AB7
VCC VSS E16
B13
VSS AC11 AA7 VCC VSS A14
VSS AF11 AD7 VCC VSS D13
V_CPU_GTLREF AD26 GTLREF VSS AE11 AC7 VCC VSS C14
VSS AB8 B20 VCC VSS F13
10 CPU_BSEL0 CPU_BSEL0 B22 AA8 A20 E14
CPU_BSEL1 BSEL0 VSS VCC VSS
6 CPU_BSEL1 B23 BSEL1 VSS AD8 F20 VCC VSS B11
C CPU_BSEL2 C
6 CPU_BSEL2 C21 BSEL2 VSS AC8 E20 VCC VSS A11
VSS AF8 B18 VCC VSS D11
COMP0 R26 AE8 B17 C11
COMP1 COMP0 VSS VCC VSS
U26 COMP1 VSS AA5 A18 VCC VSS F11
COMP2 U1 AD5 A17 E11
COMP3 COMP2 VSS VCC VSS
V1 COMP3 VSS AC6 D18 VCC VSS B8
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
+VCC_CORE E7 VCC VSS AC3 C17 VCC VSS C8
AB20 VCC VSS AF3 F18 VCC VSS F8
Resistor placed within AA20 VCC VSS AE4 F17 VCC VSS E8
27.4_0402_1%~D
54.9_0402_1%~D
27.4_0402_1%~D
54.9_0402_1%~D
AF20 AB1 E18 G26
0.5" of CPU pin.Trace AE20
VCC VSS
AA2 E17
VCC VSS
K26
VCC VSS VCC VSS
should be at least 25 AB18 VCC VSS AD2 B15 VCC VSS J25
1
1
AB17 AE1 A15 M25
mils away from any AA18
VCC VSS
B6 D15
VCC VSS
N26
VCC VSS VCC VSS
R129
R124
R465
R457
other toggling signal. AA17 VCC VSS C5 C15 VCC VSS T26
AD18 VCC VSS F5 F15 VCC VSS R25
AD17 E6 E15 V25
2
VCC VSS VCC VSS

AC18 VCC VSS H6 B14 VCC VSS W26
AC17 VCC VSS J5 A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 C13 VCC VSS K23
VSS P6 F14 VCC VSS L24
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
F6 RSVD VSS U6 A12 VCC VSS T23
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 RSVD VSS A4 C12 VCC VSS Y24
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
B B
C24 RSVD VSS G4 B9 VCC VSS M22
133 0 0 1 AA1 RSVD VSS K4 A10 VCC VSS L21
AA4 RSVD VSS L3 A9 VCC VSS P21
AB2 RSVD VSS P3 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
166 0 1 1 M4 RSVD VSS T4 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
T2 RSVD VSS Y3 F10 VCC
V3 RSVD VSS W4 F9 VCC
B2 RSVD VSS D1 E10 VCC
C3 RSVD VSS C2 E9 VCC
T22 RSVD VSS F2 B7 VCC
B25 RSVD VSS G1 A7 VCC
F7 VCC
TYCO_1-1674770-2_Yonah~D TYCO_1-1674770-2_Yonah~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Yonah in mFCPGA479
LA-2791
5 4 3 2 1
5 4 3 2 1
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(North side C100 C429 C98 C430 C99 C472 C473 C119 C142 C141
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
D D
+VCC_CORE
Place these inside 1 1 1 1 1 1 1 1 1 1

socket cavity on L8
(Sorth side C428 C138 C447 C470 C469 C467 C471 C97 C102 C433
Secondary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1

socket cavity on L8
(North side C468 C140 C139 C446 C466 C137
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
2 2 2 2 2 2
+VCC_CORE
Place these inside 1 1 1 1 1 1 22uF 0805 X5R -> 85 degree C 10uF 0805 X5R -> 85 degree C
socket cavity on L8
(Sorth side C448 C432 C426 C427 C431 C120
Primary) 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
C 2 2 2 2 2 2 C
High Frequence Decoupling
Near VCORE regulator.
+VCC_CORE
The caps need change to ESR=6m ohms
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
330U_D_2.5VM_R6M~D
South Side Secondary 1 1 1 1 1 1 North Side Secondary

ESR <= 1.5m ohm
C352
C496
C354
C497
C618
C365
+ + + + + +
2 2 2 2 2 2 Capacitor > 1980uF

@
B B
7mOhm 7mOhm 7mOhm 7mOhm 7mOhm 7mOhm

PS CAP PS CAP PS CAP PS CAP PS CAP PS CAP
+1.05V_VCCP
330U_D2E_2.5VM_R9~D
1
1 1 1 1 1 1
@ C372
+ Place these inside

C415 C439 C451 C416 C462 C414 socket cavity on L8
0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D (North side
2 2 2 2 2 2 2 Secondary)
A CRB was 270uF A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CPU Bypass
LA-2791
5 4 3 2 1
5 4 3 2 1
Description at page12
Note :
CFG3:17 has
internal pullup,
CFG18:19 has
+1.05V_VCCP internal pulldown
U40B
221_0402_1%~D
1
D D
7 H_D#[0..63] U40A H_A#[3..31] 7
R85
DMI_MRX_ITX_N0 AE35 K16 CPU_BSEL0 CPU_BSEL0 8
23 DMI_MRX_ITX_N0 DMIRXN0 CFG0
H_D#0 F1 H9 H_A#3 DMI_MRX_ITX_N1 AF39 K18 MCH_CLKSEL1
HD0# HA3# 23 DMI_MRX_ITX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 6
H_D#1 J1 C9 H_A#4 DMI_MRX_ITX_N2 AG35 J18 MCH_CLKSEL2
HD1# HA4# 23 DMI_MRX_ITX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 6
H_D#2 H1 E11 H_A#5 DMI_MRX_ITX_N3 AH39 F18 CFG3 PAD~D T34
23 DMI_MRX_ITX_N3
2
H_D#3 HD2# HA5# H_A#6 H_SWNG1 DMIRXN3 CFG3 CFG4
J6 HD3# HA6# G11 CFG4 E15 PAD~D T35
H_D#4 H3 F11 H_A#7 F15 CFG5 CFG5 12
HD4# HA7# CFG5
0.1U_0402_16V4Z~D
H_D#5 K2 G12 H_A#8 DMI_MRX_ITX_P0 AC35 E18 CFG6 CFG6 12
HD5# HA8# 23 DMI_MRX_ITX_P0 DMIRXP0 CFG6
1
100_0402_1%~D
H_D#6 G1 F9 H_A#9 DMI_MRX_ITX_P1 AE39 D19 CFG7 CFG7 12
R86
H_D#7 G2 H11 H_A#10 1 DMI_MRX_ITX_P2 AF35 D16 CFG8 PAD~D T41
DMI
H_D#8 K9 J12 H_A#11 DMI_MRX_ITX_P3 AG39 G16 CFG9 CFG9 12
H_D#9 K1 G14 H_A#12 E16 CFG10 PAD~D T42
HD9# HA12# CFG10
C65
H_D#10 K7 D9 H_A#13 D15 CFG11 CFG11 12
2
H_D#11 HD10# HA13# H_A#14 2 DMI_MTX_IRX_N0 CFG11 CFG12
J8 HD11# HA14# J14 23 DMI_MTX_IRX_N0 AE37 DMITXN0 CFG12 G15 CFG12 12
H_D#12 H4 H13 H_A#15 DMI_MTX_IRX_N1 AF41 K15 CFG13 CFG13 12
HD12# HA15# 23 DMI_MTX_IRX_N1 DMITXN1 CFG13
H_D#13 J3 J15 H_A#16 DMI_MTX_IRX_N2 AG37 C15 CFG14
CFG
HD13# HA16# 23 DMI_MTX_IRX_N2 DMITXN2 CFG14 PAD~D T43
H_D#14 K11 F14 H_A#17 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD~D T44
HD14# HA17# 23 DMI_MTX_IRX_N3 DMITXN3 CFG15
H_D#15 G4 D12 H_A#18 G18 CFG16 CFG16 12
H_D#16 HD15# HA18# H_A#19 CFG16 CFG17
T10 HD16# HA19# A11 CFG17 H15 PAD~D T45
H_D#17 W11 C11 H_A#20 DMI_MTX_IRX_P0 AC37 J25 CFG18 CFG18 12
HD17# HA20# +1.05V_VCCP 23 DMI_MTX_IRX_P0 DMITXP0 CFG18
H_D#18 T3 A12 H_A#21 DMI_MTX_IRX_P1 AE41 K27 CFG19 CFG19 12
HD18# HA21# 23 DMI_MTX_IRX_P1 DMITXP1 CFG19
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_P2 AF37 J26 CFG20 CFG20 12
HD19# HA22# 23 DMI_MTX_IRX_P2 DMITXP2 CFG20
H_D#20 U9 E13 H_A#23 DMI_MTX_IRX_P3 AG41
HD20# HA23# 23 DMI_MTX_IRX_P3 DMITXP3
221_0402_1%~D
H_D#21 U11 G13 H_A#24
HD21# HA24#
1
H_D#22 T11 F12 H_A#25 AG33 CLK_MCH_3GPLL 6
HD22# HA25# G_CLKP
R64
H_D#23 W9 B12 H_A#26 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL# 6
HD23# HA26# 16 M_CLK_DDR0 SM_CK0 G_CLKN
H_D#24 T1 B14 H_A#27 M_CLK_DDR1 AR1
HD24# HA27# 16 M_CLK_DDR1 SM_CK1
H_D#25 T8 C12 H_A#28 M_CLK_DDR2 AW7 A27
CLK
HD25# HA28# 17 M_CLK_DDR2 SM_CK2 D_REF_CLKN DREFCLK# 6
H_D#26 T4 A14 H_A#29 M_CLK_DDR3 AW40 A26 DREFCLK 6
17 M_CLK_DDR3
2
H_D#27 HD26# HA29# H_A#30 H_SWNG0 SM_CK3 D_REF_CLKP
W7 HD27# HA30# C14
H_D#28 U5 D14 H_A#31 M_CLK_DDR#0 AW35 C40
HD28# HA31# 16 M_CLK_DDR#0 SM_CK0# D_REF_SSCLKN DREF_SSCLK# 6
0.1U_0402_16V4Z~D
H_D#29 T9 M_CLK_DDR#1 AT1 D41
HD29# 16 M_CLK_DDR#1 SM_CK1# D_REF_SSCLKP DREF_SSCLK 6
1
100_0402_1%~D
C H_D#30 M_CLK_DDR#2 C
W6 HD30# 1 17 M_CLK_DDR#2 AY7 SM_CK2#
R65
H_D#31 T5 M_CLK_DDR#3 AY40 H32 CLK_3GPLLREQ# 6
HOST
HD31# H_REQ#[0..4] 7 17 M_CLK_DDR#3 SM_CK3# CLK_REQ#

H_D#32 AB7 D8 H_REQ#0
HD32# HREQ#0
C48
H_D#33 AA9 G8 H_REQ#1 DDR_CKE0_DIMMA AU20
HD33# HREQ#1 2 16 DDR_CKE0_DIMMA SM_CKE0
DDR MUXING
H_D#34 W4 B8 H_REQ#2 DDR_CKE1_DIMMA AT20
16 DDR_CKE1_DIMMA
2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE2_DIMMB SM_CKE1
W3 HD35# HREQ#3 F8 17 DDR_CKE2_DIMMB BA29 SM_CKE2 NC0 A3
H_D#36 Y3 A8 H_REQ#4 DDR_CKE3_DIMMB AY29 A39
HD36# HREQ#4 17 DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#37 Y7 A4
H_D#38 HD37# DDR_CS0_DIMMA# AW13 NC2
W5 HD38# 16 DDR_CS0_DIMMA# SM_CS0# NC3 A40
H_D#39 Y10 B9 H_ADSTB#0 DDR_CS1_DIMMA# AW12 AW1
HD39# HADSTB#0 H_ADSTB#0 7 16 DDR_CS1_DIMMA# SM_CS1# NC4
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS2_DIMMB# AY21 AW41
HD40# HADSTB#1 H_ADSTB#1 7 17 DDR_CS2_DIMMB# SM_CS2# NC5
H_D#41 W2 DDR_CS3_DIMMB# AW21 AY1
HD41# 17 DDR_CS3_DIMMB# SM_CS3# NC6
H_D#42 AA4 AG1 BA1
NC
HD42# HCLKN CLK_MCH_BCLK# 6 NC7
H_D#43 AA7 AG2 M_OCDOCMP0 AL20 BA2
HD43# HCLKP CLK_MCH_BCLK 6 SM_OCDCOMP0 NC8
H_D#44 AA2 M_OCDOCMP1 AF10 BA3
HD44# H_DSTBN#[0..3] 7 +1.05V_VCCP SM_OCDCOMP1 NC9
H_D#45 AA6 K4 H_DSTBN#0 BA39
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_ODT0 NC10
AA10 HD46# HDSTBN#1 T7 16 M_ODT0 BA13 SM_ODT0 NC11 BA40
100_0402_1%~D
H_D#47 Y8 Y5 H_DSTBN#2 +1.8V_SUS M_ODT1 BA12 BA41
HD47# HDSTBN#2 16 M_ODT1 SM_ODT1 NC12
1
H_D#48 AA1 AC4 H_DSTBN#3 M_ODT2 AY20 C1
HD48# HDSTBN#3 H_DSTBP#[0..3] 7 17 M_ODT2 SM_ODT2 NC13
R326
H_D#49 AB4 K3 H_DSTBP#0 M_ODT3 AU21 AY41
HD49# HDSTBP#0 17 M_ODT3 SM_ODT3 NC14
H_D#50 AC9 T6 H_DSTBP#1 B2
H_D#51 HD50# HDSTBP#1 H_DSTBP#2 R142 1 NC15
AB11 HD51# HDSTBP#2 AA5 2 80.6_0402_1%~D SMRCOMPN AV9 SM_RCOMPN NC16 B41
H_D#52 AC11 AC5 H_DSTBP#3 1 2 SMRCOMPP AT9 C41
2
H_D#53 HD52# HDSTBP#3 H_VREF R141 80.6_0402_1%~D SM_RCOMPP NC17
AB3 HD53# NC18 D1
+1.05V_VCCP H_D#54 AC2 AK1
HD54# SM_VREF0
0.1U_0402_16V4Z~D
H_D#55 AD1 J7 V_DDR_MCH_REF AK41
HD55# HDINV#0 H_DINV#0 7 SM_VREF1
200_0402_1%~D
H_D#56 AD9 W8 1 T32
HD56# HDINV#1 H_DINV#1 7 RESERVED1
R325
C363
H_D#57 AC1 U3 R32
HD57# HDINV#2 H_DINV#2 7 RESERVED2
H_D#58 AD7 AB10 23 PM_BMBUSY# G28 F3
HD58# HDINV#3 H_DINV#3 7 PM_BMBUSY# RESERVED3
1
1
54.9_0402_1%~D
54.9_0402_1%~D
H_D#59 AC6 16 PM_EXTTS#0 PM_EXTTS#0 F25 F7

HD59# 2 PM_EXTTS0# RESERVED4
PM
H_D#60 AB5 23 PM_EXTTS#1 PM_EXTTS#1 H26 AG11
RESERVED
2
HD60# PM_EXTTS1# RESERVED5
R80
R52
H_D#61 AD10 B7 H_RESET# 18 THERMTRIP_MCH# G6 AF11

B HD61# HCPURST# H_RESET# 7 PM_THERMTRIP# RESERVED6 B
H_D#62 AD4 E8 H_ADS# ICH_PWRGD AH33 H7
HD62# HADS# H_ADS# 7 23,42 ICH_PWRGD PWROK RESERVED7
H_D#63 AC8 E7 H_TRDY# 21,23,28,34,52 PLTRST# 2 1 PLTRST_R# AH34 J19
H_TRDY# 7
2
HD63# HTRDY# 100_0402_1%~D R441 RSTIN# RESERVED8

HDPWR# J9 H_DPWR# 7 RESERVED9 A41
H8 H_DRD Y# 21 MCH_ICH_SYNC# K28 A34
HDRDY# H_DRDY# 7 ICH_SYNC# RESERVED10
J13 C3 H_DEFER# D28
HVREF0 HDEFER# H_DEFER# 7 RESERVED11
H_VREF K13 D4 H_HITM# D27
HVREF1 HHITM# H_HITM# 7 RESERVED12
H_XRCOMP E1 D3 H_HIT# A35
HXRCOMP HHIT# H_HIT# 7 RESERVED13
H_XSCOMP E2 B3 H_LOCK#
HXSCOMP HLOCK# H_LOCK# 7
H_YRCOMP Y1 C7 H_BR0# CALISTOGA A0_FCBGA1466~D
HYRCOMP HBREQ0# H_BR0# 7
H_YSCOMP U1 C6 H_BNR# +3.3V_RUN_R
HYSCOMP HBNR# H_BNR# 7
H_SWNG0 E4 F6 H_BPRI#
HXSWING HBPRI# H_BPRI# 7
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# 7
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# 7,22
24.9_0402_1%~D
24.9_0402_1%~D
Route as short
1
R336
B4 H_RS#0 as possible 10K_0402_5%~D
HRS0#
R57
R90
E6 H_RS#1 PM_EXTTS#0 2 1
HRS1# H_RS#2 V_DDR_MCH_REF
HRS2# D6 16,17,48 V_DDR_MCH_REF
0.1U_0402_16V4Z~D
@ R253
2
H_RS#[0..2] 7 10K_0402_5%~D
CALISTOGA A0_FCBGA1466~D 1 PM_EXTTS#1 2 1
M_OCDOCMP0
C425
M_OCDOCMP1
2
40.2_0402_1%~D
40.2_0402_1%~D
@
1
R335
75_0402_5%~D
@ R435
@ R437
THERMTRIP_MCH# 1 2 +1.05V_VCCP
2
A A
Stuff R435 & R437 for A1 Calistoga

Layout Note:
H_XRCOMP & H_YRCOMP trace width
and spacing is 10/20
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistoga(1 of 6)
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
D
E
U40D U40E
DDR_A_D[0..63] 16 DDR_B_D[0..63] 17
DDR_A_BS0 AU12 AJ35 DDR_A_D0 DDR_B_BS0 AT24 AK39 DDR_B_D0
16 DDR_A_BS0 SA_BS0 SA_DQ0 17 DDR_B_BS0 SB_BS0 SB_DQ0
DDR_A_BS1 AV14 AJ34 DDR_A_D1 DDR_B_BS1 AV23 AJ37 DDR_B_D1
DDR_A_BS2 BA20 AM31 DDR_A_D2 DDR_B_BS2 AY28 AP39 DDR_B_D2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
AK35 DDR_A_D5 AK38 DDR_B_D5
16 DDR_A_DM[0..7] SA_DQ5 17 DDR_B_DM[0..7] SB_DQ5
DDR_A_DM0 AJ33 AJ32 DDR_A_D6 DDR_B_DM0 AK36 AN41 DDR_B_D6
DDR_A_DM1 SA_DM0 SA_DQ6 DDR_A_D7 DDR_B_DM1 SB_DM0 SB_DQ6 DDR_B_D7
AM35 SA_DM1 SA_DQ7 AH31 AR38 SB_DM1 SB_DQ7 AP41
DDR_A_DM2 AL26 AN35 DDR_A_D8 DDR_B_DM2 AT36 AT40 DDR_B_D8
AN22 SA_DM3 SA_DQ9 AP33 BA31 SB_DM3 SB_DQ9 AV41
DDR_A_DM4 AM14 AR31 DDR_A_D10 DDR_B_DM4 AL17 AU38 DDR_B_D10
AL9 SA_DM5 SA_DQ11 AP31 AH8 SB_DM5 SB_DQ11 AV38
DDR_A_DM6 AR3 AN38 DDR_A_D12 DDR_B_DM6 BA5 AP38 DDR_B_D12
AH4 SA_DM7 SA_DQ13 AM36 AN4 SB_DM7 SB_DQ13 AR40
AM34 DDR_A_D14 AW38 DDR_B_D14
SA_DQ15 AN33 SB_DQ15 AY38
AK26 DDR_A_D16 BA38 DDR_B_D16
16 DDR_A_DQS[0..7] SA_DQ17 AL27 17 DDR_B_DQS[0..7] SB_DQ17 AV36
DDR_A_DQS0 AK33 AM26 DDR_A_D18 DDR_B_DQS0 AM39 AR36 DDR_B_D18
DDR_A_DQS1 SA_DQS0 SA_DQ18 DDR_A_D19 DDR_B_DQS1 SB_DQS0 SB_DQ18 DDR_B_D19
AT33 SA_DQS1 SA_DQ19 AN24 AT39 SB_DQS1 SB_DQ19 AP36
DDR_A_DQS2 AN28 AK28 DDR_A_D20 DDR_B_DQS2 AU35 BA36 DDR_B_D20
DDR SYS MEMORY A
DDR SYS MEMORY B

AM22 SA_DQS3 SA_DQ21 AL28 AR29 SB_DQS3 SB_DQ21 AU36
DDR_A_DQS4 AN12 AM24 DDR_A_D22 DDR_B_DQS4 AR16 AP35 DDR_B_D22
AN8 SA_DQS5 SA_DQ23 AP26 AR10 SB_DQS5 SB_DQ23 AP34
DDR_A_DQS6 AP3 AP23 DDR_A_D24 DDR_B_DQS6 AR7 AY33 DDR_B_D24
AG5 SA_DQS7 SA_DQ25 AL22 AN5 SB_DQS7 SB_DQ25 BA33
C DDR_A_D26 DDR_B_D26 C
SA_DQ26 AP21 SB_DQ26 AT31
AN20 DDR_A_D27 AU29 DDR_B_D27
16 DDR_A_DQS#[0..7] SA_DQ27 17 DDR_B_DQS#[0..7] SB_DQ27
DDR_A_DQS#0 AK32 AL23 DDR_A_D28 DDR_B_DQS#0 AM40 AU31 DDR_B_D28
DDR_A_DQS#1 AU33 SA_DQS0# SA_DQ28 DDR_A_D29 DDR_B_DQS#1 SB_DQS0# SB_DQ28 DDR_B_D29
SA_DQS1# SA_DQ29 AP24 AU39 SB_DQS1# SB_DQ29 AW31
DDR_A_DQS#2 AN27 AP20 DDR_A_D30 DDR_B_DQS#2 AT35 AV29 DDR_B_D30
DDR_A_DQS#3 AM21 SA_DQS2# SA_DQ30 DDR_A_D31 DDR_B_DQS#3 SB_DQS2# SB_DQ30 DDR_B_D31
SA_DQS3# SA_DQ31 AT21 AP29 SB_DQS3# SB_DQ31 AW29
DDR_A_DQS#4 AM12 AR12 DDR_A_D32 DDR_B_DQS#4 AP16 AM19 DDR_B_D32
DDR_A_DQS#5 AL8 SA_DQS4# SA_DQ32 DDR_A_D33 DDR_B_DQS#5 SB_DQS4# SB_DQ32 DDR_B_D33
SA_DQS5# SA_DQ33 AR14 AT10 SB_DQS5# SB_DQ33 AL19
DDR_A_DQS#6 AN3 AP13 DDR_A_D34 DDR_B_DQS#6 AT7 AP14 DDR_B_D34
DDR_A_DQS#7 AH5 SA_DQS6# SA_DQ34 DDR_A_D35 DDR_B_DQS#7 SB_DQS6# SB_DQ34 DDR_B_D35
SA_DQS7# SA_DQ35 AP12 AP5 SB_DQS7# SB_DQ35 AN14
AT13 DDR_A_D36 AN17 DDR_B_D36
SA_DQ37 AT12 SB_DQ37 AM16
AL14 DDR_A_D38 AP15 DDR_B_D38
16 DDR_A_MA[0..13] SA_DQ38 17 DDR_B_MA[0..13] SB_DQ38
DDR_A_MA0 AY16 AL12 DDR_A_D39 DDR_B_MA0 AY23 AL15 DDR_B_D39
DDR_A_MA1 SA_MA0 SA_DQ39 DDR_A_D40 DDR_B_MA1 SB_MA0 SB_DQ39 DDR_B_D40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDR_A_MA2 AW16 AN7 DDR_A_D41 DDR_B_MA2 AY24 AH10 DDR_B_D41
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDR_A_MA4 BA17 AK7 DDR_A_D43 DDR_B_MA4 AT27 AN10 DDR_B_D43
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDR_A_MA6 AV17 AN9 DDR_A_D45 DDR_B_MA6 AU27 AH11 DDR_B_D45
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDR_A_MA8 AW17 AL5 DDR_A_D47 DDR_B_MA8 AV27 AJ8 DDR_B_D47
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDR_A_MA10 AU13 AW2 DDR_A_D49 DDR_B_MA10 AV24 AW10 DDR_B_D49
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDR_A_MA12 AV20 AN2 DDR_A_D51 DDR_B_MA12 AY27 AW4 DDR_B_D51
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDR_A_D53 AY9 DDR_B_D53
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDR_A_D55 AY5 DDR_B_D55
DDR_A_CAS# AY13 SA_DQ55 DDR_A_D56 DDR_B_CAS# SB_DQ55 DDR_B_D56
16 DDR_A_CAS# SA_CAS# SA_DQ56 AG7 17 DDR_B_CAS# AR24 SB_CAS# SB_DQ56 AV4
DDR_A_RAS# AW14 AF9 DDR_A_D57 DDR_B_RAS# AU23 AR5 DDR_B_D57
B 16 DDR_A_RAS# SA_RAS# SA_DQ57 17 DDR_B_RAS# SB_RAS# SB_DQ57 B
DDR_A_WE# AY14 AG4 DDR_A_D58 DDR_B_WE# AR27 AK4 DDR_B_D58
16 DDR_A_WE# SA_WE# SA_DQ58 17 DDR_B_WE# SB_WE# SB_DQ58
SA_RCVENIN# AK23 AF6 DDR_A_D59 SB_RCVENIN# AK16 AK3 DDR_B_D59
T2022 PAD~D SA_RCVENOUT# AK24 SA_RCVENIN# SA_DQ59 DDR_A_D60 T2023 PAD~D SB_RCVENOUT# SB_RCVENIN# SB_DQ59 DDR_B_D60
SA_RCVENOUT# SA_DQ60 AG9 AK18 SB_RCVENOUT# SB_DQ60 AT4
T2024 PAD~D AH6 DDR_A_D61 T2025 PAD~D AK5 DDR_B_D61
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDR_A_D63 AJ3 DDR_B_D63
SA_DQ63 SB_DQ63
CALISTOGA A0_FCBGA1466~D CALISTOGA A0_FCBGA1466~D
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Calistogo(2 of 6)
LA-2791
5 4 3 2 1
5 4 3 2 1
LOW = Moby Dick
C +1.5VRUN_PCIE
R1493
U40C 24.9_0402_1%~D
SDVO_CTRLDATA H27 D40 PEGCOMP 1 2
52 SDVO_CTRLDATA SDVOCTRL_DATA EXP_COMPI
SDVO_CTRLCLK H28 D38
52 SDVO_CTRLCLK SDVOCTRL_CLK EXP_COMPO
EXP_RXN0 F34 Strap Pin Table

D 19 LCD_A0+ B37 LA_DATA0 EXP_RXN1 G38 SDVOB_INT- 52 Low = DMI x 2 D
19 LCD_A1+ B34 LA_DATA1 EXP_RXN2 H34 CFG5
19 LCD_A2+ A36 LA_DATA2 EXP_RXN3 J38 High = DMI x 4 *
L34 R307 1 2 @ 2.2K_0402_5%~D
EXP_RXN4 10 CFG5
19 LCD_A0- C37 LA_DATA#0 EXP_RXN5 M38 LOW = Moby Dick
B35 N34 CFG6 R67 1 2 @ 2.2K_0402_5%~D
19 LCD_A1- LA_DATA#1 EXP_RXN6 10 CFG6
19 LCD_A2- A37 LA_DATA#2 EXP_RXN7 P38 HIGH = Calistoga *
R34 R281 1 2 @ 2.2K_0402_5%~D
EXP_RXN8 10 CFG7
19 LCD_B0+ F30 LB_DATA0 EXP_RXN9 T38 Low = DT/Transportable CPU
CFG7 R282 @ 2.2K_0402_5%~D
LVDS
19 LCD_B1+ D29 LB_DATA1 EXP_RXN10 V34 10 CFG9 1 2
19 LCD_B2+ F28 LB_DATA2 EXP_RXN11 W38 High = Mobile CPU *
Y34 R357 1 2 @ 2.2K_0402_5%~D
EXP_RXN12 10 CFG11
19 LCD_B0- G30 LB_DATA#0 EXP_RXN13 AA38 Low = Reverse Lane
D30 AB34 CFG9 R288 1 2 @ 2.2K_0402_5%~D
19 LCD_B1- LB_DATA#1 EXP_RXN14 10 CFG12
19 LCD_B2- F29 LB_DATA#2 EXP_RXN15 AC38 High = Normal Operation * R323 1 2 @ 2.2K_0402_5%~D
10 CFG13
19 LCD_ACLK+ A32 LA_CLK EXP_RXP0 D34
A33 F38 R346 1 2 @ 2.2K_0402_5%~D
19 LCD_ACLK- LA_CLK# EXP_RXP1 SDVOB_INT+ 52 10 CFG16
19 LCD_BCLK+ E26 LB_CLK EXP_RXP2 G34 CFG11
19 LCD_BCLK- E27 LB_CLK# EXP_RXP3 H38
J34 CFG[3:17] have internal pullup
PCI-EXPRESS GRAPHICS
BIA_PWM_R EXP_RXP4
D32 LBKLT_CTL EXP_RXP5 L38 00 = Reserved
PANEL_BKEN J30 M34 01 = XOR Mode Enabled
19 PANEL_BKEN LBKLT_EN EXP_RXP6
LCTLA_CLK H30 N38 CFG[13:12] 10 = All Z Mode Enabled
LCTLB_DATA LCTLA_CLK EXP_RXP7 +3.3V_RUN_R
H29 LCTLB_DATA EXP_RXP8 P34 11 = Normal Operation *
LDDC_CLK G26 R38 (Default)
19 LDDC_CLK LDDC_CLK EXP_RXP9
LDDC_DATA G25 T34
19 LDDC_DATA LDDC_DATA EXP_RXP10
F32 V38 @
19 ENVDD LVDD_EN EXP_RXP11
2 1 L_IBG B38 W34 CFG16 Low = Disabled R308 1 2 1K_0402_5%~D
LIBG EXP_RXP12 10 CFG18
R251 C35 Y38 1 2
LVBG EXP_RXP13 10 CFG19
1.5K_0402_1%~D (FSB Dynamic ODT) High = Enabled R306 @1K_0402_5%~D
LVREF for Alviso N.C
C33
C32
LVREFH EXP_RXP14 AA34
AB38
* 1 2
LVREFL EXP_RXP15 10 CFG20
R310 @1K_0402_5%~D
C for Calistoga to GND C
EXP_TXN0 F36 DVO_RED#_C C1346 1 2 0.1U_0402_16V4Z~D
SDVOB_RED- 52 CFG18 Low = 1.05V (Default) *
36 TV_CVBS A16 TVDAC_A EXP_TXN1 G40 DVO_GREEN#_CC1347 1 2 0.1U_0402_16V4Z~D
SDVOB_GREEN- 52
36 TV_Y C18 TVDAC_B EXP_TXN2 H36 DVO_BLUE#_C C1348 1 2 0.1U_0402_16V4Z~D
SDVOB_BLUE- 52 (VCC Select) High = 1.5V CFG[18:20] have internal pulldown
36 TV_C A19 TVDAC_C EXP_TXN3 J40 DVO_CLK#_C C1349 1 2 0.1U_0402_16V4Z~D
SDVOB_CLK- 52
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
TV
EXP_TXN4 L36 Low = Normal *

1
TVIREF J20 M40

TV_IREF EXP_TXN5 Operation (Default):
1
4.99K_0402_1%~D
EXP_TXN6 N36 CFG19

R25
R24
R23
B16 TV_IRTNA EXP_TXN7 P40 Lane number in Order

R314
B18 TV_IRTNB EXP_TXN8 R36 (DMI Lane Reversal)

B19 T40 High = Reverse Lane
2
TV_IRTNC EXP_TXN9
V36
2
EXP_TXN10
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 TV_DCONSEL0 EXP_TXN12 Y36 Low = No SDVO Device Present
EXP_TXN13 AA40 SDVO_CTRLDATA (Default)*
Close to U40.J20 EXP_TXN14 AB36 High = SDVO Device Present
EXP_TXN15 AC40
G_CLK_DDC2 C26 DDCCLK
CRT
G_DAT_DDC2 C25 D36 DVO_RED_C C1350 1 2 0.1U_0402_16V4Z~D Low = Only PCIE or SDVO is
DDCDATA EXP_TXP0 SDVOB_RED+ 52
F40 DVO_GREEN_CC1360 1 2 0.1U_0402_16V4Z~D CFG20
EXP_TXP1 SDVOB_GREEN+ 52 operational. (Default)
DVO_BLUE_C C1372 1 0.1U_0402_16V4Z~D
20 VGA_VSYNC H23 VSYNC EXP_TXP2 G36
DVO_CLK_C C1359 1
2
0.1U_0402_16V4Z~D
SDVOB_BLUE+ 52 *
20 VGA_HSYNC G23 HSYNC EXP_TXP3 H40 2 SDVOB_CLK+ 52 (PCIE/SDVO select)
20,36 VGA_BLU E23 BLUE EXP_TXP4 J36 High = PCIE/SDVO are operating
D23 L40
C22
BLUE# EXP_TXP5
M36 simu.
20,36 VGA_GRN GREEN EXP_TXP6
B22 GREEN# EXP_TXP7 N40
20,36 VGA_RED A21 RED EXP_TXP8 P36
B21 RED# EXP_TXP9 R40
EXP_TXP10 T36
EXP_TXP11 V40
2 1 J22 CRT_IREF EXP_TXP12 W36
Close to U40.J22 EXP_TXP13 Y40
R150 AA36
B 255_0402_1%~D EXP_TXP14 B
EXP_TXP15 AB40
+3.3V_RUN_R
CALISTOGA A0_FCBGA1466~D VGA_RED 1 2

R261 150_0402_1%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
VGA_GRN 1 2
1
R260 150_0402_1%~D
R229
R232
VGA_BLU 1 2
R295 150_0402_1%~D
D
G_CLK_DDC2 3 1 CLK_DDC2
CLK_DDC2 20,36
Q31
BSS138W-7-F_SOT323~D
G
2
+3.3V_RUN_R +3.3V_RUN_R
2
G
+3.3V_RUN_R
1 2 LCTLA_CLK G_DAT_DDC2 3 1 DAT_DDC2
DAT_DDC2 20,36
R283 10K_0402_5%~D
D
Q27
5
1 2 LCTLB_DATA BSS138W-7-F_SOT323~D
R279 10K_0402_5%~D 1
P
IN1 BIA_PWM_R
19,39 BIA_PWM 4 O
IN2 2
G
U8
3
74AHC1G08GW_SOT353-5~D
A A
1 2 PANEL_BKEN
R300 100K_0402_5%~D
LA-2791
5 4 3 2 1
5 4 3 2 1
U40H +2.5V_RUN
+1.05V_VCCP H22 C465 1
VCC_SYNC 0.1U_0402_16V4Z~D
AC14
AB14
VTT0
VTT1 VCCTX_LVDS0 B30 +2.5V_RUN 2
Should be placed on top
+2.5V_RUN
+3V_TVDAC
W14 C30 +3VRUN_TVDACA +3V_TVDAC L9
VTT2 VCCTX_LVDS1 +1.5VRUN_PCIE BLM18PG181SN1_0603~D
V14 A30
T14
VTT3
VTT4
VCCTX_LVDS2 W=30 mils BLM21PG600SN1D_0805~D
1
1 2 2 1 +3.3V_RUN_R
10U_0805_4VAM~D
R14 AB41 2 1 +1.5V_RUN C345
VTT5 VCC3G0
22n_0805_25V
0.1U_0402_16V4Z~D
220U_V_4VM_R45~D
10U_0805_4VAM~D
10U_0805_4VAM~D
P14 AJ41 0.1U_0402_16V4Z~D 1
VTT6 VCC3G1 2 3
C599
N14 L41 1 L35 1
VTT7 VCC3G2
C35
C22
CRB 270uF M14 VTT8 VCC3G3 N41 1 1
C49
C53
C59
L14 R41 +
VTT9 VCC3G4 2
AD13 VTT10 VCC3G5 V41
2
AC13 VTT11 VCC3G6 Y41
2 2 2 Route +2.5VRUN from GMCH pinG41 to
220U_V_4VM_R45~D
AB13 VTT12
D 1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VRUN_3GPLL decoupling cap (C345)<200mil to the edge. D
Y13 G41
VTT14 VCCA_3GBG +2.5V_RUN
C411
+ W13 H41
VTT15 VSSA_3GBG
V13 VTT16
U13 L37 BLM18PG181SN1_0603~D +3VRUN_TVDACB
2 VTT17 +2.5V_CRTDAC
T13 VTT18 VCCA_CRTDAC0 E21 1 2 +2.5V_RUN
0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
R13 VTT19 VCCA_CRTDAC1 F21 1 2
0.1U_0402_16V4Z~D
N13 VTT20 VSSA_CRTDAC2 G21 1 1
C357
22n_0805_25V
M13 VTT21 3
C364
L13 +2.5V_RUN 1
VTT22
C306
AB12 VTT23 VCCA_DPLLA B26 +1.5VRUN_DPLLA 2 2 CRTDAC: Route caps within
C299
AA12 VTT24 VCCA_DPLLB C39 +1.5VRUN_DPLLB
2
Y12 VTT25 VCCA_HPLL AF1 +1.5VRUN_HPLL 250mil of Alviso. Route FB
2
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
W12 R92
VTT26 within 3" of Calistoga
V12 VTT27 0_0603_5%~D
U12 VTT28 VCCA_LVDS A38 +2.5V_RUN 1 1
C323
T12 B39
1
+3VRUN_ATV
VTT29 VSSA_LVDS
C318
R12 VTT30
P12 VTT31 2 2 +3VRUN_ATVBG
N12 AF2
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VRUN_MPLL
+3VRUN_ATVBG Route VSSACRTDAC gnd from GMCH to +3VRUN_TVDACC
4.7U_0603_6.3V4Z~D
2.2U_0603_6.3V6K~D
L12 VTT34 VCCA_TVBG H20

R11 VTT35 VSSA_TVBG G20 VSSA_TVBG decoupling cap ground lead and then 1 2
1 1 P11 VTT36 connect to the gnd plane. 1 2
C36
C391
C390
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
N11 VTT37 3
22n_0805_25V
M11 VTT38 VCCA_TVDACA0 E19 +3VRUN_TVDACA 1
3
@ C598
22n_0805_25V
2 2
R10 VTT39 VCCA_TVDACA1 F19 Route VSSA_TVBG GND from GMCH to close pin A38 1 1
C305
P10 VTT40 VCCA_TVDACB0 C20 +3VRUN_TVDACB
decoupling cap ground lead and then
C23
C298
N10 VTT41 VCCA_TVDACB1 D20
2 C35, C305, C306 replace by 0
M10 VTT42 VCCA_TVDACC0 E20 +3VRUN_TVDACC connect to the GND plane.
P9 VTT43 VCCA_TVDACC1 F20 2 2 ohm 0805 resistor
N9 VTT44
M9 VTT45
R8 AH1 +1.5V_RUN VSSA_TVBG
VTT46 VCCD_HMPLL0
C
P8 VTT47 VCCD_HMPLL1 AH2 C
N8 +1.5V_RUN
VTT48
M8 VTT49
P7 A28 +2.5V_RUN
VTT50 VCCD_LVDS0
N7 VTT51 VCCD_LVDS1 B28
0.01U_0402_16V7K~D
M7 VTT52 VCCD_LVDS2 C28
10U_0805_4VAM~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5V_RUN_TVDAC 1 1
C310
0.47U_0402_16V4Z~D
M6 VTT55 VCCDQ_TVDAC H19 +1.5VRUN_QTVDAC 1 1
C325
C314
C324
U40_A6 A6 VTT56
R5 VTT57 VCCHV0 A23 +3.3V_RUN_R 2 2 +1.5VRUN_QTVDAC +1.5V_RUN +1.5V_RUN_TVDAC
0.1U_0402_16V4Z~D
P5 B23 L11
VTT58 VCCHV1 2 2 +1.5V_RUN
10U_0805_4VAM~D
1 N5 B25 BLM18PG181SN1_0603~D
VTT59 VCCHV2
C316
M5 VTT60 1 1 2 1
C336
C385
P4 VTT61 VCCAUX0 AK31
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
N4 VTT62 VCCAUX1 AF31
2 M4 AE31
VTT63 VCCAUX2 2 2 1 1 1 1
R3 VTT64 VCCAUX3 AC31 close pin B30/C30/A30
C37
C24
C304
C297
P3 VTT65 VCCAUX4 AL30
N3 VTT66 VCCAUX5 AK30
2 2 2 2
M3 VTT67 VCCAUX6 AJ30
+1.5V_RUN
0.22U_0402_10V4Z~D
R2 VTT68 VCCAUX7 AH30

P2 VTT69 VCCAUX8 AG30
1 M2 VTT70 VCCAUX9 AF30
C118
U40_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1
0.22U_0402_10V4Z~D
0.1U_0402_16V4Z~D
R1 VTT73 VCCAUX12 AC30

2
C437
U40_AB1
1 P1 VTT74 VCCAUX13 AG29

C164
N1 VTT75 VCCAUX14 AF29

2
M1 VTT76 VCCAUX15 AE29
0.47U_0402_16V4Z~D
VCCAUX16 AD29
2 AC29
1 VCCAUX17
C435
VCCAUX18 AG28
AF28 +1.5VRUN_HPLL +1.5VRUN_MPLL
VCCAUX19 L39 L38
VCCAUX20 AE28
2
B
VCCAUX21 AH22 45mA Max. 2 1 +1.5V_RUN 45mA Max. 2 1 +1.5V_RUN B
AJ21 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D
VCCAUX22
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AG14 VCCAUX32 VCCAUX23 AH21
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20 1 1 1 1
C413
C418
Y14 VCCAUX35 VCCAUX26 AH19
AF13 P19 Should be placed in cavity C94 C419
VCCAUX36 VCCAUX27 22U_0805_6.3VAM~D 22U_0805_6.3VAM~D
AE13 VCCAUX37 VCCAUX28 P16
+1.5V_RUN 2 2 2 2
AF12 VCCAUX38 VCCAUX29 AH15
AE12 P15 +1.5V_RUN
VCCAUX39 VCCAUX30 +1.5VRUN_3GPLL R267 L34
AD12 VCCAUX40 VCCAUX31 AH14
0.5_0805_1%~D BLM18PG181SN1_0603~D
1 2+3GPLL_R 2 1
0.1U_0402_16V4Z~D
10U_0805_4VAM~D
0.1U_0402_16V4Z~D
CALISTOGA A0_FCBGA1466~D
1 1 1
+1.5VRUN_DPLLA +1.5VRUN_DPLLB
C332
C404
C311
L28 L33
10U_MLZ2012E100PTAIN_60mA_25%_0805~D 10U_MLZ2012E100PTAIN_60mA_25%_0805~D
2 2 2
40mA Max. 2 1 +1.5V_RUN 40mA Max. 2 1 +1.5V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
470U_D2_2.5VM~D
1 1
470U_D2_2.5VM~D
1 1
C294
C331
C335
+ +
C322
2 2 2 2
+1.5V_RUN
+1.05V_VCCP
2 +3.3V_RUN_R
2 +2.5V_RUN
A
1 1 2 A
1 1 2 R12
R320 3 10_0402_5%~D
3 10_0402_5%~D
D8
D14 MMBD4148_SOT23~D
MMBD4148_SOT23~D DELL CONFIDENTIAL/PROPRIETARY
CRT DAC Voltge Follower Circuit - 700mV TV DAC Voltge Follower Circuit - 700mV
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
LA-2791
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP U40G +1.8V_SUS
AA33 VCC0 VCC_SM0 AU41

+1.5V_RUN W33 AT41 VCCSM_LF4
VCC1 VCC_SM1 VCCSM_LF5
P33 VCC2 VCC_SM2 AM41
+1.05V_VCCP N33 AU40
U40F VCC3 VCC_SM3
0.47U_0402_16V4Z~D
0.47U_0402_16V4Z~D
L33 VCC4 VCC_SM4 BA34
J33 VCC5 VCC_SM5 AY34
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA32 VCC6 VCC_SM6 AW34 1 1
C615
AC27 VCC_NCTF1 VCCAUX_NCTF1 AF27 Y32 VCC7 VCC_SM7 AV34
C612
D D
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 W32 VCC8 VCC_SM8 AU34
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 V32 VCC9 VCC_SM9 AT34
2 2
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 P32 VCC10 VCC_SM10 AR34
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 N32 VCC11 VCC_SM11 BA30
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 M32 VCC12 VCC_SM12 AY30
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 L32 VCC13 VCC_SM13 AW30
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 J32 VCC14 VCC_SM14 AV30
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 AA31 VCC15 VCC_SM15 AU30

AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 W31 VCC16 VCC_SM16 AT30
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 V31 VCC17 VCC_SM17 AR30 Place near U40.AT41 & AM41
C379
C358
C383
AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 T31 VCC18 VCC_SM18 AP30

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 R31 VCC19 VCC_SM19 AN30
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 P31 VCC20 VCC_SM20 AM30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 N31 VCC21 VCC_SM21 AM29
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 M31 VCC22 VCC_SM22 AL29
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 AA30 VCC23 VCC_SM23 AK29
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 Y30 VCC24 VCC_SM24 AJ29
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 W30 VCC25 VCC_SM25 AH29
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 V30 VCC26 VCC_SM26 AJ28
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 U30 VCC27 VCC_SM27 AH28
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 T30 VCC28 VCC_SM28 AJ27 1 1 1 1
C438
C441
C444
C452
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 R30 VCC29 VCC_SM29 AH27
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 P30 VCC30 VCC_SM30 BA26
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
V25 AB17 M30 AW26
U25
VCC_NCTF26
VCC_NCTF27
VCCAUX_NCTF26
VCCAUX_NCTF27 AA17 L30
VCC32
VCC33
P O W E R VCC_SM32
VCC_SM33 AV26
1U_0603_10V4Z~D
10U_0805_4VAM~D
10U_0805_4VAM~D
T25 W17 AA29 AU26

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC34 VCC_SM34
R25 VCC_NCTF29 VCCAUX_NCTF29 V17 Y29 VCC35 VCC_SM35 AT26
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 W29 VCC36 VCC_SM36 AR26
C366
C367
C368
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 V29 VCC37 VCC_SM37 AJ26

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 U29 VCC38 VCC_SM38 AH26
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 R29 VCC39 VCC_SM39 AJ25
C 2 2 2 C
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 P29 VCC40 VCC_SM40 AH25
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 M29 VCC41 VCC_SM41 AJ24
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 L29 VCC42 VCC_SM42 AH24
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 AB28 VCC43 VCC_SM43 BA23
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 AA28 VCC44 VCC_SM44 AJ23
0.47U_0402_16V4Z~D
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 Y28 VCC45 VCC_SM45 BA22
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 V28 VCC46 VCC_SM46 AY22
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 U28 VCC47 VCC_SM47 AW22 1
U23 VCC_NCTF42 VCCAUX_NCTF42 U16 T28 VCC48 VCC_SM48 AV22
C616
T23 VCC_NCTF43 VCCAUX_NCTF43 T16 R28 VCC49 VCC_SM49 AU22
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 P28 VCC50 VCC_SM50 AT22
2
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 N28 VCC51 VCC_SM51 AR22
220U_V_4VM_R45~D
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 M28 VCC52 VCC_SM52 AP22

1 U22 VCC_NCTF47 VCCAUX_NCTF47 AE15 L28 VCC53 VCC_SM53 AK22
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 P27 VCC54 VCC_SM54 AJ22
C423
+ R22 AC15 N27 AK21

AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 M27 VCC56 VCC_SM56 AK20 Place near U40.BA23
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 L27 VCC57 VCC_SM57 BA19
2
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 P26 VCC58 VCC_SM58 AY19
330U_D2E_2.5VM_R9~D
10U_0805_4VAM~D
10U_0805_4VAM~D
T21 VCC_NCTF53 VCCAUX_NCTF53 W15 N26 VCC59 VCC_SM59 AW19
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 L26 VCC60 VCC_SM60 AV19 1
AD20 VCC_NCTF55 VCCAUX_NCTF55 U15 N25 VCC61 VCC_SM61 AU19 1 1
V20 T15 M25 AT19 +
C160
C158
@ C165
CRB 270uF U20
T20
VCC_NCTF57 VCCAUX_NCTF57 R15 L25
P24
VCC63 VCC_SM63 AR19
AP19
VCC_NCTF58 VCC64 VCC_SM64 2 2 2
R20 VCC_NCTF59 N24 VCC65 VCC_SM65 AK19
AD19 VCC_NCTF60 VSS_NCTF0 AE27 M24 VCC66 VCC_SM66 AJ19
V19 VCC_NCTF61 VSS_NCTF1 AE26 AB23 VCC67 VCC_SM67 AJ18
U19 VCC_NCTF62 VSS_NCTF2 AE25 AA23 VCC68 VCC_SM68 AJ17
220U_V_4VM_R45~D
T19 VCC_NCTF63 VSS_NCTF3 AE24 Y23 VCC69 VCC_SM69 AH17

1 AD18 VCC_NCTF64 VSS_NCTF4 AE23 P23 VCC70 VCC_SM70 AJ16
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N23 VCC71 VCC_SM71 AH16
C620
B + AB18 AE21 M23 BA15 B

VCC_NCTF66 VSS_NCTF6 VCC72 VCC_SM72
AA18 VCC_NCTF67 VSS_NCTF7 AE20 L23 VCC73 VCC_SM73 AY15
0.47U_0402_16V4Z~D
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AC22 VCC74 VCC_SM74 AW15
2
W18 VCC_NCTF69 VSS_NCTF9 AE18 AB22 VCC75 VCC_SM75 AV15
V18 VCC_NCTF70 VSS_NCTF10 AC17 Y22 VCC76 VCC_SM76 AU15 1
U18 VCC_NCTF71 VSS_NCTF11 Y17 W22 VCC77 VCC_SM77 AT15
C617
T18 VCC_NCTF72 VSS_NCTF12 U17 P22 VCC78 VCC_SM78 AR15
N22 VCC79 VCC_SM79 AJ15
+1.05V_VCCP 2
M22 VCC80 VCC_SM80 AJ14
M19 +1.8V_SUS L22 AJ13
VCC100 VCC81 VCC_SM81
L19 VCC101 VCC_SM100 AR6 AC21 VCC82 VCC_SM82 AH13
N18 VCC102 VCC_SM101 AP6 AA21 VCC83 VCC_SM83 AK12
M18 VCC103 VCC_SM102 AN6 W21 VCC84 VCC_SM84 AJ12
L18 VCC104 VCC_SM103 AL6 N21 VCC85 VCC_SM85 AH12
P17 VCC105 VCC_SM104 AK6 M21 VCC86 VCC_SM86 AG12
N17 VCC106 VCC_SM105 AJ6 L21 VCC87 VCC_SM87 AK11
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC20 VCC88 VCC_SM88 BA8 Place near U40.BA15
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AB20 VCC89 VCC_SM89 AY8
M16 VCC109 Y20 VCC90 VCC_SM90 AW8
0.47U_0402_16V4Z~D
0.47U_0402_16V4Z~D
L16 VCC110 W20 VCC91 VCC_SM91 AV8

P20 VCC92 VCC_SM92 AT8
1 1 N20 VCC93 VCC_SM93 AR8
CALISTOGA A0_FCBGA1466~D M20 AP8
VCC94 VCC_SM94
C613
C614
L20 VCC95 VCC_SM95 BA6

AB19 VCC96 VCC_SM96 AY6
2 2
AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6
CALISTOGA A0_FCBGA1466~D
A
Place near U40.AV1 & AJ1 A
LA-2791
5 4 3 2 1
5 4 3 2 1
U40I
U40J
AC41 VSS0 VSS100 AE34
AA41 VSS1 VSS101 AC34 AN21 VSS200 VSS280 AG10
W41 VSS2 VSS102 C34 AL21 VSS201 VSS281 AC10
T41 VSS3 VSS103 AW33 AB21 VSS202 VSS282 W10
P41 VSS4 VSS104 AV33 Y21 VSS203 VSS283 U10
D D
M41 VSS5 VSS105 AR33 P21 VSS204 VSS284 BA9
J41 VSS6 VSS106 AE33 K21 VSS205 VSS285 AW9
F41 VSS7 VSS107 AB33 J21 VSS206 VSS286 AR9
AV40 VSS8 VSS108 Y33 H21 VSS207 VSS287 AH9
AP40 VSS9 VSS109 V33 C21 VSS208 VSS288 AB9
AN40 VSS10 VSS110 T33 AW20 VSS209 VSS289 Y9
AK40 VSS11 VSS111 R33 AR20 VSS210 VSS290 R9
AJ40 VSS12 VSS112 M33 AM20 VSS211 VSS292 G9
AH40 VSS13 VSS113 H33 AA20 VSS212 VSS291 E9
AG40 VSS14 VSS114 G33 K20 VSS213 VSS293 A9
AF40 VSS15 VSS115 F33 B20 VSS214 VSS294 AG8
AE40 VSS16 VSS116 D33 A20 VSS215 VSS295 AD8
B40 VSS17 VSS117 B33 AN19 VSS216 VSS296 AA8
AY39 VSS18 VSS118 AH32 AC19 VSS217 VSS297 U8
AW39 VSS19 VSS119 AG32 W19 VSS218 VSS298 K8
AV39 VSS20 VSS120 AF32 K19 VSS219 VSS299 C8
AR39 VSS21 VSS121 AE32 G19 VSS220 VSS300 BA7
AN39 VSS22 VSS122 AC32 C19 VSS221 VSS301 AV7
AJ39 VSS23 VSS123 AB32 AH18 VSS222 VSS302 AP7
AC39 VSS24 VSS124 G32 P18 VSS223 VSS303 AL7
AB39 VSS25 VSS125 B32 H18 VSS224 VSS304 AJ7
AA39 VSS26 VSS126 AY31 D18 VSS225 VSS305 AH7
Y39 VSS27 VSS127 AV31 A18 VSS226 VSS306 AF7
W39 VSS28 VSS128 AN31 AY17 VSS227 VSS307 AC7
V39 VSS29 VSS129 AJ31 AR17 VSS228 VSS308 R7
T39 AG31 AP17 G7
R39
VSS30
VSS31
VSS130
VSS131 AB31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
P39 VSS32 VSS132 Y31 AK17 VSS231 VSS311 AG6
N39 VSS33 VSS133 AB30 AV16 VSS232 VSS312 AD6
M39 E30 AN16 AB6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 AL16
VSS233
VSS234
VSS313
VSS314 Y6
J39 VSS36 VSS136 AN29 J16 VSS235 VSS315 U6
C C
H39 VSS37 VSS137 AB29 F16 VSS236 VSS316 N6
G39 VSS38 VSS138 T29 C16 VSS237 VSS317 K6
F39 VSS39 VSS139 N29 AN15 VSS238 VSS318 H6
D39 VSS40 VSS140 K29 AM15 VSS239 VSS319 B6
AT38 VSS41 VSS141 G29 AK15 VSS240 VSS320 AV5
AM38 VSS42 VSS142 E29 N15 VSS241 VSS321 AF5
AH38 VSS43 VSS143 C29 M15 VSS242 VSS322 AD5
AG38 VSS44 VSS144 B29 L15 VSS243 VSS323 AY4
AF38 VSS45 VSS145 A29 B15 VSS244 VSS324 AR4
AE38 VSS46 VSS146 BA28 A15 VSS245 VSS325 AP4
C38 VSS47 VSS147 AW28 BA14 VSS246 VSS326 AL4
AK37 VSS48 VSS148 AU28 AT14 VSS247 VSS327 AJ4
AH37 VSS49 VSS149 AP28 AK14 VSS248 VSS328 Y4
AB37 VSS50 VSS150 AM28 AD14 VSS249 VSS329 U4
AA37 VSS51 VSS151 AD28 AA14 VSS250 VSS330 R4
Y37 VSS52 VSS152 AC28 U14 VSS251 VSS331 J4
W37 VSS53 VSS153 W28 K14 VSS252 VSS332 F4
V37 VSS54 VSS154 J28 H14 VSS253 VSS333 C4
T37 VSS55 VSS155 E28 E14 VSS254 VSS334 AY3
R37 VSS56 VSS156 AP27 AV13 VSS255 VSS335 AW3
P37 VSS57 VSS157 AM27 AR13 VSS256 VSS336 AV3
N37 VSS58 VSS158 AK27 AN13 VSS257 VSS337 AL3
M37 VSS59 VSS159 J27 AM13 VSS258 VSS338 AH3
L37 VSS60 VSS160 G27 AL13 VSS259 VSS339 AG3
J37 VSS61 VSS161 F27 AG13 VSS260 VSS340 AF3
H37 VSS62 VSS162 C27 P13 VSS261 VSS341 AD3
G37 VSS63 VSS163 B27 F13 VSS262 VSS342 AC3
F37 VSS64 VSS164 AN26 D13 VSS265 VSS343 AA3
D37 VSS65 VSS165 M26 B13 VSS264 VSS344 G3
AY36 VSS66 VSS166 K26 AY12 VSS263 VSS345 AT2
AW36 VSS67 VSS167 F26 AC12 VSS266 VSS346 AR2
AN36 VSS68 VSS168 D26 K12 VSS267 VSS347 AP2
B B
AH36 VSS69 VSS169 AK25 H12 VSS268 VSS348 AK2
AG36 VSS70 VSS170 P25 E12 VSS269 VSS349 AJ2
AF36 VSS71 VSS171 K25 AD11 VSS270 VSS350 AD2
AE36 VSS72 VSS172 H25 AA11 VSS271 VSS351 AB2
AC36 VSS73 VSS173 E25 Y11 VSS272 VSS352 Y2
C36 VSS74 VSS174 D25 J11 VSS273 VSS353 U2
B36 VSS75 VSS175 A25 D11 VSS274 VSS354 T2
BA35 VSS76 VSS176 BA24 B11 VSS275 VSS355 N2
AV35 VSS77 VSS177 AU24 AV10 VSS276 VSS356 J2
AR35 VSS78 VSS178 AL24 AP10 VSS277 VSS357 H2
AH35 VSS79 VSS179 AW23 AL10 VSS278 VSS358 F2
AB35 VSS80 VSS180 AT23 AJ10 VSS279 VSS359 C2
AA35 VSS81 VSS181 AN23 VSS360 AL1
Y35 VSS82 VSS182 AM23
W35 AH23 CALISTOGA A0_FCBGA1466~D
VSS83 VSS183
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21
A CALISTOGA A0_FCBGA1466~D A
LA-2791
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS +1.8V_SUS
11 DDR_A_DQS#[0..7] ON TOP SIDE V_DDR_MCH_REF
V_DDR_MCH_REF 10,17,48
11 DDR_A_D[0..63]
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIM2
11 DDR_A_DM[0..7] 1 VREF VSS 2
1
3 4 DDR_A_D7 1 1
DDR_A_D0 VSS DQ4 DDR_A_D4 R51
11 DDR_A_DQS[0..7] Layout Note: 5 DQ0 DQ5 6
C226
C224
DDR_A_D1 7 8 100K_0402_5%~D
Place near JDIM1 9
DQ1 VSS
10 DDR_A_DM0
11 DDR_A_MA[0..13] VSS DM0 2 2
DDR_A_DQS#0 11 12
2
DDR_A_DQS0 DQS0# VSS DDR_A_D6
13 DQS0 DQ6 14
15 16 DDR_A_D5
DDR_A_D3 VSS DQ7
17 DQ2 VSS 18
D DDR_A_D2 DDR_A_D13 D
19 DQ3 DQ12 20
21 22 DDR_A_D12
DDR_A_D14 VSS DQ13
23 DQ8 VSS 24
+1.8V_SUS DDR_A_D8 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
DDR_A_DQS#1 29 30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 10
DDR_A_DQS1 31 32 M_CLK_DDR#0
DQS1 CK0# M_CLK_DDR#0 10
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
33 VSS VSS 34
1 1 1 1 1 DDR_A_D11 35 36 DDR_A_D15
DQ10 DQ14
C213
C214
C222
C225
C229
DDR_A_D10 37 38 DDR_A_D9
DQ11 DQ15
39 VSS VSS 40
2 2 2 2 2
41 VSS VSS 42
DDR_A_D17 DQ16 DQ20 DDR_A_D21
45 DQ17 DQ21 46 PM_EXTTS#0_R 17
47 VSS VSS 48
DDR_A_DQS#2 49 50 PM_EXTTS#0_R 1 2 PM_EXTTS#0 10
DDR_A_DQS2 DQS2# NC DDR_A_DM2 R177
51 DQS2 DM2 52
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
53 54 0_0402_5%~D
DDR_A_D22 VSS VSS DDR_A_D18
1 1 1 1 55 DQ18 DQ22 56
C212
C215
C223
C227
DQ19 DQ23
59 VSS VSS 60
2 2 2 2 DDR_A_D29 DQ24 DQ28 DDR_A_D25
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
10 DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA 10
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS2 85 86
11 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
Layout Note: 91 A9 A7 92
Place one cap close to every 2 pullup 95
A8 A6
96
DDR_A_MA5 VDD VDD DDR_A_MA4
resistors terminated to +0.9V_DDR_VTT 97 A5 A4 98
DDR_A_MA1 A3 A2 DDR_A_MA0
101 A1 A0 102
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 11
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
11 DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# 11
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
11 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 10
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
11 DDR_A_CAS# CAS# ODT0 M_ODT0 10
+0.9V_DDR_VTT DDR_CS1_DIMMA# 115 116 DDR_A_MA13
10 DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
M_ODT1 119 120
10 M_ODT1 NC/ODT1 NC
121 VSS VSS 122
DDR_A_D35 123 124 DDR_A_D36
125 DQ33 DQ37 126
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
127 VSS VSS 128

DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
1 1 1 1 1 1 1 1 1 1 1 1 1 131 DQS4 VSS 132
133 134 DDR_A_D39
DDR_A_D34 VSS DQ38 DDR_A_D38
135 DQ34 DQ39 136
DDR_A_D33 137 138
2 2 2 2 2 2 2 2 2 2 2 2 2 DQ35 VSS DDR_A_D44
139 VSS DQ44 140
C221
C220
C219
C218
C217
C216
C231
C232
C233
C235
C237
C236
C234
DDR_A_D43 141 142 DDR_A_D40

B DDR_A_D45 DQ40 DQ45 B
143 DQ41 VSS 144
145 146 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
147 DM5 DQS5 148
149 VSS VSS 150
DDR_A_D46 151 152 DDR_A_D41
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D49
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1
NC,TEST CK1 M_CLK_DDR1 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#1
VSS CK1# M_CLK_DDR#1 10
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
RN25 RN27 169 170
DDR_A_MA1 DQS6 DM6
1 4 4 1 DDR_A_MA9 171 VSS VSS 172
DDR_A_MA3 2 3 3 2 DDR_A_MA12 DDR_A_D55 173 174 DDR_A_D50
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D51 DQ50 DQ54 DDR_A_D54
175 DQ51 DQ55 176
RN24 RN19 Layout Note: 177 VSS VSS 178
DDR_A_BS0 1 4 4 1 DDR_A_MA7 Place these resistor DDR_A_D60 179 180 DDR_A_D57
DDR_A_MA10 DQ56 DQ60
2 3 3 2 DDR_A_MA6 closely DIMM0,all DDR_A_D61 181 DQ57 DQ61 182 DDR_A_D56
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 183 184
RN16 RN26 trace length<750 mil DDR_A_DM7 VSS VSS DDR_A_DQS#7
185 DM7 DQS7# 186
DDR_A_RAS# 1 4 4 1 DDR_A_MA5 187 188 DDR_A_DQS7
DDR_CS0_DIMMA# 2 VSS DQS7
3 3 2 DDR_A_MA8 DDR_A_D58 189 DQ58 VSS 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_A_D59 191 192 DDR_A_D62
RN18 DQ59 DQ62 DDR_A_D63
RN23 193 194
DDR_A_CAS# VSS DQ63
1 4 4 1 DDR_A_MA4 6,17 CLK_SDATA
CLK_SDATA 195 SDA VSS 196
DDR_A_WE# 2 3 3 2 DDR_A_MA2 CLK_SCLK 197 198 R175 1 2 100K_0402_5%~D
6,17 CLK_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 R176 1 2 100K_0402_5%~D
RN17 VDDSPD SA1
RN22
0.1U_0402_16V4Z~D
M_ODT1 2.2U_0603_6.3V6K~D
1 4 4 1 DDR_A_MA0 201 GND GND 202
DDR_CS1_DIMMA# 2 3 3 2 DDR_A_BS1 1 1
C228
C230
A 56_0404_4P2R_5%~D 56_0404_4P2R_5%~D TYCO_1470815-2~D A
RN15
4 1 M_ODT0
2 2
DIMMA
3 2 DDR_A_MA13
56_0404_4P2R_5%~D RESERVE
RN20
RN21 Layout Note:
DDR_CKE0_DIMMA 2 1 DDR_CKE1_DIMMA
DDR_A_BS2 1
3
4
4
3 2 DDR_A_MA11
Place these resistor
closely DIMM0,all
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT1
LA-2791
5 4 3 2 1
5 4 3 2 1
+1.8V_SUS +1.8V_SUS
11 DDR_B_DQS#[0..7]
V_DDR_MCH_REF
11 DDR_B_D[0..63]
ON BOTTOM SIDE V_DDR_MCH_REF 10,16,48
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
JDIM1
11 DDR_B_DM[0..7] Layout Note: 1 VREF VSS 2
3 4 DDR_B_D5 1 1
Place near JDIM2 DDR_B_D1 5
VSS DQ4
6 DDR_B_D4
11 DDR_B_DQS[0..7] DQ0 DQ5
C253
C252
DDR_B_D0 7 8
DQ1 VSS DDR_B_DM0
11 DDR_B_MA[0..13] 9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D2
DQS0 DQ6 DDR_B_D3
15 VSS DQ7 16
DDR_B_D6 17 18
DDR_B_D7 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
D +1.8V_SUS 21 22 DDR_B_D13 D
DDR_B_D8 VSS DQ13
23 DQ8 VSS 24
DDR_B_D9 25 26 DDR_B_DM1
DQ9 DM1
27 VSS VSS 28
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 10
1 1 1 1 1 DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 10
C249
C254
C261
C242
C241
33 VSS VSS 34
DDR_B_D14 35 36 DDR_B_D10
DDR_B_D15 DQ10 DQ14 DDR_B_D11
37 DQ11 DQ15 38
2 2 2 2 2
39 VSS VSS 40
41 VSS VSS 42
45 DQ17 DQ21 46
47 VSS VSS 48
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_B_DQS#2 49 50 PM_EXTTS#0_R PM_EXTTS#0_R 16
DDR_B_DQS2 DQS2# NC DDR_B_DM2
1 1 1 1 51 DQS2 DM2 52
C240
C239
C251
C255
53 VSS VSS 54
57 DQ19 DQ23 58
2 2 2 2
59 VSS VSS 60
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
75 DQ27 DQ31 76
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
C 10 DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB 10 C
81 VDD VDD 82
83 NC NC/A15 84
Layout Note: DDR_B_BS2 85 86
11 DDR_B_BS2 BA2 NC/A14
87 88
Place one cap close to every 2 pullup DDR_B_MA12 89
VDD VDD
90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
resistors terminated to +0.9V_DDR_VTT 91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 DDR_B_BS1 11
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
11 DDR_B_BS0 107 BA0 RAS# 108 DDR_B_RAS# 11
+0.9V_DDR_VTT DDR_B_WE# 109 110 DDR_CS2_DIMMB#
11 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 10
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
11 DDR_B_CAS# CAS# ODT0 M_ODT2 10
DDR_CS3_DIMMB# 115 116 DDR_B_MA13
10 DDR_CS3_DIMMB# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
M_ODT3 119 120

10 M_ODT3 NC/ODT1 NC
121 VSS VSS 122
1 1 1 1 1 1 1 1 1 1 1 1 1 DDR_B_D33 123 124 DDR_B_D36
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_B_DQS#4 129 130 DDR_B_DM4
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_B_DQS4 DQS4# DM4
131 DQS4 VSS 132
C248
C247
C246
C245
C244
C243
C269
C268
C267
C266
C265
C264
C263
133 134 DDR_B_D38

DDR_B_D35 VSS DQ38 DDR_B_D39
135 DQ34 DQ39 136
DDR_B_D34 137 138
DQ35 VSS DDR_B_D44
139 VSS DQ44 140
DDR_B_D41 141 142 DDR_B_D45
DDR_B_D40 DQ40 DQ45
143 DQ41 VSS 144
B DDR_B_DQS#5 B
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5
DM5 DQS5
149 VSS VSS 150
DDR_B_D43 151 152 DDR_B_D42
153 DQ43 DQ47 154
155 VSS VSS 156
DDR_B_D49 157 158 DDR_B_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR2
NC,TEST CK1 M_CLK_DDR2 10
+0.9V_DDR_VTT 165 166 M_CLK_DDR#2
VSS CK1# M_CLK_DDR#2 10
DDR_B_DQS#6 167 168
RN13 DDR_B_DQS6 DQS6# VSS DDR_B_DM6
RN11 169 170
DDR_B_MA1 DDR_B_MA9 DQS6 DM6
1 4 4 1 171 VSS VSS 172
DDR_B_MA3 2 3 3 2 DDR_B_MA12 DDR_B_D55 173 174 DDR_B_D54
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DDR_B_D50 DQ50 DQ54 DDR_B_D51
175 DQ51 DQ55 176
RN10 RN7 177 178
DDR_B_BS0 DDR_CKE3_DIMMB DDR_B_D61 VSS VSS DDR_B_D60
1 4 4 1 179 DQ56 DQ60 180
DDR_B_MA10 2 3 3 2 DDR_B_MA11 DDR_B_D56 181 182 DDR_B_D57
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D DQ57 DQ61
Layout Note: 183 VSS VSS 184
RN4 RN12 Place these resistor DDR_B_DM7 185 186 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA5 DM7 DQS7# DDR_B_DQS7
1 4 4 1 closely DIMM0,all 187 VSS DQS7 188
DDR_B_BS1 2 3 3 2 DDR_B_MA8 DDR_B_D58 189 190
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D trace length<750 mil DDR_B_D59 DQ58 VSS DDR_B_D62
191 DQ59 DQ62 192
RN3 RN6 193 194 DDR_B_D63 +3.3V_RUN
DDR_B_RAS# DDR_B_MA7 CLK_SDATA VSS DQ63
1 4 4 1 6,16 CLK_SDATA 195 SDA VSS 196
DDR_CS2_DIMMB# 2 3 3 2 DDR_B_MA6 CLK_SCLK 197 198
6,16 CLK_SCLK SCL SAO
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D +3.3V_RUN 199 200 2 1
VDDSPD SA1
100K_0402_5%~D
RN9 RN5
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
DDR_B_CAS# 1 4 4 1 DDR_B_MA4 201 202 R174

GND GND
1
DDR_B_WE# 2 3 3 2 DDR_B_MA2 10K_0402_5%~D
R173
56_0404_4P2R_5%~D 56_0404_4P2R_5%~D 1 1 TYCO_1565917-4~D
C549
C548
A RN2 A
4 1 M_ODT2 DIMMB
3 2 DDR_B_MA13
STANDARD
2
56_0404_4P2R_5%~D 2 2
RN14
RN8 Layout Note:
DDR_CS3_DIMMB# 2 DDR_B_BS2
M_ODT3 1
3
4
4
3
1
2 DDR_CKE2_DIMMB
Place these resistor
closely DIMM0,all
56_0404_4P2R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
56_0404_4P2R_5%~D trace length TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Max=1.3" BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRII-SODIMM SLOT2
LA-2791
5 4 3 2 1
5 4 3 2 1
FAN1 Control and Tachometer

Place near the bottom SODIMM
+3.3V_RUN
+5V_SUS +5V_SUS
1
R479
1
1 2
D R413 R481 R480 D
10K_0402_5%~D 2.21K_0603_1%~D 10K_0603_1%_TSM1A103F34D3RZ~D 10K_0402_5%~D
2
FAN1_TACH 39
2
1
D
VCP2 Q21 2 5V_CAL_SIO2# 38
1 2N7002W-7-F_SOT323~D G
C1778 1 S
3
100P_0402_50V8J~D
@ C79
2 2200P_0402_25V7K~D
2
JFAN1
R479 place on bottom side
+FAN1_VOUT 1 1 next to SoDIMM connector
FAN1_TACH_FB 2 2
22U_0805_6.3VAM~D
22U_0805_6.3VAM~D
3 3
1
1 1
C210
@ C1779
@ D35 MOLEX_53398-0371~D
RB751S40T1_SOD523-2~D
2 2
2
R262
VSET=
x 3.3V
R249+R262
Tp-70
C VSET = C
Place C341 close to the Guardian

21
pins as possible
7 H_THERMDA
1
DP2, DN2 routing together. Trace
C341
width / Spacing = 10 / 10 mil 2200P_0402_50V7K~D
2
7 H_THERMDC
U15
R50 39 DAT_SMB 7
+3.3V_SUS 49.9_0603_1%~D SMDATA
39 CLK_SMB 8 SMBCLK ATF_INT# 17 ATF_INT# 39
+3.3V_SUS 1 2 R136
1 +3.3V_SUS 1 2 7.5K_0402_5%~D 23 LDO_SHDN#_ADDR
1
R241 C41 35
8.2K_0402_5%~D 0.1U_0402_16V4Z~D DP2
34 DN2 VCP 3
2 VCP2
VCP 40
+3VSUS_THRM 12 REM_DIODE1_N, REM_DIODE1_P routing together.
2
+1.05V_VCCP THERMATRIP1# +3V_SUS

23,42 SUSPWROK 1 2 21 VSUS_PWRGD PAD_GND 41 Trace width / Spacing = 10 / 10 mil
R40 R42 1K_0402_5%~D
1
2.2K_0402_5%~D C 1 18
+RTC_CELL +RTC_PWR3V
1 2 2 1 LDO_POK 31 2.5V_RUN_PWRGD 42
B C42 C44 1 2 13
42 ICH_PWRGD# +3V_PWROK#
Q39 E 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D R38 1K_0402_5%~D Place C47 close to the Guardian
3
MMST3904-7-F_SOT323~D
MMST3904-7-F_SOT323~D 39,40 POWER_SW# 38
7 H_THERMTRIP#
2 POWER_SW# pins as possible
THERMATRIP1# 14 36 REM_DIODE1_N
THERMTRIP1# DN1 REM_DIODE1_P
DP1 37 1 1
3
B
E B
THERMATRIP2# 15 THERMTRIP2# +3.3V_ALW
Q12
B
2
+3.3V_SUS 1 2 THERMATRIP3# 16 30 C47 @ C1803
+3.3V_SUS R41 8.2K_0402_5%~D THERMTRIP3# THERMTRIP_SIO 2 2200P_0402_50V7K~D C 2 2200P_0402_50V7K~D
4
1
ACAV_CLR
1
1
1 39 VSET
29 R60 Place under CPU
HW_LOCK#
1
C303 R249 9 22 10K_0402_5%~D

R239 0.1U_0402_16V4Z~D 332K_0402_1%~D VSS SYS_SHDN#
8.2K_0402_5%~D 2
2
2
2
1K_0402_5%~D
1 24 LDO_SET THERMTRIP_SIO 38 @ R1634

DP3 LDO_SET
R61
2200P_0402_50V7K~D
2 10K_0402_5%~D
2
+1.05V_VCCP THERMATRIP2# DN3

LDO_OUT 25 ACAV_IN 39,50,51 2 1 +RTC_CELL
1
R39 1 +FAN1_VOUT 6 27
FAN_OUT LDO_OUT
1
C317
2.2K_0402_5%~D C 1 THERM_STP# 46
1
1 2 2 R262 33
B C43 118K_0402_1%~D FAN_DAC
LDO_IN 26
Q34 E 0.1U_0402_16V4Z~D 2 +2.5V_RUN
28
3
MMST3904-7-F_SOT323~D 2 LDO_IN
10 GPIO1 +2.5V_RUN
10U_0805_10V4Z~D
10 THERMTRIP_MCH# 11 GPIO2
1
19 GPIO3
20 5 1 1 @ R1800
GPIO4 VDD_5V
C1774
REM_DIODE3_N, REM_DIODE3_P routing together. 31.6K_0402_1%~D
+3V_LDOIN
32 GPIO5
Trace width / Spacing = 10 / 10 mil C150
0.1U_0402_16V4Z~D
2
REM_DIODE3_N EMC4000 C_QFN40~D 2 2 @
Q84 1 REM_DIODE3_P LDO_SET
3
1K_0402_5%~D
E
MMST3904-7-F_SOT323~D
1 SMBUS ADDRESS : 2F
1
B
2 R1643
R1789
@ C1804 C1773 Place cap close to the 2 1 +3.3V_RUN
2200P_0402_50V7K~D 2
10U_0805_10V4Z~D
1U_0603_10V4Z~D
C
2200P_0402_50V7K~D Guardian pins as possible. 0.27_1210_5%~D
1
2
1 1
C571
1 1 +5V_RUN
2
C1776
A SNIFFER_GREEN# C152 A
Place near the bottom SODIMM 43 SNIFFER_GREEN#
0.1U_0402_16V4Z~D
43 SNIFFER_YELLOW# SNIFFER_YELLOW# C1777
0.1U_0402_16V4Z~D 2 2 @
2 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
Q9
JLVDS SI3456BDV-T1-E3_TSOP6~D
45 44 LCD_BCLK- +15V_SUS +LCDVDD +3.3V_RUN_R
D
MGND1 TXUCLKUT- LCD_BCLK- 12
LCD_BCLK+
S
46 MGND2 TXUCLKUT+ 43 LCD_BCLK+ 12 6
47 42 +15V_SUS 4 5
MGND3 GND1 LCD_B2- +LCDVDD
48 MGND4 TXUOUT2- 41 LCD_B2- 12 2
1
49 40 LCD_B2+ 1
MGND5 TXUOUT2+ LCD_B2+ 12
0.1U_0402_16V4Z~D
R272
G
50 MGND6 GND2 39
1
51 38 LCD_B1- R54 100K_0402_5%~D
LCD_B1- 12
3
MGND7 TXUOUT1- LCD_B1+ R35 100K_0402_5%~D
52 MGND8 TXUOUT1+ 37 LCD_B1+ 12 1
C29
53 36 470_0402_5%~D
2
MGND9 GND3 LCD_B0-
54 35 LCD_B0- 12
2
MGND10 TXUOUT0- LCD_B0+
55 34 LCD_B0+ 12
2
MGND11 TXUOUT0+ 2
2N7002W-7-F_SOT323~D
0.1U_0603_50V4Z~D
56 NC GND4 33
1
57 32 LCD_ACLK-
NC TXLCLKOUT- LCD_ACLK- 12
1
LCD_ACLK+ +3.3V_RUN_R D D @ R79
TXLCLKOUT+ 31 LCD_ACLK+ 12 1
Q10
C315
30 2 2 100K_0402_5%~D
GND5 LCD_A2- G G
TXLOUT2- 29 LCD_A2- 12
28 LCD_A2+ S Q37 S
LCD_A2+ 12
2
TXLOUT2+ 2
10K_0402_5%~D
10K_0402_5%~D
27 2N7002W-7-F_SOT323~D
GND6
1
26 LCD_A1-
TXLOUT1- LCD_A1- 12
R73
R74
25 LCD_A1+
O
TXLOUT1+ LCD_A1+ 12
GND7 24
23 LCD_A0-
TXLOUT0- LCD_A0- 12
22 LCD_A0+ 2
LCD_A0+ 12 12 ENVDD
2
TXLOUT0+ I
GND8 21
C LDDC_CLK C
PANEL_I2C_CLK 20 LDDC_CLK 12
G
19 LDDC_DATA Q8
PANEL_I2C_DAT LDDC_DATA 12
18 DDTC124EUA-7-F_SOT323~D
3
GND9
VEDID 17 +3.3V_RUN_R
GND10 16
LCDVDD1 15 +LCDVDD
14 C27 1 1
LCDVDD2 LCD_TST
PNL_SLFTST 13 LCD_TST 23
12 C26
LCDPWR_SRC 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
LCDPWR_SRC 11
2 2
LCDPWR_SRC 10
GND11 9
8 BACKLITEON
BACKLITEON for D'05;
FPBACK
GND12 7 BIA_PWM for M'07
PBAT_SMBCLK 6 SBAT_SMBCLK 39,45 1 2 BIA_PWM 12,39
5 R520 0_0402_5%~D
PBAT_SMBDAT SBAT_SMBDAT 39,45
GND13 4
+5V_ALWF 3 +5V_ALW
LAMP_START 2
1 D2 1
GND14 LAMP_D_STAT# 1 2
IPEX_20330-044E-11F~D C28
RB751S40T1_SOD523-2~D 0.1U_0402_16V4Z~D
2
@
LAMP_STAT#
LAMP_STAT# 23
Q32 +INV_PWR_SRC
M'07 inverter support - Depop D2. +PWR_SRC FDS4435_NL_SO8~D
40mil
D'05 inverter support - Populate D2 40mil 8
1 7
B B
2 6
+INV_PWR_SRC 3 5
1000P_0402_50V7K~D
1
1
1 1
+3.3V_RUN_R
C290
R235 C289
4
C296 100K_0402_5%~D 0.1U_0603_50V4Z~D
0.1U_0603_50V4Z~D 2
2 2
2
5
U7
FPBACK_EN 1
P
38 FPBACK_EN IN1
4 BACKLITEON
PANEL_BKEN O
1 2 2 IN2
G
R1767 0_0402_5%~D R236 Q29

74AHC1G08GW_SOT353-5~D 3 2N7002W-7-F_SOT323~D
S
12 PANEL_BKEN 1 2 1
3
@ 100K_0402_5%~D
1
R1760
G
2
100K_0402_5%~D
X01 support M07 inverter 37,39,41,42,46,47,48 RUN_ON

2
FDS4435: P CHANNAL
M'07 inverter support - Populate R520,R1767 Depop U7.

D'05 inverter support - Populate U7, Depop R520,R1767
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Internal LVDS
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
D29 D30 D31

DA204U_SOT323~D DA204U_SOT323~D DA204U_SOT323~D
1
@ @ @
+3.3V_RUN_R
3
+5V_RUN
L78
BLM18BB600SN1D_0603~D D32
2
VGA_RED 1 2 SDM10U45-7_SOD523-2~D
12,36 VGA_RED
L79
BLM18BB600SN1D_0603~D CRT_VCC
VGA_GRN 1 2
12,36 VGA_GRN
L80
1
BLM18BB600SN1D_0603~D
0.01U_0402_16V7K~D
VGA_BLU 1 2
12,36 VGA_BLU
150_0402_1%~D
150_0402_1%~D
150_0402_1%~D
22P_0402_50V8J~D
22P_0402_50V8J~D
22P_0402_50V8J~D
C C
1 1 1 1 1 1 1
1
C1406
C1407
C1408
C1412
C1409 C1410 C1411
R1396
R1397
R1398
10P_0402_50V8J~D 10P_0402_50V8J~D 10P_0402_50V8J~D

2 2 2 2 @ 2 @ 2 @ 2
@ @ @
2
JCRT
CRT_VCC 6
11
RED 1
7
DAT_DDC2 12
T46 PAD~D GREEN 2
8 16
2
1 JVGA_HS 13 17
2.2K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
R1402 BLUE 3
R1399
R1401
2.2K_0402_5%~D C1413 CRT_VCC 9
R1400
0.1U_0402_16V4Z~D JVGA_VS
@
14
2 M_ID2#
Evaluate Package 4
1
10
CLK_DDC2 15
5
12,36 DAT_DDC2 SUYIN_070915FR015S201CU~D
12,36 CLK_DDC2
D2005 R1403
SDM10U45-7_SOD523-2~D 1K_0402_5%~D
+5V_RUN 2 1 1 2
5
U190 L81
R1404 BLM18AG121SN1D_0603~D
P
OE#
B B
12 VGA_HSYNC 1 2 2 A Y 4 1 2 1 2
G
39_0402_5%~D R102
HSYNC_R 36
SN74AHCT1G125GW_SC70-5~D 0_0402_5%~D
3
VSYNC_R 36
5
L82
R1405 BLM18AG121SN1D_0603~D
P
OE#
12 VGA_VSYNC 1 2 2 A Y 4 1 2 1 2
G
22P_0402_50V8J~D
22P_0402_50V8J~D
39_0402_5%~D R123 1 1
0_0402_5%~D
3
C1414
C1415
U191
SN74AHCT1G125GW_SC70-5~D
2 2
A
DA204U A
K1 A2
A1 K2 Compal Electronics, Inc.
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT
LA-2791
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS
14
U21A
1
P
IN1
OUT 3
2 IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
30,35 PCI_AD[0..31] U45B
PCI_AD0 E18 D7 PCI_REQ0#
AD0 REQ0# PCI_REQ0# 36
PCI_AD1 C18 E7 PCI_GNT0#
AD1 GNT0# PCI_GNT0# 35,36
PCI_AD2 PCI_REQ1#
D PCI_AD3
A16
F18
AD2 PCI REQ1# C16
D16 PCI_GNT1#
PCI_REQ1# 30 D
AD3 GNT1# PCI_GNT1# 30
PCI_AD4 E16 C17 PCI_REQ2#
+3.3V_RUN_R PCI_AD5 AD4 REQ2# +3.3V_SUS
A18 AD5 GNT2# D17
PCI_AD6 E17 E13 PCI_REQ3#
PCI_AD7 AD6 REQ3#
14
A17 AD7 GNT3# F13
PCI_AD8 A15 A13 PCI_REQ4# U21C
PCI_DEVSEL# PCI_AD9 AD8 REQ4# / GPIO22 PCI_GNT4# PCI_PCIRST#
1 2 C14 A14 10
P
R254 8.2K_0402_5%~D PCI_AD10 AD9 GNT4# / GPIO48 PCI_REQ5# IN1 PCI_RST#
E14 AD10 GPIO1 / REQ5# C8 OUT 8 PCI_RST# 30,31,35
1 2 PCI_STOP# PCI_AD11 D14 D8 PCI_GNT5# 9
AD11 GPIO17 / GNT5# IN2
G
R46 8.2K_0402_5%~D PCI_AD12 B12
PCI_TRDY# PCI_AD13 AD12 PCI_C_BE0# 74VHC08MTCX_NL_TSSOP14~D
1 2 C13 B15 PCI_C_BE0# 30,35
7
R47 8.2K_0402_5%~D PCI_AD14 AD13 C/BE0# PCI_C_BE1#
G15 AD14 C/BE1# C12 PCI_C_BE1# 30,35
1 2 PCI_FRAME# PCI_AD15 G13 D12 PCI_C_BE2# PCI_C_BE2# 30,35
R258 8.2K_0402_5%~D PCI_AD16 AD15 C/BE2# PCI_C_BE3#
E12 AD16 C/BE3# C15 PCI_C_BE3# 30,35
PCI_AD17 C11
PCI_PLOCK# PCI_AD18 AD17 PCI _IRDY#
1 2 D11 AD18 IRDY# A7 PCI_IRDY# 30,35,36
R327 8.2K_0402_5%~D PCI_AD19 A11 E10 PCI_PAR
AD19 PAR PCI_PAR 30,35
1 2 PCI _IRDY# PCI_AD20 A10 B18 PCI_PCIRST# +3.3V_SUS
R69 8.2K_0402_5%~D PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# 30,35
PCI_SERR# PCI_AD22 PCI_PERR#
14
1 2 F10 AD22 PERR# C9 PCI_PERR# 30,35
R257 8.2K_0402_5%~D PCI_AD23 E9 E11 PCI_PLOCK# U21D
AD23 PLOCK# PCI_PLOCK# 35
1 2 PCI_PERR# PCI_AD24 D9 B10 PCI_SERR# PCI_PLTRST# 13
P
AD24 SERR# PCI_SERR# 35 IN1
R255 8.2K_0402_5%~D PCI_AD25 B9 F15 PCI_STOP# 11 PLTRST#
AD25 STOP# PCI_STOP# 30,35 OUT PLTRST# 10,23,28,34,52
PCI_AD26 A8 F14 PCI_TRDY# 12
AD26 TRDY# PCI_TRDY# 30,35 IN2
G
PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# 30,35,36
PCI_AD28 C7 74VHC08MTCX_NL_TSSOP14~D
7
PCI_AD29 AD28 PCI_PLTRST#
B6 AD29 PLTRST# C26
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH 6
PCI_AD31 D6 B19 ICH_PME#
+3.3V_RUN_R AD31 PME# ICH_PME# 38
+3.3V_SUS
C PCI_PIRQA# PCI_PIRQA#
Interrupt I/F ICH_GPIO2_PIRQE# C
14
1 2 35 PCI_PIRQA# A3 PIRQA# GPIO2 / PIRQE# G8
R43 8.2K_0402_5%~D PCI_PIRQB# B4 F7 ICH_GPIO3_PIRQF# U21B
PCI_PIRQB# PCI_PIRQC# PIRQB# GPIO3 / PIRQF# ICH_GPIO4_PIRQG#
1 2 C5 F8 4
P
30 PCI_PIRQC# PIRQC# GPIO4 / PIRQG# IN1
R45 8.2K_0402_5%~D PCI_PIRQD# B5 G7 ICH_GPIO5_PIRQH# 6 PLTRST2#
PIRQD# GPIO5 / PIRQH# OUT PLTRST2# 38,39
1 2 PCI_PIRQC# 5 IN2
G
R44 8.2K_0402_5%~D
1 2 PCI_PIRQD# AE5
MISC AE9 74VHC08MTCX_NL_TSSOP14~D
7
R286 8.2K_0402_5%~D RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
AG4 RSVD[3] RSVD[8] AH8
AH4 RSVD[4] RSVD[9] F21
1 2 ICH_GPIO2_PIRQE# AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# 10
R350 8.2K_0402_5%~D
1 2 ICH_GPIO3_PIRQF#
R324 8.2K_0402_5%~D ICH7M A0_BGA652~D
1 2 ICH_GPIO4_PIRQG#
R309 8.2K_0402_5%~D
1 2 ICH_GPIO5_PIRQH#
R315 8.2K_0402_5%~D
1 2 PCI_REQ0#
R317 8.2K_0402_5%~D Place closely pin U45.A9
1 2 PCI_REQ1#
R72 8.2K_0402_5%~D PCI_GNT4# PCI_GNT5#
1 2 PCI_REQ2# CLK_PCI_ICH
R340 8.2K_0402_5%~D
2
1 2 PCI_REQ3#
R77 8.2K_0402_5%~D R347 R328 @ R332
1 2 PCI_REQ4# @ 1K_0402_5%~D 1K_0402_5%~D 10_0402_5%~D
R256 8.2K_0402_5%~D
1 2 PCI_REQ5#
1
R339 8.2K_0402_5%~D
B B
1
@ C349
8.2P_0402_50V8J~D
2
GNT5# GNT4#
R328 R347
LPC (11) unstuff unstuff
PCI (10) unstuff stuff
SPI (01) stuff unstuff

*
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH7(1/4)
LA-2791
5 4 3 2 1
5 4 3 2 1
C38
2.2P_0402_50V8C
2 1 ICH_RTCX1
32.768KHZ_6PF_1TJS060BJ4A376P~D
10M_0402_5%~D
4
1
R36
Package X1
9.6X4.06 mm
2
U45A
LPC_LAD[0..3] 28,38,39
2
D C40 R97 D
RTC
2.2P_0402_50V8C 0_0402_5%~D AB1 AA6 LPC_LAD0
ICH_RTCX2 RTCX1 LAD0 LPC_LAD1
2 1 1 2 AB2 RTCX2 LAD1 AB5
AC4 LPC_LAD2
ICH_RTCRST# LAD2 LPC_LAD3
+RTC_CELL 1 2 AA3 RTCRST# LAD3 Y6
R297 20K_0402_5%~D
LPC
1 2 ICH_INTVRMEN W4 AC3 LPC_LDRQ0#
R301 332K_0402_1%~D INTVRMEN LDRQ0# LPC_LDRQ1# LPC_LDRQ0# 38
Y5 INTRUDER# LDRQ1# / GPIO23 AA5 LPC_LDRQ1# 38
1 2 SM_INTRUDER#
R276 1M_0402_5%~D AB3 LPC_LFRAME#
LFRAME# LPC_LFRAME# 28,38,39
W1 EE_CS
CMOS Y1
@SHORT PADS~D EE_SHCLK SIO_A20GATE
Y2 EE_DOUT A20GATE AE22 SIO_A20GATE 39
LAN
W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# 7
1 2 R438 2 1 @ 0_0402_5%~D H_CPUSLP#
CPU
1 2 H_CPUSLP# 7,10
V3 AG27 H_CPUSLP_R#
LAN_CLK CPUSLP# R121 2 1 0_0402_5%~D H_DPRSTP#
H_DPRSTP# daisy
H_DPRSTP# 7,49
U3 AF24 DPRSLP#
LAN_RSTSYNC TP1 / DPRSTP#
AH25 H_DPSLP#
ICH7-M --> Yonah --> IMVP6
TP2 / DPSLP# H_DPSLP# 7
U5 LAN_RXD0
C348 V4 AG26 H_FERR#
LAN_RXD1 FERR# H_FERR# 7
1U_0603_10V4Z~D T5 LAN_RXD2 H_PW RGOOD
1 2 GPIO49 / CPUPWRGD AG24 H_PWRGOOD 7
U7 LAN_TXD0
V6 AG22 H_IGNNE#
LAN_TXD1 IGNNE# H_IGNNE# 7
V7 LAN_TXD2 INIT3_3V# AG21
@ C499 27P_0402_50V8J~D AF22 H_INIT# +1.05V_VCCP
INIT# H_INIT# 7
AF25 H_INTR R118
INTR H_INTR 7
2 1 56_0402_5%~D
AC-97/AZALIA
1 2 ICH_AC_BITCLK_R U1 H_FERR# 2 1
33 MDC_AC_BITCLK ACZ_BCLK
33_0402_5%~D
1 2 R553 ICH_AC_SYNC_RR6 AG23 SIO_RCIN#
33 ICH_SYNC_MDC ACZ_SYNC RCIN# SIO_RCIN# 39
33_0402_5%~D R81
C ICH_AC_RST_R# R5 H_SMI# +3.3V_RUN_R C
33 ICH_RST_MDC# 1 2 ACZ_RST# SMI# AF23 H_SMI# 7
33_0402_5%~D R83 AH24 H_NMI
NMI H_NMI 7
ICH_AC_SDIN0 T2 R277
26 ICH_AC_SDIN0 ACZ_SDIN0
ICH_AC_SDIN1 T3 AH22 H_STPCLK# 10K_0402_5%~D
33 ICH_AC_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# 7
T1 SIO_RCIN# 2 1
R371 ACZ_SDIN2 THRMTRIP_ICH#
THERMTRIP# AF26 1 2 +1.05V_VCCP
1 2 ICH_AC_SDOUT_R T4 R115 R1631
33 ICH_SDOUT_MDC ACZ_SDOUT
IDE_DA[0..2] 25 1 56_0402_5%~D 10K_0402_5%~D
33_0402_5%~D AH17 IDE_DA0 SIO_A20GATE 2 1
SATA_ACT# DA0 IDE_DA1 @ C69
43 SATA_ACT# AF18 SATALED# DA1 AE17
AF17 IDE_DA2 0.1U_0402_16V4Z~D
DA2 2
PSATA_IRX_DTX_N0_C IDE_DCS1#
Place near ICH7 side. 25 PSATA_IRX_DTX_N0_C
PSATA_IRX_DTX_P0_C
AF3
AE3
SATA0RXN DCS1# AE16
AD16 IDE_DCS3#
IDE_DCS1# 25
25 PSATA_IRX_DTX_P0_C SATA0RXP DCS3# IDE_DCS3# 25
2 1 PSATA_ITX_DRX_N0_C AG2
25 PSATA_ITX_DRX_N0 SATA0TXN
SATA
C270 3900P_0402_50V7K~D PSATA_ITX_DRX_P0_C AH2 IDE_DD[0..15] IDE_DD[0..15] 25
SATA0TXP IDE_DD0
25 PSATA_ITX_DRX_P0 2 1 DD0 AB15
C271 AF7 AE14 IDE_DD1
3900P_0402_50V7K~D SATA2RXN DD1 IDE_DD2
AE7 SATA2RXP DD2 AG13
AG6 AF13 IDE_DD3
SATA2TXN DD3 IDE_DD4
AH6 SATA2TXP DD4 AD14
AC13 IDE_DD5
CLK_PCIE_SATA# DD5 IDE_DD6
6 CLK_PCIE_SATA# AF1 SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 IDE_DD7
6 CLK_PCIE_SATA SATA_CLKP DD7
AE12 IDE_DD8
R380 24.9_0402_1%~D DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12
1 2 AG10 AB13 IDE_DD10
SATARBIASP DD10 IDE_DD11
DD11 AC14
Within 500 mils AF14 IDE_DD12
DD12 IDE_DD13
DD13 AH13
+3.3V_RUN_R AH14 IDE_DD14
IDE_ DIORDY AG16
IDE DD14
AC15 IDE_DD15
B 25 IDE_DIORDY IORDY DD15 B
R414 IDE_IRQ AH16
25 IDE_IRQ IDEIRQ
2 1 IDE_IRQ IDE_DDACK# AF16
25 IDE_DDACK# DDACK#
IDE_DIOW# AH15 AE15 IDE_DDREQ
25 IDE_DIOW# DIOW# DDREQ IDE_DDREQ 25
8.2K_0402_5%~D IDE_DIOR# AF15
25 IDE_DIOR# DIOR#
ICH7M A0_BGA652~D
Close to U45
R378
33_0402_5%~D
26 ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R
R82
33_0402_5%~D
26 ICH_SYNC_AUDIO 1 2 ICH_AC_SYNC_R
R84
33_0402_5%~D
26 ICH_RST_AUDIO# 1 2 ICH_AC_RST_R#
R189
33_0402_5%~D
26 ICH_AC_BITCLK 1 2 ICH_AC_BITCLK_R
A A
1
C503
27P_0402_50V8J~D
2
@
LA-2791
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS
+3.3V_SUS
+3.3V_RUN_R +3.3V_RUN_R
2.2K_0402_5%~D
2.2K_0402_5%~D
1
2
R351
R352
10K_0402_5%~D
10K_0402_5%~D
1 2 SIO_THRM# R425
@ R428 8.2K_0402_5%~D 8.2K_0402_5%~D Place closely pin U45.AC1
3.2
2
2
2
1 2 IRQ_SERIRQ U45C
1
R432 10K_0402_5%~D CLK_ICH_14M
R341
R363
ICH_SMBCLK C22 AF19
D 6,28,34 ICH_SMBCLK SMBCLK GPIO21 / SATA0GP D
1 2 CLKRUN# ICH_SMBDATA B22 AH18
6,28,34 ICH_SMBDATA SMBDATA GPIO19 / SATA1GP
1
SMB
SATA
GPIO
R111 8.2K_0402_5%~D LINKALERT# A26 AH19
1
ICH_SMLINK0 ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP R379
B25 SMLINK0 GPIO37 / SATA3GP AE19
1 2 BT_RADIO_DIS# ICH_SMLINK1 ICH_SMLINK1 A25 10_0402_5%~D
R1755 10K_0402_5%~D SMLINK1
@
2
1 2 WWAN_RADIO_DIS# AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M 6
Clocks
R1756 10K_0402_5%~D +3.3V_SUS 1 R303 2 I CH_RI# A28 B2 CLK_ICH_48M 1
RI# CLK48 CLK_ICH_48M 6
8.2K_0402_5%~D
1 2 LAMP_STAT# SPKR A19 T36 C380
26 SPKR SPKR
R75 10K_0402_5%~D A27 C20 ICH_SUSCLK PAD~D @
ITP_DBRESET# SUS_STAT# SUSCLK 2 4.7P_0402_50V8C~D
7,39 ITP_DBRESET# A22 SYS_RST#
SYS
B24 SIO_SLP_S3#
PM_BMBUSY# SLP_S3# SIO_SLP_S3# 39
10 PM_BMBUSY# AB18 GPIO0 / BM_BUSY# SLP_S4# D23
F22 SIO_SLP_S5#
SMBALERT# SLP_S5# SIO_SLP_S5# 39 R280
B23 GPIO11 / SMBALERT#
+3.3V_SUS AA4 ICH_PWRGD 10K_0402_5%~D
PWROK ICH_PWRGD 10,42
POWER MGT
H_STP_PCI# AC20 1 2
6 H_STP_PCI# GPIO18 / STPPCI#
GPIO
1 2 SIO_EXT_SCI# H_STP_CPU# AF21 AC22 DPRSLPVR
R1633 10K_0402_5%~D 6 H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR 49
1 2 PM_EXTTS#1 10
LCD_TST A21 C21 ICH_BATLOW# R1799 0_0402_5%~D
SIO_EXT_SMI# 19 LCD_TST GPIO26 TP0 / BATLOW#
1 2
R1632 10K_0402_5%~D B21 C23 SIO_PWRBTN#
GPIO27 PWRBTN# SIO_PWRBTN# 39
R373 IDE_RST_MOD E23
10K_0402_5%~D 25 IDE_RST_MOD GPIO28 PLTRST#
LAN_RST# C19 PLTRST# 10,21,28,34,52
1 2 LINKALERT# CLKRUN# AG18 +3.3V_SUS
30,38,39 CLKRUN# GPIO32 / CLKRUN#
Y4 SUSPWROK
RSMRST# SUSPWROK 18,42
R372 BT_RADIO_DIS# AC19 1 2
40 BT_RADIO_DIS# GPIO33 / AZ_DOCK_EN#
2
10K_0402_5%~D U2 R296 10K_0402_5%~D
SMBALERT# GPIO34 / AZ_DOCK_RST# R784
1 2
ICH_PCIE_WAKE# F20 E20 SIO_EXT_SCI# SIO_EXT_SCI# 39 100K_0402_5%~D
R269 38 ICH_PCIE_WAKE# IRQ_SERIRQ WAKE# GPIO9
28,30,38,39 IRQ_SERIRQ AH21 SERIRQ GPIO10 A20
C 8.2K_0402_5%~D SIO_THRM# USB_IDE# C
39 SIO_THRM# AF20 F19
1
ICH_BATLOW# THRM# GPIO12 SATA_DET# USB_IDE# 25
1 2 GPIO13 E19 SATA_DET# 25
IMVP_PWRGD AD22 R4
42,49 IMVP_PWRGD VRMPWRGD GPIO14
R318 2 1 @ E22
680_0402_5%~D C82 0.1U_0402_16V4Z~D GPIO15 GPIO24
GPIO24 R3
1 2 ICH_PCIE_WAKE# AC21 D20 T39 PAD~D
39 SIO_EXT_WAKE#
LAMP_STAT# AC18
GPIO6 GPIO GPIO25
AD21
19 LAMP_STAT# GPIO7 SATACLKREQ#/GPIO35 SATA_CLKREQ# 6
(PCI Express Wake Event) SIO_EXT_SMI# E21 AD20
39 SIO_EXT_SMI# GPIO8 GPIO38
AE20 WWAN_RADIO_DIS#
GPIO39 WWAN_RADIO_DIS# 34
1 2 DPRSLPVR ICH7M A0_BGA652~D
R554
100K_0402_5%~D
close to ICH7-M USB_OC2# 25

U45D
PCIE_IRX_WANTX_N1 F26 V26 DMI_MTX_IRX_N0
34 PCIE_IRX_WANTX_N1 PERn1 DMI0RXN DMI_MTX_IRX_N0 10 USB_OC3# 32
PCIE_IRX_WANTX_P1 F25 V25 DMI_MTX_IRX_P0
34 PCIE_IRX_WANTX_P1 PERp1 DMI0RXP DMI_MTX_IRX_P0 10
DIRECT MEDIA INTERFACE

MiniWLAN (Mini Card 2)---> C1 1 2 0.1U_0402_16V4Z~D PCIE_ITX_WANRX_N1 E28 U28 DMI_MRX_ITX_N0
34 PCIE_ITX_WANRX_N1_C PETn1 DMI0TXN DMI_MRX_ITX_N0 10
PCIE_ITX_WANRX_P1 E27 U27 DMI_MRX_ITX_P0
PETp1 DMI0TXP DMI_MRX_ITX_P0 10
C2 1 2 0.1U_0402_16V4Z~D
34 PCIE_ITX_WANRX_P1_C PCIE_IRX_WLANTX_N2 DMI_MTX_IRX_N1
34 PCIE_IRX_WLANTX_N2 H26 PERn2 DMI1RXN Y26 DMI_MTX_IRX_N1 10
PCIE_IRX_WLANTX_P2 H25 Y25 DMI_MTX_IRX_P1 USB_OC3# 1 2
34 PCIE_IRX_WLANTX_P2 PERp2 DMI1RXP DMI_MTX_IRX_P1 10 +3.3V_SUS
MiniWWAN (Mini Card 1) ---> C602 1 2 0.1U_0402_16V4Z~D PCIE_ITX_WLANRX_N2 G28 W28 DMI_MRX_ITX_N1 R1622 10K_0402_5%~D
34 PCIE_ITX_WLANRX_N2_C PETn2 DMI1TXN DMI_MRX_ITX_N1 10
PCIE_ITX_WLANRX_P2 G27 W27 DMI_MRX_ITX_P1 USB_OC0# 1 2
C603 1 2 0.1U_0402_16V4Z~D R1623 10K_0402_5%~D
34 PCIE_ITX_WLANRX_P2_C
PCI-EXPRESS
PCIE_IRX_LOMTX_N3 K26 AB26 DMI_MTX_IRX_N2 USB_OC1# 1 2
28 PCIE_IRX_LOMTX_N3 PERn3 DMI2RXN DMI_MTX_IRX_N2 10
PCIE_IRX_LOMTX_P3 K25 AB25 DMI_MTX_IRX_P2 R1624 10K_0402_5%~D
28 PCIE_IRX_LOMTX_P3 PERp3 DMI2RXP DMI_MTX_IRX_P2 10
GIGA LAN ---> C281 1 2 0.1U_0402_16V4Z~D PCIE_ITX_LOMRX_N3 J28 AA28 DMI_MRX_ITX_N2 USB_OC2# 1 2
28 PCIE_ITX_LOMRX_N3_C PETn3 DMI2TXN DMI_MRX_ITX_N2 10
PCIE_ITX_LOMRX_P3 J27 AA27 DMI_MRX_ITX_P2 R1625 10K_0402_5%~D
C282 1 2 0.1U_0402_16V4Z~D USB_OC7# 1 2
28 PCIE_ITX_LOMRX_P3_C DMI_MTX_IRX_N3 R1626 10K_0402_5%~D
M26 PERn4 DMI3RXN AD25 DMI_MTX_IRX_N3 10
B DMI_MTX_IRX_P3 USB_OC5# B
M25 PERp4 DMI3RXP AD24 DMI_MTX_IRX_P3 10 1 2
L28 AC28 DMI_MRX_ITX_N3 R1627 10K_0402_5%~D
PETn4 DMI3TXN DMI_MRX_ITX_N3 10
L27 AC27 DMI_MRX_ITX_P3 USB_OC6# 1 2
R1628 10K_0402_5%~D
P26 AE28 CLK_PCIE_ICH# USB_OC4# 1 2
+3.3V_SUS +3.3V_SUS +3.3V_SUS PERn5 DMI_CLKN CLK_PCIE_ICH# 6
P25 AE27 CLK_PCIE_ICH R1629 10K_0402_5%~D
PERp5 DMI_CLKP CLK_PCIE_ICH 6
N28 PETn5 Within 500 mils
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
N27 C25 R427 24.9_0402_1%~D

PETp5 DMI_ZCOMP USB_OC4# 32
2
D25 DMI_IRCOMP 1 2 +1.5V_RUN

DMI_IRCOMP USB_OC6# 32
R384
R388
R389
T25 PERn6 USB_OC5# 32

T24 F1 USBP0-
PERp6 USBP0N USBP0- 34
R28 F2 USBP0+ <---Mini2 WLAN
PETn6 USBP0P USBP0+ 34
R1786 R27 G4 USBP1-
USBP1- 38
1
47_0402_5%~D PETp6 USBP1N USBP1+

USBP1P G3 USBP1+ 38 <---SIO USB Hub
ICH_EC_SPI_CLK 1 2 R2 H1 USBP2- Place closely pin U45.B2
39 ICH_EC_SPI_CLK SPI_CLK USBP2N USBP2- 25
SPI_CS# P6 H2 USBP2+ <---D Moudle
39 SPI_CS# SPI_CS# USBP2P USBP2+ 25
SPI
R1787 P1 J4 USBP3-
SPI_ARB USBP3N USBP3- 32
47_0402_5%~D J3 USBP3+ <---SIDE TOP CLK_ICH_48M
USBP3P USBP3+ 32
ICHO_ECI_SPI_DATA 1 2 P5 K1 USBP4-
39 ICHO_ECI_SPI_DATA SPI_MOSI USBP4N USBP4- 32
ICHI_ECO_SPI_DATA P2 K2 USBP4+ <---SIDE BOTTOM
39 ICHI_ECO_SPI_DATA SPI_MISO USBP4P USBP4+ 32
1
L4 USBP5-
USBP5N USBP5- 32
L5 USBP5+ <---REAR R126
USBP5P USBP5+ 32
USB_OC0# D3 M1 USBP6- 10_0402_5%~D
OC0# USBP6N USBP6- 32
USB_OC1# C4 M2 USBP6+ <---REAR
USB_OC2# D5
OC1# USB USBP6P
N4 USBP7-
USBP6+ 32 @
USBP7- 36
2
USB_OC3# OC2# USBP7N USBP7+
D4 OC3# USBP7P N3 USBP7+ 36 <---Docking
USB_OC4# E5 1
USB_OC5# OC4# R113 22.6_0402_1%~D
C3 OC5# / GPIO29
USB_OC6# A2 D2 USBRBIAS 1 2 C124
USB_OC7# OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1 4.7P_0402_50V8C~D
2
Within 500 mils @
A ICH7M A0_BGA652~D A
LA-2791
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
U45F
U45E
ICH_V5REF_RUN G10 L11 A4 P28
V5REF[1] Vcc1_05[1] VSS[0] VSS[98]
0.1U_0402_16V4Z~D
330U_D2E_2.5VM_R9~D
Vcc1_05[2] L12 A23 VSS[1] VSS[99] R1
1U_0603_10V4Z~D
AD17 V5REF[2] Vcc1_05[3] L14 B1 VSS[2] VSS[100] R11
Vcc1_05[4] L16 1 1 1 B8 VSS[3] VSS[101] R12
+1.5VRUN_L
C387
ICH_V5REF_SUS F6 L17 B11 R13
V5REF_Sus Vcc1_05[5] VSS[4] VSS[102]
C392
C450
L41 L18 + B14 R14
D +1.5VRUN_L Vcc1_05[6] VSS[5] VSS[103] D
+1.5V_RUN 1 2 AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B17 VSS[6] VSS[104] R15
2 2
220U_V_4VM_R45~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
BLM21PG600SN1D_0805~D 1 AA23 M18 B20 R16
+5V_RUN +3.3V_RUN_R Vcc1_5_B[2] Vcc1_05[8] 2 VSS[7] VSS[105]
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B26 VSS[8] VSS[106] R17
C151
C454
C453
C459
+ AB23 P18 B28 R18
Vcc1_5_B[4] Vcc1_05[10] VSS[9] VSS[107]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C2 VSS[10] VSS[108] T6
1
AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C6 VSS[11] VSS[109] T12

R535 2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 CRB is 270uF C27 VSS[12] VSS[110] T13
100_0402_5%~D D16 AC26 U18 D10 T14
RB751S40T1_SOD523-2~D Vcc1_5_B[8] Vcc1_05[14] VSS[13] VSS[111]
AD26 Vcc1_5_B[9] Vcc1_05[15] V11 D13 VSS[14] VSS[112] T15
AD27 V12 D18 T16
2
Vcc1_5_B[10] Vcc1_05[16] VSS[15] VSS[113]

AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D21 VSS[16] VSS[114] T17
ICH_V5REF_RUN D26 V16 D24 U4
Vcc1_5_B[12] Vcc1_05[18] VSS[17] VSS[115]
1 D27 Vcc1_5_B[13] Vcc1_05[19] V17 E1 VSS[18] VSS[116] U12
D28 Vcc1_5_B[14] Vcc1_05[20] V18 E2 VSS[19] VSS[117] U13
C370 E24 E4 U14
Vcc1_5_B[15] VSS[21] VSS[118]
0.1U_0402_16V4Z~D E25 Vcc1_5_B[16] Vcc3_3 / VccHDA U6 +3.3V_RUN_R E8 VSS[22] VSS[119] U15
2
E26 Vcc1_5_B[17] 1 E15 VSS[23] VSS[120] U16
F23 R7 +1.05V_VCCP F3 U17
Vcc1_5_B[18] VccSus3_3/VccSusHDA +3.3V_SUS VSS[24] VSS[121]
F24 C442 C339 F4 U24
Vcc1_5_B[19] 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D VSS[25] VSS[122]
G22 Vcc1_5_B[20] V_CPU_IO[1] AE23 F5 VSS[26] VSS[123] U25
2
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F12 VSS[27] VSS[124] U26
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F27 VSS[28] VSS[125] V2
+5V_SUS +3.3V_SUS
H23 Vcc1_5_B[23] F28 VSS[29] VSS[126] V13
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3.3V_RUN_R 1 2 G1 VSS[30] VSS[127] V15
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G2 VSS[31] VSS[128] V24
1
K22 AB20 1 C445 G5 V27

R537 Vcc1_5_B[26] Vcc3_3[5] 0.1U_0402_16V4Z~D VSS[32] VSS[129]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G6 VSS[33] VSS[130] V28
10_0402_5%~D D17 L22 AD13 C361 1 2 G9 W6
RB751S40T1_SOD523-2~D Vcc1_5_B[28] Vcc3_3[7] VSS[34] VSS[131]
L23 Vcc1_5_B[29] Vcc3_3[8] AD18 0.1U_0402_16V4Z~D G14 VSS[35] VSS[132] W24
2 C424
M22 AG12 G18 W25
2
ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0603_6.3V4Z~D VSS[36] VSS[133]

M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G21 VSS[37] VSS[134] W26
1 N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G24 VSS[38] VSS[135] Y3
C C
N23 Vcc1_5_B[33] G25 VSS[39] VSS[136] Y24
C436 P22 A5 +3.3V_RUN_R G26 Y27
Vcc1_5_B[34] Vcc3_3[12] VSS[40] VSS[137]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D P23 Vcc1_5_B[35] Vcc3_3[13] B13 H3 VSS[41] VSS[138] Y28
2
+3.3V_RUN_R R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H4 VSS[42] VSS[139] AA1
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H5 VSS[43] VSS[140] AA24
0.1U_0402_16V4Z~D
C412
C388
C338
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H24 VSS[44] VSS[141] AA25
1 R25 Vcc1_5_B[39] Vcc3_3[17] D15 H27 VSS[45] VSS[142] AA26
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 H28 VSS[46] VSS[143] AB4
C449
T22 Vcc1_5_B[41] Vcc3_3[19] G11 J1 VSS[47] VSS[144] AB6

2
T27 Vcc1_5_B[44] J24 VSS[50] VSS[147] AB16
T28 Vcc1_5_B[45] VccRTC W5 +RTC_CELL J25 VSS[51] VSS[148] AB19
U22 Vcc1_5_B[46] J26 VSS[52] VSS[149] AB21
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3.3V_SUS K24 VSS[53] VSS[150] AB24
V22 Vcc1_5_B[48] 1 1 1 1 K27 VSS[54] VSS[151] AB27
V23 Vcc1_5_B[49] VccSus3_3[2] A24 K28 VSS[55] VSS[152] AB28
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L13 VSS[56] VSS[153] AC2
W23 Vcc1_5_B[51] VccSus3_3[4] D19 L15 VSS[57] VSS[154] AC5
+1.5V_DMIPLL 2 C393 2 2 2
C347
C328
R37 L42 Y22 D22 C407 L24 AC9
0.5_0603_1%~D BLM18AG601SN1D_0603~D Vcc1_5_B[52] VccSus3_3[5] 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D VSS[58] VSS[155]
Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L25 VSS[59] VSS[156] AC11
+1.5V_RUN 1 2 1 2 L26 VSS[60] VSS[157] AD1
0.01U_0402_16V7K~D
B27 Vcc3_3[1] VccSus3_3[7] K3 +3.3V_SUS M3 VSS[61] VSS[158] AD3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
VccSus3_3[8] K4 M4 VSS[62] VSS[159] AD4
10U_0805_4VAM~D
1 1 +1.5V_DMIPLL AG28 K5 1 1 M5 AD7

VccDMIPLL VccSus3_3[9] VSS[63] VSS[160]
C460
C406
VccSus3_3[10] K6 M12 VSS[64] VSS[161] AD8
C458
C405
+1.5V_RUN AB7 Vcc1_5_A[1] VccSus3_3[11] L1 M13 VSS[65] VSS[162] AD11
AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M14 VSS[66] VSS[163] AD15
2 2 2 2
AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M15 VSS[67] VSS[164] AD19
1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M16 VSS[68] VSS[165] AD23
C353 AE6 L7 M17 AE2
0.1U_0402_16V4Z~D Vcc1_5_A[5] VccSus3_3[15] VSS[69] VSS[166]
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M24 VSS[70] VSS[167] AE4
B B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M27 VSS[71] VSS[168] AE8
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 M28 VSS[72] VSS[169] AE11
L107 +VCCSATAPLL
AH5 Vcc1_5_A[9] N1 VSS[73] VSS[170] AE13
10UH_LB2012T100MR_20%_0805~D AB17 +1.5V_RUN N2 AE18
+VCCSATAPLL Vcc1_5_A[19] VSS[74] VSS[171]
+1.5V_RUN 1 2 1 2 AD2 VccSATAPLL Vcc1_5_A[20] AC17 N5 VSS[75] VSS[172] AE21
N6 VSS[76] VSS[173] AE24
10U_0805_4VAM~D
0.1U_0402_16V4Z~D
R59 1 1 AH11 T7 +1.5V_RUN N11 AE25

+3.3V_RUN_R Vcc3_3[2] Vcc1_5_A[21] VSS[77] VSS[174]
0.1U_0402_16V4Z~D
0.5_0603_1%~D F17 N12 AF2

Vcc1_5_A[22] VSS[78] VSS[175]
C286
C337
1 +1.5V_RUN AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 +1.5V_RUN N13 VSS[79] VSS[176] AF4
AB9 Vcc1_5_A[11] N14 VSS[80] VSS[177] AF8
2 2
C374
1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 +1.5V_RUN N15 VSS[81] VSS[178] AF11

C455 AD10 AC8 N16 AF27
2 1U_0603_10V4Z~D Vcc1_5_A[13] Vcc1_5_A[25] VSS[82] VSS[179]
AE10 Vcc1_5_A[14] 1 2 N17 VSS[83] VSS[180] AF28
AF10 Vcc1_5_A[15] VccSus1_05[1] K7 N18 VSS[84] VSS[181] AG1
2 C474 0.1U_0402_16V4Z~D
AF9 Vcc1_5_A[16] N24 VSS[85] VSS[182] AG3
AG9 Vcc1_5_A[17] VccSus1_05[2] C28 N25 VSS[86] VSS[183] AG7
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 N26 VSS[87] VSS[184] AG11
P3 VSS[88] VSS[185] AG14
+3.3V_SUS E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5V_RUN P4 VSS[89] VSS[186] AG17
1 Vcc1_5_A[27] H6 P12 VSS[90] VSS[187] AG20
C422 +1.5V_RUN C1 H7 P13 AG25
VccUSBPLL Vcc1_5_A[28] VSS[91] VSS[188]
1 Vcc1_5_A[29] J6 1 P14 VSS[92] VSS[189] AH1
0.1U_0402_16V4Z~D C382 AA2 J7 P15 AH3
2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] C1444 VSS[93] VSS[190]
Y7 VccSus1_05/VccLAN1_05[2] P16 VSS[94] VSS[191] AH7
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D P17 AH12
2 2 VSS[95] VSS[192]
V5 VccSus3_3/VccLAN3_3[1] P24 VSS[96] VSS[193] AH23
+3.3V_SUS V1 VccSus3_3/VccLAN3_3[2] P27 VSS[97] VSS[194] AH27
W2 VccSus3_3/VccLAN3_3[3]
1 W7 ICH7M A0_BGA652~D
C461 VccSus3_3/VccLAN3_3[4]
ICH7M A0_BGA652~D
0.1U_0402_16V4Z~D
A 2 A
LA-2791
5 4 3 2 1
5 4 3 2 1
+5VMOD
1
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
JMOD
71
72
1 1 1 1
C1302
C1303
C1304
C1305
2
1 1
2 2 2 2 3
D 2 D
3 3
4 4 6
6
5 5 4
6
7 7
8 8
9 9
10 10
11
5
11
12 12
WF1F068N1A
8.3 13 SATA_DET#
13 SATA_DET# 23
14 14
15 USB_OC2#
15 USB_OC2# 23
16 16
17 17
18 18
19 USBP2+
22 IDE_DD[0..15] 19 USBP2+ 23
20 20
21 USBP2-
21 USBP2- 23
IDE_DD0 22
IDE_DD1 22
23 23
IDE_DD2 24
IDE_DD3 24 DASP#
25 25
IDE_DD4 IDE_DCS3# 26
IDE_DD5 26 IDE_DCS1#
27 27
IDE_DD6 IDE_DA2 28
IDE_DD7 28
29 29
IDE_DD8 IDE_DA0 30
IDE_DD9 30 PDIAG#
31 31
IDE_DD10 IDE_DA1 32
IDE_DD11 32 IDE_IRQ
33 33
IDE_DD12 34
C IDE_DD13 34 IDE_DDACK# C
35 35
IDE_DD14 CSEL2 36
IDE_DD15 36 IDE_ DIORDY
IDE_DIOR# 38
37 37 TOP VIEW
38
470_0402_5%~D
22 IDE_DA[0..2] 39 39
2
IDE_DIOW# 40
IDE_DA0 40 IDE_DDREQ
41 41
R1328
IDE_DA1 IDE_DD15 42
IDE_DA2 42 IDE_DD0
43 43
44
1
IDE_DCS1# 44 IDE_DD14
22 IDE_DCS1# 45 45
IDE_DCS3# IDE_DD1 46
22 IDE_DCS3# 46
47 IDE_DD13
IDE_DD2 47
48 48
IDE_DDACK# 49 +5VHDD +3.3V_RUN
22 IDE_DDACK# IDE_DD12 49
50 50
10U_0805_10V4Z~D
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
IDE_DIOR# 51 IDE_DD3
22 IDE_DIOR# 51
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
IDE_DIOW# IDE_DD11 52
22 IDE_DIOW# 52
@ C1317
IDE_ DIORDY 53 IDE_DD4 1 1 1 1 1 1 1 1 1 1
22 IDE_DIORDY 53
C1310
C1311
C1312
C1314
C1315
C1316
C1345
IDE_DDREQ 54
22 IDE_DDREQ 54
IDE_IRQ 55 IDE_DD10 C1313 @ C1318
22 IDE_IRQ IDE_DD5 55
56 56 IDE_DD9 2 2 2 2 2 @ 2 @ 2 2 2 2 @
57 57
IDE_DD6 58 1U_0603_10V4Z~D 1U_0603_10V4Z~D
58
59 59
R1329 IDE_DD8 60
33_0402_5%~D 60 IDE_DD7
61 61 Pleace near HD CONN Pleace near HD CONN
IDE_RST_MOD 1 2 MOD_RST 62
23 IDE_RST_MOD 62
63 63
USB_IDE# 64
23 USB_IDE# 64 INT_CD_R JSATA
65 65
R1330 CD_AUDIORET 66 1
B 100K_0402_5%~D 66 INT_CD_L PSATA_ITX_DRX_P0 GND B
67 67 22 PSATA_ITX_DRX_P0 2 RX+
1 2 BAY_MODPRES# 68 C1319 PSATA_ITX_DRX_N0 3
+3.3V_SUS 38 BAY_MODPRES# 68 22 PSATA_ITX_DRX_N0 RX-
3900P_0402_50V7K~D 4 GND
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 1 PSATA_IRX_DTX_N0 5
22 PSATA_IRX_DTX_N0_C TX-
G
1 1 1 PSATA_IRX_DTX_P0 6 TX+
C1320
C1321
TYCO_1770530-1~D 7
69
70
+3.3V_RUN GND
C1322
+3.3V_ALW 1 2 22 PSATA_IRX_DTX_P0_C 2 1
@ 8
R1331 2 @ 2 @ 2 C1323 3.3V
9 3.3V
100K_0402_5%~D 3900P_0402_50V7K~D 10 3.3V
11 GND
+5VHDD 12 GND
13 GND
14 5V
close SATA connector 15 5V
16 5V
17 GND
18 Reserved GND1 23
19 GND GND2 24
20 12V
21 12V
22 12V
TYCO_1775191-1_RV~D
+3.3V_RUN
1 2 IDE_ DIORDY
R512 4.7K_0402_5%~D
A
Main SATA +5V Default A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL DVD MODULE
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2791 0.6
5 4 3 2 1
5 4 3 2 1
5 4
+VDDA +5V_RUN
D +5V_SUS D
L47
U22 +VDDA=4.75V @
1 IN OUT 5 1 2
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
+VDDA
1 2 3
1U_0603_10V4Z~D
2 GND BLM18AG601SN1D_0603~D
1 1 1 1 1 1
C498
C492
C486
C500
C169
C505
AUDIO_AVDD_ON 3 4 TPS793475_BYPASS +Z2401
38 AUDIO_AVDD_ON EN BYPASS
1
single gate TTL
0.1U_0402_16V4Z~D
TPS793475DBVRG4_SOT23-5~D C539
2 2 2 2 2 2 0.1U_0402_16V4Z~D
From SIO 1
C523
2
5
U28 R496 C529
2 10K_0402_5%~D 0.1U_0402_16V4Z~D
1
P
23 SPKR A
4 Z2402 1 2 Z2404 1 2 PC_BEEP
Y PC_BEEP 27
Default POP the LDO U22 38 BEEP 2 B
1
When U22 is popped, no pop L47. SN74AHCT1G86DCKR_SC70-5~D
TRACE>15 mil
3
R162
2.2K_0402_5%~D
2
+3.3V_RUN +VDDA Note:U28,R496,R162,C529
place as close as U19
W=30 mil
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
1U_0603_10V4Z~D
1 1
1 1 1
C176
C506
C487
C1825
C1826
C C
2 2
2 2 2 STAC9200 Rev. R22 R109
26
6
U10 CA1 5.11K 10K
DVDD
AVDD
22 ICH_RST_AUDIO# 8 RESET# LINE_IN_L 15
B1 39.2K 20K
22 ICH_SYNC_AUDIO 7 SYNC
LINE_IN_R 16 INT_MIC 27
22 ICH_SDOUT_AUDIO 2 SDATA_OUT
22 ICH_AC_BITCLK 3 BIT_CLK
CD_L 10
1 2 ICH_AC_SDIN0_R 5
22 ICH_AC_SDIN0 SDATA_IN
R160 33_0402_5%~D
VREFOUT 19 VREF_OUT CD_R 12
Close to U10.3 AC97VREFI 18 VREF_IN

CAP2 20 13
ICH_AC_BITCLK @ R48
0_0402_5%~D
CAP2
STAC9200 MIC1 NB_MICIN_L 27
1
HP_NB_SENSE 1 2 21 14
27,38 HP_NB_SENSE GPIO0 MIC2 NB_MICIN_R 27
R361
22_0402_5%~D
@ SPDIF_SHDN 22
38 SPDIF_SHDN GPIO1
27 HP_OUT_L 27
2
HP_L
1
DOCK_HP_MUTE# 30
38 DOCK_HP_MUTE# GPIO2
C362 28
HP_R HP_OUT_R 27
22P_0402_50V8J~D
B 2 EAPD B
@ 27 EAPD 31 SPDIF _ IN/EAPD /GPIO3 C189 0.1U_0402_16V4Z~D
LOUT_L 23 1 2 1 2 AUD_LINE_OUT 27
R89 2.2K_0402_5%~D
C179
SPDIF_DOCK 32 24 1 2 1 2
36 SPDIF_DOCK SPDIF _OUT LOUT_R R96 2.2K_0402_5%~D
Close to U10.5 0.1U_0402_16V4Z~D
MONO_OUT 25 1 2
ICH_SDOUT_AUDIO C1780 1000P_0402_50V7K~D
PAD_GND
1 NC1 1 2
11 9 C1781 1000P_0402_50V7K~D
AVSS1
AVSS2
NC2 SENSE_A
1
DVSS +VDDA
R488
47_0402_5%~D R1768
@ STAC9200X5NAEB1XR_QFN32~D 5.1K_0402 _1%~D
33
17
29
SENSE_A 2 1
2
39.2K_0402_1%~D
20K_0402_1%~D
C495
1
22P_0402_50V8J~D
2 @
R22
R109
2
2
1
1
D D
Close to U10.18 Close to U10.20 HP_NB_SENSE 2 2 MIC_SWITCH 27
G G
Q44 S S Q54
3
AC97VREFI CAP2 2N7002W-7-F_SOT323~D 2N7002W-7-F_SOT323~D
1U_0603_10V4Z~D
A A
1U_0603_10V4Z~D
0.1U_0402_16V4Z~D
1 1 1
C491
C181
C510
2 2 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Azalia (HD) Codec
LA-2791
5 4 3 2 1
5 4 3 2 1
C1795
VREFOUT 1 2
+3VRUN_4411 +VDDA 1U_0603_10V4Z~D
4.7K_0402_5%~D
4.7K_0402_5%~D
L52
1
BLM18AG601SN1D_0603~D
R1771
R1772
1
1 2 +VDDA
+3.3V_RUN
1 R1775
100K_0402_5%~D
2
C114 U9B
8
+3.3V_RUN 2.2U_0603_6.3V6K~D LM358DR2G_SOIC8~D R1770 C1775 L17
2
2 4.99_0402_1%~D 2.2U_0603_6.3V6K~D BLM18AG121SN1D_0603~D
5
P
MIC_BIAS IN+
7 O 26 NB_MICIN_L 2 1 MIC_L1 1 2 MIC_L2 2 1 JMIC
IN- 6 1
G
D C1794 D
2
100K_0402_5%~D
R132 1 2 1 MIC_R1 1 2 MIC_R2 2 1 6
4
26 NB_MICIN_R
R1776
100K_0402_5%~D R2140 L108 3
C1796 4.99_0402_1%~D 2.2U_0603_6.3V6K~D BLM18AG121SN1D_0603~D
2.2U_0603_6.3V6K~D
19
10
4
2
U5 2
100P_0402_50V8J~D
100P_0402_50V8J~D
5
PVDD
SVDD
+3.3V_RUN
20K_0402_1%~D
20K_0402_1%~D
HP_NB_SENSE 14 11 HP_SPK_R1 1 1 7
SHDNR# OUTR
C153
C177
8
+VDDA
R1774
R1773
18 9 HP_SPK_L1
SHDNL# OUTL
100K_0402_5%~D
FOX_JA9033L-B1N6-7F~D
1
2 2
R1769
2
R1781 R1784
C148 1U_0603_10V4Z~D 4 1K_0402_5%~D 100K_0402_5%~D
AUD_LINE_IN_R NC-4 C1800 MIC_BIAS
26 HP_OUT_R 1 2 15 1 2
2
INR 2.2U_0603_6.3V6K~D
6
2
AUD_LINE_IN_L NC-6
26 HP_OUT_L 1 2 13 INL 2 1 26 MIC_SWITCH
NC-8 8
1
C147
1U_0603_10V4Z~D C1P 12 R1780
NC-12 1K_0402_5%~D +VDDA
1
47P_0402_50V8J~D
47P_0402_50V8J~D
1 C1P NC-16 16
1 1
2
PGND
SGND
C493
C501
3 20 C1798 R1777 U9A

PVss
SVss
C1N NC-20
8
2 C1N 0.1U_0402_16V4Z~D 10K_0402_5%~D LM358DR2G_SOIC8~D
INT_MIC+ 1 2 1 2 3
P
2 2 32 INT_MIC+ IN+
C146 MAX4411ETP+_TQFN20~D 1 1 2
5
17 O INT_MIC 26
2.2U_0603_6.3V6K~D INT_MIC- 1 2 1 2 2
32 INT_MIC- IN-
G
C1797
PVSS
C1799 R1778 0.1U_0402_16V4Z~D
4
0.1U_0402_16V4Z~D 10K_0402_5%~D
C C
1 1 2 L16 JAUDIO
1
C113 R1779 BLM18AG121SN1D_0603~D 1
2.2U_0603_6.3V6K~D R1782 100K_0402_5%~D HP_SPK_L1 2 1 HP_SPK_L2 2
1K_0402_5%~D 6
2 C1801 HP_SPK_R1 HP_SPK_R2
2 1 3
100P_0402_50V8J~D
100P_0402_50V8J~D
2.2U_0603_6.3V6K~D L15
2
2 1 BLM18AG121SN1D_0603~D 4
1
1 1 26,38 HP_NB_SENSE 5
C108
C109
R1783 7
1K_0402_5%~D 8
2 2 FOX_JA9033L-B1N6-7F~D
Speaker Connector
2
JSPK
INT_SPK_R1 1
INT_SPK_R2 1
2 2
15 mils trace MOLEX_53398-0271~D
L45
1 2 +5VAMPVCC
+5V_SUS
1000P_0402_50V7K~D
1000P_0402_50V7K~D
W=40mils BLM21PG600SN1D_0805~D +5VAMPVCC

1 1 Gain Setting
C566
C565
+5VAMPVCC
2 @ 2 @ 1 1 1 1
1
C534 C485 C502 C494
1
1U_0603_10V4Z~D 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D R165
2 2 2 2 1K_0402_5%~D R164
16
15
6
B U19 1K_0402_5%~D B
VDD
PVDD1
PVDD2
2
AUD_GAIN0
PC_BEEP 7 2 AUD_GAIN0 AUD_GAIN1

26 PC_BEEP RIN+ GAIN0
3 AUD_GAIN1
GAIN1
1
C199
2 1 RI N- 17 R171 R170
26 AUD_LINE_OUT RIN-
18 INT_SPK_R1 @ 1K_0402_5%~D 1K_0402_5%~D
ROUT+
47P_0402_50V8J~D
0.047U_0402_16V4Z~D
0.022U_0402_16V7K~D @
47P_0402_50V8J~D
2
1 1 1 C1791 14 INT_SPK_R2 NOTE: SPEAKER TRACE WIDTH
ROUT-
C1793
2 1 9 LIN+ SHOULD BE MINIMUM 10 MILS

C536
C293
0.047U_0402_16V4Z~D 4
2 2 2 C1792 LOUT+
2 1 5 LIN-
+3.3V_RUN 8
0.047U_0402_16V4Z~D LOUT-
GAIN0 GAIN1 AV(inv) INPUT
IMPEDANCE
2
R156
100K_0402_5%~D 12 0 0 6dB 90K ohm

NC
10 BYPASS
1
SPK_SHUTDOWN# BYPASS
19 SHUTDOWN 0 1 10dB 70K ohm
1
21 C537
PAD_GND
GND1
GND2
GND3
GND4
1 0 15.6dB 45K ohm

0.47U_0402_16V4Z~D
1
A D D 2 A
2 2 @ Q11 * 1 1 21.6dB 25K ohm
20
13
11
1
38 NB_MUTE G 26 EAPD G 2N7002W-7-F_SOT323~D

S Q43 S
3
2N7002W-7-F_SOT323~D TPA6017A2PWP_TSSOP20~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, AMP and PHONE JACK
LA-2791
5 4 3 2 1
5 4 3 2 1
Layout Notice : Place as close

MMJT9435 +3VLAN Layout Notice : 1.2V filter. Place as close
chip as possible. C chip as possible.
2
4.7U_0603_6.3V4Z~D
E +3VLAN +1.2VLAN
0.1U_0402_16V4Z~D
+3.3V_SRC
Q62 B C 1 1
SI3456BDV-T1-E3_TSOP6~D
C1740
C1741
D 1 4 3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
6
S
2 2
4.7U_0603_6.3V4Z~D
5 4 +3VLAN 2 2 2 2 2 2 2 2
4
2_1210_5%~D
2_1210_5%~D
2
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C1351
C1352
C1353
C1354
C1355
C1356
C1357
C1358
1 1 1 Q68
R120
R9
R7
D D
C1368
C1362
2 2 2 2 2
G
REGCTL_PNP25 1 1 1 1 1 1 1 1 1
2 3
3
C1363
C1364
C1365
C1366
C1367
R7, R9 are 1/2 W rating MBT35200MT1G_TSOP6~D
41 ENAB_3VLAN
2
2 2 0_0603_5%~D
1 1 1 1 1
1
1
2
5
6
C80 +2.5VLAN
3
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@
10U_0805_10V4Z~D
REGCTL_PNP12 Q63 2
1
MMJT9435T1G_SOT223~D 1 1
C1742
C1743
2
4
+1.2VLAN
2 2
1
0.1U_0402_16V4Z~D
C1375
10U_0805_10V4Z~D
470P_0402_50V7K~D
2 @ 1 1
C1361
C1369
+2.5VLAN +1.2VLAN U214B
2 2
Pop C1375 for 5752-A0, BCM5752
D5 B2
De-pop for 5752-A1 D6
VDDC_0 VSS_0
B10
VDDC_1 VSS_1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
U214A D7 E4
VDDC_2 VSS_2
D8 E5
CLK_PCI_LOM BCM5752 1 1 VDDC_3 VSS_3
C1370
C1371
6 CLK_PCI_LOM H5 VDDC_4 VSS_4 E6
J8 B11 LAN_TX3+ H6 E7
LCLK TRD3+ LAN_TX3+ 29 VDDC_5 VSS_5
B12 LAN_TX3- H8 E8
22,38,39 LPC_LAD[0..3] TRD3- LAN_TX3- 29 2 2 VDDC_6 VSS_6
LPC_LAD0 J7 C11 LAN_TX2+ J4 E9
LAD0 TRD2+ LAN_TX2+ 29 +3VLAN VDDC_7 VSS_7
LPC_LAD1 L10 C12 LAN_TX2- F4
LAD1 TRD2- LAN_TX2- 29 VSS_8
LPC_LAD2 LAN_TX1+
Media
Digial power
LPC/TPM
J5 LAD2 TRD1+ D11 LAN_TX1+ 29 VSS_9 F5

C LPC_LAD3 LAN_TX1- C
K9 LAD3 TRD1- D12 LAN_TX1- 29 A3 VDDIO_0 VSS_10 F6
E11 LAN_TX0+ C2 F7
TRD0+ LAN_TX0+ 29 VDDIO_1 VSS_11
LPC_LFRAME# J9 E12 LAN_TX0- D10 F8
22,38,39 LPC_LFRAME# LFRAME TRD0- LAN_TX0- 29 VDDIO_2 VSS_12
PLTRST# M10 F1 F9
10,21,23,34,52 PLTRST# LRESET VDDIO_3 VSS_13
IRQ_SERIRQ H7 +2.5VLAN G10 G5
23,30,38,39 IRQ_SERIRQ SERIRQ VDDIO_4 VSS_14
H4 L60 J2 GND G6
LOW_PWR LAN_LOW_PWR 38 VDDIO_5 VSS_15
R1585 2 1 10K_0402_5%~D TPM_GPIO0 G4 2 1 XTALVDD L1 G7
R1584 TPM_GPIO0 VDDIO_6 VSS_16
1 10K_0402_5%~D TPM_GPIO1 R1439 1 4.7K_0402_5%~D BLM18AG601SN1D_0603~D 1
Control
2 J3 TPM_GPIO1 ATTN_BTTN A2 2 +3VLAN L12 VDDIO_7 VSS_17 G8

R1583 1 10K_0402_5%~D TPM_GPIO2
Power
2 H3 TPM_GPIO2 VMAINPRSNT G11 2 1 +3.3V_RUN_R VSS_18 L2

2 1 J6 R11 1K_0402_5%~D C1378 +2.5VLAN L6
38 LAN_TPM_EN# TPM_EN VSS_19
R17 0_0402_5%~D B6 2 1 0.1U_0402_16V4Z~D A5 M6
VAUXPRSNT R10 1K_0402_5%~D 2 VDDP_0 VSS_20
2 1 G3 VDDP_1
@ R1586 4.7K_0402_5%~D L11 A1
L61 VDDP_2 NC_0
H9 GPIO0 REGSUP12 K12 +3VLAN NC_1 A6
GPIO
H11 J11 REGCTL_PNP12 2 1 BIASVDD A7

GPIO1 REGCTL12 BLM18AG601SN1D_0603~D 1 NC_2
C5 GPIO2 XTALVDD H12 XTALVDD NC_3 B7
Regulator
LOM_CABLE_DETECT C4 J12 +1.2VLAN C1

38 LOM_CABLE_DETECT GPIO3 REGSEN12 C1376 NC_4
Control
PCIE_SDS_VDD K4 PCIE_SDSVDD NC_5 C3

M11 REGCTL_PNP25 0.1U_0402_16V4Z~D D1
REGCTL25 2 NC_6
NC_7 D2
REGSEN25 M12 +2.5VLAN NC_8 D3
L62 BIASVDD A12 BIAS E1
BIASVDD NC_9
SMBUS
6,23,34 ICH_SMBCLK C8 SMB_CLK 2 1 AVDD NC_10 E2

C7 C1377 BLM18AG601SN1D_0603~D
1 F2
6,23,34 ICH_SMBDATA SMB_DATA NC_11
0.1U_0402_16V4Z~D Place closely pin J8 AVDDL F10 G1
PCIE_IRX_LOMTX_N3_C 1 C1382 AVDDL_0 NC_12
PCIE_TXDN M3 2 PCIE_IRX_LOMTX_N3 23 F11 AVDDL_1 Analog NC_13 G2
CLK_PCI_LOM 0.1U_0402_16V4Z~D G9
L3 PCIE_IRX_LOMTX_P3_C 1 2
2
A11 power NC_14
H1
PCIE_TXDP PCIE_IRX_LOMTX_P3 23 AVDD AVDD_0 NC_15
C1379 F12 H2
AVDD_1 NC_16
1
LOM_SCLK C9 L7 0.1U_0402_16V4Z~D H10
+3VLAN SCLK PCIE_RXDN PCIE_ITX_LOMRX_N3_C 23 NC_17
LOM_SI E10 R78 J10
SI NC_18
SPI
R1267 LOM_SO D9 M7 22_0402_5%~D +1.2VLAN K1

SO PCIE_RXDP PCIE_ITX_LOMRX_P3_C 23 NC_19
PCI-E
B 4.7K_0402_5%~D LOM_CS# L63 B

C10 K6 K2
@
CS PCIE_PLLVDD PCIE_PLLVDD NC_20
1 2 M2 A4 PCIE_WAKE# 2 1 AVDDL PLL K3
PCIE_WAKE# 34,38
2
NV_STRAP0 WAKE CLK_PCIE_LOM# BLM18AG601SN1D_0603~D NC_21
1 2 M1 NV_STRAP1 REFCLK- L5 CLK_PCIE_LOM# 6 1 1 GPHY_PLLVDD G12 GPHY_PLLVDD NC_22 K5
@ R1268 4.7K_0402_5%~D M5 CLK_PCIE_LOM 1 K7
REFCLK+ CLK_PCIE_LOM 6 C1387 C1388 NC_23
REFCLK_SEL B3 1 2 NC_24 K8
@ R18 4.7K_0402_5%~D C78 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D K10
PLTRST# 22P_0402_50V8J~D 2 2 NC_25
PERST B1 PLTRST# 10,21,23,34,52 NC_26 K11
2
L4
@
LINK_10# L64 NC_27
29 LINK_10# A9 LINKLED NC_28 L8
LED
LINK_100# B9 2 1 GPHY_PLLVDD M8
29 LINK_100# SPD100LED BLM18AG601SN1D_0603~D NC_29
A10 SPD1000LED TCK B5 1 1
LAN_ACT# B8 F3 BCM5752KFBG A2_FPBGA144~D
29 LAN_ACT# TRAFFICLED TDI @ R1360 +3VLAN C1385 C1386
TDO B4
TEST
E3 4.7K_0402_5%~D +3VLAN 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D

R1367 TMS 2 2
TRST D4 1 2
2 1 XTALO M9 J1
XTALO SERIAL_DI
Clock
4.7K_0402_5%~D
200_0402_1%~D M4 1 2 L65 1 2 1 2
SERIAL_DO 38 LAN_LOW_PWR
4.7K_0402_5%~D
C6 @ R13 4.7K_0402_5%~D 2 1 PCIE_PLLVDD @ R68 @ R70
GPHY_TVCOI
1
X4 1 2 1 BLM18AG601SN1D_0603~D
1 1 20K_0402_5%~D 39K_0402_5%~D
R1365
R1366
25MHZ_18PF_1BX25000CK1D~D XTALI L9 R14 4.7K_0402_5%~D
XTALI C1383 C1384
27P_0402_50V8J~D
1 2 1 2
27P_0402_50V8J~D
@ R16 0_0402_5%~D 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D

Bias
RDAC A8
@ 2 2 @ R58
2 2
2
2
C1393
C1394
LOM_CLKREQ# 2 1
6 LOM_CLKREQ#
+3VLAN U3 R1368
2
1.18K_0402_1%~D
BCM5752KFBG A2_FPBGA144~D 8 1 LOM_SO 2 1 PCIE_SDS_VDD 0_0402_5%~D

1 1 Q D
R1364
7 2 LOM_SCLK 0_0603_5%~D 1 1
VSS C
6 VCC RESET# 3
Layout Notice : No high 5 4 LOM_CS# @ C1390 C1391 @
W# S# 4.7U_0603_6.3V4Z~D 0.1U_0402_16V4Z~D
speed signal should be
1
M45PE20-VMN6TP_SO8~D 2 2
routed near RDAC or on
A adjacent layer to RDAC @ U188 A
LOM_SI 8 1
SO SI
0.1U_0402_16V4Z~D
7 GND SCK 2
6 VCC RESET# 3 +3VLAN
5 WP# CS# 4
2 1 2
C1392
NV_STRAP1 NV_STRAP0 SO SI CS# SCLK AT45BCM021B-SU_SO8~D @ R53

4.7K_0402_5%~D
1
Atmel AT45BCM021B 0 0 1 0 1 1 Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BCM5751M
ST M45PE20 0 1 1 0 0 1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
5 4 3 2 1
5 4 3 2 1
+3VLAN
LAN ANALOG
SWITCH
56
50
38
27
18
10
4
C1395 1 2 0.1U_0402_16V4Z~D R1370 1 2 49.9_0402_1%~D LAN_TX0- U189
R1371 1 2 49.9_0402_1%~D LAN_TX0+
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
C1398 1 2 0.1U_0402_16V4Z~D R1372 1 2 49.9_0402_1%~D LAN_TX1- 48 SW_LAN_TX0-
0B1 SW_LAN_TX0- 32
R1373 1 2 49.9_0402_1%~D LAN_TX1+ 47 SW_LAN_TX0+
1B1 SW_LAN_TX0+ 32
C1399 1 2 0.1U_0402_16V4Z~D R1374 1 2 49.9_0402_1%~D LAN_TX2- LAN_TX0- 1 2 LAN_TX0-R 2
28 LAN_TX0- A0
R1375 1 2 49.9_0402_1%~D LAN_TX2+ L68 36NH_0603CS-360EJTS_5%_0603~D 43 SW_LAN_TX1-
2B1 SW_LAN_TX1- 32
C1400 1 2 0.1U_0402_16V4Z~D R1376 1 2 49.9_0402_1%~D LAN_TX3- LAN_TX0+ 1 2 LAN_TX0+R 3 42 SW_LAN_TX1+
28 LAN_TX0+ A1 3B1 SW_LAN_TX1+ 32
R1377 1 2 49.9_0402_1%~D LAN_TX3+ L69 36NH_0603CS-360EJTS_5%_0603~D
D SW_LAN_TX2- D
4B1 37 SW_LAN_TX2- 32
LAN_TX1- 1 2 LAN_TX1-R 7 36 SW_LAN_TX2+
28 LAN_TX1- A2 5B1 SW_LAN_TX2+ 32
L70 36NH_0603CS-360EJTS_5%_0603~D
LAN_TX1+ 1 2 LAN_TX1+R 8 32 SW_LAN_TX3-
28 LAN_TX1+ A3 6B1 SW_LAN_TX3- 32
L71 36NH_0603CS-360EJTS_5%_0603~D 31 SW_LAN_TX3+
7B1 SW_LAN_TX3+ 32
Layout Notice : Place LAN_TX2- 1 2 LAN_TX2-R 11 22 LAN_LEDACT#
28 LAN_TX2- A4 0LED1
L72 36NH_0603CS-360EJTS_5%_0603~D 23 LINK_LED10#
termination as close as LAN_TX2+ 1 LAN_TX2+R 1LED1 LINK_LED100#
28 LAN_TX2+ 2 12 A5 2LED1 52
ASIC as possible L73 36NH_0603CS-360EJTS_5%_0603~D
46 DOCK_LAN_TX0-
0B2 DOCK_LAN_TX0- 36
The resistors need at LAN_TX3- 1 2 LAN_TX3-R 14 45 DOCK_LAN_TX0+
28 LAN_TX3- A6 1B2 DOCK_LAN_TX0+ 36
L74 36NH_0603CS-360EJTS_5%_0603~D
least 1/16W LAN_TX3+ 1 LAN_TX3+R DOCK_LAN_TX1-
28 LAN_TX3+ 2 15 A7 2B2 41 DOCK_LAN_TX1- 36
L75 36NH_0603CS-360EJTS_5%_0603~D 40 DOCK_LAN_TX1+
3B2 DOCK_LAN_TX1+ 36
DOCKED 17 35 DOCK_LAN_TX2-
36,38 DOCKED SEL 4B2 DOCK_LAN_TX2+ DOCK_LAN_TX2- 36
5B2 34 DOCK_LAN_TX2+ 36
19 30 DOCK_LAN_TX3-
28 LAN_ACT# LED0 6B2 DOCK_LAN_TX3- 36
20 29 DOCK_LAN_TX3+
28 LINK_10# LED1 7B2 DOCK_LAN_TX3+ 36
Layout Notice : Place bead as 28 LINK_100# 54 LED2
25 DOCK_LAN_ACTLED_YEL#
close PI3L500 as possible 0LED2 DOCK_LED_10#
DOCK_LAN_ACTLED_YEL# 36
5 NC 1LED2 26 DOCK_LED_10# 36
51 DOCK_LED_100#
2LED2 DOCK_LED_100# 36
57 PAD_GND
GND10
GND11
GND12
GND13
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
PI3L500E_TQFN56~D
1
6
9
13
16
21
24
28
33
39
44
49
53
55
C
1: TO DOCK TO C
FROM NIC DOCKED DOCK
0: TO RJ45
+3VLAN
@
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
1
1
R1379
R1380
R1381
2
2
LAN_ACT#
LINK_10#
LINK_100#
B B
R1382
LAN_LEDACT# 1 2 LAN_ACTLED_YEL_R#
LAN_ACTLED_YEL_R# 32
150_0402_5%~D
R1384
LINK_LED10# 1 2 LED_10_GRN_R#
LED_10_GRN_R# 32
150_0402_5%~D
R1385
LINK_LED100# 1 2 LED_100_ORG_R#
LED_100_ORG_R# 32
150_0402_5%~D
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN TRANSFOMER
5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: +5V_RUN
4.7U_0603_6.3V4Z~D 4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
THIS PAGE SHOWS THE OZ601B CONFIGURED WITH 1 1
EXTERNAL IDSEL AND WITHOUT 12V VPP SUPPORT.
C1416
C1417
IDSEL SELECT POWER-ON-STRAPPING 2 2
(SEE NOTE & TABLE FOR OPTIONS) +CBS_VCC
+3.3V_RUN
+3.3V_RUN +3.3V_RUN
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 1 1 1 U2
33K_0402_5%~D
33K_0402_5%~D
C1418
C1419
C1420
C1421
C1422
C1423
D D
19 +5V AVCC 29
20 +5V AVCC 30
1
2 2 2 2 2 2
21 +5V AVCC 31
R1406
R1407
3 +3.3V AVPP 28
4 +3.3V
5 13
2
+3.3V BVCC
+3.3V_RUN U193 1 14 CBS_CCD1#
DATA CD1#
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 15 CBS_CCD2#
CBS_SATA CLK CD2# CBS_CVS1
1 1 1 64 CORE_VCC VCC5#/VCCD0#/SDATA 124 6 LATCH VS1 16
77 125 CBS_SCLK 17 CBS_CVS2
CORE_VCC VCC3#/VCCD1#/SCLK VS2
C1424
C1425
C1448
97 123 CBS_SLATCH PCI_RST# 32
CORE_VCC VPP_PGM/VPPD0/SLATCH RESET#
115 CORE_VCC HOST_DN 24 USB_HUBP1- 38
2 2 2
18 HOST_CLK HOST_DP 27 USB_HUBP1+ 38
1 103 CBS_CAD31 22
PCI_VCC D10/CAD31 CBS_CAD30 SC_CLK CBS_CAD15
20 PCI_VCC D9/CAD30 102 11 HOST_RST CARD_DN 23
33 101 CBS_CAD29 12 26 CBS_CAD13
PCI_VCC D1/CAD29 CBS_CAD28 SC_RST CARD_DP
21,35 PCI_AD[0..31] D8/CAD28 100 9 HOST_I/O
PCI_AD31 4 99 CBS_CAD27 10
PCI_AD30 AD31 D0/CAD27 CBS_CAD26 SC_I/O
5 AD30 A0/CAD26 110 NC 8
PCI_AD29 6 109 CBS_CAD25 7 25
NOTE: IDSEL SELECTION! PCI_AD28
PCI_AD27
7
AD29
AD28
A1/CAD25
A2/CAD24 108 CBS_CAD24
CBS_CAD23
GND NC
8 106 OZ2522LN-A1_QFN32~D
THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. PCI_AD26 AD27 A3/CAD23 CBS_CAD22
9 AD26 A4/CAD22 105
IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI_AD25 10 104 CBS_CAD21
PCI AD LINES OR EXTERNAL IDSEL SIGNAL. PCI_AD24 AD25 A5/CAD21 CBS_CAD20
13 AD24 A6/CAD20 118
PCI_AD23 14 95 CBS_CAD19
22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE PCI_AD22 AD23 A25/CAD19 CBS_CAD18
15 AD22 A7/CAD18 94
REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO PCI_AD21 16 93 CBS_CAD17
SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. PCI_AD20 AD21 A24/CAD17 CBS_CAD16
17 AD20 A17/CAD16 75
THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS. PCI_AD19 18 73 CBS_CAD15
C PCI_AD18 AD19 IOW#/CAD15 CBS_CAD14 C
19 AD18 A9/CAD14 74
CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS PCI_AD17 21 71 CBS_CAD13
FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY PCI_AD16 AD17 IORD#/CAD13 CBS_CAD12
22 AD16 A11/CAD12 72
CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST PCI_AD15 28 70 CBS_CAD11
BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC. PCI_AD14 AD15 OE#/CAD11 CBS_CAD10
29 AD14 CE2#/CAD10 69
PCI_AD12 AD13 A10/CAD9 CBS_CAD8
31 AD12 D15/CAD8 85
VCC5# VPP_PGM IDSEL SELECT PCI_AD10 AD11 D7/CAD7 CBS_CAD6
35 AD10 D13/CAD6 82
(124) (123) PCI_AD9 36 83 CBS_CAD5
PCI_AD8 AD9 D6/CAD5 CBS_CAD4
37 AD8 D12/CAD4 80
DOWN DOWN AD18 PCI_AD6 AD7 D5/CAD3 CBS_CAD2
39 AD6 D11/CAD2 78
PCI_AD4 AD5 D4/CAD1 CBS_CAD0 JCBUS
41 AD4 D3/CAD0 76
DOWN UP AD20 PCI_AD3 42 1 41
PCI_AD2 AD3 R4 33_0402_5%~D CBS_CCLK CBS_CAD0 GND1 GND9 CBS_CCD1#
43 AD2 2 A_CAD0 A_CCD1# 42
R1307 PCI_AD1 44 107 CBS_CAD1 3 43 CBS_CAD2
UP DOWN AD25 100_0402_5%~D PCI_AD0 AD1 A16/CCLK CBS_CFRAME# CBS_CAD3 A_CAD1 A_CAD2 CBS_CAD4
46 AD0 A23/CFRAME# 114 4 A_CAD3 A_CAD4 44
PCI_AD17 1 2 CBS_IDSEL 127 117 C BS_CIRDY# CBS_CAD5 5 45 CBS_CAD6
PCI_C_BE3# VPP_VCC/VPPD1/IDSEL A15/CIRDY# CBS_CTRDY# CBS_CAD7 A_CAD5 A_CAD6 CBS_RSVD/D14
21,35 PCI_C_BE3# 11 C/BE3# A22/CTRDY# 116 6 A_CAD7 CB_A_D14 46
UP UP PIN 127 PCI_C_BE2# 12 113 CBS_CDEVSEL# CBS_CC/BE0# 7 47 CBS_CAD8
21,35 PCI_C_BE2# C/BE2# A21/CDEVSEL# A_PCI_C/BE0# A_CAD8
21,35 PCI_C_BE1# PCI_C_BE1# 49 61 CBS_CSTOP# 8 48
PCI_C_BE0# C/BE1# A20/CSTOP# CBS_CPAR CBS_CAD9 GND2 GND10 CBS_CAD10
21,35 PCI_C_BE0# 50 C/BE0# A13/CPAR 58 9 A_CAD9 A_CAD10 49
60 CBS_CPERR# CBS_CAD11 10 50 CBS_CVS1
CLK_PCI_PCM A14/CPERR# CBS_CSERR# CBS_CAD12 A_CAD11 A_CVS1 CBS_CAD13
6 CLK_PCI_PCM 26 PCI_CLK WAIT#/CSERR# 91 11 A_CAD12 A_CAD13 51
PCI_DEVSEL# 27 89 CBS_CREQ# 12 52
21,35 PCI_DEVSEL# DEVSEL# INPACK#/CREQ# GND3 GND11
PCI_FRAME# 23 62 CBS_CGNT# CBS_CAD14 13 53 CBS_CAD15
21,35,36 PCI_FRAME# FRAME# WE#/CGNT# A_CAD14 A_CAD15
PCI _IRDY# 24 88 CBS_CINT# CBS_CC/BE1# 14 54 CBS_CAD16
21,35,36 PCI_IRDY# IRDY# RDY/IREQ#/CINT# A_PCI_C/BE1# A_CAD16
PCI_TRDY# 25 59 CBS_CBLOCK# CBS_CPAR 15 55 CBS_RSVD/A18
21,35 PCI_TRDY# TRDY# A19/CBLOCK# A_CPAR CB_A_A18
PCI_STOP# 47 87 CBS_CCLKRUN# 16 56
21,35 PCI_STOP# STOP# WP/CCLKRUN# GND4 GND12
PCI_PAR 48 119 CBS_CRST# CBS_CPERR# 17 57 CBS_CBLOCK#
B 21,35 PCI_PAR PAR RESET/CRST# A_CPERR# A_CBLOCK# B
98 CBS_RSVD/D2 CBS_CGNT# 18 58 CBS_CSTOP#
PCI_PERR# D2/RFU CBS_RSVD/D14 CBS_CINT# A_CGNT# A_CSTOP# CBS_CDEVSEL#
21,35 PCI_PERR# 51 PERR#/SPKR_OUT D14/RFU 86 19 A_CINT# A_CDEVSEL# 59
63 CBS_RSVD/A18 +CBS_VCC 20 60 +CBS_VCC
PCI_REQ1# A18/RFU CBS_CVS1 +AVCC0 +AVCC1
21 PCI_REQ1# 2 REQ# VS1/CVS1 57 21 +AVPP0 +AVPP1 61
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
PCI_GNT1# 3 121 CBS_CVS2 CBS_CCLK 22 62 CBS_CTRDY#
21 PCI_GNT1# GNT# VS2/CVS2 A_CCLK A_CTRDY#
56 CBS_CCD1# 1 C BS_CIRDY# 23 63 CBS_CFRAME# 1
PCI_RST# CD1#/CCD1# CBS_CCD2# CBS_CC/BE2# A_CIRDY A_CFRAME# CBS_CAD17
21,31,35 PCI_RST# 126 RST# CD2#/CCD2# 122 24 A_PCI_C/BE2# A_CAD17 64
C1426
C1447
1 2 120 92 CBS_CAUDIO CBS_CAD18 25 65 CBS_CAD19
35,38 SYS_PME# @ R71 0_0402_5%~D PME#/RI_OUT# BVD2/LED/CAUDIO CBS_CSTSCHNG CBS_CAD20 A_CAD18 A_CAD19 CBS_CVS2
BVD1/STSCHG#/RI#/CSTSCHG 90 26 A_CAD20 A_CVS2 66
CLKRUN# 2 2
23,38,39 CLKRUN# 55 MF6 27 GND5 GND13 67
54 111 CBS_CC/BE3# CBS_CAD21 28 68 CBS_CRST#
IRQ_SERIRQ MF4 REG#CCBE3# CBS_CC/BE2# CBS_CAD22 A_CAD21 A_CRST# CBS_CSERR#
23,28,38,39 IRQ_SERIRQ 53 MF3 A12/CCBE2# 112 29 A_CAD22 A_CSERR# 69
PCI_PIRQC# 52 66 CBS_CC/BE1# CBS_CAD23 30 70 CBS_CREQ#
21 PCI_PIRQC# MF0 A8/CCBE1# CBS_CC/BE0# CBS_CAD24 A_CAD23 A_CREQ# CBS_CC/BE3#
CE1/CCBE0# 67 31 A_CAD24 A_PCI_C/BE3# 71
32 72
GND
GND
GND
GND
GND
22K TO 47K PULL-UPS MUST BE PLACED CBS_CAD25 GND6 GND14 CBS_CAUDIO

33 A_CAD25 A_CAUDIO 73
ON INTA#, PME#, SERIRQ# & CLKRUN#. CBS_CAD26 34 74 CBS_CSTSCHNG
OZ601TN_TQFP128~D CBS_CAD27 A_CAD26 A_CSTSCHG CBS_CAD28
35 75
32
45
65
96
128
A_CAD27 A_CAD28
36 GND7 GND15 76
CBS_CAD29 37 77 CBS_CAD30
CBS_RSVD/D2 A_CAD29 A_CAD30 CBS_CAD31
38 CB_A_D2 A_CAD31 78
CBS_CCLKRUN# 39 79 CBS_CCD2#
A_CCLKRUN# A_CCD2#
Place closely pin 26 40 GND8 GND16 80
CLK_PCI_PCM TYCO_1734648-1~D
1
R88
22_0402_5%~D
@
A A
1
C81
22P_0402_50V8J~D
2
@
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Bus OZ601
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R128 33_0402_5%~D
D D
1 2
R137 33_0402_5%~D
1 2
@ L5
4 3
USB SMARTCARD READER. 4 3 USB_BIO- 40
TYPE A (5V), B (3V), AB (5V/3V) 1 1 2 2 USB_BIO+ 40

& USB SMARTCARDS ARE SUPPORTED. DLW21SN900SQ2_0805~D
47P_0402_50V8J~D
47P_0402_50V8J~D
1
1
+5V_RUN
15K_0402_5%~D
15K_0402_5%~D
15K_0402_5%~D
15K_0402_5%~D
1 1
1
+3V_PWR
R1595
R1596
R1416
4.7U_0603_6.3V4Z~D
R1417
2 2
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2
+3.3V_RUN
1 1 1 1
2
C457
C1433
C1748
C1749
C84
C83
1.5K_0402_1%~D
1
2 2 2 2 +SC_PWR
R1597
U1
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
1U_0603_10V4Z~D
5 VCC5V_IN +3.3V_OUT 29
10K_0402_5%~D
47K_0402_5%~D
C C
28 1 1 1 1
2
VCC5V_IN
1
C1437
C1436
R1336
C1439
C1440
R1419
19 USB_BIO_L-
USB_HUBP3- DPD- USB_BIO_L+
38 USB_HUBP3- 17 UPD- DPD+ 18
USB_HUBP3+ 2 2 2 2
38 USB_HUBP3+ 16
2
UPD+ SCCD- JSC
21
2
PCI_RST# EGATED- SCCD+
21,30,35 PCI_RST# 14 RST# EGATED+ 20 12 GND
11 GND
30 27 +SC_PWR
NC SC_VCC
31 NC 10 10
24 SC_RST# R1420 2 1 220_0402_5%~D 9
CLK_SMC_48M SC_RST# SC_CLK R1421 9
6 CLK_SMC_48M 3 XI/48M_IN SC_CLK 23 2 1 33_0402_5%~D 8 8
4 22 SC_C4 R1423 2 1 220_0402_5%~D SCCD+ 7
XO SC_C4 7
SC_IO 25 6 6
MD0 32 15 5
MODE0/SC_LED# SC_DET# SC_IO R1424 5
1 MODE1 2 1 330_0402_5%~D 4 4
2 SCCD- 3
MODE2 SC_DET# 3
RF_OUT 8 2 2
11 GND RF_IN/RX 7 1 1
VR_CPR
VR_CPR
4.7K_0402_5%~D
0.1U_0402_16V4Z~D
13 GND RF_CLK 9
26 10 1 MOLEX_52207-1085~D
GND RF_AUX
1
C76
R1425
MODE1 CLOCK INPUT OZ77C6LN-A1_QFN32~D

6
12
2
C1443
10.1
2
2 1 VRCPR
LOW 48MHz SC_DET#
SC_DET# 38
1U_0603_10V4Z~D
B
HIGH 6MHz Crystal B
Place closely pin 3

CLK_SMC_48M
1
@
R133
10_0402_5%~D
2
@ 1
C135
4.7P_0402_50V8C~D
2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Smart Card OZ77C6
LA-2791
8 7 6 5 4 3 2 1
5 4 3 2 1
D D
+USB_SIDE_PWR
0.1U_0402_16V4Z~D
@ L8 DLW21SN900SQ2_0805~D
C1745
1 1 USBP5_D+
23 USBP5+ 2 2 1
JIO
4 3 USBP5_D- 1 2 LAN_ACTLED_YEL_R#
23 USBP5- 4 3 2 1 2 LAN_ACTLED_YEL_R# 29
R29 3 4 +3VLAN
0_0402_5%~D 3 4 SW_LAN_TX0+
5 5 6 6 SW_LAN_TX0+ 29
1 2 USBP3- 7 8 SW_LAN_TX0-
23 USBP3- 7 8 SW_LAN_TX0- 29
R28 USBP3+ 9 10 SW_LAN_TX1+
23 USBP3+ 9 10 SW_LAN_TX1+ 29
0_0402_5%~D 11 12 SW_LAN_TX1-
11 12 SW_LAN_TX1- 29
1 2 USBP4- 13 14 +2.5VLAN
23 USBP4- 13 14
USBP4+ 15 16 SW_LAN_TX2+
23 USBP4+ 15 16 SW_LAN_TX2+ 29
BREATH_GREEN_LED 17 18 SW_LAN_TX2-
43 BREATH_GREEN_LED 17 18 SW_LAN_TX2- 29
BATT_GREEN_LED 19 20 SW_LAN_TX3+
43 BATT_GREEN_LED 19 20 SW_LAN_TX3+ 29
BATT_AMBER_LED 21 22 SW_LAN_TX3-
43 BATT_AMBER_LED 21 22 SW_LAN_TX3- 29
R_BT_ACT 23 24
43 R_BT_ACT 23 24
@ L7 DLW21SN900SQ2_0805~D R_MPCI_ACT 25 26 LED_10_GRN_R#
43 R_MPCI_ACT 25 26 LED_10_GRN_R# 29
1 1 USBP6_D+ INT_MIC+ LED_100_ORG_R#
23 USBP6+ 2 2 27 INT_MIC+ INT_MIC-
27 27 28 28
R_SATA_ACT
LED_100_ORG_R# 29
27 INT_MIC- 29 29 30 30 R_SATA_ACT 43
4 3 USBP6_D-
23 USBP6- 4 3
R27 31 34
0_0402_5%~D GND GND
32 GND GND 35
1 2 33 GND GND 36
R26
C 0_0402_5%~D TYCO_3-1775014-0~D C
1 2 USB Port
+USB_SIDE_PWR +USB_BACK_PWR
@ U187
@ U186 USBP5+ 1 4 USBP6+
USBP3+ USBP4+ D1+ D2+
1 D1+ D2+ 4
2 GND VCC 5
2 GND VCC 5
USBP6- 3 6 USBP5-
USBP4- USBP3- D2- D1-
3 D2- D1- 6
IP4220CZ6_SO6~D
IP4220CZ6_SO6~D
+USB_BACK_PWR
Place ESD diodes as close as USB connector.
+5V_SUS
U14
1 8 USB_OC5#
GND OC1# USB_OC5# 23
2 IN OUT1 7 +USB_BACK_PWR
USB_BACK_EN# 3 6
38 USB_BACK_EN# EN1# OUT2
0.1U_0402_16V4Z~D
4 5 USB_OC6#
EN2# OC2# USB_OC6# 23
150U_D2_6.3VM~D
1 1 TPS2062DR_SO8~D 1 1
C19
C9 C13
C18
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D + JUSB1
B B
1 A_VCC
2 2 2 USBP6_D- 2 A_D-
2 USBP6_D+ 3 A_D+
4 A_GND
5 B_VCC
USBP5_D- 6
USBP5_D+ B_D-
7 B_D+
+USB_SIDE_PWR
0.1U_0402_16V4Z~D
8 B_GND
1 9 G1
C292
+5V_SUS 10
U17 G2
11 G3
1 8 USB_OC3# 12
GND OC1# USB_OC3# 23 2 G4
2 IN OUT1 7
USB_SIDE_EN# 3 6 FOX_UB9112C-SB201-4F~D
38 USB_SIDE_EN# EN1# OUT2
4 5 USB_OC4#
EN2# OC2# USB_OC4# 23
1 1 TPS2062DR_SO8~D
C343 C342
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
2 2
Rear USB Ports
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 2.0 Port
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
C C
@ R1442
0_0402_5%~D
1 2
New MDC connector.
ICH_RST_MDC_R#
1 GND RES 2
S
22 ICH_RST_MDC# 1 3
Q64
BSS138W-7-F_SOT323~D
3 IAC_SDATA0 RES 4
1
+5V_SUS
G
2
R1443
100K_0402_5%~D
5 GND 3.3V 6
1 R1441
2
10K_0402_5%~D
7 IAC_SYNC GND 8
2
38 MDC_RST_DIS# 9 IAC_SDATAIN GND 10

11 IAC_RESET# IAC_BITCLK 12
B B
+3.3V_SUS
JMDC ICH_SDOUT_MDC
22 MDC_AC_BITCLK MDC_AC_BITCLK
1 2
GND1 RES0 W=20 mil
@ 10_0402_5%~D
22 ICH_SDOUT_MDC ICH_SDOUT_MDC 3 4
IAC_SDATA_OUT RES1
2
@ 10_0402_5%~D
5 GND2 3.3V 6
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
R406
22 ICH_SYNC_MDC ICH_SYNC_MDC 7 8
IAC_SYNC GND3
R98
1 2 MDC_SDIN 9 10 1 1
22 ICH_AC_SDIN1 IAC_SDATA_IN GND4
C89
C403
ICH_RST_MDC_R# 11 12 MDC_AC_BITCLK
R91 IAC_RESET# IAC_BITCLK
1
33_0402_5%~D
2 2
ICH_AC_SDOUT_MDCTERM
GND
GND
GND
GND
GND
GND
MDC_AC_BITCLK_TERM
13
14
15
16
17
18
TYCO_1-1775149-2~D
Connector for MDC Rev1.5
1 1
@
C396
10P_0402_50V8J~D C86
10P_0402_50V8J~D
A 2 2 A
@
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, BT PORT and MDC
LA-2791
5 4 3 2 1
5 4 3 2 1
JCLIP1
1 GND1
2 GND2
3
Mini Card 4
GND3
GND4
TYCO_1775837-1~D
Wire less WAN

D Mini-Card Latch D
+3.3V_RUN +3.3V_RUN
L101 DLW21SN900SQ2_0805~D JMINI1

1 USB_HUBP2_D- PCIE_WAKE#
38 USB_HUBP2- 1 @ 2 2 28,38 PCIE_WAKE# 1 1 2 2
3 3 4 4
5 5 6 6 +1.5V_RUN
4 3 USB_HUBP2_D+ MINI1CLK_REQ# 7 8 +SIM_PWR
38 USB_HUBP2+ 4 3 6 MINI1CLK_REQ# 7 8
R1577 9 10 UIM_DATA
0_0402_5%~D CLK_PCIE_MINI1# 9 10 UIM_CLK
6 CLK_PCIE_MINI1# 11 11 12 12
1 2 CLK_PCIE_MINI1 13 14 UIM_RESET
R1578 6 CLK_PCIE_MINI1 13 14 UIM_VPP
15 15 16 16
0_0402_5%~D 17 18
17 18 WWAN_RADIO_DIS#
1 2 39 8051_TX 19 19 20 20 WWAN_RADIO_DIS# 23
21 22 PLTRST#
21 22 PLTRST# 10,21,23,28,52
PCIE_IRX_WANTX_N1 23 24 +3VLAN
23 PCIE_IRX_WANTX_N1 PCIE_IRX_WANTX_P1 23 24
23 PCIE_IRX_WANTX_P1 25 25 26 26
27 27 28 28
29 30 ICH_SMBCLK
29 30 ICH_SMBCLK 6,23,28
R104 @ PCIE_ITX_WANRX_N1_C 31 32 ICH_SMBDATA
23 PCIE_ITX_WANRX_N1_C 31 32 ICH_SMBDATA 6,23,28
1 2 PCIE_ITX_WANRX_P1_C 33 34
23 PCIE_ITX_WANRX_P1_C 33 34
JCLIP2 35 36 USB_HUBP2_D-
0_0402_5%~D 35 36 USB_HUBP2_D+
1 GND1 37 37 38 38
2 GND2 39 39 40 40
3 GND3 41 41 42 42 8051_RX 39
4 1 2 WLAN_RADIO_OFF# 43 44
GND4 38 WLAN_RADIO_DIS# 43 44
45 45 46 46
TYCO_1775837-1~D 47 48
D2003 47 48
49 49 50 50
RB751S40T1_SOD523-2~D 51 52
51 52
C C
53 54
Mini-Card Latch GND1 GND2
TYCO_1775838-1~D
Mini Card +SIM_PWR
1U_0603_10V4Z~D
Wire less LAN 1
C1747
+3.3V_RUN_R +3.3V_RUN_R 2
JSIM
JMINI2 1 4
UIM_RESET VCC GND UIM_VPP
28,38 PCIE_WAKE# 1 1 2 2 2 RST VPP 5
R1609 1 2 0_0402_5%~D 3 4 UIM_CLK 3 6 UIM_DATA
40 COEX2_WLAN_ACTIVE 3 4 CLK I/O
R1610 1 2 0_0402_5%~D 5 6 +1.5V_RUN
40 COEX1_BT_ACTIVE 5 6
33P_0402_50V8J~D
33P_0402_50V8J~D
6 MINI2CLK_REQ# 7 7 8 8 7 NC NC 8
9 9 10 10
11 12 SUYIN_254020MA006G502ZL~D 1 1
6 CLK_PCIE_MINI2# 11 12
33P_0402_50V8J~D
6 CLK_PCIE_MINI2 13 13 14 14
C57
C60
33P_0402_50V8J~D
15 15 16 16
17 17 18 18 1 1
WLAN_RADIO_OFF# 2 @ 2
19 19 20 20
3
C56
C55
21 22 PLTRST#
21 22 PLTRST# 10,21,23,28,52
PCIE_IRX_WLANTX_N2 23 24 +3VLAN
23 PCIE_IRX_WLANTX_N2 PCIE_IRX_WLANTX_P2 23 24 2 2
23 PCIE_IRX_WLANTX_P2 25 25 26 26
27 27 28 28
29 29 30 30 ICH_SMBCLK 6,23,28
B PCIE_ITX_WLANRX_N2_C D5 B
23 PCIE_ITX_WLANRX_N2_C 31 31 32 32 ICH_SMBDATA 6,23,28
PCIE_ITX_WLANRX_P2_C 33 34 NNCD5.6LG~D +3VLAN +1.5V_RUN
23 PCIE_ITX_WLANRX_P2_C 33 34
35 36 USBP0-
USBP0- 23
4
35 36 USBP0+
37 37 38 38 USBP0+ 23
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
39 40 +3.3V_RUN
39 40
41 41 42 42
43 44 LED_WLAN_OUT# 1 1 1
43 44 LED_WLAN_OUT# 43
C1787
45 45 46 46 1 2 BT_ACTIVE 40,43
330U_V_6.3VM_R25~D
C1785
C1786
47 48 @ R1603 0_0402_5%~D 1
47 48
49 49 50 50 1 1 1 1
C166 C440 C136 C131 + 2 2 @ 2
51 51 52 52
C143
@
53 54 0.047U_0402_16V4Z~D 0.047U_0402_16V4Z~D 33P_0402_50V8J~D 22U_0805_6.3VAM~D
GND1 GND2 2 2 2 2 2
TYCO_1775838-1~D
Primary Power Aux Power

PWR Voltage
Rail Tolerance Peak Normal Normal
+3VLAN +1.5V_RUN
+3.3V +-9% 1000 750
250 (Wake enable)
+3.3V_RUN_R +3.3Vaux +-9% 330 250 5 (Not wake enable)
0.1U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
A A
1 1 1 +1.5V +-5% 500 375 NA
C463
1 1 1 1 1
C159
C117
C168 C464 C170 C77

C1790
2 2 2 0.047U_0402_16V4Z~D 0.047U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 4.7U_0603_6.3V4Z~D
2 2 2 2 2 DELL CONFIDENTIAL/PROPRIETARY
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card
LA-2791
5 4 3 2 1
5 4 3 2 1
+5V_RUN
+VCC_QBUF
D26 D27
2 1 +VCC_QBUFD 2 1
0.1U_0402_16V4Z~D
0.47U_0402_16V4Z~D
1
RB751S40T1_SOD523-2~D RB751S40T1_SOD523-2~D 1 1
R1332
C1822
C1823
10K_0402_5%~D
2 2
2
D QUIETE# D
C1325
U194 0.1U_0402_16V4Z~D
1 NC1 VCC4 80 1 2
PCI_AD31 2 79
PCI_AD30 A1 OE1# DOCK_AD31
3 A2 B1 78
PCI_AD29 4 77 DOCK_AD30
PCI_AD28 A3 B2 DOCK_AD29
5 A4 B3 76
7 A6 B5 74
9 A8 B7 72
10 71 DOCK_AD24
GND1 B8
11 NC2 VCC3 70
PCI_AD23 12 69
13 A10 B9 68
15 A12 B11 66
17 A14 B13 64
19 A16 B15 62
20 61 DOCK_AD16
GND2 B16
21 NC3 VCC2 60
PCI_AD15 22 59
23 A18 B17 58
25 A20 B19 56
27 A22 B21 54
C PCI_AD8 DOCK_AD10 C
28 A23 B22 53
A24 B23 DOCK_AD9
30 GND3 B24 51
31 NC4 VCC1 50
PCI_AD7 32 49
33 A26 B25 48
35 A28 B27 46
37 A30 B29 44
39 A32 B31 42
40 41 DOCK_AD0
GND4 B32
PI5C34X2245BE_BQSOP80~D
DOCK_AD[0..31] 36
21,30 PCI_AD[0..31]
+3.3V_RUN_R
C1824
0.47U_0402_16V4Z~D
1 2
1
2
C1328 C1329
U184 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
QUIETE# 47 36 1 2 R1335
OE1 VCC1 100K_0402_5%~D 2
35 OE2 VCC2 48
B B
1
PCI_PIRQA# 2 46 DOCK_PIRQA#
21 PCI_PIRQA# A0 B0 DOCK_PIRQA# 36
5
PCI_GNT0# 3 45 DOCK_GNT0# U185
21,36 PCI_GNT0# A1 B1 DOCK_GNT0# 36
PCI_RST# 4 44 DOCK_PCIRST# DOCK_PCI_EN# 1
P
21,30,31 PCI_RST# A2 B2 DOCK_PCIRST# 36 36 DOCK_PCI_EN# INA
SYS_PME# 5 43 DOCK_SPME# 4 QUIETE#
30,38 SYS_PME# A3 B3 DOCK_SPME# 36 O
PCI_C_BE3# 6 42 DOCK_C_BE3# QBUFEN# 2
21,30 PCI_C_BE3# A4 B4 DOCK_C_BE3# 36 38 QBUFEN# INB
G
PCI_C_BE2# 7 41 DOCK_C_BE2#
21,30 PCI_C_BE2# A5 B5 DOCK_C_BE2# 36
PCI_C_BE1# 8 40 DOCK_C_BE1# SN74AHC1G32DCKR_SC70-5~D
21,30 PCI_C_BE1# DOCK_C_BE1# 36
3
PCI_C_BE0# A6 B6 DOCK_C_BE0#
21,30 PCI_C_BE0# 9 A7 B7 39 DOCK_C_BE0# 36
PCI _IRDY# 10 38 DOCK_IRDY#
21,30,36 PCI_IRDY# A8 B8 DOCK_IRDY# 36
PCI_FRAME# 11 37 DOCK_FRAME#
21,30,36 PCI_FRAME# A9 B9 DOCK_FRAME# 36
PCI_TRDY# 14 34 DOCK_TRDY#
21,30 PCI_TRDY# A10 B10 DOCK_TRDY# 36
PCI_STOP# 15 33 DOCK_STOP#
21,30 PCI_STOP# A11 B11 DOCK_STOP# 36
PCI_PLOCK# 16 32 DOCK_LOCK#
21 PCI_PLOCK# A12 B12 DOCK_LOCK# 36
PCI_DEVSEL# 17 31 DOCK_DEVSEL#
21,30 PCI_DEVSEL# A13 B13 DOCK_DEVSEL# 36
PCI_PERR# 18 30 DOCK_PERR#
21,30 PCI_PERR# A14 B14 DOCK_PERR# 36
PCI_SERR# 19 29 DOCK_SERR#
21 PCI_SERR# A15 B15 DOCK_SERR# 36
PCI_PAR 20 28 DOCK_PAR
21,30 PCI_PAR A16 B16 DOCK_PAR 36
PCI_AD24 21 27 DOCK_PCI_IDSEL
A17 B17 DOCK_PCI_IDSEL 36
22 A18 B18 26
23 A19 B19 25
1 NC1 GND1 12
13 NC2 GND2 24
PI5C162861BE_BQSOP48~D
A A
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DOCKING BUFFER
5 4 3 2 1
5 4 3 2 1
+DOCK_PWR_SRC
JDOCKA JDOCKB JDOCKC
1 69 DOCK_DET# 137 205 DOCK_DET# P1 P5 DOCK_DC_IN
S1 S69 S137 S205 P1 P5 DOCK_DC_IN 44
2 70 VGA_RED VGA_GRN 138 206
S2 S70 S138 S206 DAT_DDC2 12,20
52 DVI_CLK- 3 S3 S71 71 139 S139 S207 207 CLK_DDC2 12,20 P2 P2 P6 P6
4 72 VGA_BLU 140 208
52 DVI_CLK+ S4 S72 S140 S208
0.1U_0603_50V4Z~D
1000P_0402_50V7K~D
5 73 141 209 HSYNC_R P3 P7
S5 S73 D_SERIRQ 38 S141 S209 HSYNC_R 20 P3 P7
6 74 D_LAD1 142 210 VSYNC_R 2 1
S6 S74 DOCK_PCI_IDSEL 35 38 D_LAD1 S142 S210 VSYNC_R 20
C291
C1827
DVI_TX4- 7 75 D_LAD2 143 211 P4 P8
S7 S75 38 D_LAD2 S143 S211 P4 P8
0.1U_0603_50V4Z~D
DVI_TX4+ 8 76 D_LAD3 144 212
D S8 S76 38 D_LAD3 S144 S212 D_CLKRUN# 38 D
9 77 145 213 D_LAD0
S9 S77 D_DLRQ1# 38 S145 S213 D_LAD0 38 1 2
10 78 DOCK_AD1 146 214 DOCK_SIO_ALERT# 2 MH1 MH2
S10 S78 D_LFRAME# 38 S146 S214 DOCK_SIO_ALERT# 38 MH1 MH2
C1296
DVI_TX3+ 11 79 DOCK_AD0 147 215
DVI_TX3- S11 S79 S147 S215 DOCK_AD2
12 S12 S80 80 148 S148 S216 216 MH5 SHLD1 SHLD3 MH7
13 81 DOCK_AD3 149 217 DOCK_AD5
S13 S81 DVI_SCLK 52 S149 S217 1
82 DOCK_AD4 150 218 DOCK_AD6 MH6 MH8
S82 DVI_SDATA 52 S150 S218 SHLD2 SHLD4
15 83 DOCK_AD7 151
44 PS_ID_IN S15 S83 DVI_DETECT 52 S151
84 DOCK_AD8 152 220 MH9 MH11
S84 DOCK_C_BE0# DOCK_AD9 S152 S220 SHLD5 SHLD7
17 S17 S85 85 DOCK_C_BE0# 35 153 S153
DVI_TX5+ 18 86 DOCK_AD10 154 222 DOCK_AD12 MH10 MH12
DVI_TX5- S18 S86 DOCK_AD11 S154 S222 DOCK_AD13 SHLD6 SHLD8
19 S19 S87 87 155 S155 S223 223
20 88 DOCK_AD14 156 224 DOCK_C_BE1#
S20 S88 S156 S224 DOCK_C_BE1# 35
21 89 DOCK_AD15 157 225
S21 S89 35 DOCK_PAR S157 S225 DOCK_PERR#
52 DVI_TX2+ 22 S22 S90 90 35 DOCK_SERR# 158 S158 S226 226 DOCK_PERR# 35
23 91 159 227 DOCK_STOP# MH13 MH14
52 DVI_TX2- S23 S91 35 DOCK_LOCK# S159 S227 DOCK_STOP# 35 MH13 MH14
24 92 160 228 DOCK_TRDY# MH15 MH16
S24 S92 DOCK_DEVSEL# 35 S160 S228 DOCK_TRDY# 35 MH15 MH16
25 S25 S93 93 DOCK_IRDY# 35 35 DOCK_FRAME# 161 S161 S229 229
26 94 DOCK_C_BE2# 162 230 DOCK_AD17
52 DVI_TX1+ S26 S94 35 DOCK_C_BE2# S162 S230
27 95 DOCK_AD16 163 231 DOCK_AD18 TYCO_2-1612415-1~D
52 DVI_TX1- S27 S95 S163 S231
28 96 DOCK_AD19 164 232 DOCK_AD21
S28 S96 DOCK_AD20 DOCK_AD22 S164 S232
29 S29 S97 97 165 S165 S233 233
30 98 DOCK_AD23 166 234 DOCK_C_BE3#
52 DVI_TX0+ S30 S98 S166 S234 DOCK_C_BE3# 35
31 99 DOCK_AD24 167 235 DOCK_AD25
52 DVI_TX0- S31 S99 S167 S235
32 100 DOCK_AD27 168 236 DOCK_AD26
S32 S100 DOCK_AD28 DOCK_AD29 S168 S236 DOCK_AD0
33 S33 S101 101 169 S169 S237 237
DOCK_AD31 34 102 DOCK_AD30 170 238 PCI_REQ0# DOCK_AD1
S34 S102 35 DOCK_SPME# S170 S238 DOCK_PCIRST# PCI_REQ0# 21 DOCK_AD2
6 CLK_DOCKPCI_33M 35 S35 S103 103 DOCK_GNT0# 35 171 S171 S239 239 DOCK_PCIRST# 35
36 104 TV_C 172 240 DOCK_AD3
35 DOCK_PIRQA# S36 S104 USBP7- S172 S240 TV_CVBS DOCK_AD4
37 S37 S105 105 USBP7- 23 173 S173 S241 241
38 106 USBP7+ 174 242 DOCK_AD5
S38 S106 USBP7+ 23 35 DOCK_PCI_EN# S174 S242
39 107 SPDIF_DOCK 175 243 TV_Y DOCK_AD6 TV_C 1 2
39 DOCK_SMB_CLK S39 S107 26 SPDIF_DOCK S175 S243 DOCK_AD7 R1790 150_0402_1%~D
39 DOCK_SMB_DAT 40 S40 S108 108 DOCK_SMB_INT# 39 176 S176 S244 244
C DOCK_LED_10# DOCK_AD8 TV_CVBS C
39 CLK_DOCK 41 S41 S109 109 CLK_KBD 39 29 DOCK_LED_10# 177 S177 S245 245 1 2
42 110 DOCK_LED_100# 178 246 DOCK_LAN_ACTLED_YEL# DOCK_AD9 R1791 150_0402_1%~D
39 DAT_DOCK S42 S110 DAT_KBD 39 29 DOCK_LED_100# S178 S246 DOCK_LAN_ACTLED_YEL# 29
43 111 179 247 DOCK_AD10 TV_Y 1 2
S43 S111 DOCK_OWNS_PCI S179 S247 R_PIDEACT DOCK_AD11 R1792 150_0402_1%~D
S112 112 180 S180 S248 248 R_PIDEACT 43
45 113 +2.5VLAN 181 DOCK_AD12
S45 S113 S181 DOCK_AD13
S114 114 182 S182 S250 250
47 115 183 DOCK_AD14
S47 S115 C1297 C1298 S183 DOCK_AD15
48 S48 S116 116 184 S184 S252 252
CLK_DOCKPCI_33M 49 117 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 185 253 DOCK_AD16
S49 S117 S185 S253 DOCK_AD17
50 S50 S118 118 1 2 2 1 186 S186 S254 254
51 119 187 255 DOCK_AD18
S51 S119 C1299 C1300 S187 S255 DOCK_AD19
52 S52 S120 120 188 S188 S256 256
1
@ 53 121 0.01U_0402_16V7K~D 0.01U_0402_16V7K~D 189 257 DOCK_AD20

R1334 S53 S121 S189 S257 DOCK_AD21
54 S54 S122 122 1 2 2 1 190 S190 S258 258
33_0402_5%~D 55 259 DOCK_AD22
S55 S259 DOCK_AD23
S125 125 DOCK_LAN_TX3- 29 29 DOCK_LAN_TX1- 193 S193
126 194 DOCK_AD24
DOCK_LAN_TX3+ 29
2
S126 29 DOCK_LAN_TX1+ S194 DOCK_AD25

1 S127 127 DOCK_LAN_TX2- 29 29 DOCK_LAN_TX0- 195 S195
@ 128 196 DOCK_AD26
S128 DOCK_LAN_TX2+ 29 29 DOCK_LAN_TX0+ S196
C1327 DOCK_AD27
22P_0402_50V8J~D 136 DOCK_RING DOCK_TIP 204 DOCK_AD28
2 M136 M204 DOCK_AD29
TYCO_2-1612415-1~D TYCO_2-1612415-1~D DOCK_AD30
DOCK_AD31
PLACE TERMINATIONS CLOSE TO DOCK CONNECTOR Q59
DOCK_AD[0..31] 35
FDS4435_NL_SO8~D
+3.3V_RUN_R 8 +DOCK_PWR_SRC
+PWR_SRC 1 7
2 6 1
1 2 3 5
2
+3.3V_RUN_R C1301 R1321 C1821
B C1820 0.1U_0603_50V4Z~D 100K_0402_5%~D 1000P_0402_50V7K~D B
0.1U_0402_16V4Z~D 2
4
2 +3.3V_ALW 1
1
5
1
C1818 G_DOC_PWRSRC
P
NC
2
PCI_GNT0# 2 4 0.1U_0402_16V4Z~D
21,35 PCI_GNT0# A Y 2 R1322
DOCKED 29,38
G
U177 U178 100K_0402_5%~D
1
NC7SZ04P5X_NL_SC70-5~D Z3305 1 +5V_ALW
P
3
IN1 DOCK_OWNS_PCI R1323

4
1
+3.3V_RUN_R O 100K_0402_5%~D
2 IN2
G
C1819 NB no power dock
2
1 2 74AHC1G08GW_SOT353-5~D R1324
3
2
1
100K_0402_5%~D
5
U179 0.1U_0402_16V4Z~D @ D25

PCI _IRDY# 1 SM05TCT_SOT23-3~D
P
21,30,35 PCI_IRDY#
1
IN1 Z3306
O 4
PCI_FRAME# 2 DOCK_DET#
Z3307
21,30,35 PCI_FRAME# 2
1
IN2
G
3
Q60
3
DDTC144EUA-7-F_SOT323~D PWR_SRC self power dock

TV_C U180
12 TV_C
3
1
D
2
G
TV_Y IN2 Z3308 Q61
12 TV_Y O 4 2
DOCK_PWR_EN 1 G 2N7002W-7-F_SOT323~D
38 DOCK_PWR_EN IN1
P
S
3
100K_0402_5%~D
TV_CVBS
12 TV_CVBS C1817
2
JW IRE 2 1 +3.3V_SUS
A VGA_RED A
12,20 VGA_RED 1 1
R1325
DOCK_RING 2 2
3 3 0.1U_0402_16V4Z~D
1
VGA_GRN DOCK_TIP 4 4
12,20 VGA_GRN
1 2
MOLEX_53398-0471~D
VGA_BLU R1326
12,20 VGA_BLU
@ 0_0402_5%~D
Title
DOCKING CONN.
5 4 3 2 1
5 4 3 2 1
+3.3V_SUS
1
D C1254 D
0.1U_0402_16V4Z~D
C1255
2 0.47U_0402_16V4Z~D
1 2
C1256
26
0.1U_0402_16V4Z~D U173 JSIO
1 2 3243C1+ 28 DCD0 1
VCC
C1+ 3243V+ C1257 DSR0 DCD0
V+ 27 6 DSR0
C1258 0.47U_0402_16V4Z~D RXD0# 2
0.47U_0402_16V4Z~D 3243C1- 3243V- RTS0 RXD0#
24 C1- V- 3 1 2 7 RTS0F
1 2 3243C2+ 1 TXD0# 3
C2+ CTS0 TXD0F#
8 CTS0
DTR0 4
3243C2- R I0 DTR0F
2 C2- 9 RI0
TXD0 14 9 TXD0# 5
38 TXD0 T1IN T1OUT GND0
RTS0# 13 10 RTS0
38 RTS0# T2IN T2OUT
DTR0# 12 11 DTR0 10
38 DTR0# T3IN T3OUT GND1
DCD0# 19 4 DCD0 11
38 DCD0# R1OUT R1IN GND2
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
270P_0402_50V7K~D
RI0# 18 5 R I0
38 RI0# R2OUT R2IN
RXD0 17 6 RXD0#
38 RXD0 CTS0# R3OUT R3IN CTS0 SUYIN_070921MR009S203BR~D
38 CTS0# 16 R4OUT R4IN 7 1 1 1 1 1 1 1 1
DSR0# 15 8 DSR0
38 DSR0# R5OUT R5IN
C238
C256
C257
C258
C259
C260
C262
C272
20 R2OUTB
INVALID# 21
2 2 2 2 2 2 2 2
+3.3V_SUS 23 FORCEON
25 @ @ @ @ @ @ @ @
GND
19,39,41,42,46,47,48 RUN_ON 22 FORCEOFF#
MAX3243ECUI+T_TSSOP28~D
C C
FIR
R1287
47_0805_5%~D +3.3V_RUN
+3.3V_RUN 2 1 IRVCC
U175
R1289 6 1
0_0402_5%~D VCC IRED_ANODE
1 2 SD_MODE 5 4
38 D_IRMODE SD_MODE RXD IRRX 38
4.7U_0603_6.3V4Z~D
2 IRED_CATHODE MODE 7
10K_0402_5%~D
1
1
10K_0402_5%~D
38 IRTX 3 TXD GND 8 1
R1290
R1291
C1259
B B
TFDU6102-TR3_8P~D
4.7U_0603_6.3V4Z~D
2
0.1U_0402_16V4Z~D
2
2
2 1
C1260
C1261
1 2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Serial & FIR
LA-2791
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+3.3V_ALW +3.3V_ALW
1 1 1 1
1 2 DOCK_SIO_ALERT# 1 2 SYS_PME#
R1620 10K_0402_5%~D R1362 10K_0402_5%~D C1750 C1751 C1752 C1753
1 2 PCIE_WAKE# 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
R1361 10K_0402_5%~D 2 2 2 2
D D
1 2 SBAT_ALARM# 1
108
R1363 10K_0402_5%~D
34
57
85
1 2 PBAT_ALARM# U215 C1754 +3.3V_ALW
R1369 10K_0402_5%~D 0.1U_0402_16V4Z~D
VCC1
VCC1
VCC1
VCC1
2
PCIE_WAKE# 97 L104
28,34 PCIE_WAKE# GPIOA[0]
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
SYS_PME# 98 BLM18PG181SN1_0603~D
30,35 SYS_PME# GPIOA[1]
DOCK_SIO_ALERT# 99 8 SIO_VDDA 1 2
+3.3V_RUN 36 DOCK_SIO_ALERT# GPIOA[2] VDDA33
4.7U_0603_6.3V4Z~D
PBAT_PRES# 100 14 1 1 1 1 1
45 PBAT_PRES# GPIOA[3] VDDA33
SBAT_PRES# 101 20
45,51 SBAT_PRES# GPIOA[4]
ECE5018 VDDA33
C67
C1755
C1756
C1757
1 2 IMVP6_PROCHOT# 51 CHG_PBATT
CHG_PBATT 102 GPIOA[5]
C1758
R34 100K_0402_5%~D CHG_SBATT 103 119 4.7U_0603_6.3V4Z~D
51 CHG_SBATT SBAT_LOW GPIOA[6] VCC1 2 2 2 2 2
51 SBAT_LOW 104 GPIOA[7]
1 2 DOCK_HP_MUTE# USBDP0 9 USBP1+
USBP1+ 23
@ R87 100K_0402_5%~D DOCKED 24 10 USBP1-
29,36 DOCKED GPIOH[0] USBDN0 USBP1- 23
35 QBUFEN# QBUFEN# 25 13 USB_HUBP1+
GPIOH[1] USBDP1 USB_HUBP1+ 30
36 DOCK_PWR_EN DOCK_PWR_EN 26 12 USB_HUBP1- <---PC Card Bay
GPIOH[4] USBDN1 USB_HUBP1- 30
SNIFFER_WIRELESS_ON/OFF# 27 15 USB_HUBP2+ +3.3V_RUN
43 SNIFFER_WIRELESS_ON/OFF# GPIOH[5] USBDP2 USB_HUBP2+ 34
BC_INT 58 16 USB_HUBP2- <---Mini1 WWAN
+3.3V_SUS
39
39 BC_INT
BC_DAT
BC_DAT 59
BC_INT#
BC_DAT
USB USBDN2
USBDP3 19 USB_HUBP3+
USB_HUBP2-
USB_HUBP3+
34
31
BC_CLK 60 18 USB_HUBP3- <---Smart Card D_CLKRUN# 2 1
39 BC_CLK BC_CLK USBDN3 USB_HUBP3- 31
21 USB_HUBP4+ R1645 100K_0402_5%~D
USBDP4 USB_HUBP4+ 40
RXD0 1 22 USB_HUBP4- <---Blue Tooth D_SERIRQ 2 1
37 RXD0 GPIOE[0]/RXD USBDN4 USB_HUBP4- 40
1
TXD0 2 R1646 100K_0402_5%~D

37 TXD0 GPIOE[1]/TXD
R1171 RTS0# 3 125 D_DLRQ1# 2 1
37 RTS0# GPIOE[2]/RTS# VDDA33PLL
10K_0402_5%~D DSR0# 4 124 R1437 100K_0402_5%~D
37 DSR0# GPIOE[3]/DSR# VDDA18PLL
CTS0# 5 120
37 CTS0# GPIOE[4]/CTS# VDD18 +3.3V_ALW +3.3V_ALW
DTR0# 84 86
37 DTR0#
2
RI0# GPIOE[5]/DTR# CAP_LDO RBIAS

37 RI0# 83 GPIOE[6]/RI# RBIAS 127
DCD0# 6
37 DCD0# GPIOE[7]/DCD#
1
12K_0402_1%~D
LAN_TPM_EN# 2 1
R1598
C TEST_PIN is a No Connect R1599 R1440 @ 100K_0402_5%~D C
65 GPIOB[0]/INIT#
66 Route RBIAS and its 10K_0402_5%~D
MDC_RST_DIS# GPIOB[1]/SLCTIN# return to pin 128 very
Place closely pin 64 33 MDC_RST_DIS#
ADAPT_OC
67 GPIOC[2]/SCLT TEST_PIN 35
68 short.
50 ADAPT_OC TEST
2
CLK_SIO_14M GPIOC[3]/PE
69
70
GPIOC[4]/BUSY
GPIOC[5]/ACK#
GPIO
71 126 REG_EN C1451
GPIOC[6]/ERROR# ATEST
1
NB_MUTE 73 15P_0402_50V8J~D
R135 27 NB_MUTE GPIOC[7]/ALF# ECE5018_XTAL1
74 GPIOD[0]/STROBE# XTAL1/CLKIN 123 1 2
22_0402_5%~D @ R55 2 1 0_0402_5%~D 75 122 ECE5018_XTAL2 2 1
28 LOM_CABLE_DETECT GPIOC[1]/PD7 CLK XTAL2
1M_0402_5%~D
@ SPDIF_SHDN 76 R66
26 SPDIF_SHDN GPIOC[0]/PD6
1
IMVP6_PROCHOT# 77 0_0402_5%~D Y1
49 IMVP6_PROCHOT#
2
GPIOB[7]/PD5 24MHZ_12PF_1BX24000CE1B~D
78 GPIOB[6]/PD4 LPC_LAD[0..3] 22,28,39
R1600
1 79 54 LPC_LAD0
GPIOB[5]/PD3 LAD0 LPC_LAD1
18 5V_CAL_SIO2# 80 52
2
C145 DOCK_HP_MUTE# GPIOB[4]/PD2 LAD1 LPC_LAD2 C1452
26 DOCK_HP_MUTE# 81 49
2
22P_0402_50V8J~D HP_NB_SENSE GPIOB[3]/PD1 LAD2 LPC_LAD3
26,27 HP_NB_SENSE 82 GPIOB[2]/PD0 LAD3 47 1 2
@ 2 LPC_LFRAME#
LFRAME# 42 LPC_LFRAME# 22,28,39
SBAT_ALARM# 61 41 PLTRST2# 15P_0402_50V8J~D
45 SBAT_ALARM#
45 PBAT_ALARM#
PBAT_ALARM# 62
GPIOD[1]
GPIOD[2]
LPC LRESET#
PCICLK 56 CLK_PCI_5018
PLTRST2# 21,39
CLK_PCI_5018 6
37 CLKRUN#
CLKRUN# CLKRUN# 23,30,39
LAN_TPM_EN# 63 46 LPC_LDRQ0#
28 LAN_TPM_EN# GPIOD[3]/VBUS_DET LDRQ0# LPC_LDRQ0# 22
LAN_LOW_PWR 28 44 LPC_LDRQ1#
28 LAN_LOW_PWR GPIOD[4]/OCS1_N LDRQ1# LPC_LDRQ1# 22
AUDIO_AVDD_ON 29 39 IRQ_SERIRQ Place closely pin 56
26 AUDIO_AVDD_ON GPIOD[5]/OCS2_N SER_IRQ IRQ_SERIRQ 23,28,30,39
BEEP 30
26 BEEP GPIOD[6]/OCS3_N CLK_SIO_14M CLK_PCI_5018
31 GPIOD[7]/OCS4_N CLKI (14.318 MHz) 64 CLK_SIO_14M 6
BAY_MODPRES# 32 96
25 BAY_MODPRES# GPIOH[6] VSS
1
SC_DET# 33
31 SC_DET# GPIOH[7]
55 D_LAD0 R134
ICH_PCIE_WAKE# DLAD0 D_LAD1 D_LAD0 36
23 ICH_PCIE_WAKE# 88 GPIOG[0] DLAD1 53 D_LAD1 36 22_0402_5%~D
ICH_PME# 89 50 D_LAD2
@
B 21 ICH_PME# THERMTRIP_SIO GPIOG[1] DLAD2 D_LAD3 D_LAD2 36 B
18 THERMTRIP_SIO 90 DLPC 48
2
GPIOG[2] DLAD3 D_LFRAME# D_LAD3 36
91 GPIOG[3] DLFRAME# 43 D_LFRAME# 36
92 38 D_CLKRUN# 1
GPIOG[4] DCLK_RUN# D_CLKRUN# 36
19 FPBACK_EN FPBACK_EN 93 45 D_DLRQ1#
GPIOG[5] DLDRQ1# D_DLRQ1# 36
94 40 D_SERIRQ C144
GPIOG[6] DSER_IRQ D_SERIRQ 36
7 CPU_PROCHOT# CPU_PROCHOT# 95 22P_0402_50V8J~D
GPIOG[7] 2
@
HDDC_EN# 106
41 HDDC_EN# SYSOPT1/GPIOH[2]
MODC_EN# 107
41 MODC_EN# SYSOPT0/GPIOH[3]
7 RUNPWROK
PWRGD RUNPWROK 39,42,49
BID3 109
BID2 GPIOF[7] WLAN_RADIO_DIS#
110 GPIOF[6] OUT65 105 WLAN_RADIO_DIS# 34
BID1 111
BID0 GPIOF[5]
112 GPIOF[4]
VSS 11
IRTX 113 17
37 IRTX IRTX VSS
IRRX 114 23
37 IRRX IRRX VSS
VSS 36
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
D_IRMODE 115 51
37 D_IRMODE GPIOF[3]/IRMODE/IRRX3B VSS
USB_SIDE_EN# 116 72
32 USB_SIDE_EN# GPIOF[2]/IRTX2 VSS
USB_BACK_EN# 117 87 1 1 1 1
32 USB_BACK_EN# GPIOF[1]/IRRX2 VSS
118 GPIOF[0]/IRMODE/IRRX3A VSS 121
C1759
C1760
C1761
C1762
VSS 128
2 2 2 2
ECE5018 A0_VTQFP128~D
+3.3V_ALW
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
2
2
R94
R95
R405
R404
A
BID3 BID2 BID1 BID0 REV A
1
@ @ 0 0 0 0 M00
BID0 R419 1 2 @ 10K_0402_5%~D
0 0 0 1 M01
BID1 R107 1 2 10K_0402_5%~D
0 0 1 0 X00 DELL CONFIDENTIAL/PROPRIETARY
BID2 R108 2 @ 10K_0402_5%~D
1
0 0 1 1 X01 Compal Electronics, Inc.
BID3 R418 1 2 10K_0402_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
0 1 0 0 X02 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ECE5018
0 1 0 1 X03 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Size Document Number Rev
0.6
LA-2791
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
+3.3V_ALW
1
+RTC_CELL
R119
100K_0402_5%~D
1 2 R125
2
R62 1 1 1 1 1 1 10K_0402_5%~D
0_0402_5%~D POWER_SW_IN# 1 2 POWER_SW#
C105 POWER_SW# 18,40
1U_0603_10V4Z~D
+3.3V_ALW C1763 C1764 C1765 C1766 C1767 1
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
R93 2 2 2 2 2 2
C130
1 2 BAT_SEL#
2
10K_0402_5%~D
121
116
21
44
65
83
U216 +RTC_CELL
D D
VCC0
VCC1
VCC1
VCC1
VCC1
VCC1
1
40 KSO[0..17]
KSO17 12 R30
KSO16 KSO17/GPIOA1 100K_0402_5%~D +RTC_CELL
13 KSO16/GPIOA0
KSO15 14
KSO14 GPIO5/KSO15 R31
15
2
+5V_RUN KSO13 GPIO4/KSO14 A LWON 10K_0402_5%~D POWER_SW_IN1#
16 KSO13/GPIO18 ALWON 120 ALWON 46 2 1
KSO12 17 119 S NIFFER_PWR_SW# S NIFFER_PWR_SW# 1 2 SN IFFER# R1637 100K_0402_5%~D
PWR SW
KSO12/OUT8 POWER_ SW_IN2# SNIFFER# 43
KSO11 18 126 POWER_SW_IN1# 1
KSO10 KSO11/GPIOC7 POWER_ SW_IN1# POWER_SW_IN#
19 KSO10/GPIOC6 POWER_ SW_IN0# 127
1 2 CLK_KBD KSO9 20 128 ACAV_IN C46 +5V_ALW
KSO9/GPIOC5 ACAV_IN ACAV_IN 18,50,51
R468 4.7K_0402_5%~D KSO8 23 118 1U_0603_10V4Z~D
KSO7 KSO8/GPIOC4 BGPO0 2 DOCK_SMB_DAT
24 KSO7/GPIO3 2 1
Keyboard and Mouse Interface

1 2 DAT_KBD KSO6 25 8 PBAT_SMBCLK R99 8.2K_0402_5%~D
KSO6/GPIO2 AB1B_CLK PBAT_SMBCLK 45,50
R469 4.7K_0402_5%~D KSO5 27 7 PBAT_SMBDAT DOCK_SMB_CLK 2 1
KSO5/GPIO1 AB1B_DATA PBAT_SMBDAT 45,50
KSO4 28 6 DOCK_SMB_CLK R100 8.2K_0402_5%~D
KSO4/GPIO0 AB1A_CLK DOCK_SMB_CLK 36
1 2 CLK_DOCK KSO3 29 5 DOCK_SMB_DAT DOCK_SMB_INT# 2 1
KSO3/GPIOC3 AB1A_DATA DOCK_SMB_DAT 36
R1607 4.7K_0402_5%~D KSO2 30 93 VAUX_EN R1618 10K_0402_5%~D
KSO2/GPIOC2 GPIO11/AB2A_DATA VAUX_EN 41,46
KSO1 31 94 SUS_ON
KSO1/GPIOC1 GPIO12/AB2A_CLK SUS_ON 41,42,46
1 2 DAT_DOCK KSO0 32 95 RUN_ON
KSO0/GPIOC0 GPIO13/AB2B_DATA RUN_ON 19,37,41,42,46,47,48
R1608 4.7K_0402_5%~D 96 ITP_DBRESET# +3.3V_ALW
40 KSI[0..7] GPIO14/AB2B_CLK ITP_DBRESET# 7,23
KSI7 33 111 SBAT_SMBDAT +3.3V_ALW
KSI7/GPIO19 GPIO87/AB1C_DATA SBAT_SMBDAT 19,45
KSI6 34 112 SBAT_SMBCLK
KSI6/GPIO17 GPIO86/AB1C_CLK SBAT_SMBCLK 19,45
KSI5 35 9 DAT_SMB DAT_SMB 1 2
KSI5/GPIO10 GPIO85/AB1D_DATA DAT_SMB 18
KSI4 36 10 CLK_SMB R106 10K_0402_5%~D
KSI4/GPIO9 GPIO84/AB1D_CLK CLK_SMB 18
1
KSI3 37 97 SIO_SLP_S5# CLK_SMB 1 2
KSI3/GPIO8 GPIO93/AB1F_DATA SIO_SLP_S5# 23
KSI2 38 98 SIO_SLP_S3# R482 R105 10K_0402_5%~D
KSI2/GPIO7 GPIO92/AB1F_CLK SIO_SLP_S3# 23
KSI1 39 99 S IO_RCIN# 1M_0402_5%~D SBAT_SMBDAT 1 2
KSI1/GPIO6 GPIO91/AB1E_DATA SIO_RCIN# 22
KSI0 40 100 SIO_EXT_WAKE# R444 2.2K_0402_5%~D
+3.3V_ALW +3.3V_ALW KSI0/SGPIO30 GPIO90/AB1E_CLK SIO_EXT_WAKE# 23 R473 SBAT_SMBCLK 1 2
2
SIO_A20GATE 92 43 SNIFFER_LED_OFF# SNIFFER_LED_OFF# 43 10_0402_5%~D R131 2.2K_0402_5%~D
22 SIO_A20GATE SGPIO34/A20M GPIO82/FAN_TACH3
10K_0402_5%~D
10K_0402_5%~D
SIO_THRM# 50 42 LID_CL_SIO# 2 1 LID_CL# PBAT_SMBDAT 1 2

23 SIO_THRM# OUT5/KBRST GPIO16/FAN_TACH2 LID_CL# 40
1
41 FAN1_TACH R449 4.7K_0402_5%~D

+3.3V_ALW GPIO15/FAN_TACH1 FAN1_TACH 18
R103
R1636
CLK_TP_SIO 75 1 PBAT_SMBCLK 1 2
40 CLK_TP_SIO GPIO94/IMCLK
DAT_TP_SIO 76 48 C482 R447 4.7K_0402_5%~D
40 DAT_TP_SIO GPIO95/IMDAT OUT2/PWM3 0.047U_0402_16V4Z~D
CLK_KBD 77 47
36 CLK_KBD KCLK OUT9/PWM2
C DAT_KBD 78 46 C
36 DAT_KBD
2
CLK_DOCK KDAT OUT11/PWM1 BREATH_LED 2 R1635 +3.3V_SUS

36 CLK_DOCK 79 EMCLK OUT10/PWM0 45 BREATH_LED 43
5 DAT_DOCK 80 10K_0402_5%~D
5 36 DAT_DOCK EMDAT
4 8051_RX 8051_RX 81 66 SIO_EXT_SCI# ATF_INT# 2 1
4 34 8051_RX GPIO20/PS2CLK/8051RX nEC_SCI/SPDIN2 SIO_EXT_SCI# 23
3 8051_TX 8051_TX 82 55
Molex_53261 3 34 8051_TX GPIO21/PS2DAT/8051TX SGPIO45/MSDATA/SPDOUT2
2 1 2 DEBUG_ENABLE# 54 PS_ID
@ JDEBUG 2 R1752 0_0402_5%~D SGPIO44/MSCLK/SPCLK2 VGA_IDENTIFY PS_ID 44
1 1 SGPIO46/SPDIN1 69
68 LID_CL_SIO#
PLTRST2# SGPIO47/SPDOUT1 DEBUG_ENABLE#
57 67
LPC Interface
21,38 PLTRST2# LRESET# SGPIO31/TIN1/SPCLK1
R1752 no stuff when doing CLK_PCI_5004 58
6 CLK_PCI_5004 PCICLK
LPC_LFRAME# 59 70 HOST_DEBUG_TX PAD~D T6
flash recovery 22,28,38 LPC_LFRAME#
LPC_LAD0 60
LFRAME# SYSOPT0/SGPIO32/LPC_TX
71 HOST_DEBUG_RX PAD~D T7
LAD0 SYSOPT1/SGPIO33/LPC_RX
10K_0402_5%~D
10K_0402_5%~D
LPC_LAD1 61
LPC_LAD[0..3] LPC_LAD2 LAD1 CAP_LED# +3.3V_ALW
22,28,38 LPC_LAD[0..3] 62 LAD2 SGPIO40 91 CAP_LED# 43
1
LPC_LAD3 63 90 SCRL_LED#
LAD3 SGPIO41 SCRL_LED# 43
CLK RUN# 64 89 NUM_LED#
23,30,38 CLKRUN# CLKRUN# SGPIO42 NUM_LED# 43
1
R1604
R1605
IRQ_SERIRQ 56 4 SPI_CS_L# 1 2
23,28,30,38 IRQ_SERIRQ SER_IRQ SGPIO43 SPI_CS_R#
R143 0_0402_5%~D R475
1 DOCK_SMB_INT# 10K_0402_5%~D
DOCK_SMB_INT# 36
2
ICH_EC_SPI_CLK SGPIO35 SFPI_EN @ @
23 ICH_EC_SPI_CLK 102 HSTCLK SGPIO36 (SFPI_EN) 2 @
ICHI_ECO_SPI_DATA 105 3 PS_ID_DISABLE#
Host/8051
2
23 ICHI_ECO_SPI_DATA ICHO_ECI_SPI_DATA HSTDATAIN SGPIO37 PS_ID_DISABLE# 44
23 ICHO_ECI_SPI_DATA 107 HSTDATAOUT
52 ATF_INT# VGA_IDENTIFY SFPI_EN
GPIO96/TOUT1 ATF_INT# 18
FC LK 103 FLCLK
1
ICHI_FDATAOUT 106 11 SIO_EXT_SMI#
FLDATAIN OUT7/nSMI SIO_EXT_SMI# 23
ICHO_FDATAIN 108 115 BAT2_LED# Bat2 = Amber LED R474
FLDATAOUT nPWR_LED BAT2_LED# 43
114 BAT1_LED# Bat1 = Green LED 1 = Discrete Gfx R521 10K_0402_5%~D
nBAT_LED BAT1_LED# 43
SIO_PWRBTN# 109 100K_0402_5%~D
23 SIO_PWRBTN# FLCS0
50 BAT_SEL# BAT_SEL# 110 84 FW P# 20mA drive pins 0 = UMA
2
FLCS1 nFWP
Place closely pin 58 73 SIO_BIAPWM 2 1 BIA_PWM 12,19
BC_CLK GPIOA3/WINDMON @ R63 0_0402_5%~D
38 BC_CLK 87 BC_CLK
1=Flash Recovery Enabled
CLK_PCI_5004 BC_DAT 86 117 0=Flash Recovery Disabled
BC Bus
38 BC_DAT BC_DAT GPIO83/32KHZ_OUT

BC_INT 85
38 BC_INT BC_INT
49 RUNPW ROK
PWRGD RUNPWROK 38,42,49
1
R130 MEC5004_XTAL1 122 53 RESET_OUT#

XTAL1 nRESET_OUT/OUT6 RESET_OUT# 42
22_0402_5%~D MEC5004_XTAL2 2 1 124
B
R1785 0_0402_5%~D XTAL2 R122 1 +3.3V_SUS B
72 2
@
MEC5004_XOSEL TEST_PIN +3.3V_SUS

123
VCC_PLL
VSS_PLL
2
XOSEL
VR_CAP
0_0402_5%~D
1
AGND
1
VSS
VSS
VSS
VSS
VSS
0.1U_0402_16V4Z~D
R1606
1
C134 10K_0402_5%~D
1
22P_0402_50V8J~D MEC5004_VTQFP128~D R1579 1
1 125
26
51
74
88
113
22
101
104
2 +3.3V_ALW 10K_0402_5%~D R1753

@
C1739
10K_0402_5%~D
L106
2
BLM18AG121SN1D_0603~D C1768 L105 2
2
2 1 1 2 +3.3V_ALW R127 47_0402_5%~D U213
BLM18AG121SN1D_0603~D 1 2 SPI_CS_R# 1 8
0.1U_0402_16V4Z~D 23 SPI_CS# ICHI_FDATAOUT 1 S# VCC
2 2 Q HOLD# 7
R1788 3 6 FC LK
2
W# C
1
47_0402_5%~D 4 5 ICHO_FDATAIN
32 KHz Clock R138
100K_0402_5%~D
VSS D
M25P80-VMW6TP_SO8~D
Sam e as Laguna @
Flash ROM
Work Around
2
FW P#
low=write protected 150 MIL SO8
1
MEC5004_XTAL1 +3.3V_ALW
R139
100K_0402_5%~D
Y2
2
1
32.768K_12.5PF_Q13MC30610003~D
MEC5004_XTAL2 4 1 R112 @ R114 @
100K_0402_5%~D 10K_0402_5%~D @ U217
3 2 1 S# VCC 8
22P_0402_50V8J~D
22P_0402_50V8J~D
1 1 4.7U_0603_6.3V6M~D Flash write protect bottom 4K 2 7

2
Q HOLD#
C1450
1 2 of internal bootblock flash 3 W# C 6

C1449
C54 4 5
@ R110 @ VSS D
2 2 R117 @ 0_0402_5%~D M25P80-VMW6TP_SO8~D
3
E
10K_0402_5%~D B 1 2
A A LWON 1 2 1 2 2 Q19 A
PMST3906_SOT323-3~D 200 MIL SO8
1
D2002 @
C D
@ 1
1
RB751S40T1_SOD523-2~D 2 C1769
G 4.7U_0603_6.3V4Z~D
S
3
Q20 @ 2
2N7002W-7-F_SOT323~D
1
R101
2
100K_0402_5%~D
@
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EMC5004
LA-2791
5 4 3 2 1
5 4 3 2 1
Touch PAD
JTPAD +3.3V_RUN
1 1 2 2
34 COEX1_BT_ACTIVE 3 3 4 4
5 5 6 6
USB_HUBP4- 7 8 BT_RADIO_DIS#
38 USB_HUBP4- 7 8 BT_RADIO_DIS# 23
USB_HUBP4+ 9 10 COEX3 T31 PAD~D
38 USB_HUBP4+ 9 10
11 12 FAN
11 12 BT_ACTIVE 34,43
100P_0402_50V8J~D
COEX2_WLAN_ACTIVE 13 14 Part Number Description
34 COEX2_WLAN_ACTIVE 13 14
10K_0402_5%~D
15 16 SP_GND 1
15 16
C596
17 18 SP_X DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
31 USB_BIO- 17 18
33P_0402_50V8J~D
R6
19 20 SP_Y 1
D 31 USB_BIO+ 19 20 D
+3.3V_RUN 21 22 SP_V+
21 22 2
10K_0402_5%~D
1 23 24 C564 Speak
2
23 24
C570
25 26 TP_CLK @ 0.1U_0402_16V4Z~D Part Number Description
25 26 2
R518
LID_CL# 27 28 TP_DATA
39 LID_CL# 27 28
+3.3V_ALW 29 29 30 30 +5V_RUN PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
2
0.1U_0402_16V4Z~D
31 G1 G2 32
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1 1 1
2
JST_BM30B-SRDS-G-TFC~D C561 SM CARD BODY
C85
C63
C62
0.1U_0402_16V4Z~D Part Number Description
39 KSO[0..17]
KSO17 2 2 2 2
SP070007V0L S SOCKET TYCO 1770551-1
KSO16 10P H5.9 SMART
KSO15
KSO14
KSO13 PCMCIA BODY
KSO12 Part Number Description
KSO11
KSO10 DC000001Q0L PCMCIA TYCO
KSO9 1759096-1
KSO8
KSO7
KSO6 Bluetooth wire set cable
KSO5 Part Number Description
KSO4
KSO3 DC020004A0L H-CONN SET ZJX
KSO2 MB-B/T MODU
KSO1
KSO0
MDC wire set cable
39 KSI[0..7]
Part Number Description
KSI7
KSI6 DC020003Z0L H-CONN SET ZJX
C KSI5 C
MB-MDC
KSI4
KSI3
KSI2
KSI1 T/P wire set cable
KSI0 Part Number Description
DC020004T0L H-CONN SET ZJX

MB-TP
JKYBRD LVDS cable

1 1 Part Number Description
KSO10 2
KSO11 2 H-CONN SET ZJX
3 3 DC020003Y0L
KSO9 4 MB-LCD 14 WXGA+
KSO14 4
5 5
KSO13 6
KSO15 6 +5V_RUN RTC BATT
7 7
KSO16 8 Part Number Description
KSO12 8
9 9
KSO0 10 GC20323MX00 BATT CR2032 3V
10
4.7K_0402_5%~D
4.7K_0402_5%~D
KSO2 11 220MAH MAXELL
11
1
KSO1 12
KSO3 12
13 13
R515
R517
KSO8 14
KSO6 14
15 15
KSO7 16 35
2
KSO4 16 35 L1
17 17 36 36
KSO5 18 37 SP_GND BLM18AG601SN1D_0603~D
KSI0 18 37 SP_X TP_DATA DAT_TP_SIO
19 19 38 38 1 2 DAT_TP_SIO 39
KSI3 20 39 SP_V+
B KSI1 20 39 SP_Y TP_CLK CLK_TP_SIO B
21 21 40 40 1 2 CLK_TP_SIO 39
KSI5 22 L2
22
10P_0402_50V8J~D
10P_0402_50V8J~D
KSI2 23 BLM18AG601SN1D_0603~D
23
10P_0402_50V8J~D
10P_0402_50V8J~D
KSI4 24
KSI6 24
25 25 1 1 1 1
C562
C560
KSI7 26 26
C66
C73
POWER_SW# 27
18,39 POWER_SW# R_NUM_LED# 27
43 R_NUM_LED# 28 28
R_CAP_LED# 2 2 2 2
43 R_CAP_LED# 29 29
R_SCRL_LED# 30 41
43 R_SCRL_LED# 30 GND
KSO17 31 42
31 GND
+3.3V_RUN 32 32
33 33
34 34
FOX_GS12403-0001K-8F~D
Power Switch
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
100P_0402_50V8J~D
POWER_SW# 1 2
1 2
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ C1802
100P_0402_50V8J~D PWR_SW
2 @SHORT PADS~D
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
C34
C33
C32
C31
C30
C25
C45
C75
C74
C21
C20
C17
C16
C15
C14
C12
C11
C10
C39
C1789
C8
C7
C6
C5
C4
C3
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, INT KB
LA-2791
5 4 3 2 1
5 4 3 2 1
DC/DC Interface
+15V_SUS +3.3V_SRC +5V_SUS

Q23 +3VSUS Source +3.3V_ALW +15V_SUS
SI3456BDV-T1-E3_TSOP6~D +3.3V_SUS
+5V_ALW
1
D
6
S
R1759 5 4 R1293
1
10U_0805_10V4Z~D
100K_0402_5%~D 2 1 100K_0402_5%~D
1
2
5
6
C285
1 R222 R2148
D R1758 20K_0402_5%~D 10K_0402_5%~D D Q57 D
G
2
2
100K_0402_5%~D G SI3456BDV-T1-E3_TSOP6~D
3
SUS_ENABLE 2 2 MOD_EN 3
2
S
1
D +5VMOD +5V_RUN
4
0.1U_0603_50V4Z~D
SUS_ON_5V# 2 Q86 PJP22
1 G 2N7002W-7-F_SOT323~D
1A Rating 1 1 2
D
4.7U_0603_6.3V4Z~D
S 1
1
C1262
C1263
SUS_ON 2 Q85 2 @PAD-OPEN 4x4m
39,42,46 SUS_ON 38 MODC_EN#
G 2N7002W-7-F_SOT323~D R1295
S 2 100K_0402_5%~D
3
Q58 2
DDTC144EUA-7-F_SOT323~D
2
+5VMOD Source
+5V_ALW +15V_SUS
+5V_SUS +5VRUN Source

Q24
46 RUN_ENABLE
SI4800BDY-T1-E3_SO8~D +5V_RUN
1
8 1
R202 R223 7 2
1
100K_0402_5%~D 100K_0402_5%~D 6 3 1
5 R215
20K_0402_5%~D
HDD PWR
2
10U_0805_10V4Z~D
4
2
C283
RUN_ENABLE
2
1
D
4700P_0402_25V7K~D
C RUN_ON_5V# C
2
G +5V_SUS
S 1 +3.3V_ALW +15V_SUS
3
C284
Q22
2N7002W-7-F_SOT323~D
1 +1.8V_SUS Q3001 +1.8V_RUN
1
1
D 2 R1764 SI3456BDV-T1-E3_TSOP6~D
2 200K_0402_5%~D R507
19,37,39,42,46,47,48 RUN_ON
1
2
5
6
D
G 6 100K_0402_5%~D
S
S Q17 5 4 D Q50
3
2N7002W-7-F_SOT323~D 2 R2149 G SI3456BDV-T1-E3_TSOP6~D
2
10U_0805_10V4Z~D
1 10K_0402_5%~D HDD_EN_5V 3
1
1 S
1
R3011 +5VHDD +5V_RUN
4
C3033
20K_0402_5%~D PJP24
0.1U_0603_50V4Z~D
1 2
2
4.7U_0603_6.3V4Z~D
100K_0402_5%~D
38 HDDC_EN# 2 1 1 PAD-OPEN 4x4m
1
@ C547
C546
R504
@
Q51
DDTC144EUA-7-F_SOT323~D 2 2
3
1 +3.3V_SRC
2
C1788 +3.3V_RUN_R
470P_0402_50V7K~D Q3002
2 SI4800BDY-T1-E3_SO8~D
8 1 +5V_HDD Source
1
10U_0805_10V4Z~D
7 2 1
C3034
6 3 R3012
5 20K_0402_5%~D
B 2 B
4
2
Discharg Circuit
+3.3V_SRC
Q6 +3.3V_RUN
SI4800BDY-T1-E3_SO8~D +1.8V_SUS +5V_RUN +3.3V_RUN +1.5V_RUN +0.9V_DDR_VTT +2.5V_RUN
8 1
7 2
1
1
30_0603_5%
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
1K_0402_5%~D
6 3 1
10U_0805_10V4Z~D
R1795
R1793
R1794
R1796
R1797
R1798
5 R1757
C1782
20K_0402_5%~D
4
2 @ @ @ @ @
2
2
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
2N7002W-7-F_SOT323~D
1
1
D D D D D D
SUS_ON_5V# 2 RUN_ON_5V# 2 2 2 2 2
Q89
Q87
Q88
Q90
Q91
Q92
G G G G G G
+PWR_SRC +PWR_SRC S S S S S S
3
3
@ @ @ @ @
1
R1615
1
100K_0402_5%~D
R1614
100K_0402_5%~D
2
ENAB_3VLAN 28
2
D
2N7002W-7-F_SOT323~D
A A
Q83
N21917830 2 R1617
2N7002W-7-F_SOT323~D
200K_0402_5%~D
G 470K_0402_5%~D
1
D
S
3
Q82
R1616
2
39,46 VAUX_EN
2
G
S
3

2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
LA-2791
5 4 3 2 1
5 4 3 2 1
For EMI
+3.3V_RUN_R +3.3V_SRC +3.3V_RUN_R +SDC_IN +3.3V_SRC +SDC_IN
@ C1806 @ C1810 @ C1814
1 2 1 2 1 2
0.047U_0402_16V4Z~D 0.047U_0402_25V4Z~D 0.047U_0402_25V4Z~D
+1.5V_RUN +3.3V_SRC +5V_SUS +SDC_IN +3.3V_SRC +1.8V_SUS

D @ C1807 @ C1811 @ C1815 D
1 2 1 2 1 2
0.047U_0402_16V4Z~D 0.047U_0402_25V4Z~D 0.047U_0402_25V4Z~D
+1.8V_SUS +3.3V_SRC +3.3V_SRC +SDC_IN +3.3V_RUN

@ C1808 @ C1812 +3.3V_SUS C483
1 2 1 2 0.1U_0402_16V4Z~D
1
1 2
0.047U_0402_16V4Z~D 0.047U_0402_25V4Z~D R494
20K_0402_5%~D +3.3V_SUS
+3.3V_RUN +3.3V_SRC +3.3V_SRC +1.5V_RUN
@ C1809 @ C1813
8
1 2 1 2 U24A U24B
P
0.047U_0402_16V4Z~D 0.047U_0402_16V4Z~D 3VRUNRC 1 7 6 2 +3.3V_SUS C480
A Y A Y 0.1U_0402_16V4Z~D
1
G
1 2
C520 74LVC3G14DC_VSSOP8~D 74LVC3G14DC_VSSOP8~D
4
1
1
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0_0402_5%~D
0.01U_0402_16V7K~D
2
R49
R313
R319
R334
14
U26A
1 74VHC08MTCX_NL_TSSOP14~D
P
IN1
3
2
OUT
2 IN2
G
18 2.5V_RUN_PWRGD +3.3V_SUS
14
47 1.5V_RUN_PWRGD
U26D
13
P
47 1.05V_RUN_PWRGD IN1
11 RUNPWROK RUNPWROK 38,39,49
OUT
48 0.9V_DDR_PWRGD 19,37,39,41,46,47,48 RUN_ON 12 IN2
G
C C
74VHC08MTCX_NL_TSSOP14~D
7
+3.3V_ALW 39,41,46 SUS_ON
48 SUSPWROK_1P8V
1
+3.3V_SUS +3.3V_SUS
R1383
1
100K_0402_5%~D
14
U26C
8
R1386 U24C 10
P
2
10K_0402_5%~D IN1
8
P
OUT SUSPWROK 18,23
3 5 9
2
A Y IN2
G
1
G
D 74VHC08MTCX_NL_TSSOP14~D
7
2 Q7 74LVC3G14DC_VSSOP8~D
4
1 G 2N7002W-7-F_SOT323~D
S
3
C1816
0.1U_0402_16V4Z~D
2
+3.3V_SUS
14
U26B R463
IMVP_PWRGD 4 0_0402_5%~D
P
B
23,49 IMVP_PWRGD IN1 B
OUT 6 1 2 ICH_PWRGD 10,23
RESET_OUT# 5
39 RESET_OUT# IN2
G
74VHC08MTCX_NL_TSSOP14~D +COINCELL
COIN RTC Battery
7
1
R471
+3.3V_SUS 1K_0402_5%~D
+3.3VX
2
1
R453 JCOIN
Z4012
100K_0402_5%~D +COINCELL COINCELL 1
1
2 2
2
ICH_PWRGD# ICH_PWRGD# 18 MOLEX_53398-0271~D

2
3
+RTC_CELL
1
D
ICH_PWRGD 2 Q41 D15
G 2N7002W-7-F_SOT323~D BAT54CW_SOT323~D
S
3
1
C528
1U_0603_10V4Z~D
2
A A
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Good
LA-2791
5 4 3 2 1
5 4 3 2 1
H29 H30
Fiducial Mark
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 @H_O115X31D115X31N @H_O115X31D115X31N
H_T146B217D91 H_T146B217D91 @H_C315D110 H_T256B63D47 @H_C315D110 @H_C236B256D110 @H_C315D110 @H_T217B315D98 @H_C315D110 @H_C315D110
FD3
FD1 FD2 FD4 FD5 FD6
1
1 1 1 1 1 1
1
1
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
FD7 FD8 FD9 FD10 FD11 FD12

1 1 1 1 1 1
H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
@H_T315B237D118 @H_C315D118 @H_C315D118 @H_T315B237D118 @H_C315D118 @H_T217B315D98 @H_T217B315D98 @H_C217D91 @H_C217D91 @H_T217B315D98 R231 FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
330_0402_5%~D
2 1 R_CAP_LED# R_CAP_LED# 40
39 CAP_LED#
FD13 FD14 FD15 FD16 FD17 FD18
1
1
D
1 1 1 1 1 1 D
R237
330_0402_5%~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
2 1 R_NUM_LED# R_NUM_LED# 40
39 NUM_LED#
H31 H32 H26 H27 H28 FD19
@H_C24D24N @H_C24D24N @H_C472D376 @H_C472D431X376 @H_O115X31D115X31N R21 1
330_0402_5%~D
2 1 R_SCRL_LED# R_SCRL_LED# 40 FIDUCIAL MARK~D
39 SCRL_LED#
1
1
Disable HDD LED
+3.3V_RUN_R +3.3V_RUN_R +5V_RUN
1
R1448
R76 @ 0_0402_5%~D
EMI CLIP
3
10K_0402_5%~D 1 2
3
2
2
S
SATA_ACT# 3 1 SATA_ACT#_R 2 CLIP1 @ CLIP2 @

22 SATA_ACT#
EMI_CLIP EMI_CLIP
Q66 Q1 DDTA114EUA-7-F_SOT323~D
+3.3V_ALW BSS138W-7-F_SOT323~D DDTA114EUA-7-F_SOT323~D Q18
G
1 1
2
GND GND
1
R1434 R8
1
1
1
R2 10K_0402_5%~D D 1K_0402_5%~D CLIP4 @ CLIP3 @
R1445 1 2 R_SATA_ACT 32 BT_ACTIVE 1 2 2 1 2 R_BT_ACT R_BT_ACT 32 EMI_CLIP EMI_CLIP
34,40 BT_ACTIVE
10K_0402_5%~D G Q4
@ 330_0402_5%~D S BSS138W-7-F_SOT323~D 1 1
3
GND GND
2
C 39 SNIFFER_LED_OFF# C
CLIP5 @ CLIP6 @
R_PIDEACT 36
3
E
EMI_CLIP EMI_CLIP
B
39 SNIFFER_LED_OFF# 2 Q65
PMST3906_SOT323-3~D 1 1
C GND GND
1
+3.3V_SUS
R3
1
10K_0402_5%~D C
39 BREATH_LED 1 2 BREATH_LED_B 2 Q3
B MMST3904-7-F_SOT323~D
E
3
+3.3V_RUN_R R1
1 2 BREATH_GREEN_LED BREATH_GREEN_LED 32
56_0402_5%~D
B 34 LED_WLAN_OUT# 2 3 +3.3V_ALW
B
Q5
+3.3V_SUS DDTA114EUA-7-F_SOT323~D
3
1
R15
3
1 2 R_MPCI_ACT R_MPCI_ACT 32 BAT1_LED# 2

39 BAT1_LED#
100_0402_5%~D Q2
SNIFFER_YELLOW# 2 DDTA114EUA-7-F_SOT323~D
18 SNIFFER_YELLOW# +3.3V_ALW
1
R5
1 2 BATT_GREEN_LED BATT_GREEN_LED 32
1
Q16 220_0402_5%~D
1
DDTA114EUA-7-F_SOT323~D R56 +3.3V_ALW

10K_0402_5%~D
2
3
JSNIFF
38 SNIFFER_WIRELESS_ON/OFF# SNIFFER_WIRELESS_ON/OFF# 4 4
3 BAT2_LED# 2
3 39 BAT2_LED#
2 Q35
+3.3V_SUS 2 DDTA114EUA-7-F_SOT323~D
39 SNIFFER# SN IFFER# 1 1
1
1BS008-13130-002-7F_4P~D
3
R265
1 2 BATT_AMBER_LED BATT_AMBER_LED 32
330_0402_5%~D
SNIFFER_GREEN# 2
18 SNIFFER_GREEN#
Q13 D4
A DDTA114EUA-7-F_SOT323~D 1 2 SNIFFE R_Y 3 Y A
1
R20 220_0402_5%~D 1
1 2 SNIFFER_G 2
R19 220_0402_5%~D G
12-22AUYSYGC/530-A2/TR8_G/Y~D
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, PAD and Standoff
LA-2791
5 4 3 2 1
5 4 3 2 1
D D
+5V_ALW
+3.3V_ALW
DA204U_SOT323~D
2
PD2
2
2.2K_0402_5%~D
PR2
@ PR346
1 2
0_0402_5%~D
1
PR184 +PWR_SRC
33_0402_5%~D +3.3VX Source +3.3VX
PS_ID_IN
S
1 3 1 2 PS_ID 39
36 PS_ID_IN
PQ1 +5V_ALW PU1
+5V_ALW 1
G
2
IN
100K_0402_1%~D
DA204U_SOT323~D
FDV301N_SOT23~D 5
OUT
2
PR6
10K_0402_1%~D
1
2
PD41
3 EN
PR7
1U_0805_25V4Z~D
4
GND
NC 1
2
@
1
1
PC1
PD53 @ PC7
SM24_SOT23 MIC5235-3.3BM5_SOT23-5~D 2.2U_0603_6.3V6K~D
2
2
2
@ PR299
1
1 2
PS_ID_DISABLE# 39
100_0402_5%~D
1
C
C 2 PQ2 C
B MMST3904-7-F_SOT323~D
15K_0402_1%~D
E
3
2
PR10
36 DOCK_DC_IN
DC_IN+ Source
PL1
FBM-L11-160808-601LMT 0603~D PQ3 +DC_IN
2 1 PS_ID_IN FDS6679Z_SO8~D
Z-series AC Adaptor 1
2
8
7
Connctor PWR_ID
PL2 3 6
FBMA-L18-453215-900LMA90T_1812~D 5
1 2 DOC K_DC_IN
150K_0402_1%~D
PJPDC1
1
0.47U_0805_25V7k
TYCO_1566065-2~D
2
1000P_0402_50V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
4.7K_0603_5%~D
10U_1206_25V6M~D
1
4
Low_PWR
1
PR11
PC2
B
9 GND_4 1 B
PR12
2
1
DC+_1
PC3
PC4
PC5
PC6
8
2
2
GND_3 +ADP_DCIN
DC+_2 3
2
2
7 4 @
GND_2 DC-_1 100K_0402_1%~D
6 GND_1 DC-_2 5 1
MH1
MH2
PR13
PL34
2
FBMA-L18-453215-900LMA90T_1812~D
1 2
THESE CAPS MUST BE

NEXT TO JCHG
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.6
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-2792
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
ESD Diodes
2
+3.3V_ALW
D D
Secondary Battery Connector PD42 PD43 PD44 PD45
10K_0402_5%~D
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D PL32 9
1
FBMA-L18-453215-900LMA90T_1812~D
PR300
1 2 8
SBATT+
0.1U_0603_25V7K~D
1
PC230
PJP1 7
1 PR301
2
BATT1+
2200P_0402_50V7K~D
2 100_0402_5%~D PR302 6
2
BATT2+ Z4301 100_0402_5%~D PR303
SMB_CLK 3 1 2 SBAT_SMBCLK 19,39
4 Z4302 1 2 100_0402_5%~D 5
SMB_DAT SBAT_SMBDAT 19,39
1
PC231
5 Z4303 1 2 PR304
BATT_PRES# SBAT_PRES# 38,51 4
6 100_0402_5%~D
SYSPRES#
7 1 2 SBAT_ALARM# 38
2
BATT_VOLT 3
10 GND BATT1- 8
11 GND BATT2- 9
2
TYCO_1734077-1~D
1
+3.3V_ALW
SUYIN_20175A-09G1
ESD Diodes TOP view
2
C +3.3V_ALW C
Primary Battery Connector PD9 PD10 PD11 PD12
1
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D PL6
1
10K_0402_1%~D
FBMA-L18-453215-900LMA90T_1812~D
1 2 PBATT+
0.1U_0603_25V7K~D
PR19
1
PBATT1
PC9
1 PR20
2
BATT1+ 100_0402_5%~D PR21
2
2
BATT2+
2200P_0402_50V7K~D
3 Z4304 1 2 100_0402_5%~D PR22

SMB_CLK PBAT_SMBCLK 39,50
4 Z4305 1 2 100_0402_5%~D
SMB_DAT PBAT_SMBDAT 39,50
5 Z4306 1 2 PR23
BATT_PRES# PBAT_PRES# 38
1
PC10
6 100_0402_5%~D
SYSPRES#
BATT_VOLT 7 1 2 PBAT_ALARM# 38
10 8
2
GND BATT1-
11 GND BATT2- 9
SUYIN_200277MR009G506ZR~D
B B
A A
Title
Battery Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.6
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2792
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Tuesday, February 07, 2006 Sheet 45 of 63
5 4 3 2 1
5 4 3 2 1
PJP25
1 2
PAD-OPEN 4x4m
DC/DC +3V/ +5V/ +15V
Place these CAPs +15V_SUSP
+DC1_PWR_SRC PR203
PL22 close to FETs 100_0805_5%~D
FBM-L11-453215-900LMAT_1812~D +15VS_L 1 2
+PWR_SRC 1 2
MMBZ5245B_SOT23~D
2.2U_1206_25V7M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0_1206_5%~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
2.2U_1206_25V7M~D
2
1
EC11FS2_SOD106~D
1 1 1 1
1
PR27
PC15
PD35
100U_25V_M
PC156
1
1
PC16
PC17
PC252
PC268
+
2
PC18
PC19
PD13
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
+VCC_MAX1999 +5V_ALW
2
D 2 2 @ 2 D
2
2 PR28
3
1
1
47_0603_5%~D
PC25
PC26
2 1
4.7U_1206_25V6K~D
0.1U_0603_25V7K~D
1U_0603_10V6K~D
2
1U_0603_10V6K~D
4.7U_1206_25V6K~D
+15VS
1
PC23
RB717F_SOT323~D
1
PC22
Place these CAPs
PC20
PC21
PC24
close to FETs
5
6
7
8
Typical:4A Typical:5A
PD14
PQ78
8
7
6
5
@ SI4800BDY-T1_SO8~D
Peak current:8A PQ77 Peak current:7A
2
SI4800BDY-T1_SO8~D
OCP point is from 8.2A to 10.5A 4
OCP point is from 8A to 11.2A
4 PU3 PL8
4.7U_STQB125A-4722_8A_30%~D
20 18 PR29 PC27 +5V_SUSP
3
2
1
3
+3.3V_SRCP V+ LDO5 0_0603_5%~D 0.1U_0603_25V7K~D
PL9 17 14 1 2 1 2
1
2
3
VCC BST5
5
6
7
8
4.7U_SPC-1205P-4R7B_+40-20%~D
1 2 PC28 PR32 6 16
SHDN DH5
0.1U_0402_10V7K~D
330U_D3L_6.3V_R25~D
0.1U_0603_25V7K~D 2.2_0603_5%~D
330U_D3L_6.3V_R25~D
330U_D3L_6.3V_R25~D
0.1U_0402_10V7K~D
330U_D3L_6.3V_R25~D
2 1 1 2 28 BST3 LX5 15 1 1
1
8
7
6
5
1 1 @ PQ6
1
PC30
PR344 26 19 4 SI4810BDY_SO8~D + +
DH3 DL5
1
PC32
PC29
PC245
+ + 0_0402_5%~D
PC31
PC244
27 21
2
LX3 OUT5 2 2
PQ5 1
2
2 2 SI4810BDY_SO8~D N.C. @
4 24 9
3
2
1
DL3 FB5
1
@ 10
PRO
22 OUT3
1
ILIM5 11
7 5 @
1
2
3
FB3 ILIM3
1
8 PR353
2
@ PR345 REF 0_0402_5%~D
3 ON3 TON 13
C NC_TEST1 PR355 0_0402_5%~D 4 23 C
2
0_0603_5%~D ON5 GND

2
SKIP
PGOOD
25
2
LDO3
1
MAX8734AEEI_QSOP28~D MAX8734_REF
12
MAX8734_REF PR354
1U_0603_10V6K~D
0_0402_5%~D
45.3K_0402_1%~D
@
1
PC33
+3.3V_ALW +VCC_MAX1999 PR356
2
2
12.7K_0402_1%~D
0_0603_5%~D
2
+3.3VX
PR37
NC_TEST2
PR38
4.7U_1206_10V7K~D
100K_0402_1%~D
PC251
0.1U_0603_25V7K~D
1
PC34
2 1
PR347
PR46
1
0_0402_5%~D
2
PU17
5
TC7SH32FU_SSOP5~D PR41 @
2
2 2K_0402_1%~D
P
39,41,42 SUS_ON I0 +3.3V_SRCP

O 4 39,41,42 SUS_ON 1 2
100K_0402_1%~D
39,41 VAUX_EN 1 I1
G
1000P_0402_50V7K~D
2
240K_0402_5%~D
0_0402_5%~D
3
2
PR42
1
1
D
PR47
453K_0402_1%~D
243K_0402_1%~D
PR349
@ PR343 2 THERM_STP# 18
PC36
PR44
PR188
0_0402_5%~D G
2
1
2 1 S @ PQ80
1
3
RHU002N06_SOT323
SUSPWROK_5V 48
MAX1999_SKIP#
@
+3.3V_SRC
PQ82
FDC655BN_NL_SSOT-6~D PR48
4
PR49 @ 0_0402_5%~D
B S B
3 RUN_ENABLE 41 1K_0402_1%~D 2 1 +VCC_MAX1999
G 39 ALWON 1 2
D PR50
@ 0_0402_5%~D
2 1 RUN_ON 19,37,39,41,42,47,48
6
5
2
1
0_0402_5%~D
1
18 THERM_STP#
PR51
+3.3V_ALW
PJP4
+15V_SUSP 1 2 +15V_SUS
PAD-OPEN 4x4m
PJP5
1 2 +5V_SUS
+5V_SUSP
PAD-OPEN 4x4m
PJP6
+3.3V_SRCP 1 2 +3.3V_SRC
PAD-OPEN 4x4m
A A
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +3.3V/+5V/+15V
5 4 3 2 1
A B C D
+1.5VRUNP / +VCCP_1P05VP
+PWR_SRC +DC2_PWR_SRC
PL25
1
FBM-L11-453215-900LMAT_1812~D 1
1 2
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1 1 1 1
1
PC161
PC164
+5V_SUS
PC159
PC160
PC262
PC162
PC163
PC263
2
2
2 2 2 2
RB751V_SOD323~D
1U_0603_10V6K~D
RB751V_SOD323~D
2
2
PR216
PD36
PC205
PD37
10_0805_5%~D
2.2U_0805_10V6K~D
FDS8880_SO8~D
0.01U_0402_25V7K~D
2
5
6
7
8
1
1
PC165
PQ38
PC261
FDS8880_SO8~D
4 Typical:8A
2
8
7
6
5
0.1U_0603_25V7K~D
Peak current:10A
0.1U_0603_25V7K~D
PQ8
Max current:5A OCP=14.23~18.39A
3
2
1
PU9
2
OCP=7.08~11.96A 4 28 VCC DDR 13
PC166
2 PR278 14 2
VIN
2
PC167
0_0603_5%~D PR277
1
+1.5V_RUNP 2 1 23 6 2 1 +VCCP_1P05VP
BOOT2 BOOT1
1
2
3
ISL6227CA-T
1
PL26 24 5 0_0603_5%~D PL27
3.8uH_SIL104-3R8_6A_30%~D UGATE2 UGATE1 1.5uH_SIL104-1R5_10A_30%~D
1 2 +1.5VRUNP_L 25 4 +VCCP_1P05VP_L 1 2
PHASE2 PHASE1
0.01U_0402_25V7K~D
330U_D2E_2.5VM_R9~D
PR219 27 2 PR220
LGATE2 LGATE1
330U_D2E_2.5VM_R9~D
0.01U_0402_25V7K~D
10U_0805_6.3V5K~D
1.43K_0402_1%~D 2.1K_0402_1%~D 1
8
7
6
5
10U_0805_6.3V5K~D
19.6K_0402_1%~D
FDS6670AS_SO8~D
1 1 2 22 ISEN2 ISEN1 7 1 2
1
1
5.11K_0402_1%~D
PC206
+
1
1
PC168
PR221
PC170
PR222
PC207
+ 26 3
PGND2 PGND1
PQ83
PC208
PC169
19 10
2
VSEN2 VSEN1 2
20 9
2
2 VOUT2 VOUT1 @
4
2
2
@ 21 8
EN2 EN1
1 PR223 2 18 OCSET2 OCSET1 11 1 PR224 2
100P_0402_50V8K
124K_0402_1% 124K_0402_1%
1
2
3
1
1 2 17 SOFT2 SOFT1 12 1 2
100P_0402_50V8K
30.1K_0603_1%~D
PC264
PR225
1
1
28.7K_0603_1%~D PC172 16 15 PC173
PG2/REF PG1
5
6
7
8
FDS6670AS_SO8~D
PR226
0.01U_0402_25V7K~D 0.01U_0402_25V7K~D
2
1
PC265
@ 1
2
GND
PQ40
ISL6227CA-T_SSOP28~D
2
PR279 @
2
4
1
0_0402_5%~D PR280
0_0402_5%~D
3 3
3
2
1
1
0_0402_5%~D
2
1
PR281
PR227 PR272
1K_0402_1%~D 1K_0402_1%~D
1
@
@ PC210
1
1000P_0402_50V7K~D
1000P_0402_50V7K~D
2
2
1
RUN_ON 19,37,39,41,42,46,48
PC211
@ PR282
0_0402_5%~D
2
@
1
19,37,39,41,42,46,48 RUN_ON
PJP19
1 2
PAD-OPEN 4x4m
42 1.5V_RUN_PWRGD 1.05V_RUN_PWRGD 42
PJP23
+1.5V_RUNP 1 2 +1.5V_RUN
PAD-OPEN 4x4m
PJP21
4 +VCCP_1P05VP 1 2 +1.05V_VCCP 4
PAD-OPEN 4x4m
PJP20
1 2
PAD-OPEN 4x4m
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5VSUSP /+VCCP_1P05VP
A B C D
5 4 3 2 1
D +1.8VSUSP/ +0.9V_DDR_VTT D
DDR2 Termination
+DDR_PWR_SRC
PL24
PR193, PD20 are only used with the second-source MAX8632.
FBM-L11-453215-900LMAT_1812~D
+PWR_SRC 1 2
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
PJP32
10U_1206_25V6M~D
10U_1206_25V6M~D
PAD-OPEN 4x4m
1 2 1 1 +5V_SUS
1
@ PR193
PC55
PC56
PC57
PC58
2 1 +3.3V_SUS +3.3V_RUN
10_1206_5%~D
2
2 2
1U_0603_10V6K~D
RB751V-40_SOD323~D
4.7U_1206_10V7K~D
1
1
PC62
PC63
2
PD20
100K_0402_1%~D
2
2
100K_0402_1%~D
2
PR194
88550_AVDD
PR195
1
1
@ @
1
1
PR213
0_0402_5%~D
IRF7821_SO8~D
Design current 8A for +1.8V_SUSP
2
8
7
6
5
22
28
26
2
PQ34 PU6
Peak current 10.1A for +1.8VSUSP
D
D
D
D
PC68
OVP/ UVP
TP0
VDD
AVDD
0.22U_0603_10V7K~D PR73
C
OCP point is 12.7A for +1.8VSUSP 1 2 2 1 20
VIN 17
C
BST
G
S
S
S
1_0603_5%~D 5
+1.8V_SUSP POK1 SUSPWROK_1P8V 42
1
2
3
4
3
18 DH POK2 6 0.9V_DDR_PWRGD 42
1 2 +1.8VSUSP_L 27
SHDN SUSPWROK_5V 46
19 PR212
PL14 LX 0_0402_5%~D
8
7
6
5
1.4UH_HMU1350-1R4PF_15A_20%~D 7 2 1
STBY RUN_ON 19,37,39,41,42,46,47
IRF7832_SO8~D
21 DL
330U_D2E_2.5VM~D
330U_D2E_2.5VM~D
0.1U_0402_10V7K~D
PQ11
13 +1.8V_SUSP
VTTI PR204
1 1 23 PGND1
4 ISL88550A_TQFN28~D 20_0603_1%~D 1
1
PC70
PC71
PC72
+ + 14 2 1 +1.8V_SUSP
REFIN PC146
16 VOUT
1
PC77 10U_0805_6.3V6M~D
2
2 2 0.1U_0402_10V7K~D 2
11
1
2
3
PGND2
15
2
PR84 FB
@ 0_0402_5%~D 12 +0.9V_DDR_VTTP
VTT
2 1 1 TON
0.1U_0402_10V7K~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
VTTS 9
1 1 1
PC153
PC154
PC157
3 REF VTTR 10 Design current 1.05A for +0.9V_DDR_VTTP
PC74
100K_0402_1%~D
Peak current 1.5A for +0.9V_DDR_VTTP
SKIP
GND
GND
2
ILIM
2
2 2 2
SS
PR200
25
24
29
PR348
0_0402_5%~D
1
1
1 2 88550_AVDD
1
PC155
V_DDR_MCH_REF 10,16,17
0.22U_0402_6.3V 5K~D PC66
2
1000P_0402_50V7K~D
2
1
PR202
B B
48.7K_0402_1%~D
1
PC64
2
1U_0603_10V6K~D
PJP9
PAD-OPEN 4x4m
1 2
PJP10
PAD-OPEN 4x4m
+1.8V_SUSP 1 2 +1.8V_SUS
A A
PJP11
+0.9V_DDR_VTTP 1 2 +0.9V_DDR_VTT
PAD-OPEN 4x4m
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT +1.8VSUSP/ +0.9V_DDR_VT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.6
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2792
5 4 3 2 1
8 7 6 5 4 3 2 1
+CPU_PWR_SRC PL28
FBMA-L18-453215-900LMA90T_1812~D
1 2 +PWR_SRC
PJP30
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
4.7U_1206_25V6K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
H H
1 2
1 1
1
PC249
PC223
PC176
PC270
PAD-OPEN 4x4m
PC224
PC175
PJP31
2
2 @ 2
1 2
8
7
6
5
+CPU_PWR_SRC
IRF7821_SO8~D
PAD-OPEN 4x4m
D
D
D
D
PQ42
+5V_RUN
G
S
S
S
1U_0603_10V6K~D
PR228
1
2
3
4
1
PC178
10_0603_5%~D
0.01U_0402_25V7K~D
PR229 PC179
2
PU10 0_0603_5%~D 0.22U_0603_10V7K~D
G 5 1 2 1 1 2 G
VCC BOOT PL29
6 8 0.45UH_MPC1040LR45_27A_20%~D
FCCM UGATE
1
PC180
2 7 PHASE1 4 1 +VCC_CORE
PWM PHASE
3 4 3 2
2
GND LGATE
3
FDS7088SN3_SO8~D
ISL6208CRZ-T_QFN8~D
2
+5V_RUN
1500P_0805_50V7K
PQ56
1
PR232
+3.3V_RUN
1U_0603_10V6K~D 10_0603_5%~D
PC246
GNDA_VCORE 10_0402_1%~D
2
2 PR230 PC181
2
G 10K_0402_1%~D 0.22U_0603_10V7K~D
1
PR233
@ 1 2 2 1
2
1
1
PR231
2
7.68K_0805_1%~D
1
F PR234 F
PC182
1.91K_0603_1%~D VO
1
VSUM
2
1
IMVP_PWRGD 23,42
1
+CPU_PWR_SRC
0_0603_5%~D
PR290
GNDA_VCORE +5V_RUN
19
20
18
39
40
2
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
4.7U_1206_25V6K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
VSS
3V3
VDD
VIN
PGOOD
8
7
6
5
IRF7821_SO8~D
1 1
1
1U_0603_10V6K~D
PC239
PC194
PC177
PC271
D
D
D
D
38 IMVP6_PROCHOT#
PQ57
PC240
4 VR_TT#
PC241
2
2 2
2 PR238 1 3 RBIAS PWM1 27 @
G
S
S
S
@ 147K_0402_1%~D @ PH1
2
E E
2 PR284 1 2 1 5
1
2
3
4
0_0402_5%~D NTC PR328 PC242
2 1 470KB_0402_5%_NCP15WM474J03RB~D 6 PU11 23 PU16 0_0603_5%~D 0.22U_0603_10V7K~D
PC187 SOFT ISEN1
5 VCC BOOT 1 2 1 1 2
GNDA_VCORE 0.01U_0402_16V7K~D ISL6260CRZ-T_QFN40~D
8 VID0 2 PR239 1 28 VID0 6 FCCM UGATE 8 PL33
8 VID1 2 PR240 1 0_0402_5%~D 29 VID1
0.45UH_MPC1040LR45_27A_20%~D
0_0402_5%~D 2 PR241 1 30 26 2 7 PHASE2 4 1 +VCC_CORE
8 VID2 VID2 PWM2 PWM PHASE
8 VID3 2 PR242 1 0_0402_5%~D 31 VID3
0_0402_5%~D 2 PR243 1 32 3 4 3 2
8 VID4 VID4 GND LGATE
3
FDS7088SN3_SO8~D
8 VID5 2 PR244 1 0_0402_5%~D 33 VID5
0_0402_5%~D 2 PR245 1 34 22 ISL6208CRZ-T_QFN8~D
D
8 VID6 VID6 ISEN2
1500P_0805_50V7K
0_0402_5%~D
PQ60
2
7,22 H_DPRSTP# 37 DPRSTP#
PC247
PR248 PR329
23 DPRSLPVR 2 1 36 2 10_0402_1%~D
2
499_0402_1%~D DPRSLPVR G PR330 PC243
8 H_PSI# 2 @ PR2491 1 @ 10K_0402_1%~D 0.22U_0603_10V7K~D
1
PSI#
S
D 0_0402_5%~D 1 2 2 1 D
38,39,42 RUNPWROK 2 PR252 1 2 24
1
PGD_IN FCCM
2
2 PR372 1 0_0402_5%~D
0_0402_5%~D 2 PR253 1 38 PR331
6 CLK_ENABLE# 0_0402_5%~D CLK_EN# 7.68K_0805_1%~D
2 PR254 1 35 VO
38,39,42 RUNPWROK VR_ON
0_0402_5%~D
1
12 25 VSUM
8 VCCSENSE VSEN PWM3
GNDA_VCORE 13 RTN
PC213 21 +CPU_PWR_SRC
ISEN3
2 1 11 VDIFF
PC214 +5V_RUN
1000P_0402_50V7K~D 2 1
4.7U_1206_25V6K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0603_25V7K~D
2200P_0402_50V7K~D
10 PR260
1000P_0402_50V7K~D FB 11.5K_0402_1%~D
OCSET 7 2 1 1 1
8
7
6
5
1
IRF7821_SO8~D
PC272
PC193
PC227
GNDA_VCORE 9
8 VSSSENSE COMP
1U_0603_10V6K~D
PC192
PC228
C C
D
D
D
D
PQ50
17 VSUM
2
VSUM
1
2 2
0.068U_0402_10V7K~D
2.43K_0402_1%~D
PC196
PR257 8 @
VW
1
2 1 1 2 PR258 2 PR287 1
G
S
S
S
PR261
DROOP
332_0402_1%~D 2 1 0_0603_5%~D 41 PR262 PC198

2
GND
4.53K_0402_1%~D
PC215
PC190 2.21K_0402_1%~D PU13 0_0603_5%~D 0.22U_0603_10V7K~D

DFB
1
2
3
4
1
680P_0402_50V7K~D
VO
2 5 VCC BOOT 1 2 1 1 2
0.33U_0603_10V7K
2
2
PR263
1 2 2 PR259 1 6 8 PL31
14
15
16
FCCM UGATE
PC191
PC195 PC250 82.5K_0402_1%~D 0.45UH_MPC1040LR45_27A_20%~D

220P_0402_50V8J~D 1500P_0402_50V7K~D 1 PHASE3
2 7 1 4 +VCC_CORE
2
1 PWM PHASE
1 2
0.01U_0402_16V7K~D
6.8KB_0603_5%_ERTJ1VR682J~D
3 GND LGATE 4 2 3
3
FDS7088SN3_SO8~D
1500P_0805_50V7K
PC229
PC197 VO
1
2 1 ISL6208CRZ-T_QFN8~D
PC248
PQ61
2
1000P_0402_50V7K~D 1
2
GNDA_VCORE PR271
2 1 2 @ 10_0402_1%~D
G
1
B B
15K_0402_1%~D
PR267 PR268 PR269 PC200

PR264 10.5K_0402_1% 1K_0402_1%~D 2 10K_0402_1%~D 0.22U_0603_10V7K~D
1
S
PH2
PR266
6.34K_0402_1%~D 2 1 2 1 1 2 2 1
2
2
PR270
PC201 7.68K_0805_1%~D
2 1
VO
1
330P_0402_50V7K~D VSUM
0.1U_0603_25V7K~D
2
PC260
1
A A
Title
GNDA_VCORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCORE
8 7 6 5 4 3 2 1
5 4 3 2 1
+DC_IN discharge path
PR138 +SDC_IN
0.01_2512_1%~D PL19 CHAGER_SRC
FBMA-L18-453215-900LMA90T_1812~D
+DC_IN 1 4 1 2
10U_1206_25V6M~D
0.1U_0603_25V7K~D
2 3
2200P_0402_50V7K~D
D D
1
1
PC127
PC128
PC99
2
2
2
@
2
PR337
PR142 0_0402_5%~D
150K_0402_1%~D
1
1
2
PR336
LDO 0_0402_5%~D
10K_0402_1%~D
PC202
1
1
1U_0603_10V6K~D
1
PR342
28
27
1 2
1
PR149
806K_0402_1%~D PC102 PU8

1U_0805_25V4Z~D
CSSP
GND
CSSN
2
PR143 2 1 22 26
2
20K_0402_1%~D DCIN VCC PR275 PR274

2
RB751V_SOD323~D
2 1 2 0_0603_5%~D 33_0603_1%~D
PR146 ACIN
BST 25 1 2
15.8K_0402_1%~D
PC110 1 2 13
1
18,39,51 ACAV_IN ACOK
1
0.1U_0603_25V7K~D
0_0402_5%~D
1
1
C C
2 1 11 VDD
PR341
PC203
PD40
SI4800BDY-T1_SO8~D
5
6
7
8
0.01U_0402_25V7K~D 10 PC204
2
SCL
5
6
7
8
IRF7821_SO8~D
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1U_0603_10V6K~D @
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
9 21 LDO 1 2
D
D
D
D
2
+5V_ALW SDA LDO +5V_ALW
PQ75
PQ79
1 1 1
1
PC103
PC104
39 BAT_SEL# 1 PR335 2 14 BATSEL
PC105
PC106
PC273
Vin Detector 24 PR360 4
DHI
G
S
S
S
1SS355_SOD323~D
0_0402_5%~D MAX8731_IINP 8 1_0603_1%~D
2
IINP
1
High 17.9 V 23 2 1
2 2 @ 2
4
3
2
1
LX
2
PC221 6
Low 17.24 V CCV 1
3300PF_0402_50V7K~D
0.1U_0402_10V7K~D
2
3
2
1
4.7K_0402_5%~D
PD54
5 PC253
CCI
1
220P_0402_50V7K~D PL20
2
0.01U_0402_25V7K~D
PR148
4 20 5.6U_HMU1356-5R6_8.8A_20%~D
1
CCS DLO
1
+VCHGR
0.01U_0402_25V7K~D
PR145
1
39,45 PBAT_SMBCLK
PC212
PC119
PC267
0.01_2512_1%~D
PR373
2
2
MAX8731_REF 3 19 +VCHGR_B 2 1+VCHGR_L1 4 1 2
2
39,45 PBAT_SMBDAT REF PGND

CSIP 18
5
6
7
8
0.1U_0402_10V7K~D
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
2 3 1K_0603_1%~D
0.01U_0402_25V7K~D
1U_0603_10V6K~D
0.1U_0603_25V7K~D
7 DAC CSIN 17 1 1
1
1
0.1U_0402_10V7K~D
10K_0402_1%~D
1
1
PC122
PC120
PC112
PC113
PC114
FBSA 15 1 2 +VCHGR
1
1
PR150
PC121
PC118
12 PQ76
2
2
GND PR368 SI4810BDY_SO8~D 2 2
16 4
2
FBSB 100_0402_5%~D
29
2
GND
1
2
0.01U_0603_50V7K~D
MAX8731_TQFN28~D
3
2
1
2
PC266
B B
MAX8731_REF
+5V_ALW +3.3V_ALW
100K_0402_5%~D
PR365
4.32M_0402_1%~D
1
301K_0402_1%~D
1 2
1
PR362
PR367
100K_0402_1%~D
1
2
+5V_ALW
2
PR366
ADAPT_OC 38
4
8
PR361 PU19A
2
1
MAX8731_IINP LM393DR_SO8~D D
1 2 2 5
P
G
0_0402_5%~D IN- IN+

O 1 2 O 7
59K_0402_1%~D
3 G 6
IN+ IN-
G
P
0.01U_0402_25V7K~D
10P_0402_50V8J~D
S PQ81 PU19B
3
1
PR363
PC259
RHU002N06_SOT323 LM393DR_SO8~D
8
4
1
100P_0402_50V8K
100P_0402_50V8K
1
100P_0402_50V8K
0.01U_0402_25V7K~D
PC254
2
1
1
PC255
PC256
A A
2
1
PC257
PC258
2
2
27.4K_0402_1%~D
2
2
1
+5V_ALW
PR364

2
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
5 4 3 2 1
5 4 3 2 1
+DC_IN discharge path
PQ62 +PWR_SRC
SI4835BDY_SO8~D
8 1
+SDC_IN 7 2
0.1U_0603_25V7K~D
10K_0402_5%~D
6 3
2200P_0402_50V7K~D
D D
5
1
PR305
PC232
PC233
4
PR306 PR307
2
10K_0402_5%~D 100K_0402_5%~D
1
2 1 2 1
1
D D
2 PQ63 2 PQ64
18,39,50 ACAV_IN
@ PR308 G RHU002N06_SOT323 G RHU002N06_SOT323
PQ65 100K_0402_5%~D S S PD47
3
8 D2 S2 1CHG_SBAT 2 1 B540C~D
7 D2 G2 2CHG_SBATT_N 2 1
+VCHGR 6 D1 S1 3
5 D1 G1 4
PQ66
FDS4935_SO8~D SI4835BDY_SO8~D
8 1
PR309 PR310 SBATT+ 7 2 +PWR_SRC
10K_0402_5%~D 100K_0402_5%~D 6 3
CHG_SBAT_N 2 1 2 1 5
1
D PC234 PD48
4
2 PQ67 0.1U_0603_25V7K~D 2
38 CHG_SBATT
G RHU002N06_SOT323 1 2 1 SBAT_G
S 3
3
CHG_SBATT_N RB715F_SOT323
33K_0402_5%~D
2
PR311
C C
1
CHG_PBATT_N
PC235
0.1U_0603_25V7K~D PBATT+
3
S
1 2 PD49
RHU002N06_SOT323
G
2 B540C~D
38 CHG_PBATT PQ68 PR312 PR313 2 1
D 10K_0402_5%~D 100K_0402_5%~D
1
CHG_PBAT_N 2 1 2 1
PQ69 PQ70
PQ71 PQ72 SI4835BDY_SO8~D SI4835BDY_SO8~D
4
SI4835BDY_SO8~D SI4835BDY_SO8~D 1 8 8 1
5 5 2 7 7 2
+VCHGR 6 3 CHG_PBAT 3 6 3 6 6 3
7 2 2 7 5 5
8 1 1 8
4
470K_0402_5%~D
470K_0402_5%~D
PR316
1
47K_0402_1%~D
PR314
PR315
1 2
PD50
2
1 PBAT_G
1
10K_0402_5%~D
B B
3
33K_0402_5%~D
PR317
2
RB715F_SOT323
PR318
2
PBATT+
1
PR319 PU14A
8
SBATT+ 47K_0402_1%~D LM393DR_SO8~D
1
D
1 2 3
P
IN+ PQ73
O 1 2
2 G RHU002N06_SOT323
IN-
1
470K_0402_5%~D
PR321 S
3
147K_0402_1%~D 4
PR320
1 2
PR322
0.1U_0603_25V7K~D
100K_0402_5%~D
2
2
42.2K_0402_1%~D
PBATT+ 1 2
2
0.1U_0603_25V7K~D
PC236
PR323
1
@
1
2
PC237
+3.3V_ALW
+3.3V_ALW
1
PR324
8
10K_0402_5%~D PD51
1 2 5 2
P
PU15 IN+
O 7 1
5
TC7SH32FU_SSOP5~D 1 2 6 3
IN-
1
D LM393DR_SO8~D
32.4K_0402_1%~D
2
P
38 SBAT_LOW I0
2
A
4 2 PR325 PU14B RB715F_SOT323 A
4
O
PR326
1 G 100K_0402_5%~D
38,45 SBAT_PRES# I1
G
PQ74 S +3.3V_ALW
3
RHU002N06_SOT323
3
Title
Selector
5 4 3 2 1
5 4 3 2 1
D D
DVI_TX2-
DVI_TX2- 36
2 1 C3012 1 2 R3015
0.1U_0402_16V4Z~D 100_0402_5%~D
DVI_TX2+
DVI_TX2+ 36
DVI_TX1-
DVI_TX1- 36
2 1 C3014 1 2 R3016
0.1U_0402_16V4Z~D 100_0402_5%~D
DVI_TX1+
DVI_TX1+ 36
DVI_TX0-
DVI_TX0- 36
2 1 C3021 1 2 R3017
0.1U_0402_16V4Z~D 100_0402_5%~D
DVI_TX0+
DVI_TX0+ 36
DVI_CLK-
DVI_CLK- 36
2 1 C3022 1 2 R3018
0.1U_0402_16V4Z~D 100_0402_5%~D
DVI_CLK+
DVI_CLK+ 36
L3002 L3003
BLM18PG181SN1_0603~D BLM18PG181SN1_0603~D
+3.3V_RUN_R 2 1 +AVCC +SVCC 2 1 +1.8V_RUN
10U_0805_10V4Z~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
C C
1 2 1
1 1 1 1 2 C3010 C3011 C3001
C3003
C3036
C3039
C3004
C3005
0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
0.1U_0402_16V4Z~D 2 1 2
2 2 @ 2 @ 2 1
L3004 +3.3V_RUN_R
+3.3V_RUN_R BLM18PG181SN1_0603~D
1 1 +SPVCC 2 1
10U_0805_10V4Z~D
100P_0402_50V8J~D
0.1U_0402_16V4Z~D
1000P_0402_50V7K~D
C3032 C3013
1 1 1 1
C3015
C3035
C3023
C3016
0.1U_0402_16V4Z~D 10U_0805_10V4Z~D
2 2 L3006
BLM18PG181SN1_0603~D
L3005 2 2 @ 2 @ 2 +PVCC1 2 1
10U_0805_6.3V6M~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
+1.8V_RUN 2 1 +VCC 1 1 1 1
C3025
C3024
C3037
1 1 1 1
C3017 C3018 C3019 C3020 C3026
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 2 2 @ 2 @ 2
2 2 2 2
L3001
+PVCC2
10
34
28
15
21
36
42
48
11
26
2 1
10U_0805_6.3V6M~D
100P_0402_50V8J~D
1000P_0402_50V7K~D
U3001
0.1U_0402_16V4Z~D
1 1 1 1
VCC
VCC
VCC
OVCC
AVCC
AVCC
SVCC
SVCC
SPVCC
PVCC1
PVCC2
C3030
C3029
C3038
C3031
C3027 0.1U_0402_16V4Z~D
B INT+ DVI_CLK- B
12 SDVOB_INT+ 1 2 32 SDI+ TXC- 13
1 2 INT- 33 14 DVI_CLK+
12 SDVOB_INT- SDI- TXC+ 2 2 @ 2 @ 2
C3028 0.1U_0402_16V4Z~D
SDVOB_RED+ 37 16 DVI_TX0-
12 SDVOB_RED+ SDR+ TX0-
SDVOB_RED- 38 17 DVI_TX0+
12 SDVOB_RED- SDR- TX0+
+5V_RUN
SDVOB_GREEN+ 40 19 DVI_TX1-
12 SDVOB_GREEN+ SDG+ TX1-
SDVOB_GREEN- 41 20 DVI_TX1+
12 SDVOB_GREEN- SDG- TX1+
SDVOB_BLUE+ 43 22 DVI_TX2-
12 SDVOB_BLUE+ SDB+ TX2-
1
1
2.2K_0402_5%~D
2.2K_0402_5%~D
SDVOB_BLUE- 44 23 DVI_TX2+
12 SDVOB_BLUE- SDB- TX2+
R3001
R3009
12 SDVOB_CLK+ 46 SDC+ SDADDC 9 DVI_SDATA 36

12 SDVOB_CLK- 47 SDC- SCLDDC 8 DVI_SCLK 36
2
10,21,23,28,34 PLTRST# 2 RESET#

DVI_SCLK 5 SDVO_CTRLCLK 12
+VSWING 25 SDSCL
+AVCC 2 1 EXT_SWING SDSDA 4 SDVO_CTRLDATA 12
DVI_SDATA R3006 220_0402_5%~D 35 6 1 2 +3.3V_RUN_R
EXT_RES A1 @ R3007 1K_0402_5%~D
2
30 TEST
36 DVI_DETECT 29 HTPLG
+2.5V_RUN R3008 A1 LOW: Address = 0x70
SPGND
PGND2
AGND
AGND
AGND
SGND
SGND
1K_0402_5%~D
GND
GND
HIGH: Address = 0x72
1
1
SII1362ACTU_LQFP48~D
7
31
27
18
24
12
39
45
3
1
1
4.7K_0402_5%~D
4.7K_0402_5%~D
R3010
1K_0402_5%~D
R3013
R3014
2
2
A A
SDVO_CTRLCLK
SDVO_CTRLDATA
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Internal LVDS
LA-2791
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D Smart card pin definition not match the Change JSC pin connection, pin1 connect to GND, pin2 connect to D
1 31 H/W 05/27 Roger cage pin define SC_DET# ~ pin10 connect to +SC_PWR 0.2
2 12,36 H/W 05/27 Roger Fix TV out issue Depop R23,R24,R25. And add R1790,R1791,R1792 75 ohms 0.2
Remove power switch to save placement
3 40 H/W 05/27 Roger spacing Remove SW1. Reseve R1793 pad for power switch 0.2
Docking CRT HSYNC, VSYNC connect to the DOCK_HSYNC connect from U190 pin4 to docking connector pin 209,
4 20 H/W 05/27 Roger out put side of buffer DOCK_VSYNC connect from U191 pin4 to docking connector pin 210 0.2
5 32 H/W 05/27 Roger Improve RJ45 center tap driving Connect +2.5VLAN to JIO pin 14 for RJ45 center tap 0.2
Change FDATAIN to ICHO_FDATAIN and connect from U216 pin 106 to U213
6 39 H/W 05/27 Roger SPI ROM pass through mode connect error pin5. Chagne FDATAOUT to ICHI_FDATAOUT and connect from U216 pin 108 to 0.2
R1788 pin1
7 39 H/W 05/27 Roger Flash Recovery strapping issue Change R474, R475 from 100K to 10K 0.2
8 ALL H/W 05/30 Brike To fix MEC5004 VCC1 power lading Change net from +3VALW to +3VSRC 0.2
C C
9 43 H/W 05/30 Brike None Delete H21 and change H4 footprint from H_C176D122to H_C176D102 0.2
10 39 H/W 06/01 Will For delay MEC5004 internal 1.8V reg. Modified C1769 from 4.7UF to 22UF. 0.2
To improve rise time of serial DO
11 23 H/W 06/01 Will from SPI ROM. Modified R389 from 10K to 1K.. 0.2
12 41 H/W 06/01 Will None Add pullup to HDDC_EN# and MODC_EN#. 0.2
13 36 H/W 06/01 Will Fix Docking TV out issue. Modified R1790,R1791,R1792 from 75 ohms to 150Ohm. 0.2
14 39 H/W 06/01 Will None Change power on SPI ROM (pins 3 and 8) from +3VALW to +3VSUS. 0.2
Use ECE5018 GPIOC2 (pin 67), pin name MDC_RST_DIS#. Reserve
15 38 H/W 06/01 Will For GPIO control. this pin for MDC disable circuit. 0.2
Remove R34, R242, R37, R247, Q7, and Q33 to connect LDDC_CLK,
16 12 H/W 06/01 Lester None LDDC_DATA directly to LVDS connector. 0.2
B B
Intel Checklist recommends a 1 nH

17 13 H/W 06/01 Lester ferrite which calculates to 200 ohm. Change L34 to BLM18PG181SN1_0603. 0.2
18 06 H/W 06/01 Lester Add resistor for cystal drive current Add R32 0 ohm resistor 0.2
limiting
ICH7M.P5 connect to MEC 5004.107, MEC5004.108 connect to SPI ROM.5.
19 39 H/W 06/01 Will Correct SPI connection for SMSC recommand ICH7M.P2 connect to MEC 5004.105, MEC5004.106 connect to SPI ROM.2 0.2
SMSC recommond add VBUS_DET pull up
20 38 H/W 06/02 Roger resistor Add R1440 100K for LAN_TPM_EN# (VBUS_DET) 0.2
21 33 H/W 06/02 Roger Add MDC disable circuit Add R1441, R1442, R1443, Q64. ECE5018 pin 67 program MDC_RST_DIS# 0.2
22 34 H/W 06/06 Roger None Change U8 NNCD6.8RL-A to D5 NNCD5.6LG 0.2
23 3 H/W 06/06 Roger None Fixed USB table 0.2
A 24 3 H/W 06/13 Roger None Add PJP22, PJP24 for +5VMOD and +5VHDD. Delete R506 0.3 A
Title
Changed-List History 1
5 4 3 2 1
5 4 3 2 1

Request
D D14 pin2 connect to +VCCP, pin1 connect to R320 pin1, R320 pin2 connect D
25 13 H/W 06/14 Roger Follow Intel CRB to +2.5VRUN. D18 pin2 connect to +1.5VRUN, pin2 connect to R12 pin1, R12 0.3
pin2 connect to +3VRUN_R
U10 (STAC9200) pin21 (GPIO0) is anlog
26 27 H/W 06/14 Roger power plane Change R156 pull up from +3VSUS to +VDDA 0.3
Change ITP debug to XDP debug definition Change R387, R417, R391, R436, R416, R415 to 56 ohms. Add R33 56 ohms.
27 7 H/W 06/14 Roger for Yonah CPU Change R424 to 1K ohms. 0.3
28 39 H/W 06/14 Roger For easier flash EC code Add short pad and change R475 to 1K ohms 0.3
29 40 H/W 06/14 Roger For easier power switch Change R1793 to a pad like CMOS pad 0.3
30 34 H/W 06/14 Roger ME change mini card stand off to Latch Remove H22,H23,H24,H25. Add JCLIP1,JCLIP2 0.3
EMI reqest add caps for the splite power
31 42 H/W 06/14 Roger plane that PCI bus routed Add C1806,C1807,C1808,C1809,C1810,C1811 0.3
Reserve discharg circuit for +5VRUN,+3VRUN,
C 32 41 H/W 06/16 Roger +1.8VRUN,+1.5VRUN,+0.9V_DDR_VTT,+2.5VRUN Add R1793,R1794,R1795,R1796,R1797,R1798,Q87,Q88,Q89,Q90,Q91,Q92 0.3 C
power rails
33 28 H/W 06/21 Gautam Reserve ST M45PE20 for LOM EEPROM Add U3 (ST M45PE20) co-layout with U188 (AT45BCM021B) 0.3
EMI reqest add caps for the splite power Add C1812~C1814 0.047uF_0402. Change C1810~C1813 from 0603 to 0402
34 42 H/W 06/23 Gary plane that PCI bus routed package 0.3
35 38 H/W 06/23 Roger +3VRUN leakage at AC mode in S5 Change R1362 pull up from +3VSRC to +3VRUN 0.3
36 All H/W 06/24 Roger Follow Dell USB assignment recommendation Update USB table, block diagram and connection 0.3
37 39 H/W 06/24 Will 4.7uF cap for VR_Cap pin of REV B 5504 Change C1769 for 22uF 0805 size to 4.7uF 0603 size 0.3
Change +3V/+5V design to follow Dell
38 All H/W 06/24 Joey recommendation Change +3VSRC to +3VALW except for LOM 0.3
IEEE testing the voltage level are closer
39 28 H/W 06/24 Gautam to the higher end of IEEE range Change R1364 from 1.15K to 1.18K_0402_1% 0.3
B B
40 7 H/W 06/24 Lester Required by Intel for B0 Yonah. Add R1378 (51_0603_1%) for TEST2 pulldown 0.3
41 39 H/W 06/24 Lester Required by Intel for B0 Yonah. Populate R1752 and add note "No stuff when doing flash recovery" 0.3
42 33 H/W 06/28 Rossana MDC signal by pass caps not require Delete C93, C82, C73 0.3
Reseved USB port of OZ77C6 for Biometrics Change JTPAD from 10 pins to 20 pins. Add USB_BIO+/- on U1 pin18,19
43 31,40 H/W 06/28 Rossana reader connect to JTPAD pin9,11 0.3
44 30 H/W 06/28 Rossana Request by Dell Remove C1783, C1784 0.3
45 34 H/W 06/28 Rossana Request by Dell Remove L18, R149, and R144 - direct connect USB to Wireless LAN card 0.3
46 34 H/W 06/28 Rossana Request by Dell Add R1603 connect to JMINI2 pin46, outgoing signal BT_ACTIVE 0.3
47 34 H/W 06/28 Rossana Gerber Gate List issue Add series 0-ohms R1609, R1610 for pins 3 and 5 of JMINI2 0.3
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
48 34 H/W 06/28 Rossana Gerber Gate List issue Change C159 and C1785 from 10uF to 0.1uF 0.3
49 34 H/W 06/28 Rossana Gerber Gate List issue Add T1 test point for JMINI1 pin 42 0.3
50 36 H/W 06/28 Rossana Gerber Gate List issue Add C1817~1820 for U180,U178,U179,U177 0.3
51 39 H/W 06/28 Rossana Gerber Gate List issue Change R30 pull up from +3VSRC to +3VALW 0.3
Change sniffer switch type, the active WIRELESS_ON/OFF# connection from pin1 to pin 4 of JSNIFF, pin3 connect
52 43 H/W 06/28 Rossana direction swap to GND, pin2 NC, pin 1 connect to SNIFFER# 0.3
53 36 H/W 06/28 Rossana Gerber Gate List issue Add C1821 1000pF for +DOCK_PWR_SRC, add C1827 1000pF for DOCK_DC_IN 0.3
54 35 H/W 06/28 Rossana Gerber Gate List issue Add C1822 0.1uF_0402 and C1823,C1824 .47uF_0402 for QBUF power 0.3
55 26,27 H/W 06/28 Rossana Gerber Gate List issue Follow Dell "Travis_Audio_0628" reference circut design 0.3
C C
56 39 H/W 06/29 Scott Gerber Gate List issue Change L4 form MURATA BLM11A121S to BLM18PG181SN1 0.3
57 24 H/W 06/30 Scott Gerber Gate List issue Remove C375, C37 for ICH_V5REF_RUN, remove C420 for ICH_V5REF_SUS 0.3
58 24 H/W 06/30 Scott Gerber Gate List issue Add R37 0.5 ohm 0603 resistor connect to L42 pin1 0.3
59 24 H/W 06/30 Scott Gerber Gate List issue Populate C347 and C442 0.3
60 24 H/W 06/30 Scott Gerber Gate List issue Change C450 for 220uF to 330uF poly cap 0.3
Match Dell JTPAD pinout definition, add C62, C63 for BIO power rail
61 40 H/W 06/30 Roger Match Dell JTPAD pinout definition bypass 0.3
R162 change from 8.2K to 2.2K, remove D33, D34, Change C1800, C1801
62 26,27 H/W 06/30 Rossana Gerber Gate List issue from 1uF to 2.2uF, change C534 from 0.1uF to 1uF, del C533. 0.3
HP_NB_SENSE move from GPIO2 to GPIO0 of U10, add series resistor 0 ohm
63 26 H/W 06/30 Rossana Gerber Gate List issue for this signal 0.3
B B
64 7 H/W 07/07 Roger Support A1 Yanah CPU De-pop R513, R514 for A1 yanah CPU 0.3
Change Change R417 to 150 ohm, R415 to 51 ohm, R387 to 39.2 ohm, R436
65 7 H/W 08/01 Roger Gerber Gate List issue item 6 to 27.4 ohm, R391 to 680 ohm, R424 to 22.6 ohm 0.4
66 38 H/W 08/01 Roger Gerber Gate List issue item 8 Change R110 from 68 ohm to 75 ohm for H_PROCHOT# pull up 0.4
Change the voltage rail on sniffer LED pull-ups (at Q13 and Q16) from
67 43 H/W 08/01 Roger Gerber Gate List issue item 9 +3VALW to +3VSUS 0.4
68 7 H/W 08/01 Roger None Remove unnecessary capacitor C1805 0.4
69 40 H/W 08/01 Roger Hall switch design on touch pad moudle Depop U46 and C54 0.4
70 38 H/W 08/01 Roger Gerber Gate List issue item 19 Move NB_MUTE from U215 pin 107 to pin73 0.4
71 16,17 H/W 08/01 Roger Gerber Gate List issue item 20,21 Remove R178, pop R177 0.4
A A
72 10,23 H/W 08/01 Roger Gerber Gate List issue item 22,23 Depop R253, populate R1799 0.4
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
73 42 H/W 08/02 Roger Gerber Gate List issue item3 Connect 2.5V_RUN_PWRGD net to LDO_POK pin. Add depop R49 0.4
74 18 H/W 08/02 Roger Gerber Gate List issue item11 Add R1800 31.6K ohm resistor for Vmargin circuit. 0.4
75 23 H/W 08/02 Roger Gerber Gate List issue item5 Change R389 from 1K to 10K 0.4
76 33, 40 H/W 08/04 Steven Conbine the BT and TP in 30 PIN connector. Delete JBT and move components to JTAP. 0.4
77 42 H/W 08/04 Steven Gerber Gate List issue item3 Add Depop resister R3019. 0.4
For intel NAPA platform check list 1.5 Chnage R425 from 33Ohm pull-down to 8.2KOhm pull-up. And add pull-up
78 22, 23 H/W 08/04 Steven request. resister R3020 in SIO_RCIN#. 0.4
79 19 H/W 08/08 Roger Follow Intel CRB circuit Pull up LDDC_CLK, LDDC_DATA to +3VRUN_R by R73, R74 0.4
80 16 H/W 08/09 Roger V_DDR_MCH_REF discharge issue Add R51 (100K_0402) connect to V_DDR_MCH_REF 0.4
C C
81 23 H/W 08/09 Roger Leakage issue when system into S3 Change SIO_EXT_SMI#, SIO_EXT_SCI# pull up to +3VSUS 0.4
82 36 H/W 08/09 Roger Refer Dell docking reference circuit Remove R1320, R1319 0.4
83 12 H/W 08/09 Roger Gerber Gate List issue item 28 Depop R357 0.4
84 28 H/W 08/10 Roger Gerber Gate List issue item 30 Add R53 4.7K resistor for LOM_SO pull down 0.4
Connect BCM5752 pin C4 to ECE5018 pin75 net name LOM_CABLE_DETECT.
85 28 H/W 08/10 Roger Gerber Gate List issue item 33 Series no stuff resistor R55 0.4
86 38 H/W 08/10 Roger Gerber Gate List issue item 39 R1171 change pull up from +3VRUN to +3VSUS 0.4
87 38 H/W 08/10 Roger Gerber Gate List issue item 42 Add a 4.7uF cap for ECE5018 VDDA33 coupling 0.4
Add a 0 Ohm 0402 resistor R62 in series with the RTC_CELL and EMC5004
88 39 H/W 08/10 Roger Gerber Gate List issue item 43 pin 121 0.4
B B
89 7 H/W 08/10 Roger Follow Intel CRB circuit R513, R514 pull up to +VCCP 0.4
Add resistor R63 (0_0402_5%) between the BIA_PWM signal and MEC5004
90 39 H/W 08/10 Roger Gerber Gate List issue item 46 pin 73 0.4
91 39 H/W 08/10 Roger Gerber Gate List issue item 47 Change ITP_DBRESET# connection from EMC5004 pin 55 to pin96 0.4
92 22 H/W 08/10 Roger Gerber Gate List issue item 50 Add no stuff C69 (0.1U_0402_16V4Z) between THRMTRIP_ICH# and GND 0.4
93 41 H/W 08/10 Roger None Change R1795 pin 1 connect from +1.8VRUN to +1.8VSUS for discharge 0.4
94 23 H/W 08/10 Roger Gerber Gate List issue item 51 Move pull-up R388 to pin 1 side of R1787 0.4
Add C70 (0.1U_0402_16V4Z) for +CK_VDD_MAIN decoupling. Remove R290,
95 6 H/W 08/10 Roger Gerber Gate List issue item 29 R343, R329 to save spacing 0.4
96 7 H/W 08/11 Roger Gerber Gate List issue item 68 Remove R513 and R514 platform no longer use Yonah A00 0.4
A A
97 42 H/W 08/11 Roger Gerber Gate List issue item 65 Populate 0ohm for R49, R313, R319, R334 0.4
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
98 41 H/W 08/11 Roger Gerber Gate List issue item 67 Change R494 to 20K 0.4
99 7 H/W 08/11 Roger Gerber Gate List issue item 69 Add no stuff C71 and C72 for +VCCP of JITP 0.4
100 7 H/W 08/11 Roger Gerber Gate List issue item 70 Change R416 and R33 from 56 ohm to 54.9 ohm 0.4
101 12 H/W 08/11 Roger Gerber Gate List issue item 72 Delete R333 to follow reference schematics 0.4
Add R68 (20K_0402_5%) and R70 (39K_0402_1%) for LAN_LOW_PWR voltage
102 28 H/W 08/11 Roger Gerber Gate List issue item 34 divider connect to pin K5 0.4
DOCK_HP_MUTE# for GPIO2 of codec connect to ECE5018 pin 81. EAPD for
103 26,27,38 H/W 08/12 Roger Gerber Gate List issue item 75 GPIO3 of codec connect to additional Q11 gate 0.4
104 38 H/W 08/15 Roger Gerber Gate List issue item 38 Chnge SYS_PME# pull up from +3VRUN to +3VALW. Add no stuff R71 in series 0.4
105 38 H/W 08/15 Roger Gerber Gate List issue item 41 Remove HP_NB_SENSE from ECE5018 pin 106 to pin 82 0.4
C C
106 23 H/W 08/15 Roger Gerber Gate List issue item 188,189 Depop R428,Change value of R75 to 10k ohms 0.4
107 40 H/W 08/16 Roger Gerber Gate List issue item 48 Change R1750 and R1751 to L1 and L2 0.4
108 28 H/W 08/16 Roger Gerber Gate List issue item 213 Depop U188, R1366 and populate U3, R1267 for ST AT45BCM021B 0.4
109 39 H/W 08/16 Roger Gerber Gate List issue item 217 Remove R166. Move R1635 for AFT_INT# move to page 39 0.4
110 39 H/W 08/16 Roger Add pull up for open drain out put Add R93 pull up to +3VALW for BAT_SEL# 0.4
Mute internal speaker when docking aduio
110 38 H/W 08/16 Roger jack plug in Add pull down resistor for DOCK_HP_MUTE# 0.4
111 06 H/W 09/07 Roger Follow Dell CoE schematics Change C329, C333 from 33pF to 27pF 0.5
112 43 H/W 09/14 Roger Blue tooth LED too bright Change R8 from 3.3K to 1K ohms 0.4
B B
113 41 H/W 09/14 Roger +1.8VSUS discharge low issue Populate Q89, R1795 0.4
114 39 H/W 09/14 Roger LID_CL# can't assert low Change R482 from 100K to 1M ohms 0.4
115 40 H/W 10/04 Brike Delete U46,C54,SW1 None 0.5

Connect 8051TX to WWAN Pin 19 and Connect
116 34, 39 H/W 10/13 Brike 8051RX to WWAN Pin 42. Modified. 0.5
117 22 H/W 10/15 Brike Gerber Gate List issue item 60 Add R97 0-ohm tuning resistor between R36 pin2 and X1 pin1 0.5
118 41 H/W 10/17 Brike Gerber Gate List issue item 66 Change R1795 to a 30 ohm 0603 resistor 0.5
MEC5004 per SMSC recommendations to add Add de-pop components R101, R110, R112, R114, R117, Q20, Q19, C54, D2002.
119 39 H/W 10/18 Brike circuit for improving POR issue. And change C1769 to 22U. 0.5
120 38 H/W 10/18 Brike change board ID to X02 Pop R95, R419 and De-pop R108, R405. 0.5
A Gerber Gate List issue item 77. Add 10pF A
121 40 H/W 10/18 Brike cap between GND and pin2 of L1/L2. Add C66, C73. 0.5
Title
5 4 3 2 1
5 4 3 2 1

Request
D Gerber Gate List issue item 78. Pull up D
122 23 H/W 10/18 Brike LAMP_STAT# to +3VRUN Change R75 pull-up to +3.3V_RUN. 0.5
Gerber Gate List issue item 72. Inductor
123 6 H/W 10/19 Brike design follow M07 design on L40,L32 Change L32, L40 from 0603 to 0805. 0.5
(Size:0805).
Gerber Gate List issue item 79.
124 23 H/W 10/19 Brike SATA_DET# is pull up to +3.3V_SUS. Change R784 pull up to +3.3V_SUS. 0.5
Gerber Gate List issue item 74.Make Change R1643 prior to bypass caps " C152 and C517 " at +3VRUN
125 18 H/W 10/19 Brike R1643 prior to bypass caps at +3VRUN. power rail . 0.5
Change the 32 high frequency decoupling caps, 0805 X5R, from 22uF
to 10uF.
126 9 H/W 10/20 Brike Gerber Gate List issue item 84 Depop C354 and C618.Change C352, C496, C497, and C365 from 330uF/7mOhm 0.5
to 330uF/6mOhm SP caps.
127 34 Brike Connect PLTRST# instead of PLTRST_DELAY# to WLAN and WWAN connectors. 0.5
H/W 10/20 Gerber Gate List issue item 82
C C
128 23 H/W 10/20 Brike IMVP_PWRGD glitch issue Add C79 0.1uF cap on IMVP_PWRGD to filter the glitch 0.5
129 28 H/W 10/21 Brike Q68 surge current Add R102 (0603) and C80 0.1uF cap Q68 pin1 for reduce surge current 0.5
130 40,43 H/W 10/21 Brike BT & HDD LED is on when the SNIFFER is Added a circuit (FET and Resistors) to keep the BT LED & HDD LED off 0.5
turned on. when the SNIFFER is turned on
131 38 H/W 10/21 Brike Gerber Gate List issue item 81 Depop R1440 0.5
132 34 H/W 10/22 Brike Add Intel WoWLAN Support Circuit Add pop components Q21 and R101, and un-pop componet R24. 0.5
Gerber Gate List issue item 89. Change
133 18 H/W 10/24 Brike OTP trip temperature to 88 deg C. Change R249 to 332K and R262 to 118K. 0.5
Gerber Gate List issue item 90. Pop SMSC
134 39 H/W 10/24 Brike workround circuit for 11/7 build. Pop R101, R110, R112, R114, R117, Q20, Q19, C54, D2002. 0.5
Gerber Gate List issue item 91. Add a 0
135 39 H/W 10/24 Brike ohm pulldown resistor on TEST_PIN. Add R122 0Ohm resister. 0.5
B B
Gerber Gate List issue item 111. Remove
136 43 H/W 10/24 Brike one of the pull-ups on SNIFFER_LED_OFF#. Remove Pull up resister R1447. 0.5
137 43 H/W 10/24 Brike Gerber Gate List issue item 110. More R76 to pin 1 of Q66 and populate it. 0.5
138 34 H/W 10/24 Brike Add Intel WoWLAN Support Circuit Replace Q21 and R101 to D2003 0.5
Gerber Gate List issue item 108. Add 39
139 20 H/W 10/24 Brike ohm resistors at output of U190 and U191. Add resister R102 and R123. 0.5
Gerber Gate List issue item 92. Add
thermistor circuit to VCP2 (pin 40) of
140 18 H/W 10/24 Brike EMC4000. Please route to 5V_CAL_SIO2# Add thermistor circuit R479, R480, R481, C79, Q21. 0.5
(pin 80, GPIO B4 on ECE5018).
Gerber Gate List issue item 114.
Modified SATA_ACT# LED sniffer disable Modified the circuit and Add and D2004. Chnage Q1 to 3904,
141 43 H/W 10/24 Brike R1449/1448 change to 10K and 1K. 0.5
circuit.
Gerber Gate List issue item 119. For fix Change delay circuit R1764 from 200KOhm, C1788 to 470PF to +1.8V_run
A 142 40 H/W 10/25 Brike the IMVP_PWRGOOD glitch issue. and +3V_run. 0.5 A
Title
5 4 3 2 1
5 4 3 2 1

Request
D Gerber Gate List issue item 104. Modified Modified the circuit Pull up R1449 to +5V_SUS and R1445 to +5V_run. D
143 38 H/W 10/25 Brike the SATA_ACT# circuit. R2 move to Q1 pin 3, SNIFFER_LED change to GPIO82. 0.5
Gerber Gate List issue item 116. Add
144 20 H/W 10/25 Brike diode HSYNC and VSYNC buffers. Add D2005 (RB751) in U190, U191 Pin 5. 0.5
145 40, 43 H/W 10/26 Brike Modified HDD/BT disable circuit. Move 40 BT Disable circuit to 43. 0.5
146 19 H/W 10/26 Brike Add level shit circuit for BIA_PWM. Delete R520 and Add U8. 0.5
the delay circuit on +3.3V should get rid
147 23 H/W 11/03 Brike of the glitch Depop C82. 0.5
148 41 H/W 11/03 Brike Populate the HDD power switch circuit Pop Q51, R507, Q50 and Depop PJP24. 0.5
149 31 H/W 11/03 Brike For passing EMVCo test. Change R1424 from 220 to 330Ohm. 0.5
150 43 H/W 11/03 Brike SNIFFER_LED_OFF# is a push/pull signal. De-pop R1445. 0.5
C C
151 27 H/W 11/03 Brike To improve audio quality Change C199 to 0.022uF and pop R164, depop R170. 0.5
Change U216 P/N to D version. Depop R117, R114, R110, R101, R104,
152 39 H/W 11/11 Brike Change SMSC MEC5004 from version C to D. D2002, Q19, Q20, C54. And chnage C1769 value from 22UF to 4.7UF. 0.5
Change DOCK_SMB_CLK and DOCK_SMB_DAT for Change R99 and R100 resister from 100K to 8.2K Ohm. And R1618 change to
153 39 H/W 11/11 Brike consistent with other M07 platforms. 10KOhm. 0.5
Change R2 value from 56Ohm to 330Ohm. And modified R15 from 150Ohm to
154 43 H/W 11/11 Brike For improve LED brightness issue. 100Ohm. 0.5
For Q68 broken issue. Modified R120
155 28 H/W 11/12 Brike value for protect base pin. ChangeR120 from 0Ohm to 2KOhm. 0.5
For Dell request change D32, D2005 to
156 20 H/W 11/12 Brike RB500. Change D32 and D2005 from RB751 to RB500 0.5
157 27 H/W 11/12 Brike For improve Audio THD+n performance. Change C113, C114 and C146 from 1UF to 2.2U. 0.5
158 27 H/W 11/27 Brike For adjust Audio gain to 15.6DB. Pop R170, De-pop R164. 0.5
B B
159 42 H/W 12/06 Brike For improving SUSPWROK turn on issue. Modified Q7 to 2N7002. 0.6
Change C3030, C3025 from 1uF to 10uF; R3006 to 220Ohm; R3015, R3016,
160 52 H/W 12/06 Brike For solving DVI eye diagram issue. R3017, R3018 to 100Ohm. 0.6
For solving HD warn boot parking sound Change HDDC_EN#, MODC_EN# from ICH7 to ECE5018 Pin 106, 107 (GPIOH2/3),
161 23, 38 H/W 12/06 Brike issue. and Depop R2148, R2149. 0.6
162 7 H/W 12/06 Brike Add a De-pop resister for CPU test 1 PIN. Add De-pop resister R1387. 0.6
Add an damping resister for improving
163 39 H/W 12/07 Brike SPI_CS# overshoot issue. Add 47Ohm resister R127. 0.6
For solving SBAT_SMBDAT rising time over
164 39 H/W 12/07 Brike spec issue. Change R444 to 4.7KOhm resister. 0.6
For Gerber Gating list item 14 Depop
165 6 H/W 12/12 Brike pullup resistor on ICH_CLKREQ#. Depop resister R1761. 0.6
For Gerber Gating list item 17 Update
166 38 H/W 12/12 Brike board ID to A00 Pop R405, depop R419. 0.6
A For Gerber Gating list item 11 add 47pF A
167 31 H/W 12/12 Brike capacitors to the USB_BIO+/- pins to Add 2 capaciotr C83, C84 in USB_BIO+/-. 0.6
fix bio sensor ESD issue.
Title
5 4 3 2 1
5 4 3 2 1

Request
D For GPIOH[3:2] need, chnage pullup D
168 41 H/W 12/14 Brike resister power plane to always. Change pullup resister R2148, R2149 for +3.3V_SUS to +3.3V_ALW. 0.6
For Gerber Gating list item 18. Change
169 41 H/W 12/15 Brike pullup resister to 10K. Change pullup resister R2148, R2149 for 100K to 10KOhm. 0.6
For Gerber Gating list item 1. Remove
170 18 H/W 12/15 Brike pullup resister from 2.5V_RUN_PWRGD. Remove R116. 0.6
For Gerber Gating list item 21. Add 0 ohm
171 39 H/W 12/19 Brike series resistor to SPI_CS# at MEC5004. Add series resister R143 at MEC5004 side. 0.6
172 31 H/W 12/19 Brike For improving USB BIO sensor EMI issue. Add Pop L5, and depop resister R128, R137. 0.6
For DELL EMI request for add a 0.1uF
173 40 H/W 12/20 Steven capacitor in JTPAD. Add 0.1uF capacitor C85. 0.6
For Q68 damage issue change form BCP69 to
174 28 H/W 12/30 Steven MBT35200 as ZRS solution. Use MBT35200 to replace Q68. Modified. 0.6
Intel Design Guide 1.0 to change H_RESET
175 7 H/W 12/31 Brike pull-up resister to 51Ohm. Change resister R416 to 51Ohm. 0.6
C For enable MEC5004 BIOS write protect C
176 39 H/W 01/04 Brike function. Pop R139 and de-pop R138. 0.6
177 27 H/W 01/07 Benson For adjust Audio gain to 21.6 DB. DePop R170, pop R164. 0.6
For Q68 issue to reserve soft start
178 28 H/W 01/09 Brike circuit. Change R120 to 0Ohm, and depop C80. 0.6
For fixing issue with projector using Change R102,R123 from 39 ohm to 0 ohm
179 20 H/W 01/20 Brike long cable. 0.6
For stronger the VGS driving in
180 19 H/W 01/20 Brike Battery Mode Change R235 from 200K ohm to 100K ohm 0.6
181 6 H/W 01/20 Brike The Drive Level too high Change R32 from 0 ohm to 470 ohm 0.6
182 22 H/W 01/20 Brike The Negative Resistance too low Change X1 spec from CL=20pF to 6 pF and C38,C40 from 12pF to 2.2pF 0.6
Brike The Frequency too high & Drive Level too Change Y1 spec from CL=20pF to 12pF and C1451,C1452 from 22P to 15P 0.6
183 38 H/W 01/20 high
B B
184 31 H/W 01/20 Steven None Depop L5 ,pop R128,R137 33 ohm 0.6
185 39 H/W 02/07 Steven For solving primary battery hand issue. Change R447, R449 to 4.7KOHm; R444, R131 to 2.2KOhm. 0.6
A A
Title
5 4 3 2 1
5 4 3 2 1

Request
D M4 input current more than MAX8734 LDO3 Delete PU17 SN74AHC1G32DCKR OR GATE(SA00732018L), D
1 46 PWR 06/01 Saha output 100mA PR49 1K_0402_1%(SD03410018L) 0.2
Add PR350 0_0402_5%(SD02800008L) connact LDO3 to ON3
PU18 74AHCT1G08GW AND GATE(SA00000L30L)
PR352 1K_0402_1%(SD03410018L)
PR351 0_0402_5%(SD02800008L) 0.2
MAX8734 LDO soft start issue. Delete PR27 4.7_1210_5%(SD000007E8L)
2 46 PWR 06/01 Saha Un-pop PC20 4.7U_1206_25V6K(SE093106M8L) 0.2
3 46 PWR 06/01 Saha PWR_SRC noise issue Un-pop PC252 100U_25V_M(SF10004M008) 0.2
Rename net +3VALW to +3VSRC
4 44/45 PWR 06/01 Saha +3VALW change to +3VSRC 0.2
5 47 PWR 06/01 Saha VCCP high/low side MOSFET change from PQ38 change from IR7821(SB57821008L) to BSO072N03S(SB00000418L) 0.2
IR to Infineon PQ40 change from IR7832(SB57832008L) to BSO072N03S(SB00000418L)
No-stuff PC207 and PC208 Un-pop PC207 and PC208 10U_0805_6.3V5K(SE093106M8L)
C C
6 47 PWR 06/01 Saha VCCP_1P05VP OCP issue(5A) PR224 change from 124K_0402_1%(SD03412438L) to 60.4K_0402_1%(SD03460428L) 0.2
7 47/48 PWR 06/01 Saha Choke height issue.(5.6mm change to 5.0mm) PL14 and PL27 change from 1.4U_HMU1356-1R4_15.5A H5.6mm(SH04814AM8L)
to 1.4U_HMU1350-1R4_15A H5.0mm(SH000004H8L) 0.2
8 44 PWR 06/01 Saha PSID materiel change by Dell PQ1 change from BSS138_SOT23(SB50138008L) to FDV301_SOT23(SB50301008L) 0.2
9 50 PWR 06/01 Saha New version MAX8731 PIN1 define GND Un-pop PR337 0_0402_5%(SD02800008L),Pop PR336 0_0402_5%(SD02800008L)
0.2
10 50 PWR 06/02 Saha Add RC filter at pin 23 of MAX8731 Add PR360 1_0603_1%(SD014100B8L)
PC253 220P_0402_50V7K(SE074221K8L) 0.2
11 46/48 PWR 06/02 Saha Add support for Reliability voltage Add PR356, PR355 and PR359 0_0603_5%(SD01300008L)
margining tests PR353 and PR354 0_0402_5%(SD02800008L) 0.2
B B
12 48 PWR 06/16 Saha Change output capactior rating voltage PC70 and PC71 change from 330U_D3L_6.3V_R25(SGA00000N8L)
from 6.3V to 2.5V to 330U_D2E_2.5VM_R15(SGA19331D0L) 0.3
13 49 PWR 06/22 Saha Change VCORE DPRSLPVR input resistor value PR248 change from 0_0402_5%(SD02800008L) to 499_0402_1%(SD03449900L) 0.3
14 50 PWR 06/22 Saha Add power limit schematic Depop PR361 80.6K_0402_1%, PR362 200K_0402_1%, PR363 121K_0402_1%, 0.3
PR364 3.01K_0402_1%, PR365 499K_0402_1%, PR366 100K_0402_1%,
PR367 100K_0402_1%, PC254 0.01U_0402_25V8K, PC255 100P_0402_50V8K,
PC256 100P_0402_50V8K, PC257 100P_0402_50V8K, PC258 0.01U_0402_25V8K,
PC259 10P_0402_50J8K, PQ81 RHU002N06_SOT323, PU19 LM393DR_SO8
Add PU17 SN74AHC1G32DCKR OR GATE(SA00732018L),

15 46 PWR 06/29 Saha Discreate 3VALW and 3VSRC. PR49 1K_0402_1%(SD03410018L) 0.3
PQ82 FDC655BN_NL(SB000004P8L )
Delete PR352 1K_0402_1%(SD03410018L)
A PR351 0_0402_5%(SD02800008L) A
PR350 0_0402_5%(SD02800008L)
PU18 74AHCT1G08GW AND GATE(SA00000L30L)
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
16 46 PWR 06/29 Saha Add V+ input Resistor Add PR27 0_1206_5%(SD00100000L) 0.3
17 45/51 PWR 06/29 Saha Battery conn. and battery selector +3VSRC Rename +3VSRC to +3VALW
change to +3VALW 0.3
18 47 PWR 06/29 Saha ISL6227 Issue VCC Change from +5VRUN to +5VSUS.
change 1.05V/1.5VHigh/Low side MOSFET EN1 and EN2 change from RUNPWROK to RUN_ON. 0.3
change 1.05V choke PR221 change from 20K_04-2_1%(SD03420028L ) to 19.6K_0402_1%(SD00000358L)
adjust OCP and ISEN value PQ8 change from FDS6994S(SB56994008L) to FDS8880(SB000004U8L)
Add PQ83 FDS6670AS(SB000004T8L)
PQ38 change from BSO072N03S(SB00000418L) to FDS8880(SB000004U8L)
PQ40 change from BSO072N03S(SB00000418L) to FDS6670AS(SB000004T8L)
PL27 change from 1.4U_HMU1350(SH000004H8L) to 1.5U_SIL104(SH04215A08L)
Add PC261 0.01U_0402(SE068103K8)
Add PC262 and PC263 2200P_0402(SE074222K8L)
PR219 change from 825_0402_1%(SD03482508L) to 1.43K_0402_1%(SD03414318L)
C PR220 change from 825_0402_1%(SD03482508L) to 2.1K_0402_1%(SD03421018L) C
PR223 change from 69.8K_0402_1%(SD03469828L) to 124K_0402_1%(SD03412438L)

PR224 change from 60.4K_0402_1%(SD03460428L) to 124K_0402_1%(SD03412438L)
19 49 PWR 06/29 Saha ISL6260 Issue Delete PR338, PR339 and PR340 2.7_0603_5%
Change PC246, PC247, PC248 to 1500P_0805-----Unpop 0.3
Change PH1 from ERTJ1VR103J(SL20000020L) to NCP15WM474J03RB(SL20000098L)
PR284 change from 15.8K_0402_1%(SD03415828L) to 0_0402_5%(SD02800008L)
Add PC260 0.1U_0603(SE042104K8L)
20 50 PWR 06/29 Saha Change +VCHGR output CAP from 1206 to 1210 PC113 and PC114 change from 10U_1206(SE142106M8L) to 10U_1210(SE056106K8L)0.3
21 47 PWR 08/12 Saha Add VSEN capacitor Add PC265 and PC264 100P_0402_50V8K(SE071101K8L) 0.4
22 47 PWR 08/12 Saha Delete PGOOD pull high resistor Delete PR283 100K_0402_1%(SD03410038L) 0.4
B
De-pop PR195 100K_0402_1%(SD03410038L) B
23 48 PWR 08/12 Saha Delete reliability test resistor Delete PR283 110K_0603_1%, PR359 0_0603_1%, and PR82 59.6K_0603_1% 0.4
24 49 PWR 08/12 Saha Adjust VCORE load line PR267 change from 7.87K_0402_1%(SD03478718L) to 9.09K_0402_1%(SD034909100)0.4
PR231, PR331, and PR270 change from 7.68K_0402_1%(SD00000238L) to
7.68K_0805_1%(SD00000B08L)
25 49 PWR 08/12 Saha Delete H_PROCHOT# resistor Delete PR235 0_0402_5%(SD02800008L ) 0.4
26 50 PWR 10/17 Saha Add RC filter in FBSA/B PIN Add PR368 and PR369 100_0402_5%(SD02810008L) 0.5
Add PC266 and PC267 0.01U_0603_50V7K(SE025103K8L)
Un-pop PR371 and PR370 0_0402_5%
27 46 PWR 10/17 Saha EMI request: change BST3 resestor Change PR32 from 0_0603_5%(SD01300008L) to 2.2_0603_5%(SD013220B8L) 0.5
28 46 PWR 10/17 Saha change 3V out put CAP height change PC31 from 330U_6.3V_R25 H1.9(SGA00001C8L ) to
A
330U_6.3V_R25 H2.8(SGA0000089L) 0.5 A
Title
5 4 3 2 1
5 4 3 2 1

Request
D D
29 50 PWR 10/17 Saha Populate UL circuit Populate PR361-PR367, PC254-259, PU19, PQ81. 0.5
Change PR361 from 80.6k to 0. Change PR362 from 200k to 301k.
Change PR363 from 121k to 59k. Change PR364 from 3.01k to 27.4k.
Change PR365k from 499k to 4.32Meg.
30 49 PWR 10/20 Saha Change VCC_CORE OCP, SOFT, PR260 change from 20K_0402_1%(SD03420028L) to 11.5K_0402_1%(SD03411520L) 0.5
and DPRSTP# value PC187 change from 0.022U_0402_16V7K(SE076223K8L) to
0.01U_0402_16V7K(SE076103K8L)
Add PR372 0_0402_5%(SD02800008L)
Delete PR246 0_0402_5%(SD02800008L)
Un-pop PR249 0_0402_5%(SD02800008L)
31 48 PWR 10/20 Saha Change PU6 BST resistor PR73 change from 0_0603_5%(SD01300008L) to 1_0603_5%(SD013100B8L) 0.5
32 44 PWR 10/20 Saha Change PQ2 from RUH002N06 to 3904 PQ2 change from RHU002N06(SB50206008L) to MMST3904(SB000002R0L) 0.5
C PR267 change from 9.09K_0402_1%(SD03490918L) to 10.5K_0402 _1%(SD03410528L) C
PR261 change from 3.57K_0402_1%(SD03435718L) to 2.47K_0402 _1%(SD03424318L)

33 49 PWR 11/12 Saha Adjust CPU Load Line Add PC252 100U_25V_(6.3X7.7)(SF10004M08L) 0.5
Add PC215 0.068U_10VX7R_0402 (SE102683K8L)
Add PD54 1SS355_sod323(SC1SS35500L)

34 50 PWR 12/6 Saha Deeply dischargered battery problem. Add PR373 1K_0603_1%(SD01410018L) 0.5
35 50 PWR 12/6 Saha Follow Coe A09 schematic Add PC267 3300PF_0402_50V7K(SE074332K8L)
Depop PC266 0.01U_0603_50V7K(SE025103K8L) 0.5
36 47 PWR 12/15 Saha Follow GGL 1214 item19. Depop PR12 0.6
37 49 50 46 PWR 1/7 Saha For acoustical issue Add PC270~PC273 and PC268 10U_1206_25V6M(SE142106M8L) 0.6
B B
A A
Title
5 4 3 2 1

DELL D620 Schematics Document (UMA) - LA-2791

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Travis (UMA) Schematics Document 2

uFCPGA Mobile Yonah

Date: Tuesday, February 07, 2006 Sheet 1 of 63

FAN Thermal Pentium-M

2 DMI USB[5,6] REAR USB Ports X2 USB4 on right side of 2

+1.5V_RUN connector, USB6 on left side

48MHz USB[3,4] SIDE USB Ports X2

Tantalum or Polymer Capacitors : power +5V_ALW

10U_D2_10VX_R45 +1.8V_SUS +1.5V_RUN

Package Size S3 ON ON OFF

Value S5 S4/AC ON OFF OFF

S5 S4/AC don't exist OFF OFF OFF

Capacitor Spec Guide:

CODE Z5U Z5V Z5P Y5U Y5V Y5P X5R X7R

0 Mini 2(WLAN) 1 PC Card Bay

NPO COG X6S BJ CH CJ CK SH SJ

3,4 SIDE 4 Blue tooth

+-10% +-20% +-30% +100,-0% +30,-10% +20,-10% +40,-20% +80,-20% NOTE1:

SI3456 SI3456 793475 PL8 SI4800 SI3456 SI4800 SI4800 SI3456

2.2K 2.2K 2.2K 2.2K

ICH7-M ICH_SMBDATA CLK GEN.

DAT_SMB +3.3V_ALW GUARDIAN 197

DOCK_SMB_DAT +3.3V_ALW DOCKING SMBUS Address [C4, 72, 70, 48]

Macallan IV SBAT_SMBDAT +3.3V_ALW INV Inverter

+3.3V_RUN +CK_VDD_MAIN CLK_CPU_ITP 2 1

FCTSEL1 PIN43 PIN44 PIN47 PIN48 10K_0402_5%~D R1395 1 2 10K_0402_5%~D +3.3V_RUN

0 DOT96T DOT96C 96/100M_T 96/100M_C 68 51 PCIE_MINI1# 1 2 CLK_PCIE_MINI1#

A DOT96_SSC R1640 1 10K_0402_5%~D A

Solder Thermal Pad to GND. Add min. 4 vias. SLG84450VTR_QFN72~D

DINV0# J26 H_DINV#0 10

H_THERMDA, H_THERMDC routing together.

Length match within 25 mils

VCCSENSE AF7 AB26 AE18 K1

2 2 VCCP VSS VCC VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

1 2 VSSSENSE G21 AC16 AB9 A19

VID0 VSS VCC VSS

VCC VSS VCC VSS

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1 1 1 1 1

Place these inside 1 1 1 1 1 1

High Frequence Decoupling

Near VCORE regulator.

South Side Secondary 1 1 1 1 1 1 North Side Secondary

2 2 2 2 2 2 Capacitor > 1980uF

7mOhm 7mOhm 7mOhm 7mOhm 7mOhm 7mOhm

+ Place these inside

A CRB was 270uF A

HD31# H_REQ#[0..4] 7 17 M_CLK_DDR#3 SM_CK3# CLK_REQ#

H_D#59 AC6 16 PM_EXTTS#0 PM_EXTTS#0 F25 F7

H_D#61 AD10 B7 H_RESET# 18 THERMTRIP_MCH# G6 AF11

HD63# HTRDY# 100_0402_1%~D R441 RSTIN# RESERVED8

Stuff R435 & R437 for A1 Calistoga

DDR SYS MEMORY A

DDR SYS MEMORY B

CALISTOGA A0_FCBGA1466~D CALISTOGA A0_FCBGA1466~D

LOW = Moby Dick

EXP_RXN0 F34 Strap Pin Table

EXP_TXN4 L36 Low = Normal *

TVIREF J20 M40

EXP_TXN6 N36 CFG19

B16 TV_IRTNA EXP_TXN7 P40 Lane number in Order