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It has been fifty years since the invention of the transistor. The technology
behind this topic cannot be addressed adequately in a single presentation, but has
been separated into four modules:
Module 1: Basic Principles
Module 2: Transistor Design and Manufacturing Overview
Module 3: Semiconductor Manufacturing Processes
Module 4: Semiconductor Economics
In this third module, we will review the key semiconductor processes,
materials and equipment used to fabricate devices, and discuss process conditions
and chemistry.
Semiconductor Manufacturing Processes
The process of building a chip’s circuitry involves several different basic steps
that are repeated many times. These steps are:
• Design
• Wafer Preparation
• Front-end Processes
• Photolithography
• Etch
• Cleaning
• Thin Films
• Planarization
• Test and Assembly
I will describe each process following the typical sequence for making
leading-edge semiconductor devices.
Chamber Cleaning
Insitu chamber cleaning processes are used to extend the time that machines
can be operated between manual chamber cleaning processes.
Vacuum chambers are typically fabricated from 6061 aluminum alloy and
have either an anodized coating (aluminum oxides) or an aluminum fluoride (AlF)
passivation coating. Chamber hard-cleans, are performed infrequently (depending
on process, a interval of typically one week to monthly). Current generation
semiconductor vacuum process tool designs have evolved to a level of
sophistication where the surface composition and texture of the process
components is factored into the process design and in many cases is actively used
to capture effluent and by-products.
In deposition or etching processes, reaction by-products coat the walls of the
vacuum chambers. After these by-product coatings become too thick, they flake
off in small particles and deposit on the wafer, causing “killer” defects on the
electronic circuits being manufactured. The surface of the vacuum chamber is
treated to provide the ability to resist corrosion by aggressive cleaning agents or
process chemicals, hardness to resist physical wear, and surface texture to
minimize flaking (rough surfaces perform better than smooth surfaces in this
regard).Gas-phase cleaning has many advantages. Gas cleaning is free from
manual labor and is total cleaning, not only of the chamber, but cleans from the supply pipe up to
the exhaust pipe. It offers safe and complete cleaning and results in shorter MTOL (Mean Time
Off Line).
Planarization
Wafers are polished in a series of chemical and mechanical polishing processes called
CMP.
This process enables multiple layers of semiconductor metalization to be deposited,
allowing denser interconnection layers.
Chemical Mechanical Planarization (CMP)
Oxide Planarization
Chemical Mechanical Polish (CMP) provides planarity for the oxide dielectric used at
the metallization level. Advanced development is in the area of copper and aluminum
planarization. The chemistry of the slurry, the nature of the pad, and the mechanics of the
tool are all critical to achieving global planarization over a 300 mm wafer.
Metal Planarization
Chemical Mechanical Polish (CMP) provides planarity for the tungsten plug used at the
metallization level. Dishing is an issue for future processes, especially on soft metals such
as aluminum and copper.