EECS 16B Designing Information Devices and Systems II

Fall 2017 Miki Lustig and Michel Maharbiz Homework 1

This homework is due September 5, 2017, at 11:59AM.

1. Fundamental Theorem of Solutions to Differential Equations

In this question, you will discover the power of the fundamental theorem of solutions to differential equa-
tions. For convenience, we shall restate the theorem here.
Theorem. Consider a differential equation of the form,

dn y dn−1 y dy
n
(t) + α n−1 n−1
(t) + . . . + α1 (t) + α0 y(t) = 0
dt dt dt
Given n initial conditions of the form,

dy dn−1 y
y(t0 ) = a0 , (t0 ) = a1 , . . . , n−1 (t0 ) = an−1 ,
dt dt
there exists a unique solution (say, f ).

(a) Consider the following 2 functions.

∞
xn
φ1 (x) = ex , φ2 (x) = ∑ n!
n=0

Prove that φ1 (x) = φ2 (x) by showing that both functions satisfy the following differential equation:

df
(x) = f (x) with f (0) = 1
dx
Side note: Assume 00 = 1.
Solution:

Let’s first look at φ1 (x)

φ1 (x = 0) = e0 = 1
dφ1
(x) = ex
dx
So φ1 satisfies the conditions.

Now let’s look at φ2 (x)

∞
0n
φ2 (x = 0) = ∑ n!
n=0

EECS 16B, Fall 2017, Homework 1 1

 Removing the first term from the series, we get

00 ∞
0n
φ2 (x = 0) = +∑
1 n=1 n!

Zero to any positive finite power is zero, so we can say

∞
0n
∑ n! = 0
n=1
φ2 (x = 0) = 00 = 1

To find the derivative of φ2 (x), we can say

d ∞ ∞
df
∑ f (x) = ∑ (x)
dx n=0 n=0 dx
df d xn nxn−1
(x) = ( ) =
dx dx n! n!
dφ2 ∞
nx n−1
(x) = ∑
dx n=0 n!

If we remove the first term of the series, we get

dφ2 0x−1 ∞
nxn−1
(x) = +∑
dx 1 n=1 n!
dφ2 ∞
nxn−1
(x) = ∑
dx n=1 n!

Using the fact that

n 1
=
n! (n − 1)!
We can say

dφ2 ∞
xn−1
(x) = ∑
dx n=1 (n − 1)!

If we use substitution and let k = (n − 1), we get

∞ k
dφ2 x
(x) = ∑ = φ2 (x)
dx k=0 k!

Both φ1 and φ2 meet the conditions, therefore they must be the same function

(b) Consider the following 2 functions.

φ1 (x) = cos(x), φ2 (x) = cos(−x)

EECS 16B, Fall 2017, Homework 1 2

 Prove that φ1 (x) = φ2 (x) by showing that both functions satisfy the following differential equation:

d2 f df
2
(x) = − f (x) with f (0) = 1, (0) = 0
dx dx
Solution:

Initial conditions:

cos(0) = cos(−0) = 1

So both φ1 and φ2 satisfy f (0) = 1

Taking the first derivative of each:

dφ1
= − sin(x)
dx
dφ2
= sin(−x)
dx
Plugging in 0 for x:

− sin(0) = 0
sin(−0) = 0
df
Both functions satisfy dx (0) =0

Taking the second derivative of each:

d 2 φ1
(x) = − cos(x) = −φ1 (x)
dx2
d 2 φ2
(x) = − cos(−x) = −φ2 (x)
dx2
Both functions satisfy all three conditions, so φ1 (x) = φ2 (x)

2. Transistors and Boolean Logic

A Boolean formula can be implemented in digital circuitry using nMOS and pMOS transistors. In circuits,
the truth value 1 (true) is represented by a high voltage, called POWER (VDD ). The truth value 0 (false) is
represented by a low voltage, called GROUND (GND). In this problem, we will only use the truth values in
order to simplify notations. That is, if you see A = 1 for a point A, then it means the voltage of A is equal to
VDD . Similarly, if A = 0, then the voltage of A is equal to GND.
An inverter can be implemented with 1 nMOS and 1 pMOS, as shown in the figure below. When the input A
is 0, then the nMOS is OFF and the pMOS is ON. Thus, the output Y is pulled up to 1 because it is connected
to VDD . Conversely, when A is 1, then the nMOS is ON and the pMOS is OFF, and Y is pulled down to 0.
Therefore, the circuit implements the Boolean formula, Y = A.

EECS 16B, Fall 2017, Homework 1 3

 VDD
pMOS pull-up network

A Y

nMOS pull-down network

In general, a Boolean-formula circuit has an nMOS pull-down network to connect the output to 0 (GND)
and a pMOS pull-up network to connect the output to 1 (VDD ). The pull-up and pull-down networks in the
inverter example each consist of a single transistor.
In this problem, we will ask you to design pull-up networks when pull-down networks are given.

(a) The pull-down network of the Boolean formula (a 2-input NAND gate), Y = (A ∗ B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.

Solution:
From De Morgan’s laws, we have Y = A + B, which means that when A = 0 or B = 0, Y should be
pulled up to 1. Therefore we connect two pMOS transistors in parallel in the pull-up network.

EECS 16B, Fall 2017, Homework 1 4

 A B

(b) The pull-down network of the Boolean formula (a 2-input NOR gate), Y = (A + B), is given below.
Design the pull-up network (the dashed box) with 2 pMOS transistors.

A B

Solution:
From De Morgan’s laws, we have Y = A ∗ B, which means that when A = 0 and B = 0, Y should be
pulled up to 1. Therefore we connect two pMOS transistors in series in the pull-up network.

EECS 16B, Fall 2017, Homework 1 5

 A

A B

 
(c) The pull-down network of the Boolean formula, Y = (A ∗ B) +C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.

A
C
B

Solution:  
Let Z be Z = A + B. From De Morgan’s laws, we have Y = A + B ∗ C = Z ∗ C, which means that
when Z = 1 and C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in parallel
as in part (a). Then we connect the two pMOS transistors of Z and the one pMOS transistor of C in
series in the pull-up network.

EECS 16B, Fall 2017, Homework 1 6

 A B

A
C
B

 
(d) The pull-down network of the Boolean formula, Y = (A + B) ∗C , is given below. Design the pull-up
network (the dashed box) with 3 pMOS transistors.

A B

Solution:  
Let Z be Z = A ∗ B. From De Morgan’s laws, we have Y = A ∗ B + C = Z + C, which means that
when Z = 1 or C = 0, Y should be pulled up to 1. For Z, we connect 2 pMOS transistors in series as in
part (b). Then we connect the two pMOS transistors of Z and the one pMOS transistor of C in parallel
in the pull-up network.

EECS 16B, Fall 2017, Homework 1 7

 A

B C

A B

(e) You have designed four pull-up networks. What can you conclude about the rules for designing pull-up
networks when pull-down networks are given?
Solution:
The pull-up network is the complement of the pull-down network. Series connections of transistors
are changed to parallel connections, and vice versa.
Recall that the reason that we design things this way is to prevent power from being burned unneces-
sarily when the logical state is not changing. With this complementary configuration, either the top or
bottom network will be an open circuit. There will never be a path connecting VDD to ground.
(f) For the circuit below, write the truth table for inputs A and B with output Y. What boolean operation
is this?
Note some of the gate voltages are Ā and B̄

EECS 16B, Fall 2017, Homework 1 8

 Ā B̄

A B

A Ā

B B̄

Solution: In CMOS, if the gate of an nMOS is 1, the switch is closed and acts as a resistor. If the
gate voltage is 0, then it acts as an open. The opposite is true for pMOS.
To get the truth table, draw the circuit for each input case and see whether the output is connected to
ground or VDD
This is what the circuit should look like for A=0 B=0:

EECS 16B, Fall 2017, Homework 1 9

 Y

Y is connected to ground through resistors, so for the input combination A=0 B=0, Y=0. Repeat this
for the 3 other cases and you will get the following truth table:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
This circuit is an XOR gate (A ⊕ B)

3. RC Circuit
Consider the circuit below, assume that when t ≤ 0, the capacitor has no charge stored (Vc (t = 0) = 0). At
t = 0, the switch closes. Assume Vs = 15 V, R = 500Ω, and C = 100µF.

(a) What are the boundary conditions for Ic (t) (i.e. what is Ic (t = 0) and Ic (t → ∞)?)

EECS 16B, Fall 2017, Homework 1 10

 t =0 IR (t) R
+ −
VR (t)
+ Ic (t)

+ V Vc (t)
− s C

Figure 1: RC Circuit with Voltage Source

Solution:

No charge is on the capacitor before time t = 0. Using q = VC, we know that Vc = 0V before t = 0.

At t = 0, the switch closes we can use KVL to say

Vc +VR −Vs = 0

Since voltage across a capacitor cannot change instantaneously,

Vc (t = 0) = 0

which means

VR (t = 0) = Vs

From here we can use Ohm’s Law to get

Vs 15
Ic (t = 0) = = = 0.03A
R 500
As t goes to infinity, the capacitor will become fully charged and block all current. Therefore

Ic (t → ∞) = 0A

R
(b) Use KVL and the relationship between charge and current (q = Idt) to find the first order differential
equation in terms of the current through the capacitor, Ic . Assume dV
dt = 0 (Hint: you will need to take
s

a derivative with respect to time to get the equation)

Solution:

From KVL we get:

V1 +VR −Vs = 0

Using Ohm’s law and q = VC:

q
+ IR R −Vs = 0
C

EECS 16B, Fall 2017, Homework 1 11

 Since R and C are in series, we can say:

IR = Ic

Substituting q in terms of I, we get:

R
Ic dt
+ Ic R −Vs = 0
C
dIc
To get the differential equation in terms of Ic and dt , we take the derivative with respect to time:

Ic dIc dVs
+R − =0
C dt dt
dVs
dt = 0, so we end up with:

Ic dIc
+R =0
C dt

(c) What is the eigenvalue λ of this equation?

Solution:

We can rearrange the equation to

dIc Ic
=−
dt RC
Since this is a first order differential equation, λ is equal to the coefficient of the Ic term.
1
λ =−
RC

(d) Using the eigenvalue and boundary conditions found in previous parts, find an expression for Ic (t) in
terms of Vs , R and C
Solution:

The general solution to the equation

dy
= Ay
dt
is

y(t) = Keλt

Where K is a constant and λ is the eigenvalue of the equation. To find K, we can plug in our boundary
condition at t=0
0 Vs
Ic (t = 0) = Ke− RC =
R

EECS 16B, Fall 2017, Homework 1 12

 From this we can see
Vs
K=
R
So our overall equation ends up being
Vs − t
Ic (t) = e RC
R
We can also double check our answer by looking at the steady state boundary condition:
Vs −∞
Ic (t → ∞) = e =0
R
Which agrees with our answer from part (a)

(e) What order of magnitude of time (nanoseconds, milliseconds, 10’s of seconds, etc.) does this circuit
settle (Ic is <5% of it’s initial value)?
Solution:

The time constant τ of an RC circuit is just R*C. For our circuit:

τ = RC = 500Ω ∗ 100µF = 0.05s
After 3 time constants, the current will be 5% of it’s initial value
3τ = 0.15s
The circuit will settle on the order of tenths of seconds.

(f) Give 2 ways to reduce the settling time of the circuit if we are allowed to change one component in the
circuit.
Solution: to reduce settling time, reduce τ. We can achieve this by
1) Lowering the value of R
2) Lowering the value of C
Notice how the value of Vs does not change the settling time
(g) Sketch the current vs time plot of Ic (t) Make sure to label Ic (t) at t = 0, t = τ, t = 2τ, and t = 3τ
Solution:
Vs − t
Ic (t) = e RC
R
Ic (t) = 0.03e−20t
Ic (0) = 0.03A
Ic (τ) = 11.0mA
Ic (2τ) = 4.06mA
Ic (3τ) = 1.49mA

EECS 16B, Fall 2017, Homework 1 13

4. From Transistors to Inverter
The following circuit is an inverter built with one pMOS and one nMOS transistor. We assume Vout is
connected to the input of another identical inverter (not shown). We also assume there is a capacitance con-
nected between Vout and GND. In real transistors, this capacitance arises from a combination of capacitances
contributed by the transistors of both the inverter in question and any inverters connected to the output. For
the moment, we’ll just call this capacitance CL (for load). The resistances associated with the pMOS and
nMOS are RonP and RonN , respectively. Let the threshold voltage of the pMOS be Vt p , while that for the
nMOS be Vtn . We will now model the action of the inverter as an RC circuit with two switches controlled
by Vin as what we did in lectures.

(a) For starters, what are the on-off conditions of the two switches? Please draw the RC circuit modeling
this inverter.

EECS 16B, Fall 2017, Homework 1 14

 VDD

Vin Vout

GND

Solution:
VDD

RonP

Vin Vout

CL

RonN
GND

The upper switch is controlled by the voltage difference between gate (G) and source (S) voltages of
the pMOS. In this circuit, VG = Vin and VS = VDD . The on-condition for pMOS is VGS ≤ Vt p , where Vt p
is a negative number, around -0.4. Usually VDD is greater than |Vt p |. If VG = Vin = 0, VGS = VG −VS =
−VDD < Vt p , the switch will be on. If VG = Vin = VDD , for pMOS, VGS = VG −VS = 0 > Vt p , the switch
will be off.
The lower switch is controlled by the voltage difference between gate (G) and source (S) voltages of
the nMOS. In this circuit, VG = Vin and VS = GND. The on-condition for nMOS is VGS ≥ Vtn , where
Vtn is a positive number, around 0.4. If VG = Vin = VDD , VGS = VG −VS = VDD > Vtn , the switch will be
on. If VG = Vin = 0, for nMOS, VGS = VG −VS = 0 < Vtn , the switch will be off.
(b) Assume Vin = VDD for t < 0, and Vin = 0 for t ≥ 0. In other words, we are assuming the input to our
inverter can switch states infinitely fast (this is not true in real life, but gives us a good lower bound on
how fast an inverter can switch). How much energy does it take to fully charge CL ? Solution: When
Vin = VDD (for t < 0), nMOS is on, while pMOS is off. Vout is shorted to RonN , and there is no charge
on CL . Then when Vin becomes 0 for t ≥ 0, nMOS is off while pMOS is on. Vout is shorted to RonP ,

EECS 16B, Fall 2017, Homework 1 15

 and we start to charge CL . The energy spent on charging CL is QVDD = CL (VDD )2 . Notice that the
energy stored on this capacitor is QV2DD , but for charging CL , part of the energy is dissipated through
the resistor. The power supplied by the voltage source is V I, while the power dissipated by the resistor
is I 2 R. To compute the total energy taken to charge CL , you need to integrate power over time: Here
−t
I = (VDDR−V
onP
out )
= RVonP
DD
× e RonPCL , total energy is

V2 h −t i∞ V 2
Z ∞ 
VDD R −tC
VDD × e onP L dt = DD × (−RonPCL ) e RonPCL = DD × (−RonPCL ) [0 − 1] = CL (VDD )2
0 RonP RonP 0 RonP

(c) Given the same condition as in (b), write down the differential equation that describes Vout (t) for t ≥ 0.
Solution: The current goes through the resistor RonP is the same as the current through CL . Therefore,
we could write down the differential equation as
dVout (VDD −Vout )
CL =
dt RonP
.
(d) What is the solution to this differential equation? Plot Vout (t) for t > 0.
Solution: We could decompose Vout into a steady state function (Vss ), and a transient function
(Vtransient ): Vout = Vss + Vtransient , such that dVdtout = dV
dt +
ss dVtransient
dt . The steady state value of Vout is
VDD (a constant), because in a long run, the capacitor behaves like an open circuit, while the resistor
behaves as a short circuit. That is, dVdtout = dVtransient
dt .
The initial state of Vtransient is −VDD , because the initial state of Vout = VDD + Vtransient is 0. Now we
could replace the variable Vout in the above differential equation with Vss +Vtransient and then keep only
the derivative of Vtransient at the left hand side, then we will get the following differential equation:
dVtransient (−Vtransient )
=
dt CL RonP
. The above differential equation looks like we apply some linear operator (derivative) to a function of
time, such that the derivative of this function is itself with a scalar. We are finding an eigen-function
of this linear operator! The solution to the differential equation should be in the form of Aest , where A
and s are some constants. Compare the desired form and the differential equation, we could conclude
−t
s = CL−1 s0
RonP . The initial state (t = 0) for Vtransient is Ae = A = −VDD , so Vtransient = −VDD × e
RonP CL
.
Finally, let’s put Vtransient and Vss together, we could get
−t
Vout (t) = VDD −VDD × e RonPCL

Here we set VDD as 5 volt, RC = RonPCL = 0.05, 0.1, 0.2.

(e) The term propagation delay is used to describe the amount of time it takes between when the input
reaches VDD VDD
2 and when the output reaches 2 . Calculate the propagation delay for our inverter above
(keep in mind that the input to our inverter changes instantly). Is propagation delay a function of VDD ?
−t pd
Solution: Find t pd such that Vout (t pd ) = VDD
2 . Then we need e
RonP CL
= 12 . Take natural log of the both
−t pd
sides: RonPCL ≈ −0.6931, then we know t ≈ 0.69RonPCL
In this question, propagation delay is not related to the value of VDD . In real devices, increasing VDD
does, in fact, speed up the inverter because of transistor effects we have not discussed in this class
(namely, increasing VDD has a minor effect on the RonP and RonN of the transistors). For future refer-
ence: http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/
chapter5.pdf

EECS 16B, Fall 2017, Homework 1 16

 (f) Now consider a serial chain of inverters, each driving the one before it. If we assume that |Vtn | =
|Vt p | = VDD
2 what is the propagation delay for one of these inverters, given (d) and (e)? (If you like,
ignore the first inverter and assume it is driven by an input as in (a)). Here we let RonP = RonN = R.
Solution: Once the input voltage(output of the previous stage) reaches VDD
2 , the switch of the inverter
in the next stage will turn on/off.
Consider the above case, the propagation delay is the same, t ≈ 0.69RonPCL , because when Vin changes
from VDD to VDD2 (and continue to be 0), pMOS is on, while nMOS is off. Then this circuit starts to
charge CL . Hence the propagation delay is the time spent on charging CL from 0 to VDD 2 , which is
≈ 0.69RonPCL = 0.69RCL
Consider the other case: the input voltage is changing from 0 to VDD , while initially the capacitor is
charged to VDD , and pMOS is on, nMOS is off. When the input voltage reaches VDD 2 ,pMOS is turned
off, and nMOS is turned on. Then the capacitor starts to discharge.
The differential equation describing Vout is
dVout −Vout
CL = ,
dt RonN
where the initial state of Vout is VDD . Following the same procedure in (d), we could derive
−t
Vout (t) = VDD × e RonN CL

.
−t
Now let’s compute the time needed to reach Vout = VDD
2 : we need e
RonN CL
= 12 . Therefore t ≈ 0.69RonN CL =
0.69RCL .
(g) Now let’s consider the following scenario: there are N inverters on the chip in your cell phone. It takes
E Joules of energy to charge all of the inverters at once (from zero to VDD ). What is the value of CL ?
Solution: The energy required to charge one inverter is CL (VDD )2 , so to charge N inverters together,
we need E = CL (VDD )2 × N. That is, CL = N(VEDD )2 .
(h) Here we interpret a voltage V as logic "1" when V > VDD VDD
2 , and logic "0" when V < 2 . Let’s assume
the maximum frequency, f , at which an inverter can switch back and forth between logic "0" and
logic "1" at the output is the inverse of the propagation delay (i.e. we can only switch as fast as one
propagation delay). Find an expression that links f , CL , and R.

EECS 16B, Fall 2017, Homework 1 17

 Solution: According to the answer to (f), the propagation delay is about 0.69RCL , no matter it is
1 1
from "0" to "1" or from "1" to "0". Therefore f = t pd = 0.69RCL

5. Digital-analog converter
A digital-analog converter (DAC) is a circuit for converting a digital representation of a number (binary)
into a corresponding analog voltage. In this problem, we will consider a DAC made out of resistors only
(resistive DAC) called the R-2R ladder. Here is the circuit for a 3-bit resistive DAC.

Let b0 , b1 , b2 = {0, 1} (that is, either 1 or 0), and let the voltage sources V0 = b0VDD , V1 = b1VDD , V2 = b2VDD ,
where VDD is the supply voltage.
As you may have noticed, (b2 , b1 , b0 ) represents a 3-bit binary (unsigned) number where each of bi is a
binary bit. We will now analyze how this converter functions.

(a) If b2 , b1 , b0 = 0, 0, 1, what is Vout ? Express your answer in terms of VDD .

Solution: There are several ways to solve this problem. For this solution set, we are going to solve
for the generic solution rather than solve for each specific case of (a), (b), (c), and (d).

V1 R V2 R
Vout

2R 2R 2R 2R

+ bV + +
− 0 DD − b1VDD − b2VDD

Using KCL at nodes V1 , V2 , and Vout , we get

V1 V1 − b0VDD V1 −V2
+ + =0
2R 2R R
V2 − b1VDD V2 −V1 V1 −Vout
+ + =0
2R R R
Vout − b2VDD Vout −V2
+ =0
2R R

EECS 16B, Fall 2017, Homework 1 18

 solving this system of equations leads to
b2VDD b1VDD b0VDD
+ + = Vout
2 4 8
Plugging in 0,0,1 gives us the answer
VDD
Vout =
8
(b) If b2 , b1 , b0 = 0, 1, 0, what is Vout ? Express your answer in terms of VDD .
Solution: Plugging into the equation from part (a), we get
VDD
Vout =
4

(c) If b2 , b1 , b0 = 1, 1, 1, what is Vout ? Express your answer in terms of VDD .

Solution: Plugging into the equation from part (a), we get
7VDD
Vout =
8

(d) If b2 , b1 , b0 = 1, 0, 0, what is Vout ? Express your answer in terms of VDD .

Solution: Plugging into the equation from part (a), we get
VDD
Vout =
2

(e) Finally, solve for Vout in terms of VDD and the binary bits b2 , b1 , b0 .
Solution: From part (a)
b2VDD b1VDD b0VDD
+ + = Vout
2 4 8

(f) Explain how your results above show that the resistive DAC converts the 3-bit binary number (b2 , b1 , b0 )
to the output analog voltage VDD .
Solution: Every increment of 18 VDD on VDD represents an increment of 1 to the 3-bit binary number
(b2 b1 b0 )
For example, if Vout = 85 VDD , the input was 5 in binary (1 0 1)→ (b2 = 1 b1 = 0 b0 = 1).

Contributors:

• Siddharth Iyer.
• Yen-Sheng Ho.
• Kyle Tanghe.
• Yu-Yun Dai.
• Edward Wang.

EECS 16B, Fall 2017, Homework 1 19