Lab 2.

Using Xilinx Platform System (XPS)

Objective
The aim of the lab is to become familiar with XPS, and use software (which will run on
the PowerPC microprocessor on the FPGA) to control the LEDs.

In lab1, we used hardware (using Verilog to program the FPGA to control the LEDs). In
this lab, we will use software (C code running on the PowerPC), in order to control the
LEDs.

This lab is divided into two parts. The solutions to the problems at the end of Part A need
to be submitted by the end of first week and the solutions to problems in Part B, by the
end of the second week.

Overview

The block diagram for the complete system on the XUP board is shown in Figure 1.

OPB
Bus
PLB
Bus UART

GPIO Switches
PLB2OPB
PPC0 Push
GPIO
Button
PLB BRAM PLB BRAM
Cntlr
PPC1 GPIO LED
PLB BRAM PLB BRAM
Cntlr Timer

INTC

Figure 1. Complete System

The system consists of two buses – the Peripheral Local Bus (PLB) and the On-chip
Peripheral Bus (OPB). The PowerPC and PLB BRAM (Block RAM) controllers are
connected to the PLB Bus. A PLB2OPB Bridge connects the PLB Bus to the OPB Bus.
The peripherals are connected to the OPB Bus.
Switches, push buttons, LEDs, etc are General Purpose input-output (GPIO) devices.
Procedure
Create an empty directory called ‘lab2’ (for example, in C:/449). In Step2, we will
specify this directory as the location where all the project related files should be created
and stored.

PART A: Base System Builder (BSB): We will use the BSB to set up the design
environment.

1. Launch XPS and create a new project

Select Start → Programs → Xilinx Platform Studio 8.2i → Xilinx Platform
Studio Alternatively, double click on the XPS icon on the desktop.

The XPS window, prompting to create or open an exisiting project pops up as

shown in Figure 2.

Figure 2. Select Base System Builder

Chose Base System Builder Wizard and click OK.

2. Select the path for ‘lab2’ directory followed by system.xmp in Project File.
 Figure 3. BSB
3. In the Select Board dialog, chose:
Board Vendor: Xilinx
Board Name: XUP Virtex-II Pro Development System
Click Next.
 Figure 4. Select Board

4. Now, the Select Processor Dialog Box opens (shown in Figure 5).

The XUP board is equipped with a PowerPC hard processor core as well as a
MicroBlaze soft processor core. PowerPC is a hard processor core. It means that
you don't have to use it, but you can't remove it. It is a part of the hardware of the
chip. The Microblaze is a virtual microprocessor that is built by combining blocks
of code called cores. You only use as much of the processor as you desire.
We will be using PowerPC for our experiments.

Select PowerPC and click Next.

Figure 5. Select Processor

5. Configure the processor using the following options:

Reference Clock Frequency: 100 MHz

This the external clock source on the board you are using. This clock will be
used to generate the processor and bus clocks. The values of processor clock
allowed may depend on the FPGA or board you are using because certain on-
chip resources (Digital Clock Manager or DCM) may be required to perform
clock division or multiplication. Let’s chose a processor clock frequency of
100MHz.
Processor Clock Frequency: 100 MHz
Bus Clock Frequency: 100 MHz
JTAG Debug Interface: FPGA JTAG
On-Chip Memory (OCM) – Data: NONE
On-Chip Memory (OCM) – Instruction: NONE
 Figure 6. Configure PowerPC

6. Now, the ‘Configure IO interfaces’ dialog box appears. Check the RS232_Uart_1
option, and fill in as shown in Figure 7 (select 11520 as the Baud Rate). RS232
will be used to transfer the data from the host computer (the computer on which
you are working right now!) to the PowerPC.

Deselect Ethernet_MAC. In the next few windows, deselect all other peripherals
till you reach plb_bram_if_ctrl_1.
 Figure 7. Configure IO interface RS232

7. Add PLB BRAM (see Figure 8). The PowerPC needs some memory, to store and
run the software applications. We thus need to add a PLB_BRAM block.

Figure 8. Add Internal Peripherals: PLB BRAM

8. In the Software Setup window, choose RS232_Uart_1 as the device for STDIN
and STDOUT. Uncheck both Memory test and Peripheral selftest (If checked,
they generate the software code for testing Memory and peripherals) under
Sample Application selection. Click Next.
 Figure 9. Software Setup

9. In the screen that shows up, you will see a summary of the system you have
created. Click Generate. Click Finish to finish generating the project and OK to
start using XPS.

Figure 10. System Created

 10. The Base System has been created. Click on Hardware → Generate Netlist. It may
take several minutes. This will set up the hardware we have selected using the
BSB.
11. Click or select Software → Generate Libraries and BSPs to generate libraries
for the project. This will create header file in the directory ppc405_0/include.

Now, explore your ‘lab2’ directory. The following directories should be present in your
‘lab2’ directory (a brief description of the files contained by each is provided; we would
be modifying some of these, to achieve the desired functionality).
• data (contains UCF file that stores pin location and timing constraints)
• etc (contains option file for controlling ISE tools and command file for controlling
FPGA configuration)
• hdl (wrapper files for system, processor, and peripherals)
• implementation (netlist files for peripherals)
• pcores (repository for peripherals)
• ppc405_0, ppc405_1 (software related files for the two PowerPCs)
• synthesis (files resulting from synthesis)
• _xps (option files for various point tools in EDK)

In our lab exercises, we will understand and modify the ucf file in data directory,
software files in ppc405_0 and user-defined hardware (Verilog) files in pcores directory.
For Lab 2, we are not adding any Verilog code, the pcores directory will therefore be
empty.

Deliverables – Part A
In the XPS window, you will see the ‘Project Information Area’ on the left and ‘System
Assembly View’ on the right.

1. Demonstrate your base system to the TA [2 points]

You need to turn in a laboratory report for this lab. This report should contain the
information below.
2. From the ‘Addresses’ tab in the ‘System Assembly View’ window, note down the
Base Address, High Address and size of RS232_Uart_1. Also, note the
XPAR_RS232_UART_1_BASEADDR and
XPAR_RS232_UART_1_HIGHADDR from the file xparameters.h in
ppc405_0/include directory. [2 points]
3. Suppose I manually change the base address for the RS232_Uart_1 to a smaller
value. What problem could this cause, if any [3 points]
4. In Figure 6, we chose the “bus clock frequency” to be 100MHz. Under what
conditions would we prefer to have a lower bus clock frequency? [3 points]
 12. Cleanup your hardware and software (we will build it again after making the
required modifications). Click on Hardware → Clean Hardware followed by
Software → Clean Software. Save a copy of the directory lab2, as we will build on
the Base System Builder created, in the next lab (Lab 3) as well.

Now that the base system is setup, we will be interfacing the LEDs.

13. From the ‘Project Information Area’, click on the IP Catalog tab. It shows various
hardware blocks on the XUP board.

Figure 11. IP Catalog

Expand General Purpose IO. Right click on opb_gpio (3.01.b) and select Add IP.

14. opb_gpio_0 can be seen in the list of instances in the System Assembly Tab (as
shown in Figure 12).
 Double click on ‘opb_gpio_0’ and rename it to LEDS.
Also, connect LEDS to the OPB bus by clicking on the empty circle seen at the
connection between the OPB bus and opb_gpio_0 instance. The circle will be
filled in green color to indicate that a connection has been made.

Figure 12. opb_gpio added

Now, we need to specify that the data bus width for LEDS is four-bits, as we will
use it to interface with the 4 LEDs on the XUP board. Also, we will be writing
data to LEDs to change their value, thus the LEDs are outputs for our gpio.

To do this, right-click on LEDS and select Configure IP. Change the data bus
width to 4. Set Channel 1 “is Bi-directional” and Channel 1 “is Input Only” to
FALSE. Do NOT enable Channel 2.

15. The 4-bit port in the gpio LEDS has to be made External, to indicate that the LED
pins (on the XUP board) are external to the FPGA. To do this, select the Ports tab.
Expand LEDS, you can see the ports that can be accessed by the LEDS IP (Figure
13).
 Figure 13. Filter for LEDS

Change the Net name to LEDs_4Bit for GPIO_IO. From the drop-down list of
Net for GPIO_IO, select Make External. The LEDS port are external to the
FPGA. When you expand ‘External Ports’, you can see the LEDs_4Bit instance is
now in the list.
Click on the Filter (Applied) button, and select ‘All’. This will show some more
ports that are accessible by LEDS and are set to default values. For OPB_CLK,
change Default Connection to sys_clk_s.

16. Select Addresses under Filters. Set the Size to 64K click Generate Addresses.
Ignore the warning that pops up when you click on Generate Addresses. EDK will
assign the Base Address and High Address using available address space. You
can also modify the starting addresses if you prefer.

17. From the Projects Tab, open the UCF file system.ucf. Add the location for the
LED pins (similar to the UCF file created using PACE in Lab 1).
Net LEDs_4Bit_pin<0> LOC=AC4;
Net LEDs_4Bit_pin<1> LOC=AC3;
Net LEDs_4Bit_pin<2> LOC=AA6;
Net LEDs_4Bit_pin<3> LOC=AA5;
 Save the UCF file.

Now, Select Hardware → Generate Netlist. Our hardware is now setup for use,
and we need to write the software to control it.

18. In the XPS window, click on the Applications tab. Double-click on Add Software
Application project. Enter Project Name “lab2” and leave the Processor as
ppc405_0.

19. Click or select Software → Generate Libraries and BSPs to generate libraries
for the project. We shall be using two of the header files created in the directory
ppc405_0/include - xparameters.h contains base addresses of peripherals, and
defines parameters used to access peripherals in drivers and user programs; and
xgpio.h contains the functions for initializing, reading and writing to the GPIOs.

20. Right-click on Sources and select Add New File. Create a new file named “lab2”,
and add source code as follows:

#include<xparameters.h>
#include<xgpio.h>

int main() {
XGpio led;

XGpio_Initialize(&led, XPAR_LEDS_4BIT_DEVICE_ID);
XGpio_SetDataDirection(&led,1,0); //Set LEDS as output ports

while (1) {
XGpio_DiscreteWrite(&led, 1, 0x0);
printf(" Status of the leds is 0000\n");
sleep(1);
XGpio_DiscreteWrite(&led, 1, 0xF);
printf(" Status of the leds is 1111\n");
sleep(1);
}
}

21. Select Software → Generate Linker Script. A valid linker script should be
generated.

22. Right-click on Project: lab2 and select ‘Mark to Initialize BRAMs’. Make sure
ppc405_0_bootloop and ppc405_1_bootloop are NOT marked to initialize
BRAMs. Otherwise, the power PCs will stay in a bootloop, and the software will
not be used.
 23. Click or select Software → Build All User Applications. This will generate an
executable .elf file for the program, if no error occurs.

24. Click or select Hardware → Generate Bitstream. This should generate a

bitstream file (system.bit) which will be used to program the XUP board.

(You may see an error for IO Baking Rules in the Generate Bitstream or
Download Bitstream step. This is due to a bug in the software. If it happens, in
your .ucf file, change the IOSTANDARD for sys_rst_pin to LVCMOS25 and
compile your hardware again)

25. Now, turn on the power to the XUP board and setup the connection using
hyperterminal. Hyperterminal is a communication utility. It can be used to
transfer files from the host machine to the XUP board. You can add print
commands in your .c file; and the output will be printed on the hyperterminal.

Open hyperterminal by typing ‘hypertrm’ in start → Run.

Set COM1 as our connection. Click on Configure, and change the baudrate to
115200 (This is same as the Baud Rate we added for OPB_UARTLITE (Figure 7)
while using BSB) and flow control to None. Hit the Enter key in the Hyper
Terminal window to connect.

26. Click or select Device Configuration → Download Bitstream to download the

design (similar to device configuration done using iMPACT in Lab 1).

27. Notice the change in the status of LEDs. Also, note the LED status is printed on
the hyperterminal.

Deliverables – Part B

1. Demonstrate to the TA that the status of the leds changes as expected. [2 points]

2. Use the PowerPC to read the switches and write their value to the LEDs. The
status of switches should be seen on the LEDs (in the existing design, add a GPIO
IP for switches, in a similar manner as the LEDS were added). Demonstrate this
to tht TA [3 points]

Hints:-
- In Configure IP, declare switches as IO (bidirectional) ports.
- Remember to add the locations of the DIP switches in the .ucf file. You can get
these locations from the .ucf you created in Lab 1.
- The status from the switches should be read and written to the LEDS. We have
already done the task of writing to the LEDs in the experiment above.
You need to turn in a laboratory report for this lab. This report should contain the
information below.
3. What does the ‘while’ loop in the file leds.c do? [2 points]
4. Turn in your C code and UCF files for Part B of this lab. [3 points]