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TUTORIALS

Analog Electronics 2

rosdiyana
rosdiyana@ump.edu.my
Field Effect Transistor (FET)

1. What are the major differences between the collector characteristics of a BJT transistor and the
drain characteristics of a JFET transistor? Compare the units of each axis and the controlling
variable. How does IC react to increasing levels of IB versus changes in ID to increasingly negative
values of VGS? How does the spacing between steps of IB compare to the spacing between steps of
VGS? Compare VCsat to Vp in defining the nonlinear region at low levels of output voltages. [Q#6]

2. a) Describe in your own words why IG is effectively 0A for a JFET transistor.

b) Why is the input impedance to a JFET so high?


c) Why is the terminology field effect appropriate for this important three-terminal device? [Q#7]
3. In general, comment on the polarity of the various voltages and direction of the currents for an n-
channel JFET versus a p-channel JFET. [Q#9]

4. In what ways is the construction of a depletion-type MOSFET similar to that of a JFET? In what
ways it is different? [Q#27]

5. Explain in your own words why the application of a positive voltage to the gate of an n-channel
depletion-type MOSFET will result in a drain current exceeding IDSS. [Q#28]

6. What is the significant difference between the construction of an enhancement-type MOSFET and
a depletion-type MOSFET. [Q#35]

7. Given the transfer characteristics of Figure 1, determine VT and k and then write the general
equation for ID. [Q#37]

Figure 1
FET DC Biasing

Q1 [T1 201415-I]

Figure 1 shows graphs of n-channel E-MOSFET voltage-divider bias together with the
respective operating point. Given that the circuit is supplied by a 22 V supply. In order to
stabilize the performance of the circuit, the drain-to-source voltage is kept at 8 V while the
resistors that connected at the gate are kept at a very large resistance (around Mega Ohms).
(i) With the aid of a diagram, design the circuit by finding all the resistance value so that it
meets the requirement as stated in the graph. All resistance value must be in standard
commercial value.
(ii) What is the Threshold Voltage for the transistor?

Graph of VGS against ID


0.029
Current (A)

Voltage…
E-MOSFET…

0.008
E-MOSFET Curve,
8, 0.008

Voltage (V) 11

Figure 1
Q2 [T1 201516-I]
Figure 2 shows graphs of n-channel E-MOSFET drain-feedback configuration together with
its respective operating point. In order to stabilize the performance in low frequency, the
feedback resistor that connected between gate and drain terminals are kept at a very large
resistance (around Mega Ohms). To maximize the voltage gain, no resistor is connected
between the source terminal and the ground.
(i) With the aid of a diagram, design the circuit by finding all the resistance value so that it
meets the requirement as stated in the graph. All resistance value must be in standard
commercial value.
(ii) What parameter affecting the Q-point of the configuration?
(iii) How much the parameter you stated in (ii) need to be changed if we increase the VGSQ of
the configuration to 9 V? Given that the ID(on) and VGS(on) are 2 mA and 6 V respectively.

Figure 2

Q3 [T1 201617-I]
As a design engineer in XC Sdn Bhd, you were assigned to design a drain-feedback amplifier
using a 2N4351 E-MOSFET. The feedback resistance is set to 10 MΩ in order to prevent
reduction in the voltage gain, while, the drain resistance is three times higher than the source
resistance. In order to prevent sudden cut- off of the circuit, the operating voltage is equal to
3VTH. Given that the circuit is supplied by a 15 V supply with ID(on) = 3m A/V2 , VGS(on) = 10 V
and Threshold Voltage, VTH is 4V.
(i) Determine the commercial value of the RD and RS so that it meets the requirement as
needed in the design and construct the configuration with all the identified resistor
values.
(ii) What is the parameter that affecting the Q-point of the configuration?