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2344 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO.

4, AUGUST 2007

A Reduced-Switch-Count Five-Level Inverter With


Common-Mode Voltage Elimination for an
Open-End Winding Induction Motor Drive
Gopal Mondal, K. Gopakumar, Senior Member, IEEE, P. N. Tekwani, and Emil Levi, Senior Member, IEEE

Abstract—The paper presents a five-level inverter scheme with open up. Such a machine’s structure has been considered as
reduced power circuit complexity for an induction motor drive. a serious contender for high-power applications (traction and
The scheme is realized by cascading conventional two-level and similar) since the early 1990s [2]. In more recent times, it is
three-level neutral point clamped inverters in conjunction with an
open-end winding three-phase induction motor drive. An inverter looked at as a possible solution for electric vehicles/hybrid
control scheme with common-mode voltage (CMV) elimination, electric vehicles [14], distributed energy generation systems
along with a simple dc link voltage control, is developed by using [15], and electric ship propulsion [16], [17]. The basic idea is
only switching states with zero CMV for the entire modulation to supply the machine from both ends using inverters with a
range. Theoretical considerations are experimentally verified for certain (small) number of levels [2], [3], which results in mul-
a variety of operating conditions.
tilevel voltage across stator phase windings. Depending on the
Index Terms—Common-mode voltage (CMV) elimination, in- power level of the drive, two inverters that are connected at the
duction motor drives, multilevel inverter, open-end winding two ends of the stator winding can be of the same power/voltage
structure.
rating and can operate at the same switching frequency, or they
can be of very different power/voltage ratings in which case
I. I NTRODUCTION they operate at very different switching frequencies (the con-
cept of a “bulk” inverter operated at switching frequency equal

M ULTILEVEL inverters are nowadays the preferred


choice for high-voltage and high-power applications in
industry [1]–[11]. Typically, as the voltage level increases,
to the drive’s output frequency, and “conditioning” inverter, of
low power/voltage but operated at high switching frequency;
the intended application is for ship propulsion [16], [17]).
the power circuit complexity increases as well. Pulsewidth- When inverters at both ends of the stator winding operate
modulated inverters generate an alternating common-mode in PWM mode, at the same switching frequency, it becomes
voltage (CMV) at the motor terminals, which results in leakage possible to devise strategies for complete CMV elimination
current. This unwanted current causes bearing erosion and by selecting only those switching states that give zero CMV
motor failure. It is therefore desirable to eliminate or at least [18]–[22]. The simplest open-end winding supply configuration
reduce the CMV. Various strategies have been developed for re- consists of connecting to each side of the winding a two-
duction of the CMV in three-phase ac drives, and one approach, level inverter [2], [3], [20]. The CMV elimination strategy for
which is well suited to drives that are supplied from a multilevel such a structure has been developed in [19], [20]. It is also
inverter, consists of the design of modified pulsewidth mod- possible to connect a two-level inverter at one side and two
ulation (PWM) strategies that select only inverter states with cascaded two-level inverters (resulting in three-level structure)
reduced CMV. Such a PWM strategy for CMV reduction in the at the other side [18]. Operation with zero CMV is again
three-level neutral-point-clamped (NPC) inverter supplied drive possible by selecting appropriate switching states in the drive
is discussed in [12], whereas a CMV reduction method for the operation [18]. Another three-level inverter configuration with
cascaded H-bridge inverters is elaborated in [13]. CMV elimination has been described in [21]. This three-level
If a three-phase machine has a so-called open-end winding inverter structure has a higher number of redundant switching
(instead of the star-connected) structure of the stator winding, states for each voltage vector location as compared to the
new possibilities with regard to CMV reduction/elimination conventional three-level NPC inverter. The CMV is once more
eliminated by using only switching states with zero CMV in the
generation of the reference voltage space vector.
Manuscript received November 1, 2006; revised January 23, 2007.
A five-level inverter structure with CMV elimination is con-
G. Mondal and K. Gopakumar are with the Centre for Electronics Design sidered in [22] for an open-end winding induction motor drive.
and Technology, Indian Institute of Science, Bangalore 560012, India. The dual five-level structure is realized by connecting two
P. N. Tekwani is with the Centre for Electronics Design and Technology,
Indian Institute of Science, Bangalore 560012, India, and also with the Institute conventional two-level inverters and one conventional three-
of Technology, Nirma University of Science and Technology, Ahmedabad level inverter, in series, at each side of the three-phase stator
382481, India. winding. To eliminate the CMV, only switching states with
E. Levi is with the School of Engineering, Liverpool John Moores University,
L3 3AF Liverpool, U.K. zero CMV are used for PWM control. It is observed that there
Digital Object Identifier 10.1109/TIE.2007.899927 are more switching states present in the voltage space vector

0278-0046/$25.00 © 2007 IEEE


MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION 2345

Fig. 1. Power circuit of the nine-level inverter configuration formed by a dual


five-level inverter-fed open-end winding induction motor drive [22].
Fig. 2. Simplified dual five-level inverter-fed open-end winding induction
motor drive with CMV elimination developed in this paper.
locations than are required to eliminate the CMV [22]. The
topology of [22] presents the starting point for the development
TABLE I
of the configuration described in this paper. From a thorough POSSIBLE STATES OF THE SWITCHES FOR INVERTER SYSTEM A
study of the switching state redundancies available from the OR I NVERTER S YSTEM A’

power circuit presented in [22], it is observed that the power


circuit can be considerably simplified. In particular, two two-
level inverters are eliminated in the configuration analyzed here,
so that the topology is simplified and consists of a total of two
two-level and two three-level inverters. Although the numbers
of switching redundancies for the voltage vector locations are
lower in such a five-level inverter circuit, the CMV elimination
is still possible with the available switching states for the entire
range of operating speeds, as shown in the further development.
Developed power circuit and the PWM algorithm with com-
plete CMV elimination are experimentally verified on a 2.5-kW drive configuration. The switches are labeled in Fig. 2 as Sxy ,
open-end winding induction motor drive. where x = 1, . . . , 4 and y = 1, 2, . . . , 6. The maximum voltage
blocking capability that is required for the switches is Vdc /8 for
each switch of the two two-level inverters and Vdc /4 for each
II. F IVE -L EVEL I NVERTER S CHEME W ITH R EDUCED
switch of the NPC three-level inverters. For example, when the
P OWER C IRCUIT C OMPLEXITY
switch S11 is “on,” the voltage across S14 is Vdc /8, and when
The drive configuration of [22] is illustrated in Fig. 1. The S14 is “on,” the voltage across S11 is Vdc /8. Similarly, when
scheme uses a dual five-level inverter topology, where one S11 , S44 , S21 , and S24 are “on,” the combined voltage across
three-level and two two-level inverters are employed at each S31 and S34 is Vdc /2, so that the voltage across each switch is
side of the open-end winding induction motor drive. This results Vdc /4 (assuming equal voltage sharing by two switches).
in a voltage space vector structure that is equivalent to the The power scheme of Fig. 2 gives a significant reduction
nine-level inverter topology [22]. With the proper selection of in the circuit complexity, as compared to Fig. 1, and it also
the switching state combinations, motor phase voltages that leads to a reduction of the number of redundant switching
are equivalent to a five-level inverter with CMV elimination states. However, the available switching states are still sufficient
have been realized, and the zero CMV has been experimentally for the CMV elimination, as shown shortly. As the inverter A
demonstrated for a number of operating conditions. and inverter A’ of Fig. 2 share the two conventional two-level
The configuration of Fig. 1 is now simplified to the one of inverters, some restrictions in the combined switching states
Fig. 2 by removing two two-level inverters. Hence, the drive have to be added. This reduces the number of redundancies
configuration of Fig. 2 consists of two three-level inverters in the switching states for the voltage space vector locations.
(inverter A and inverter A’) and two conventional two-level In the inverter structure of Fig. 2, there are 241 switching
inverters that are common to both three-level inverters. Taken states that are distributed over 61 voltage space vector locations.
together, they again work as a dual five-level inverter that feeds Table I shows the states of the switches for obtaining different
the open-end winding induction motor from both ends. The voltage levels at the inverter poles (legs), where the pole (leg)
power circuit of Fig. 1 uses a total of 48 switches, whereas the voltages are measured with respect to the dc-link midpoint
circuit of Fig. 2, which is analyzed in the present paper, has a point “0” (Fig. 2). There are different complimentary pairs
total of 36 switches. Hence, a substantial reduction in the switch of the switches. The complimentary pairs for phase A are
count is achieved, as compared to [22], which leads to a simpler S11 –S14 , S21 –S34 , S24 –S31 , and S41 –S44 . For phase B, the
2346 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

TABLE II and, similarly, for inverter system A’


POSSIBLE COMBINATIONS OF VOLTAGE LEVELS FROM THE
INVERTER SYSTEM A AND INVERTER SYSTEM A’
VCMVA = (VA O + VB O + VC O )/3. (2)

The equivalent CMV for the combined inverter system (CMV


generated at the inverter phases) is

VCMV = VCMVA − VCMVA . (3)

It is observed from (3) that the resultant CMV VCMV can


be made zero either by individually making both VCMVA and
complimentary switches are S13 –S16 , S23 –S36 , S26 –S33 , and VCMVA zero or by making them equal. It can be seen that from
S43 –S46 , and those for phase C are S15 –S12 , S25 –S32 , all the available switching states of one inverter system (inverter
S22 –S35 , and S45 –S42 . Each pole voltage (from both ends system A or inverter system A’), for 19 switching states, the
of the drive system) can attain five different voltage levels CMVs VCMVA and VCMVA are zero, which results in a three-
(Table I). To generate a voltage level “2” at pole A of inverter level voltage space vector structure, as shown in Fig. 4. The
system A (three-level inverter A and the two conventional two- combinations of these 19 switching states (with zero CMV)
level inverters in series), the switches S11 , S21 , and S31 should from the two inverter systems will produce a resultant five-level
be on, and S41 can be in any state depending on pole A’ voltage space vector structure (61 locations and 241 switching
voltage level of inverter system A (three-level inverter A’ and combinations). However, all 241 switching state combinations
the two conventional two-level inverters in series). Let pole A of are not needed for PWM control with CMV elimination. In
inverter A be at voltage level “2” (Table I). To generate voltage the present study, only 103 switching state combinations are
level “1” at pole A’ of inverter A’, switches S14 , S2 1 , and S3 1 used for the PWM control. These are shown in Fig. 5 and are
should be “on” (Table I). Now, to attain these states for two listed in Table IV. Switching states of Fig. 5 are selected in
inverter systems, both switches S11 and S14 need to be “on.” such a way that the resultant pole voltage will have quarter
However, S11 and S14 are complimentary switches, and hence, wave symmetry and will not contain even harmonics. Also,
they cannot simultaneously be in “on” state. This implies that the same switching states can be used for a simple dc-link
inverter pole A and pole A’ cannot be at voltage level “2” and capacitor voltage balancing, as explained in Section V. The
voltage level “1,” respectively, at the same time. It can be shown five-level structure with CMV elimination is obtained from
using similar reasoning that opposite poles of the same phase the original nine-level structure by taking only voltage vec-
of the motor cannot be at voltage level “−1” and voltage level tors with zero CMV. Hence, there will be 15% reduction √ in
“−2” at the same time. the fundamental voltage component, as the radius ( 3/2Vdc )
Table II shows the possible voltage levels that are obtainable of the new hexagonal voltage space vector structure will be
simultaneously from the inverter system A and inverter system smaller than the actual hexagon (Vdc ). Thus, to obtain the same
A’. The state of the switches for three different voltage levels maximum fundamental phase voltage as with a conventional
in inverter legs A and A’ is shown in Fig. 3. It is obtained on five-level inverter,
√ a 15% boost can be given to the dc-link
the basis of Tables I and II. The same approach can be used to voltage (2/ 3Vdc ) [22].
find the switch transitions for the other two phases to obtain the
different voltage levels. IV. E XPERIMENTAL R ESULTS
The developed five-level inverter-fed open-end winding in-
III. CMV E LIMINATION S TRATEGY duction motor drive with CMV elimination scheme and reduced
switch count is experimentally tested on a 2.5-kW induction
The voltage space vector structures of inverter system A motor drive with volts-per-hertz (V/f) control. The V/f control
and inverter system A’, taken individually, produce a five- scheme and the PWM signal generation are implemented on a
level voltage space vector structure each. Since the individual Digital Signal Processor (DSP) TMX320F240PQ, and Spartan
inverter systems at each side will produce a total of 125 (= 53 ) xc2s100 Field-Programmable Gate Array (FPGA) is used for
switching states (Table III—only 30◦ angular sector is shown), the switching state generation for different sectors. The inverter
which are distributed over 61 voltage space vector locations, switching frequency is kept at 2.5 kHz for the entire speed
the combination of these switching states (five-level structure) range of operation. The scheme is examined throughout the
from two inverter systems will produce a nine-level voltage operating range by varying the modulation index from linear
space vector structure, this being the same as for the structure in range to 12-step operation. The algorithm for the generation of
[22, Fig. 1]. level signals for the five-level inverter uses only the sampled
CMV, which is generated by the inverters at the two ends amplitude of the reference voltages, so that the use of lookup
of the open-end winding induction motor, can be expressed as table for sector identification is avoided, and the speed of
follows. The CMV for inverter system A is defined as execution is increased [23]. A detailed description of the PWM
implementation scheme with sampled reference phase voltage
VCMVA = (VAO + VBO + VCO )/3 (1) amplitudes for the entire modulation range is available in [23].
MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION 2347

Fig. 3. State of the switches for legs A and A’ (phase A) of Fig. 2, which leads to the different voltage levels. (a) Leg A at level “2;” leg A’ at level “−2.”
(b) Leg A at level “0;” leg A’ at level “−1.” (c) Leg A at level “1;” leg A’ at level “−2.”

TABLE III
SWITCHING STATES FOR THE VECTOR LOCATIONS OF 30◦ ANGULAR
SECTOR FOR INVERTER SYSTEM A OR INVERTER SYSTEM A’

Fig. 5. Switching states for individual voltage vector locations for the overall
inverter system with zero CMV.

for PWM control (Fig. 5). The switching states for the voltage
vectors are chosen in such a way that the switching losses of
the inverter systems are reduced due to the minimum number
of transitions. Also, the selected switching state combinations
can be effectively used for the dc-link capacitor voltage control,
as explained in the following section. Experimental results for
the PWM control in the innermost sectors are shown in Fig. 6.
Fig. 6(a) shows the pole voltage and phase voltage of the
Fig. 4. Locations of the voltage space vectors for the individual inverter inverter. The top and bottom traces are the pole voltages, and
systems A or A’ with zero CMV. the middle trace is the phase voltage. The motor phase voltage
(top trace) and the motor phase current (bottom trace) are
The PWM signals and the level signals for three phases are presented in Fig. 6(c). The fast Fourier transforms (FFTs) of
generated using the DSP controller. the pole voltage and phase voltage for the PWM control in the
The switching states (Table IV) are stored in the FPGA. inner hexagon are shown in Fig. 6(b) and (d), respectively. It
Fig. 5 shows the inverter switching states, which are used for the can be observed that there are no triplen harmonics in either the
PWM control, with zero CMV at each location. For the present pole voltage or the phase voltage. Experimental results for the
PWM control, from the available redundant switching states three-level operation are given in Fig. 7. Fig. 7(a) shows once
(Table IV), two combinations at a certain location are used more the pole voltage (top and bottom traces) and the phase
2348 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

TABLE IV
SWITCHING STATE COMBINATIONS WITH ZERO CMV, USED AT ALL VOLTAGE SPACE VECTOR LOCATIONS, FOR THE FIVE-LEVEL INVERTER-FED DRIVE

are shown in Fig. 7(b) and (d), respectively. The absence of


triplen harmonics in the pole voltage and in the phase voltage
for the three-level operation is evident from the FFT spectra
results. Identical measurements have also been performed for
the 4-level, 5-level, and, finally, 12-step operations of this drive
system. Experimental results for these operating modes are
shown in Figs. 8–10. In all these figures, the same set of results
is depicted as already described in conjunction with Figs. 6
and 7. It is evident from the spectrum analysis shown in
Figs. 8–10 that the CMV elimination is provided in all
the possible operating modes of the drive system. Hence,
the experimental results confirm that the proposed inverter
structure of reduced power circuit complexity is capable of
producing a five-level voltage structure with zero CMV under
all operating conditions.

V. O PEN -L OOP C ONTROL OF DC-L INK C APACITOR


V OLTAGE B ALANCING
Fig. 6. PWM operation in the innermost (two-level) region. (a) y-axis:
1 div = 50 V; x-axis: 1 div = 20 ms. (c) y-axis: 1 div = 50 V and 1 div = The explanations provided so far are related to the strategy
5 A; x-axis: 1 div = 20 ms. (b), (d) Normalized amplitude versus harmonic
order.
for the CMV elimination by selecting only the switching states
that have zero CMV. However, the switching states (Fig. 5)
voltage (middle trace) of the inverter, whereas Fig. 7(c) shows are selected in such a way that the outer two capacitor (C4
the motor phase voltage (top trace) and the motor phase current and C1 ) and inner two capacitor (C2 and C3 ) voltages are
(bottom trace). The FFTs of the leg voltage and phase voltage kept balanced. For example, during PWM control, switching
MONDAL et al.: REDUCED-SWITCH-COUNT FIVE-LEVEL INVERTER WITH COMMON-MODE VOLTAGE ELIMINATION 2349

Fig. 7. PWM operation in the three-level region. (a) y-axis: 1 div = 50 V; Fig. 9. Five-level operation. (a) y-axis: 1 div = 100 V; x-axis: 1 div =
x-axis: 1 div = 20 ms. (c) y-axis: 1 div = 50 V and 1 div = 5 A; x-axis: 5 ms. (c) y-axis: 1 div = 160 V and 1 div = 5 A; x-axis: 1 div = 10 ms.
1 div = 20 ms. (b), (d) Normalized amplitude versus harmonic order. (b), (d) Normalized amplitude versus harmonic order.

Fig. 8. Four-level operation. (a) y-axis: 1 div = 100 V; x-axis: 1 div =


10 ms. (c) y-axis: 1 div = 100 V and 1 div = 5 A; x-axis: 1 div = 10 ms. Fig. 10. Operation in 12-step mode. (a) y-axis: 1 div = 100 V; x-axis:
(b), (d) Normalized amplitude versus harmonic order. 1 div = 5 ms. (c) y-axis: 1 div = 200 V and 1 div = 5 A; x-axis: 1 div = 5 ms.
(b), (d) Normalized amplitude versus harmonic order.
states (0 − 11, 10 − 1) and (−101, 01 − 1) are used for the
voltage space vector B8 . Fig. 11(a) and (b) shows the currents (0 − 11, 01 − 1) for the voltage vector B9 . For the switching
through the capacitors for the switching states (0 − 11, 10 − 1) state (0 − 11, 01 − 1), the current through C4 and C1 is iA +
and (−101, 01 − 1), respectively. From Fig. 11(a), the current iB , and there is no phase current through C3 and C2 , which
through capacitors C4 and C1 is iA + iB + iC , and the currents results in identical voltages across C4 and C1 and identical
through C3 and C2 are iB and iA , respectively. Next, Fig. 11(b) voltages across C3 and C2 . It is therefore possible to simplify
shows that the current through C4 and C1 is again iA + iB + the power circuit by reducing the number of dc sources from
iC , and currents through C3 and C2 are now interchanged to iA four in the power circuit of Fig. 2 to two, as shown in Fig. 12. In
and iB , respectively. These two switching states are selected Fig. 12, a dc source of Vdc /4 is connected across the inner two
in consecutive sampling interval for the voltage vector B8 . capacitors, and a dc source of Vdc /2 is connected across all the
Now, this means that after two consecutive sampling intervals, four capacitors. Therefore, the total voltage across C1 and C4
there will be identical voltages across C4 and C1 and across and the total voltage across C2 and C3 are fixed to Vdc /4. It thus
C3 and C2 since the same current will pass through these follows that the voltage balance of all the four capacitors will be
pairs of capacitors after two sampling intervals. Fig. 11(c) enabled by keeping the inner two capacitor voltages and outer
shows the current through the capacitors for the switching state two capacitor voltages equal after a maximum of two sampling
2350 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 54, NO. 4, AUGUST 2007

Fig. 13. (a) Phase voltage and current for the motor accelerating from zero
speed to the five-level mode of operation. (b) Voltages across the capacitors for
this acceleration transient.
Fig. 11. (a), (b) Phase connections and the currents through the capacitors for
the switching states of the voltage vector B’8. (c) Phase connection and the
capacitor currents for the switching states of the voltage vector B’9.
a nine-level voltage space vector structure for the drive system.
For the present study, the switching state combinations (from
both ends) with zero CMV are chosen for the PWM control,
which results in the five-level inverter-fed drive. Such five-level
inverter-fed induction motor drive scheme generates zero CMV;
hence, all the problems associated with the presence of CMV
variation (such as bearing currents, early motor failure, etc.) are
also eliminated from the drive system. Since CMV is elimi-
nated, the combined inverter system can be fed from a single
dc link. The present scheme requires a significantly smaller
number of switches when compared to the five-level inverter
for the open-end winding induction motor (obtained by cascad-
ing two-level and three-level inverters at each winding side),
previously reported, while enabling the same quality of per-
formance. There are fewer switches, and the switching loss in
the converter is therefore reduced. As two two-level inverters
have been eliminated, when compared to the previous work,
Fig. 12. Proposed power circuit with dc-link balancing and common-mode the cost and complexity of the power circuit will be lower. The
voltage elimination. power circuit is modular in nature and relies on the utilization
of only conventional inverter structures, so that a simple power
intervals. Fig. 13 shows the phase voltage, the phase current, bus structure is possible. The present scheme gives a reduced
and the voltages across the capacitors for the motor accelerating number of switching state redundancies, as compared to the
from zero speed to the five-level mode of operation. The traces previous scheme of [22]. However, the available redundancies
confirm that the present PWM control is capable of balancing are sufficient and can be effectively utilized for CMV elimina-
the voltage across all the four capacitors. However, if there tion; moreover, a simple dc-link capacitor voltage balancing is
is a momentary short circuit that results in a mismatch in also possible, as demonstrated in the paper. This further reduces
the capacitor voltages, this strategy cannot bring the capacitor the power circuit complexity due to a reduction in the number of
voltages to the balanced condition. To take the corrective action required dc-link power supplies. The proposed scheme is exper-
for such conditions, a closed loop control would be required. imentally verified on a 2.5-kW induction motor drive for differ-
Capacitor voltages would have to be sensed, and the correct ent modulation indexes up to and including the 12-step mode.
inverter switching state to balance the capacitor voltages would
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[15] M. S. Kwak and S. K. Sul, “Control of an open winding machine in
a grid-connected distribution generation system,” presented at the IEEE
Industry Applications Society Annu. Meeting (IAS), Tampa, FL, 2006, P. N. Tekwani received the B.E. degree (Uni.
Paper IAS64p4. CD-ROM. First, Gold Medallist) in power electronics from
[16] K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang, “Control the Saurashta University (LEC), Morbi, India, in
of cascaded multilevel inverters,” IEEE Trans. Power Electron., vol. 19, 1995 and the M.E. degree in electrical engineering
no. 3, pp. 732–738, May 2004. (Industrial Electronics, First Rank) from the M. S.
[17] K. A. Corzine, S. Lu, and T. H. Fikse, “Distributed control of hybrid motor University of Baroda, Vadodara, India, in 2000. He
drives,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1374–1384, is currently working toward the Ph.D. degree at
Sep. 2006. the Centre for Electronics Design and Technology,
[18] V. T. Somasekhar, K. Gopakumar, M. R. Baiju, K. K. Mohapatra, and Indian Institute of Science, Bangalore, India.
L. Umanand, “A multilevel inverter system for an induction motor From 1995 to 1996, he was with the Amtech
with open-end windings,” IEEE Trans. Ind. Electron., vol. 52, no. 3, Electronics Pvt. Ltd., Gandhinagar, India. From 1996
pp. 824–836, Jun. 2005. to 2001, he was with the Electrical Research and Development Association,
[19] V. T. Somasekhar, K. Gopakumar, E. G. Shivakumar, and S. K. Sinha, Vadodara. Since 2001, he has been a member of the faculty in the Institute of
“A space vector modulation scheme for a dual two level inverter Technology, Nirma University of Science and Technology, Ahmedabad, India.
fed open-end winding induction motor drive for the elimination of
zero sequence currents,” Eur. Power Electron. Drives J., vol. 12, no. 2,
pp. 26–36, 2002.
[20] M. R. Baiju, K. K. Mahapatra, R. S. Kanchan, and K. Gopakumar, “A
dual two-level inverter scheme with common-mode voltage elimination Emil Levi (S’89–M’92–SM’99) was born in
for an induction motor drive,” IEEE Trans. Power Electron., vol. 19, no. 3, Zrenjanin, Serbia, in 1958. He received the Dipl. Ing.
pp. 794–805, May 2004. degree from the University of Novi Sad, Novi Sad,
[21] R. S. Kanchan, P. N. Tekwani, M. R. Baiju, K. Gopakumar, and A. Pittet, Serbia, in 1982 and the M.Sc. and Ph.D. degrees
“Three level inverter configuration with common-mode voltage elimina- from the University of Belgrade, Belgrade, Serbia,
tion for induction motor drive,” Proc. Inst. Electr. Eng.—Electr. Power in 1986 and 1990, respectively.
Appl., vol. 152, no. 2, pp. 170–261, 2005. From 1982 to 1992, he was with the Department of
[22] P. N. Tekwani, R. S. Kanchan, and K. Gopakumar, “A dual five-level Electrical Engineering, University of Novi Sad. He
inverter-fed induction motor drive with common-mode voltage elimina- joined Liverpool John Moores University, Liverpool,
tion and dc-link capacitor voltage balancing using only the switching state U.K., in May 1992. Since September 2000, he has
redundancy: Part I,” IEEE Trans. Ind. Electron., to be published. been a Professor of electric machines and drives
[23] R. S. Kanchan, M. R. Baiju, K. K. Mohapatra, P. P. Ouseph, and at the same university. He has extensively published in major journals and
K. Gopakumar, “Space vector PWM signal generation for multi-level conference proceedings.
inverters using only the sampled amplitudes of reference phase voltages,” Dr. Levi is an Associate Editor of the IEEE TRANSACTIONS ON
Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 152, no. 2, pp. 297–309, INDUSTRIAL ELECTRONICS and is a member of the Editorial Board of the
Mar. 2005. IEE Proceedings—Electric Power Applications.