Diseño de Moduladores

UNIVERSIDAD DE SEVILLA
Departamento de Electrónica y Electromagnetismo
Una Contribución al Diseño de Moduladores

Sigma-Delta en Cascada Realizados Mediante
Técnicas de Circuito en Tiempo Continuo
Memoria presentada por
RAMÓN TORTOSA NAVAS
para optar al grado de Doctor por la Universidad de Sevilla
Sevilla, abril de 2012

Una Contribución al Diseño de Moduladores
Sigma-Delta en Cascada Realizados Mediante
Técnicas de Circuito en Tiempo Continuo
Memoria presentada por
RAMÓN TORTOSA NAVAS
para optar al grado de Doctor por la Universidad de Sevilla
LOS DIRECTORES
Dr. José Manuel de la Rosa Utrera Dr. Ángel Rodríguez Vázquez
Profesor Titular de Universidad Catedrático de Universidad
Departamento de Electrónica y Electromagnetismo
UNIVERSIDAD DE SEVILLA
Tesis Doctoral. Ramón Tortosa Navas I
Índice de Contenidos
Resumen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Introducción y Justificación de la Unidad Temática de esta Tesis
Doctoral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2. Convertidores Analógico-Digitales: Conceptos Básicos y Estado del
Arte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3. Moduladores de Tiempo Continuo . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Objetivos de esta Tesis Doctoral . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
5. Resultados y Discusión . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6. Conclusiones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Referencias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Anexo 1: Convertidores Sigma-Delta de Tiempo Continuo

Conceptos, Arquitecturas, Circuitos y Errores. . . . . . . . . . . . . . . 23
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.2 Fundamentals of A/D Conversion . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.3 Basics of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.4 Continuous-Time Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . .38
1.5 DT-to-CT Synthesis Methods and Basic CT- M Archictectures . .50
1.6 Circuits and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
1.7 CT Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
1.8 Building-block Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
1.9 Excess Loop Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
1.10 Comparator Metastability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
1.11 Clock Jitter Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Tesis Doctoral. Ramón Tortosa Navas II
Anexo 2: Principales Publicaciones sobre los Trabajos Recogidos

en la Tesis Doctoral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Resumen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Publicación 1: “A New High-Level Synthesis Methodology of Cascaded
Continuous-Time Modulators” . . . . . . . . . . . . . . . . . . . . . . . . . 97
Publicación 2: “Clock Jitter Error in Multi-bit Continuous-Time
Modulators with Non-Return-to-Zero Feedback Waveform” . . . . 107
Publicación 3: “Systematic Design of High-Resolution High-Frequency
Cascade Continuous-Time Sigma-Delta Modulators” . . . . . . . . . 125
Publicación 4: “Design of a 1.2-V Cascade Continuous-Time
Modulator for Broadband Telecommunications” . . . . . . . . . . . . . 139
Publicación 5: “A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time
Sigma-Delta Modulator”. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Anexo 3: Otras Publicaciones sobre los Trabajos Recogidos en la

Tesis Doctoral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Resumen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Publicación 6: “Cascaded Continuous-Time Modulators with Reduced
Number of Analog Components - Application to VDSL” . . . . . . . 153
Publicación 7: “Analysis of Clock Jitter Error in Multibit Continuous-Time
Modulators with NRZ Feedback Waveform” . . . . . . . . . . . . . 161
Publicación 8: “A Direct Synthesis Method of Cascaded Continuous-Time
Sigma-Delta Modulators” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Publicación 9: “Continuous-Time Cascaded Sigma-Delta Modulators for
VDSL: A Comparative Study” . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Publicación 10: “Design of a 1.2-V 130nm CMOS 13-bit@40MS/s
Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator” . . . . . 181
Publicación 11: “A Design Tool for High-Resolution High-Frequency
Cascade Continuous-Time Modulators”. . . . . . . . . . . . . . . . . 187
Listado Completo de Publicaciones . . . . . . . . . . . . . . . . . . . . . . . 203
Tesis Doctoral. Ramón Tortosa Navas 1
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UNA CONTRIBUCIÓN AL DISEÑO DE MODULADORES

SIGMA-DELTA EN CASCADA REALIZADOS MEDIANTE
TÉCNICAS DE CIRCUITO EN TIEMPO CONTINUO
RESUMEN
Esta tesis doctoral es el resultado de un conjunto de trabajos de investigación encaminados a sistematizar y

optimizar el diseño de convertidores analógico-digitales de tipo Sigma-Delta (ΣΔ), realizados mediante técnicas de
circuito en tiempo continuo. Para ello, se ha desarrollado una nueva metodología de diseño de alto nivel que está
especialmente orientada a topologías de moduladores ΣΔ en cascada. En esencia, el método propuesto consiste en
sintetizar el filtro del modulador complementamente en el dominio del tiempo continuo, en lugar de hacerlo a partir
de un equivalente en tiempo discreto, al que luego se le aplica una transformada discreta a continua. La síntesis
directa en el dominio del tiempo continuo permite obtener arquitecturas con un menor número de componentes
analógicos, lo que las hace más robustas frente a los errores de tolerancia de dichos componentes, principalmente
debidos a variaciones aleatorias de los parámetros físicos del proceso tecnológico.
Además de la sensibilidad a los errores de tolerancia de los circuitos analógicos, otra fuente de error que limita en la
práctica las prestaciones de los moduladores ΣΔ de tiempo continuo es debida a la incertidumbre en los instantes de
conmutación de la señal de reloj, conocida como error de “jitter”. En esta tesis se demuestra que la potencia de ruido
generada por dicho error en la banda de la señal presenta dos componentes: una que depende de los parámetros del
filtro del lazo del modulador y otra debida a la propia señal de entrada. Del análisis matemático desarrollado se
derivan ecuaciones de diseño que permiten optimizar las prestaciones de moduladores de lazo único y en cascada,
minimizando el consumo de potencia para unas determinadas especificaciones dadas.
Como aplicación de los estudios realizados, se presentan varios casos de estudio prácticos de distintas topologías de
moduladores, considerando diferentes tipos de implementación, tanto Gm-C como RC activa. Los diseños se
realizaron en una tecnologías CMOS de 130nm, empleando una única fuente de alimentación de 1.2V, y con
aplicación en la digitalización de señales con ancho de banda de 20MHz y resolución efectiva de 12 bits, lo que
suponía alcanzar prestaciones en el estado del arte del momento.
La importancia y calidad de todos estos trabajos ha sido reconocida por la comunidad científica internacional, como
se demuestra por las publicaciones de los mismos en artículos en revistas internacionales y conferencias
internacionales, todos ellos sometidos al proceso de revisión por pares y editados en su mayoría por el IEEE, así
como por otras entidades de la máxima relevancia en el área de investigación (Microelectrónica) en la que se
enmarca la presente tesis doctoral.
Tras este resumen inicial, y en cumplimiento de la normativa vigente1 el presente documento incluye un resumen del
trabajo correspondiente a esta tesis doctoral, justificándose la unidad temática de la tesis, los objetivos a alcanzar, un
resumen global de los resultados obtenidos, la discusión de estos resultados y las conclusiones finales. Finalmente se
incluyen las principales publicaciones realizadas, precedidas por un breve resumen de cada una de ellas.
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1
!Acuerdo!7.2/CG!1706011,!BOUS!nº4,!1307011.!!
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1. Introducción y Justificación de la Unidad Temática de esta Tesis Doctoral
Sería muy complicado, si no imposible, poder explicar la sociedad contemporánea sin hablar
de las tecnologías de la información y las comunicaciones (TIC). Tanto es así que posiblemente
la primera década del siglo XXI será recordada por el vertiginoso aumento de dispositivos
electrónicos portátiles con capacidad multimedia y de conexión a Internet, así como por la
proliferación de cada vez más redes de comunicación inalámbricas, que facilitan el acceso
ubicuo a la información. Esta tendencia continúa, incrementando en cada generación de nuevos
dispositivos tanto el número de aplicaciones que soportan como la tasa de transferencia de datos,
con una autonomía cada vez mayor [1].
Uno de los exponentes más evidentes de la popularización de las TIC son los teléfonos
celulares o móviles. La mayoría de terminales de última generación, conocidos como “smart
phones”, soportan un gran número de estándares de comunicación, entre los que se encuentran
GSM, GPRS/EDGE, CDMA, UMTS/WCDMA, HSDPA, Bluetooth y WLAN y más
recientemente WiMAX y LTE. De hecho, se estima que hay actualmente coexistiendo en
diferentes regiones del mundo más de cien estándares de comunicación diferentes [2].
Sin embargo, la forma actual en la que se incluyen nuevos modos de operación en un terminal
implica la incorporación de nuevos “chipsets” específicos de Radio Frequencia (RF) y de su
correspondiente circuitería de banda base. De este modo, no resulta difícil encontrar varios chips
de radio, típicamente del orden de cinco, en un terminal de última generación que podamos
adquirir hoy día en el mercado. Estos chips se interconectan normalmente en tarjetas de circuito
impreso ultracompactas, o bien mediante el empleo de tecnologías avanzadas de conexionado y
encapsulado como por ejemplo la tecnología LTCC (de “Low Temperature Co-fired Ceramic “)
o SiP (de “System-in-Package”), que hace de los teléfonos móviles más actuales unas auténticas
maravillas de la miniaturización [3].
A pesar de ello, el ritmo creciente de incorporación de nuevos estándares de comunicación y

funcionalidades de los sistemas electrónicos, hace que el modelo de incorporación de las mismas
– basados en actualización del hardware – esté llegando a sus límites, lo que está planteando la
necesidad de buscar soluciones que combinen un uso más eficiente de hardware y software, que
permitan programar o actualizar los sistemas electrónicos vía software o “firmware”. Todo ello
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está siendo impulsado por el escalado de las tecnologías micro-nanoelectrónicas, las cuales están
posibilitando una mayor integración monolítica en un único chip de sistemas electrónicos
completos, denominados “Systems on Chip” o SoC [3]-[5].
La miniaturización de sistemas electrónicos completos a escala nanométrica permite, por una

parte, alcanzar una mayor velocidad de los dispositivos (lo que se traduce en una mayor tasa de
transferencia de datos) y ahorro en términos de tamaño (lo que supone una disminución del
coste) y del consumo de potencia (lo que permite una mayor portabilidad y eficiencia
energética). Es precisamente esta tendencia hacia una mayor integración y uso masivo de
procesamiento digital de la señal lo que ha propiciado el uso de tecnologías CMOS para la
realización de sistemas de comunicación inalámbricos, en lugar de los tradicionalmente
empleados para ello (Bipolar, BiCMOS, GaAs, etc.). De hecho, gracias a las mejoras de los
procesos CMOS nanométricos actuales, se pueden alcanzar frecuencias de tránsito de centenas
de GHz, por ejemplo 200GHz en una tecnología típica de 40nm. Ello permite que el diseño de
circuitos operando en el rango de Radio Frecuencia (RF) puedan ser considerado en cierta
manera de “baja frecuencia”, y por tanto diseñarse siguiendo procedimientos similares a los
empleados en el pasado para los circuitos analógicos y de señal mixta [2].
Todo ello está dando lugar a que en los sistemas electrónicos, cada vez más funcionalidades
sean llevadas a cabo digitalmente, en lugar de analógicamente, lo que se traduce en un
desplazamiento de la frontera entre la parte analógica y la digital cada vez más cercana al punto
donde se recibe o se emite la información. En este escenario, la mayor parte del procesado de la
señal que realizan los circuitos analógicos se limitan a tareas de interfaz analógica-digital, es
decir, acondicionamiento de la señal (preamplificación, filtrado, traslación en frecuencia, etc),
conversión digital-analógico y analógico-digital, siendo ésta última el objetivo principal de esta
tesis doctoral.
2. Convertidores Analógico-Digitales: Conceptos básicos y Estado del Arte
Un convertidor analógico-digital (ADC de “Analog-to-Digital Converter”) es un circuito

electrónico que transforma una señal continua en el tiempo y en la amplitud (señal analógica) en
otra señal discreta en el tiempo cuya amplitud está cuantificada y codificada, generalmente
mediante un código binario de N bits. La Fig.1(a) muestra el diagrama de bloques conceptual de
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un ADC, el cual incluye los siguientes componentes: un filtro “anti-aliasing”, un circuito de

muestreo y retención (S/H de “Sampling-and-Hold”), un cuantizador y un codificador. La
operación de cada uno de estos bloques se ilustra en la Fig.1(b). En primer lugar, el filtro “anti-
aliasing” elimina las componentes espectrales que se encuentran por encima de la mitad de la
frecuencia de muestreo, fs , a la cual opera el circuito S/H. En caso contrario, de acuerdo con el
teorema de Nyquist, las componentes de alta frecuencia se plegarían en la banda, BW, de la señal
de entrada, xa , corrompiendo de esta manera la información. La señal limitada en banda que
resulta a la salida del filtro, xbl(t), se muestrea en el circuito S/H, dando lugar a una señal en
tiempo discreto, xs,n = xbl(nTs) , cuyo rango de amplitudes continuo se mapea en el cuantizador en
un conjunto de niveles discretos de amplitud. Finalmente, el codificador asigna un código binario
a cada uno de esos niveles, resultando en la secuencia de datos digitales de salida, yd,n [6].
x a (t ) x bl (t ) x s,n x c,n y d,n

S/H Coder
f s ⁄2
fs
AAF Quantizer
(a)
x bl (t )
Analog-to-Digital y d,n
t n
Conversion
Sampling Coding
x s,n x c,n
Quantization
nT s nT s
(b)
Fig. 1: Conversión analógica-digital: (a) Diagrama de bloques conceptual. (b) Procesamiento de la señal.
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Como se ilustra en la Fig.1(b), la conversión A/D comprende dos procesos fundamentales:

muestreo y cuantización. Ambos realizan una transformación continua-discreta de la señal
analógica de entrada; el primero en el tiempo y el segundo en amplitud. Los errores inherentes a
estos dos procesos limitan el funcionamiento de un ADC, en términos de su velocidad de
operación y de su precisión o resolución, incluso aunque los componentes de éste sean ideales.
Estas dos características, velocidad y resolución, determinan las especificaciones fundamentales
de un ADC, existiendo un compromiso de diseño entre ambas (y el consumo de potencia), de
forma que a mayor velocidad de procesamiento, el ADC obtendrá una menor resolución y
viceversa.
Las prestaciones, en términos de resolución, velocidad y consumo de potencia pueden

cuantificarse mediante la siguiente figura de mérito o FOM (de “Figure Of Merit”):
Pw (W) (1)
FOM1 ≡ ENOB(bits)
1012
pJ/conv
2 ⋅ DOR(S / s)
donde Pw (W) es la potencia en vatios, ENOB (de “Effective Number Of Bits”) es el número
efectivo de bits y DOR (de “Digital Ouput Rate”) es la tasa de muestreo correspondiente a la
frecuencia mínima de muestreo que determina el teorema de Nyquist, conocida como frecuencia
de Nyquist.
La Fig. 2 ilustra el estado del arte de ADC realizados en tecnologías CMOS reportados hasta
el año 2010, situándolos en el plano resolución – ancho de banda [7][8]. Sobre este plano se
representan las prestaciones obtenidas por diferentes técnicas utilizadas para la conversión A/D,
agrupados en dos categorías fundamentales: “Nyquist-Rate” y Sigma-Delta (ΣΔ). Como su
nombre indica, los ADC de Nyquist, que pueden implementarse mediante varias técnicas (Flash,
“Two-Step”, “Folding”, “Pipeline”, SAR o “Successive Approximation Register”) operan a la
frecuencia de Nyquist. Por el contrario, los convertidores ΣΔ emplean una frecuencia de
muestreo superior a la frecuencia de Nyquist. Al cociente entre la frecuencia de muestreo y la
frecuencia de Nyquist se le conoce como razón de sobremuestreo u OSR (“OverSampling
Ratio”).
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Sigma-Delta ADCs
Nyquist-rate ADCs
Fig. 2: Estado del arte de convertidores analógico-digitales CMOS a finales de 2010. Representación del Rango
Dinámico (DR) versus DOR. (DR=”Dynamic Range”, DOR=”Digital Output Rate”).
Las características específicas de cada una de las técnicas de conversión incluidas en la Fig. 2
– cuya descripción está fuera del alcance de esta tesis – las adecúa a diferentes rangos de
aplicación en términos de ancho de banda y resolución [9]. Como puede observarse, los ADC de
tipo ΣΔ cubren un área muy extensa del plano resolución-velocidad, abarcando un rango de
anchos de banda desde 100Hz hasta 100MHz. Sin embargo, las aplicaciones de mayor velocidad
están dominadas por los ADC de Nyquist, especialmente los de tipo SAR y Flash.
Si se comparan las prestaciones de los ADC en términos de FOM1 como se ilustra en la Fig.
3, puede verse como los ADC ΣΔ obtienen un mejor rendimiento hasta valores de DOR del
orden de 100kS/s, obteniendo resultados similares a los SAR hasta 10MS/s. Sin embargo, como
se muestra en la Fig. 2, la región del plano resolución-velocidad cubierta por los ADC ΣΔ es
mayor que la correspondiente a todos los ADC de tipo Nyquist, siendo la tendencia en los
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últimos años a aumentar aún más dicha región de dominancia de los ADC ΣΔ, como demuestran
algunos prototipos reportados, que reportan prestaciones del estado del arte, con valores de DOR
por encima de 200MS/s y frecuencias de muestreo de varios GHz [10][11].
Además de las razones expuestas, los ADC ΣΔ ofrecen ventajas clave para su integración en
SoCs. A diferencia de los ADC de Nyquist, cuya resolución depende fuertemente de la alta
precisión de sus bloques componentes, las técnicas de sobremuestreo y de conformación de ruido
de cuantización empleadas en los ADC ΣΔ permiten intercambiar velocidad por precisión. De
esta forma puede obtenerse una operación relativamente insensible a las imperfecciones de la
circuitería analógica a expensas de una mayor complejidad y velocidad en la circuitería digital
asociada (necesaria para la decimación y filtrado). Por ello las técnicas de modulación ΣΔ
resultan idóneas para la implementación de ADC de altas prestaciones integrados en tecnologías
CMOS nanométricas, las cuales son más adecuadas para proporcionar circuitos digitales rápidos
que circuitos analógicos precisos [12].
Fig. 3: Estado del arte de convertidores analógico-digitales CMOS a finales de 2010. Representación FOM1 versus
DOR. (DR=”Dynamic Range”, DOR=”Digital Output Rate”).
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Todas estas ventajas explican el alto interés – no sólo a nivel académico sino también en el
ámbito de la industria – de la comunidad científica internacional por los ADC ΣΔ, como se
demuestra por el gran número de foros dedicados a este tipo de convertidores frente al resto de
técnicas de ADC. Sin embargo, a pesar de dichas ventajas, la continua demanda de prestaciones
cada vez más exigentes (en términos de velocidad, resolución y consumo de potencia), unido a
las dificultades inherentes al diseño de circuitos analógicos en nodos tecnológicos de última
generación, requieren el uso de estrategias apropiadas, tanto a nivel de sistema como de circuito,
que permitan implementar los ADC ΣΔ de forma más eficiente.
En este escenario se enmarca el trabajo de investigación llevado a cabo en esta tesis doctoral,
cuyo objetivo principal es el diseño sistemático de ADC ΣΔ realizados mediante técnicas de
circuito de tiempo continuo, y cuyos fundamentos se resumen en el siguiente apartado. Una
explicación más detallada de los mismos se pueden encontrar en el Anexo 1 de esta tesis.
3. Moduladores ΣΔ de Tiempo Continuo
La Fig. 4 muestra el diagrama de bloques conceptual de un ADC ΣΔ concebido para la

conversión de señales paso de baja2, considerando dos casos: una implementación mediante
técnicas de circuito de tiempo discreto (DT de “Discrete-Time”), mostrada en la Fig. 4(a); y una
implementación basada en técnicas de tiempo continuo (CT de “Continuous-Time”), ilustrada en
la Fig. 4(b). En ambos casos, el diagrama de bloques comprende tres componentes principales:
un filtro “antialiasing”, un modulador ΣΔ (MΣΔ) y un decimador digital. La operación del
convertidor puede resumirse como sigue. Después de ser filtrada, la señal es sobremuestreada y
cuantizada en el MΣΔ. Este bloque filtra también el error de cuantización, conformando su
espectro en frecuencia de tal forma que la mayor parte de su potencia queda fuera de la banda de
la señal, donde es eliminada por el filtrado digital. La salida del modulador − codificada en un
número reducido de bits − pasa a través del decimador digital donde, después del filtrado de los
componentes que están fuera de la banda de la señal, los datos de salida son decimados de forma
que se reduce fs hasta la frecuencia de Nyquist, fd .
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2
!El!diagrama!de!bloques!conceptual!de!un!ADC!ΣΔ!paso!de!banda!es!análogo!al!mostrado!en!la!Fig.!4,!excepto!que!
tanto!el!filtro!anti0aliasing!como!el!filtro!del!lazo!del!modulador!deben!ser!de!tipo!paso!de!banda.!!
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Fig. 4: Diagrama de bloques de: (a) ADC ΣΔ de tiempo discreto. (b) ADC ΣΔ de tiempo continuo.
Las prestaciones de un ADC ΣΔ ideal están determinadas en última instancia por el MΣΔ, ya
que éste es el responsable de realizar la conversión A/D. Por lo tanto, nos centraremos en este
bloque de aquí en adelante.
Fundamentos de Moduladores ΣΔ
Suponiendo un modelo linealizado del cuantizador en la Fig. 4, en el que el error de

cuantización se puede modelar como una fuente aditiva de ruido blanco, se puede demostrar que
la transformada Z de la salida del modulador viene dada por la siguiente expresión:
Y (z) = STF(z) ⋅ X (z) + NTF(z) ⋅ E(z) (2)
donde X(z) y E(z) representan la transformada Z de la señal de entrada y del error de

cuantización, respectivamente; y STF(z) y NTF(z) representan la función de transferencia de la
señal y del ruido de cuantización. En el caso de un MΣΔ DT, se puede demostrar que STF(z) y
NTF(z) vienen dadas por [6]:
H (z) 1 (3)
STF(z) = ; NTF(z) =
1+ H (z) 1+ H (z)
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En el caso de los MΣΔ CT, puede demostrarse que en determinadas condiciones, se pueden
derivar unas expresiones similares a (3) en el dominio continuo de la frecuencia, f, obteniéndose
que
H( f ) 1 (4)
STF( f ) = ; NTF( f ) =
1+ H ( f ) 1+ H ( f )
De las expresiones (3) y (4), puede concluirse que si el filtro del lazo del modulador se diseña
de forma que H ( f ) → ∞ en la banda de la señal, entonces STF( f ) → 1 y NTF( f ) → 0 en
dicha banda. Es decir, la acción de la realimentación y de la ganancia del filtro del lazo del MSD
es tal que la señal de entrada no se ve alterada (idealmente), mientras que se realiza un
conformado3 del espectro del ruido de cuantización, de forma que se reduce (idealmente se
elimina) la potencia del ruido de cuantización integrado en la banda de la señal, dado por [6][13]:
X 2FS
fU
2 (5)
PQ ≡ ∫ NTF( f ) df
12 ⋅ (2 B −1) 2 ⋅ f s fL
donde B y X FS representan respectivamente es el número de bits y el fondo de escala del
cuantizador; y f L , fU denotan los los límites inferior y superior de la banda de la señal.
En el caso de señales paso de baja, y considerando una función de transferencia del ruido orden L y de
tipo diferenciadora4, es decir NTF(z) = (1− z −1 ) L , de la expresión en (5) se obtiene que:
π 2 L X 2FS (6)
PQ ≅
12 ⋅ (2 B −1) 2 ⋅ (2L +1) ⋅ OSR (2 L+1)
donde OSR representa la razón de sobremuestreo.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
3
!Debido!a!esta!acción!de!conformado!del!espectro!del!ruido!de!cuantización!a!los!ADC!ΣΔ!se!les!conoce!también!
como!“noise0shaping”!ADC![12].!
4
!Este!tipo!de!funciones!son!las!más!frecuentemente!empleadas!en!MΣΔ!paso!de!baja![12].!
!
!
La expresión (6) muestra como al aumentar L, OSR y/o B, se reduce la potencia del ruido de
cuantización en la banda de la señal, y por tanto la resolución efectiva del convertidor A/D
resultante. La combinación de estas tres estrategias no excluyentes da lugar a una pléyade de
arquitecturas de MΣΔ, las cuales pueden clasificarse atendiendo a diversos criterios, entre otros:
la naturaleza de la señal de entrada (paso de baja o paso de banda); el número de bits del
cuantizador interno (un bit o multi-bit), el número de cuantizadores incluido en el lazo (dando
lugar a arquitecturas de un único lazo o en cascada), la técnica de circuito empleada para la
implementación del filtro del lazo (tiempo discreto o tiempo continuo). La explicación detallada
de cada una de estas familias de MΣΔ – cada una con sus pros y sus contras – va más allá de los
objetivos de esta tesis doctoral y puede encontrarse en multitud de monografías [6][13][14]. En
su lugar en este resumen nos centraremos en analizar las ventajas e inconvenientes del empleo de
técnicas de circuito de tiempo continuo – objeto principal de este trabajo de investigación.
Ventajas de los Moduladores ΣΔ de Tiempo Continuo
Comparando los dos diagramas de la Fig. 4, se pueden apreciar algunas diferencias simples,
pero importantes, entre los ADC ΣΔ DT (Fig. 4(a)) y CT (Fig. 4(b)). Además de la ya
mencionada y obvia diferencia correspondiente a la técnica de circuito y la dinámica empleada
en el filtro del lazo, la diferencia más significativa que se aprecia es en la posición en la que tiene
lugar la operación de muestreo – mostrada de forma explícita y conceptual como un bloque S/H
en la Fig. 4. Puede observarse como en el caso de los convertidores ADC ΣΔ CT, la operación
S/H tiene lugar dentro del lazo del modulador, justo en la entrada del cuantizador. Esta
característica fundamental ofrece las siguientes ventajas:
• Mayor velocidad de operación con menor consumo de potencia, propiciada por la

operación en tiempo continuo del filtro del lazo, en la que la dinámica de los circuitos no
es parásita (como ocurre en los circuitos de condensadores en conmutación por ejemplo),
sino una primitiva de diseño [13].
• Filtrado extra “anti-aliasing” implícito, ya que el filtro del lazo se puede emplear para
este propósito, relajando las especificaciones o incluso eliminando la necesidad del
filtrado previo “anti-aliasing” [14].
!
!
• Menor impacto de los errores causados por la operación de muestreo. Esto es una
consecuencia directa del hecho de que la operación de muestreo no tiene lugar en el nudo
de entrada del modulador, sino dentro del lazo. De este modo, los errores de muestreo son
filtrados de manera análoga al ruido de cuantización [13].
• No necesidad de llaves de muestreo en la entrada, evitando la necesidad de emplear

técnicas como “clock boosting”, necesarias para poder obtener una linealidad aceptable
con bajas tensiones de polarización, como las que se emplean en tecnologías CMOS
nanométricas.
• Menor ruido térmico, ya que al no ser muestreado, no hay efecto de plegamiento. Por
tanto, la potencia de ruido térmico integrado en la banda de la señal es típicamente menor
que la de los MΣΔ DT, en los que debido al muestreo, una gran cantidad del ruido térmico
(KT/C) se pliega en la banda de la señal, constituyendo una limitación fundamental en la
resolución efectiva [13].
• Menor impacto del ruido de conmutación, denominado “digital noise” o “switching

noise”, ya que resulta atenuado por la acción del filtro del lazo, del mismo modo que el
ruido de cuantización.
Inconvenientes de los Moduladores ΣΔ de Tiempo Continuo
Las principales desventajas y limitaciones de los MΣΔ CT son las siguientes:
• Respuesta dinámica más complicada, debido al procesamiento de señales de tiempo

continuo y de tiempo discreto a través de un sistema no lineal. Esta característica dificulta
el análisis matemático de los MΣΔ CT, y consecuentemente la síntesis de los mismos.
• Mayor sensibilidad a las no linealidades del circuito, especialmente los que están situados
en el nudo de entrada del modulador. Esta limitación es particularmente importante en
filtros del lazo realizado con integradores del tipo Gm-C, ya que el transconductor situado
en la entrada realiza una conversión voltaje-corriente. Esta operación genera distorsión
armónica que condiciona la linealidad de todo el modulador.
!
!
• Mayor sensibilidad a los errores de tolerancia de los elementos de circuito. Esto es algo
inherente a los circuitos CT, ya que las constantes de tiempo vienen dadas como el
producto de dos parámetros descorrelacionados entre sí, por ejemplo la transconductancia
y el condensador de integración en un integrador Gm-C, o la constante RC en un
integrador RC-activo. Ello requiere el empleo de estrategias de sintonizado o “tunning”
para ajustar los coeficientes del filtro del lazo, los cuales están determinados por dichas
constantes de tiempo.
• Mayor impacto del error debido a la incertidumbre de los instantes de conmutación de la

señal de reloj, conocido como error de “jitter”. En un MΣΔ CT, hay dos bloques de
circuito sujetos a este error: el circuito de S/H y el convertidor digital-analógico (DAC de
“Digital-to-Analog Converter”) de la realimentación, en el cual se realiza una
transformación DT-a-CT en el nudo de entrada, siendo por tanto éste último el que limita
las prestaciones del modulador [15]-[17].
4. Objetivos de esta Tesis Doctoral
Los trabajos de investigación recogidos en esta tesis doctoral pretenden hacer frente a los
problemas y limitaciones mencionados en el apartado anterior de los MΣΔ CT, con el objetivo
fundamental de sistematizar el diseño de dichos moduladores, prestando especial interés a las
topologías en cascada y tratando de optimizar sus prestaciones en términos de consumo de
potencia y robustez frente las principales fuentes de error: non linealidad de los circuitos de
entrada, tolerancia de los elementos de circuito y error de “jitter” del reloj. Este objetivo general
se desglosa en los siguientes objetivos parciales:
1) Desarrollar una metodología de síntesis y diseño de alto nivel para topologías

de MΣΔ CT en cascada que permita obtener arquitecturas más robustas y
eficientes en términos de consumo de potencia y de sensibilidad a los errores de
circuito.
2) Realizar un análisis y modelado preciso del error del “jitter” de reloj, con un
doble propósito. Por una parte, encontrar un modelo preciso para la simulación
de comportamiento de MΣΔ CT. Por otra parte, obtener ecuaciones de diseño
!
!
que permitan minimizar el impacto del error y optimizar así las prestaciones de
los MΣΔ CT para unas especificaciones dadas.
3) Encontrar soluciones a nivel de circuito que reduzcan el efecto de los errores no

lineales en los MΣΔ CT.
4) Demostrar la viabilidad del uso de MΣΔ CT en cascada para la digitalización

de señales de banda ancha (20MHz) con resoluciones medias (12bit).
5. Resultados y Discusión
Los trabajos recogidos en esta tesis doctoral se estructuran alrededor de los objetivos descritos
en el apartado anterior. Los resultados obtenidos dan respuesta a los retos planteados en dichos
objetivos, demostrando la viabilidad de los moduladores ΣΔ CT para la realización de ADC de
banda ancha y resolución media. A continuación, se resumen los resultados más importantes, los
cuales se describen en detalle en las aportaciones que conforman la presente memoria, todas ellas
correspondientes a publicaciones en foros de la máxima relevancia internacional.
Propuesta de un Nuevo Método de Síntesis Directa de Moduladores ΣΔ CT en Cascada
En esta tesis doctoral se propone un nueva nueva metodología de síntesis y diseño de alto
nivel especialmente orientada a MΣΔ CT en cascada. El método – descrito en la Publicación 1
del Anexo 2 de esta memoria [18]– se basa en la síntesis directa en el dominio del tiempo
continuo de MΣΔ CT en cascada, en lugar de aplicar una transformada discreta-a-continua a un
MΣΔ DT equivalente, como se había propuesto anteriormente. En contraposición, el método
propuesto permite optimizar la función de transferencia de la señal y del ruido de cuantización,
distribuyendo los ceros de ésta última de forma óptima en la banda de la señal, de forma que se
puede minimizar la potencia del ruido integrada en banda. Las arquitecturas obtenidas mediante
el método propuesto son más eficientes que las sintetizadas a partir de un modulador DT
equivalente, reduciendo el número de componentes analógicos necesarios. De este modo, se
obtienen arquitecturas más eficientes en términos de consumo de potencia y robustez frente a las
tolerancias de los coeficientes del filtro del lazo – uno de los principales factores limitantes de
los MΣΔ CT como se describe en el apartado 4 de este resumen.
!
!
El método propuesto se puede aplicar a cualquier topología de MΣΔ CT en cascada, como se

demuestra en la primera publicación recogida en el Anexo 2 [19], en la que se sintetizan varias
cascadas diferentes, entre otras: 2-1-1, 2-1-1-1, 2-2-1 y 3-2.
Análisis y Modelado del Error del “jitter” del Reloj en MΣΔ CT con DAC NRZ
Como se mencionó en el Apartado 4, uno de los factores limitantes del funcionamiento de los
MΣΔ CT es el error de “jitter” del reloj. En la Publicación 2 del Anexo 2 [20] de esta tesis se
presenta un análsis detallado de este error para el caso de DAC NRZ (de “Non Return to Zero”)
y cuantización multi-bit. Este caso es uno de los más empleados en aplicaciones prácticas de
media resolución (11-14 bits) y banda ancha (10-20 MHz), por lo que su estudio es de interés
para el diseño óptimo de MΣΔ CT en tales aplicaciones.
El análisis llevado a cabo en esta tesis doctoral se basa en el uso de la formulación espacio
estado (“estate-space formulation”) lo que dota al estudio matemático realizado de un carácter
general y aplicable a cualquier topología de MΣΔ CT tanto de lazo único como en cascada.
Como resultado, se demuestra que la potencia de ruido integrada en la banda de la señal debida
al error de jitter puede separarse en dos componentes: uno que depende de la función de
transferencia del filtro del lazo del modulador y otra que depende de los parámetros de la señal
de entrada. Esta última componente, que no se considera en otros estudios previos, permite
predecedir con gran precisión la pérdida de resolución causada por el “jitter”, mostrando efectos
no tenidos en cuenta anteriormente en la literatura.
Como resultado del análisis se obtienen ecuaciones de diseño para la potencia de ruido
integrada en banda y la relación señal-ruido, las cuales pueden ser empleadas para la
optimización de MΣΔ CT en términos de su sensibilidad al error de “jitter”. Las predicciones
teóricas son validadas mediante simulación en el dominio del tiempo de diversas arquitecturas de
moduladores de lazo simple y en cascada.
Desarrollo de una Metodología “Top-Down/Bottom-Up” para el Diseño Sistemático de

Moduladores ΣΔ CT en Cascada
El método de síntesis directa en el dominio del tiempo continuo se integra conjuntamente con
el análisis y modelado de las principales fuentes de error que afectan al funcionamiento de MΣΔ
!
!
CT, considerando tanto efectos de circuito (ganancia finita, GBW, mismatch, ruido, etc) como
arquitecturales (exceso de retraso del laxo, “jitter” del reloj, etc) para desarrollar una
metodología sistemática “top-down/bottom-up” que permita asistir el diseño desde las
especificaciones de sistema hasta el nivel eléctrico de dispositivo.
Como se detalla en la Publicación 3 del Anexo 2 [21], la metodología propuesta combina

optimización y simulación en los dintintos niveles de abstracción de la jerarquía del modulador
(arquitectura, bloques, circuito) e incorpora la generación de frentes Pareto-óptimos que
permiten reducir el número de iteraciones en el proceso de diseño de alto nivel. El método se
aplica al estudio de diversas arquitecturas en cascada de orden 5, concretamente 2-1-1-1, 2-2-1 y
3-2, considerando unas especificaciones de 12-bit en un ancho de banda de 20MHz.
Casos de Estudio y Soluciones Circuitales
Los análisis y metodologías desarrolladas en esta tesis se han aplicado al diseño dos MΣΔ CT
en cascada, detallados en la Publicaciones 4 [22] y 5 [23] del Anexo 2, implementados en una
tecnología CMOS de 130nm con una única fuente de alimentación de 1.2V:
• El primer circuito es una arquitectura 2-2-1 y cuantización de 4 bits en las tres etapas. El
primer integrador se implementa mediante la técnica RC-activa, mientras que el resto de
los integradores son de tipo Gm-C [22].
• El segundo diseño es una arquitectura 3-2 con cuantización de 4 bits en las dos etapas y
completamente implementado mediante integradores Gm-C [23].
En ambos casos, se proponen circuitos transconductores para el filtro del lazo que
implementan una técnica de cancelación del término cuadrático, con el fin de obtener mejor
linealidad. En el segundo diseño se utiliza un transconductor basado en degeneración de fuente y
enriquecimiento de la ganancia para el integrador frontal, al ser éste el más crítico.
Los dos diseños emplean DAC de realimentación en modo corriente (“current steering DAC”)
así como algoritmos DEM (de “Dynamic Element Matching”) para compensar el error de
desapareamiento de los elementos unitarios de dichos DAC (fuentes de corriente unitarias).
!
!
Los dos circuitos se han verificado mediante simulación eléctrica a nivel de transistor,
mostrando resultados satisfactorios y validando la metodología desarrollada en esta tesis.
(b)
(a)
(d)
(c)
Fig. 5: Ejemplo de modulador ΣΔ en cascada 3-2 diseñado en esta tesis: (a) Diagrama de bloques. (b)
Esquemático del transconductor sintonizable utilizado en filtro del lazo. (c) Layout del modulador. (d) Espectro
de salida obtenido por simulación eléctrica a nivel de transistor.
!
!
6. Conclusiones
Esta tesis doctoral representa una contribución al diseño de moduladores ΣΔ (MΣΔ)

realizados mediante técnicas de tiempo continuo (CT) para la implementación de convertidores
analógico-digitales (ADC) en tecnologías CMOS nanométricas. Los estudios llevados a cabo se
centran principalmente en topologías en cascada, las cuales resultan especialmente apropiadas
para aplicaciones de banda ancha (20MHz), en las que el uso de valores bajos de sobremuestreo
obliga a aumentar el orden del filtrado del lazo del modulador para conseguir una resolución
media (12 bits). A pesar de las potenciales ventajas en velocidad de las técnicas de circuito CT,
se han reportado muy pocos circuitos integrados de MΣΔ CT en cascada. Ello es debido
principalmente a la mayor sensibilidad de los MΣΔ CT a ciertos errores de circuito, como la
tolerancia de las constantes de tiempo y el “jitter” del reloj.
En este contexto, el trabajo desarrollado en esta tesis presenta una serie de herramientas
analíticas y metodológicas encaminadas a sistematizar el diseño de MΣΔ CT en cascada,
optimizando sus prestaciones en términos de consumo de potencia y área. Las principales
contribuciones de esta tesis son las siguientes:
• Se ha desarrollado una nueva metodología de diseño de MΣΔ CT en cascada basada en

realizar la síntesis directamente en el dominio del tiempo continuo, en lugar de aplicando
una transformada discreta-continua a un MΣΔ de tiempo discreto equivalente. Como
resultado, se obtienen circuitos más simples topológicamente y más robustos frente a
errores de tolerancia de sus componentes que los circuitos obtenidos con técnicas de
síntesis convencionales.
• Se ha analizado el impacto del error de “jitter” del reloj en MΣΔ CT con cuantización
multi-bit y convertidor digital-analógico con forma de onda sin retorno a cero (NRZ de
“Non Return to Zero”). El estudio – basado en el uso de formulación espacio-estado – es
aplicable tanto a topologías de modulador en cascada como de lazo simple, obteniéndose
ecuaciones de diseño para la potencia del ruido integrado en la banda de la señal y para la
relación señal ruido. El estudio demuestra matemáticamente que el efecto del jitter se debe
a dos componentes del error: una debida a los parámetros del filtro del lazo del
modulador, del sobremuestreo y del número de bits del cuantizador interno, y otra debida
!
!
a la frecuencia y amplitud de la señal de entrada (supuesta ésta sinusoidal). Dichas

ecuaciones permiten optimizar el diseño de los MΣΔ CT, obteniendo una frecuencia de
muestreo que minimiza la potencia del ruido “jitter” en la banda de la señal.
• Se han propuesto nuevas arquitecturas de MΣΔ CT en cascada obtenidas mediante la

metodología de síntesis propuesta, destacando dos topologías de quinto orden 2-2-1 y 3-2,
ésta última ilustrada en la Fig. 5(a) considerando una implementación Gm-C.
• A nivel de circuito, se ha considerado el diseño del filtro del lazo de los moduladores
empleando tanto integradores RC-activo como Gm-C. Para estos últimos, se ha propuesto
una nueva topología de transconductor sintonizable, mostrado en la Fig. 5(b), que utilizan
técnicas de linealización basadas en la cancelación del término cuadrático, y que
extienden el ancho de banda requerido mediante la introducción de un cero de
compensación en alta frecuencia.
• Se han demostrado las ventajas de las técnicas y metodologías propuestas a través del
diseño e implementación en una tecnología CMOS de 130nm de dos moduladores en
cascada.
o El primero de ellos es una cascada 2-2-1 cuyo filtro del lazo está implementado
por un integrador RC-activo frontal mientras que el resto son Gm-C.
o La segunda topología es una cascada 3-2, implementada mediante integradores

Gm-C y con resonación en las dos etapas para distribuir de forma óptima los ceros
de la función de transferencia del ruido en el ancho de banda de la señal.
Ambos moduladores operan con una frecuencia de muestreo de 240MHz y emplean

cuantización de 4 bits en todas las etapas, incluyendo algoritmos de corrección DEM en la
primera etapa para reducir el impacto de la no linealidad debida al DAC. Los dos circuitos
han sido validados mediante simulación eléctrica a nivel de transistor, considerando una
única fuente de alimentación de 1.2V. El primer prototipo (2-2-1) obtiene una resolución
efectiva de 13bits en un ancho de banda de 20MHz con un consumo de potencia estimado
de 60mW. El segundo prototipo (3-2), cuyo layout se muestra en la Fig. 5(c), obtiene
!
!
12bits@20MHz, teniendo un consumo estimado de 70mW. Como ilustración la Fig. 5(d)

muestra el espectro de salida del modulador.
Los resultados obtenidos en esta tesis demuestran la viabilidad del uso de MΣΔ CT en cascada
para la implementación de ADC en aplicaciones de banda ancha y proporcionan herramientas
metodológicas para desarrollar topologías que permitan aumentar las prestaciones de dichos
ADC en las próximas generaciones de sistemas de comunicación.
!
!
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!
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Modulator,” Proc. of 2005 IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 1-4, May
2005.
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!
ANEXO 1: CONVERTIDORES SIGMA-DELTA DE TIEMPO

CONTINUO – CONCEPTOS, ARQUITECTURAS,
CIRCUITOS Y ERRORES
RESUMEN
Este anexo presenta una descripción panorámica de los moduladores ΣΔ de tiempo continuo,
ofreciendo una explicación de sus fundamentos, arquitecturas principales, circuitos y errores.
Algunas partes de este anexo fueron incluidas en la siguiente publicación de la que el

doctorando es coautor:
A. Rodríguez-Vázquez, R. del Río, J.M. de la Rosa, R. Tortosa, F. Medeiro and B. Pérez-

Verdú: “Sigma-Delta CMOS ADCs: An Overview of The State-of-the-Art,” Chapter 2 in the
Book CMOS Telecom Data Converters, edited by A. Rodríguez-Vázquez, F. Medeiro, Edmond
Janssens. Kluwer Academic Publishers, 2003 (ISBN: 1-4020-7546-4).
!
Eq.St 1
Fg.St 1 Annex 1
Tt.St 1
1 Rf.St 0
Continuous-time Sigma-Delta Converters

Basic Concepts, Architectures , Circuits and Errors
1.1 Introduction
Sigma-Delta Modulators ( Ms) have demonstrated to be very suited for the imple-
mentation of the Analog-to-Digital (A/D) interface in many different electronic systems,
covering a large number of applications from instrumentation to telecom
[Nors97][Geer02][Rio06][Schr05]. This type of A/D Converters (ADCs), composed of a
low-resolution quantizer embedded in a feedback loop, uses oversampling (a sampling fre-
quency much larger than the Nyquist frequency) to reduce the quantization noise and
modulation to push this noise out of the signal band [Inos62]. The combined use of redun-
dant temporal data (oversampling) and filtering ( modulation) results in high-resolution,
robust ADCs, which have lower sensitivity to circuit parasitics and tolerances, and are more
suitable for the implementation of ADCs in nanometer CMOS technologies [Rodr03]
[Schr05].
The majority of Ms reported so far have been implemented using Discrete-Time

(DT) circuit techniques, mostly based on Switched-Capacitor (SC) circuits [Rio06]. How-
ever, the increasing demand for ever faster ADCs in broadband communication systems has
boosted the interest in Continuous-Time (CT) Ms. These modulators have intrinsic anti-
aliasing filtering and are able to operate at higher sampling rates with lower power con-
sumption than their DT counterparts [Bree01][Cher00] [Ortm06].
CT- Ms have much in common with DT- Ms, whose basic properties and limita-
tions have been described elsewhere [Nors97][Mede99][Pelu99][Rabi99] [Geer02][Rio06].
However, there are some characteristics which are peculiar to CT- Ms. This annex gives
an overview of their operating principles and architectures, circuit errors and models,
design methodologies and practical considerations.
1.2 Fundamentals of A/D Conversion
An ADC is a system that transforms signals which are continuous in time and amplitude
(analog signals) into DT signals which are quantized and codified in amplitude (digital sig-
nals). Fig. 1.1(a) shows the conceptual scheme of an ADC that includes the following com-
ponents: an Anti-Aliasing Filter (AAF), a Sampling-and-Hold (S/H) circuit, a quantizer and
a coder [Rosa02]. The operation of these blocks is illustrated in Fig. 1.1(b). First, the analog
input signal, x a t , passes through the anti-aliasing filter, removing the spectral compo-
nents above one half of the sampling frequency, f s , of the subsequent S/H. Otherwise, from
the Nyquist’s sampling theorem [Oppe89], high frequency components of x a t would be
folded or aliased into the signal bandwidth, B w , thus corrupting the signal information. The
resulting band-limited signal, x bl t , is sampled at a rate of f s by the S/H circuit, thus
yielding the discrete-time signal, x s n = x bl nT s . Following the S/H, the quantizer maps
the continuous range of amplitudes of x s n into a discrete set of levels. Finally, the coder
assigns an unique binary number to each level providing the output digital data, y d n .
As illustrated in Fig. 1.1(b) the fundamental processes involved in an ADC are: sam-
pling and quantization. The sampling process performs the continuous-to-discrete time con-
version of the input signal in time, whereas the quantization process performs the
continuous-to-discrete conversion of the input signal in amplitude. These two transforma-
tions present inherent errors that limit the performance of an ADC, even assuming ideal
components.
xa t x bl t xs n xc n yd n
S/H Coder
fs 2
fs
Anti-aliasing Filter Quantizer
(a)
x bl t
Analog-to-Digital
yd n
t n
Conversion
Sampling Coding
xs n xc n
Quantization
t nT s
(b)
Figure 1.1: Operation of an ADC. (a) Conceptual scheme. (b) Signal processing.
1.2.1 Sampling
Sampling imposes a limit on the bandwidth of the analog input signal. According to the
Nyquist theorem, the minimum frequency, f s , required for sampling a signal with no loss of
information is twice the signal bandwidth, B w , i.e f N = 2B w , also called the Nyquist fre-
quency. Based on this criterion, those ADCs in that analog signals are sampled at minimum
rate ( f s = f N ) are called Nyquist-rate, or simply, Nyquist converters. Otherwise, if the ratio
between f s and f N , is larger than unity, the ADC is known as Oversampling Converter, and
M f s f N stands for the oversampling ratio.
One advantage of oversampling converters is that they simplify the requirements placed
on the AAF. This is illustrated in Fig. 1.2. Note that the anti-aliasing filter for a Nyquist
converter must have a sharp transition band, thus introducing phase distortion in signal
components located near the cut-off frequency.
1.2.2 Quantization
Quantization itself also introduces a limitation on the performance of an ideal ADC. It

degrades the quality of the input signal whose continuous-valued levels are mapped onto a
finite number of discrete levels. In this process an error is generated, called quantization
error. Contrary to the sampling process, the quantization of a DT signal is a non-reversible
operation.
Fig. 1.3(a) shows the transfer characteristic of an ideal quantizer. This can be repre-
sented mathematically by a non-linear function as follows [Cand92],
y = gq x + eq x (1.1)
where g q denotes the slope of the line intersecting the code steps or quantizer gain; e q x
stands for the quantization error. This error is a non-linear function of the input signal, x , as
shown in Fig. 1.3(b). Note that, if x is confined to the interval x min x max , the quantiza-
tion error is bounded by the interval – 2 2 , with being the quantization step,
defined as the separation between consecutive levels in the quantizer. For an B-bit quan-
Xa f
AAF
(a)
B wf s 2 frequency
Xa f
AAF
(b)
fs 2 – Bw fs 2 frequency
Figure 1.2: AAF of: (a) Nyquist-rate converters. (b) Oversampling converters.
y q e
X FS
gq 1
x min x max x
– 2 2 e
(a) (c)
eq x e
gq
2 x y x y
x
– 2
(b) (d)
Figure 1.3: Ideal quantization process. (a) Ideal transfer characteristic. (b) Quantization
error. (c) Probability density function of additive, white quantization noise. (d) Linear
model of an ideal quantizer.
B
tizer, = X FS 2 – 1 , with X FS being the full-scale range of the quantizer (see
Fig. 1.3(a)). For inputs outside of that interval, the absolute value of the quantization error
grows monotonously. This situation is known as overloading of the quantizer.
1.2.3 Quantization white noise model
In order to evaluate the performance of an ideal quantizer, some assumptions are usu-
ally made on the properties of the quantization error. As shown in Fig. 1.3(b), e q x is
strongly dependent on the input signal, x . Nevertheless, if x varies randomly from sample
to sample in the interval x min x max , and the number of levels of the quantizer is large, it
can be shown [Benn48] that the quantization error distributes uniformly in the range
– 2 2 with the rectangular probability density, q e q , shown in Fig. 1.3(c), hav-
ing a constant Power Spectral Density (PSD). Because of that, the quantization error can be
modelled as an additive white noise source, e , as shown in Fig. 1.3(d), usually called quan-
2
tization noise. As the total quantization noise power, e is uniformly distributed in the
range – f s 2 f s 2 , its PSD equals
2
2 2
e 1 1 2
S E f = -------------- = --- --- e de = ---------- (1.2)
fs fs 12f s
– 2
and the in-band noise power, calculated as,
Bw
2
PQ = S E f df = ----------- (1.3)
12M
–Bw
decreases with M at a rate of 3dB/octave . This property is exploited by oversampling con-

verters by using large values of M .
Strictly speaking, the white noise approximation is not valid for single-bit quantizers or
comparators (very interesting in practice due to their simplicity). However, experience
shows that the results obtained with this model are also applicable to the mentioned quantiz-
ers [Cand92].
1.2.4 Quantization noise shaping
An approach to further increase the accuracy of an ADC consists of reducing the error
power within the signal band through the processing of the quantization error. Let us con-
sider an B -bit quantizer with an oversampled input signal. If the oversampling ratio is large
enough, with the signal only changing slightly from sample to sample, most of the changes
in the quantization error happen at high frequencies —i.e., low-frequency components of
consecutive samples of the quantization error are similar. Hence, low-frequency in-band
components of the quantization error can be attenuated by substracting the previous sample
from the current one,
e HP n = e n – e n – 1 (1.4)
Further reduction can be achieved by involving more previous error samples,
e HP,1 n = e n – e n – 1 , 1st-or error proc.

e HP,2 n = e n – 2e n – 1 + e n – 2 , 2nd-or error proc.
(1.5)
e HP,3 n = e n – 3e n – 1 + 3e n – 2 – e n – 3 , 3rd-or error proc.
,
The procedure can be formulated in an unified manner in the Z -domain as
–1 L
E HP L z = 1 – z E z (1.6)
showing that the processed error is a filtered version of the original. The filtering transfer
function —often called Noise Transfer Function— is therefore
–1 L
N TF z = 1 – z (1.7)
where L denotes the order of the filtering realized on the quantization error [Rodr03].
For this transfer function

j 2 –j 2L 2L 2L 2 f f
N TF e = 1–e =2 sin ---- , with = -------- = ------------ (1.8)
2 fs MB w
Within the signal band ( f B w ), « 1 if M is large enough. Hence, the transfer function
takes very small values in this range and the in-band power of the filtered quantization error
results in
+B w 2 2 2L
2
PQ = ---------- N TF f df ------ ------------------------------------------- (1.9)
– B w 12f s 12 2L + 1 M 2L + 1
that is much smaller than only applying oversampling —see (1.3).
Fig. 1.4 depicts the amplitude of NTF for – +

L = 1 . Note that the error reduction happens
due to:
• the high-pass shape of the transfer func-

tion, that yields large in-band attenua-
tion, pushing noise to high frequencies. – max = – ----- + max = + -----
M M
Real z
• the inverse dependence of the integra-
2
tion interval with M . NTF f
4
Only the dark area at the bottom of Fig. 1.4
is integrated, so that the in-band error power is a
small portion of the total thanks to the noise-
shaping action — the smaller the larger M
and/or L . Note from (1.9) that the high non-line- No shaping
1
arity of the shaping results into a non-linear
dependency of P Q with M [Rio06].
–fs 2 –Bw 0 +B w +f s 2
Figure 1.4: Amplitude of NTF for
1.3 Basics of ADCs 1st-order error processing.
ADCs combine oversampling and noise shaping to reduce the quantization error
within the signal band. These two strategies can be implemented by embedding a quantizer
in a feedback loop as illustrated in Fig. 1.5(a)†1[Rodr03]. This feedback system known as
a Modulator ( M) oversamples and quantizes the input signal, x , and filters the
quantization error, by shaping its PSD in such a way that most of its power lies outside of
the signal band.
†1. As will be discussed later on, Ms can be grouped into two groups: lowpass and bandpass, attend-
ing to the type of input signal. Fig. 1.5(a) corresponds to a lowpass M.
fS clock
x +
Y
y
(a) Loop Filter H z
DAC
x +
H f Y
y
(b) Loop Filter
Figure 1.5: Conceptual block diagram of a M. (a) Ideal topology considering a Low-
pass DT loop filter, H z . (b) Conceptual architecture with no sampling.
1.3.1 Understanding signal processing in a M
In order to better understand the way in which a M process the in-coming signal
information as it is, whereas shapes the associated quantization error, let us consider the
block diagram in Fig. 1.5(b). This system is the same as the one shown in Fig. 1.5(a) but
does not contains any sampling process. Assuming that the quantizer in Fig. 1.5(b) is repre-
sented by the linear, additive noise model of Fig. 1.3(d), this system can be viewed as a two-
input, x and e , one output, y , system, which in the frequency domain can be represented
by:
Y f = S TF f X f + N TF f E f (1.10)
where X f and E f are the Fourier transforms of the input signal and the quantization
noise, respectively; S TF and N TF are the transfer functions of the input signal and quanti-
zation noise, respectively given by:
gq H f 1
S TF f = ------------------------------ N TF f = ------------------------------ (1.11)
1 + gq H f 1 + gq H f
Note that, if the loop filter is designed such that H f within the signal band, then
S TF f 1 and N TF f 0 , i.e, the input signal is allowed to pass whereas the quantiza-
tion error is ideally cancelled. However, the error cannot be completely nulled in practice
because H f has a limited gain, and the PSD of the shaped quantization noise is given by:
2
S Q f = S E f N TF f (1.12)
and the shaped quantization noise in-band power is calculated as:
PQ = S Q f df (1.13)
Signal band
The shaped quantization noise power is further reduced in the signal band thanks to the
action of oversampling as discussed in Section 1.2.4. This can be implemented in different
ways depending on the type of dynamics used for the loop filter, which can be either Con-
tinuous-Time (CT) or Discrete-Time (DT). The majority of reported Ms use a DT loop
filter, H z . Thus, assuming g q = 1 and choosing H z such that:
1 –1 L
N TF z = --------------------- = 1 – z (1.14)
1+H z
the expression in (1.13) becomes the same as (1.9).
1.3.2 Performance metrics of Ms
At this point, it is convenient to introduce the most important specifications commonly

used to characterize the performance of oversampling converters.
• Signal-to-Noise Ratio, SNR . It is the ratio of the output power at the frequency of
an input sinusoide to the uncorrelated in-band error power. Ideally, only quantiza-
tion noise is accounted to compute SNR , expressed as:
A y2
SNR dB = 10log 10 ---------- (1.15)
2P Q
where A y is the amplitude of the output sinusoide. In practice however, and due to
non-idealities of the circuitry used to implement the converter, there are other error
contributions —linear and non-linear— to the in-band error power, apart from
quantization noise. To take into account all these errors, the Signal-to-(Noise plus
Distortion) Ratio ( SNDR ) is usually defined.
Note that the SNR monoto-

DR
nously increases with A y . SNRpeak
However, beyond a certain SNDRpeak
input amplitude, usually called
SNR, SNDR (dB)

overloading level, X OL , the
quantizer input lies outside of
the interval which produces the
overloading of the latter and
consequently a sharp drop is
0
observed in the SNR curve. Xmin XOL XFS/2
The value of the SNR at said Input signal amplitude, Ax (dBV)
input amplitude the maxi- Figure 1.6: Overloading in Ms.
mum value of SNR is often
called the SNR-peak . This is
illustrated in Fig. 1.6, that shows typical curves for the SNR and the SNDR of a
M as a function of the amplitude of a sinusoid signal applied at the modulator
input. Usually, both curves coincide for small and medium input levels, since the
distortion due to non-linear effects falls below the modulator noise floor. For large
input levels, harmonic distortion becomes more evident, causing performance deg-
radation and the deviation of the SNDR curve.
• Dynamic range, DR . It is defined as the ratio of the output power at the frequency
of an input sinusoid with maximum amplitude to the output power for a small input
for which SNR = 0dB ; i.e., so it cannot be distinguished from the error. Thus, ide-
ally, a sinusoid with maximum amplitude at the converter input X FS 2 will pro-
vide an output sinusoid sweeping the full-scale range Y FS of the modulator
quantizer, and hence
Y FS 2 2
DR dB = 10log 10 ------------------------ (1.16)
2P Q
Considering the expression of P Q , given in (1.9), the above expression can be re-
written as:
B 2L + 1
DR dB 20log 10 2 – 1 + 1.76 + 10log 10 ---------------- +
2L
(1.17)
+ 2L + 1 10log 10 M
which can be increased by properly combining the basic ingredients of Ms, i.e:
oversampling ( M ), noise-shaping filtering order ( L ) and the number of bits of the
120 L=5 20
L=4 18
Effective resolution, ENOB (bit)

L=3
100 16
Dynamic range, DR (dB)
14
80 L=2 12
60 10
L=1 8
40 6
4
20
L=0 2
0 0
1 2 4 8 16 32 64 128
Oversampling ratio, OSR
Figure 1.7: Ideal performance of oversampled converters. DR and ENOB versus

M for different order L of the modulator with B = 1 [Rio06].
internal quantizer ( B ). Each of these strategies have pros and cons which will be
discussed later on.
• Effective number of bits, ENOB . The DR of an ideal N -bit Nyquist-rate con-

verter can be written as [Plas03]
DR dB = 6.02N + 1.76 (1.18)
Following the analogy, a similar expression can be established for Ms
DR dB – 1.76
ENOB = -------------------------------- (1.19)
6.02
where the ENOB can be defined as the number of bits needed for an ideal Nyquist-
rate converter to achieve the same DR as the converter. Thus, the performance
of oversampled converters and Nyquist-rate ADCs can be compared in simple
way [Bose88].
To illustrate the ideal performance of Ms, Fig. 1.7 plots DR and ENOB as a func-
tion of M and L , considering a single-bit quantizer ( B = 1 ). Note that for M 4 , the com-
bined action of oversampling and noise-shaping considerably improve the performance of
the modulator [Rio06].
1.3.3 Block diagram and components of a ADC
Because Ms are feedback systems, the conceptual block diagram of Fig. 1.1 does not
fit well to make a ADC based on the M concept [Rodr03]. Indeed, the sampler and the
quantizer of Fig. 1.1 are cascaded in an open loop configuration, as it is actually the case for
a full Nyquist flash converter [Plas03]. Instead, the diagram of a ADC is better repre-
sented through Fig. 1.8, where Fig. 1.8(a) corresponds to DT- ADCs and Fig. 1.8(b) is
for a CT- ADC. In both cases, low-pass signals are assumed to be processed. Otherwise,
the filters involved must be changed from low-pass to band-pass transfer functions.
The diagram in Fig. 1.8 comprises three main blocks, whose operation in time and fre-
quency domain is conceptually illustrated in Fig. 1.9 for a lowpass sign:
• Anti-Aliasing Filter (AAF). The function of this block, identical to that in Nyquist-
rate ADCs, is attenuating the out-of-band components of the input signal in order
to avoid aliasing when it is sampled. However, as already explained, the use of
oversampling relaxes the attenuation requirements for this analog filter, because
the frequency components of the input in the range B w f s – B w do not fold
within the baseband. Note that, in the case of CT- ADCs, the input signal could
be either subject to AAF or feeds directly into the CT- M without preceding any
filtering. This can be done thanks to the implicit AAF which is embedded in CT-
Ms, as will be elaborated later.
xs(n) Y(n) Yf(n) Yd(n)

xa(t) xf(t)
S/H H(z) M
B-bit B N N
Bw fs -Bw fs Bw
fs
Anti-aliasing filter Digital filter Downsampler
DAC
Decimator
Modulator
(a)
xa(t) Y(n) Yf(n) Yd(n)

xf(t)
H(s) M
B-bit B N N
Bw fs -Bw Bw
fs
Anti-aliasing filter Digital filter Downsampler
DAC
Decimator
Modulator
(b)
Figure 1.8: Block diagram of an ADC. (a) DT- ADC. (b) CT- ADC.
• Sigma-Delta Modulator ( M). It simultaneously performs the sampling and

quantization of the in-coming signal. In addition, the quantization error is filtered
by means of a noise-shaping technique. This, combined with oversampling, greatly
enlarges the accuracy of the A/D conversion over that of the embedded quantizer
as has been explained previously. Note that, DT- Ms implement the sampling
operation at the modulator input (see Fig. 1.8(a)), whereas CT- Ms do it at the
quantizer input and the loop filter is CT see Fig. 1.8(b). Thus, the output signal
is DT and a DT-to-CT transformation is needed to create the feedback signal, y t .
The process of reconstruction this signal, by using proper output pulse shape of the
embedded Digital-to-Analog Converter (DAC), plays a significant role on the
overall CT- M performance as will be discussed later [Ortm06][Rodr03]. In both
cases, DT- and CT- ADCs, the output of the M is a B-bit digital stream at f s sam-
pling rate.
xa(t) xa (t) Xa (f) Anti-aliasing filter

Out-of-band
components
Anti-aliasing
filter
t fb fs /2 fs-fb fs f
xf (t)
xf (t)
Xf (f)
fs S/H
MODULATOR
xs(n)
t fb fs /2 fs-fb fs f
xs
H(z) Xs (f)
DAC
B-bit t fb fs /2 fs f
Quantization noise
Y Y(f) (noise-shaping)
B Y(n)
t fb fs /2 fs f
Digital
filter Yf
DECIMATOR
Yf (f) Digital
filter
N Yf(n)
t fb fs /2 fs f
OSR
Yd
Yd (f)
N
Yd(n) t fb fs f
Figure 1.9: Illustration of the signal processing in a ADC [Rio06].
• Error-Removal Filter + Decimator. This is a purely digital block and hence iden-
tical for both DT- and CT cases that takes the high-frequency (oversampled) dig-
ital stream as input, removes its high-frequency components through high-
selectivity digital filtering, and decimates it to reduce the sampling frequency down
to the Nyquist frequency. The result is the input signal encoded at the Nyquist rate
and with an equivalent resolution given by (1.19) [Rodr03].
Out of these blocks, the one influencing most the ADC performance is the M, basi-
cally because it is the ultimate responsible for the accuracy in the A/D conversion. Thus,
from now on, we will hence focus on this block although keeping in mind that a ADC
is more than just its M [Rio06].
1.3.4 Classification of Ms
A large number of M architectures have been reported in literature that implement

some (or all) the following, non-exclusive, strategies to improve DR :
• Increasing the loop filter order, L . According to (1.17), for a given M , the
increase in DR when increasing the modulator order L in one, leads to
2L + 3 M 2
DR dB 10log 10 ---------------- ----- (1.20)
2L + 1
However, the use of high-order shaping (usually L 3 ) gives rise to stability prob-
lems. These problems can be circumvented using different techniques at the price
of reducing DR as compared with the ideal value given by (1.17) [Nors97].
• Increasing the oversampling ratio, M , leads to an increase of

L + 1 2 bit/octave in the effective resolution of the modulator. However, high
values of M are limited in practice for wideband signals, because of the prohibitive
sampling frequencies required, which force the circuitry to operate very fast, with
the subsequent penalty in power consumption.
• Increasing the number of bits of the internal quantizer, B , leads to an increase of

6dB ( 1bit ) in the modulator DR for each extra bit in the quantizer [Geer02]. The
problem associated with using B 1 , is that a multi-bit DAC is required in the
feedback loop of the modulators, that on the contrary to single-bit ones, with only
two levels is not inherently linear. Thus, in practice the linearity in the DAC
equals that wanted for the M [Rio06].
The above mentioned strategies can be combined in many different ways, giving rise to
a pleyade of M topologies reported in literature and that can be grouped attending to dif-
ferent classification criteria [Rodr03]:
• The nature of the signals being handled: lowpass Ms versus bandpass Ms.
• The number of quantizers employed. Ms employing only one quantizer are

called single-loop structures. Those employing several quantizers have different
names: cascade, dual-quantization, truncation-feedback, etc.
• Type of circuitry employed, primitives available in the fabrication technology, volt-

age supply, etc. Most of the reported DT implementations employ switched-capac-
itor circuits with high-quality passive capacitors mixed-signal technology
options. Others employ the passive capacitor structures available on standard
CMOS technologies. Others employ active capacitors built with MOS transistors.
Others employ switched-current circuits realized only with MOS transistors, etc.
• The type of dynamics for the loop filter. The majority of reported Ms used DT
loop filters. However, the increasing demand for even faster ADCs has motivated
the use of CT loop filters, which combined with a DT quantizer (see Fig. 1.8(b))
leads to the so-called CT- Ms which are the main objective of this thesis.
Describing all possible M architectures derived from previous classification goes

beyond the scope of this thesis. A detailed study of them can be found in many papers and
books [Nors97][Mede99][Schr05][Rio06][Ortm06]. Instead, we will focus on those aspects
which are specific to CT- Ms.
1.4 Continuous-Time Modulators
Although early implementations of Ms were based on the use of CT, discrete-com-

ponent, loop filters [Inos62][Inos63], the increasing development of SC circuits and their
suitability to implement robust and linear filters using standard CMOS technologies, caused
that the immense majority of Ms were implemented using DT circuit techniques and par-
ticularly SC circuits [Schr05]. However, in the last years there has been a resurgence of CT
Ms prompted by the increasing demand for high data-rate ADCs [Ortm06]. As it will be
described in this section, CT Ms have the potential to operate at higher sampling rates
with lower power consumption than their DT counterparts and, in addition, they implement
an implicit AAF leading to a more compact implementation.
Looking at both topologies depicted in Fig. 1.8, one can see a few, but important, differ-
ences among DT- and CT- Ms. Apart from the obvious and already mentioned difference
between the nature of the loop filter, the most significant difference is related to the point
where the S/H process takes place, which possibly constitutes the key advantage of CT-
Ms [Ortm06]. In the case of CT- M, S/H is realized inside the M loop, which
implies three fundamental benefits: relaxed dynamic (settling) requirements for the loop fil-
ter circuitry; implicit antialiasing filtering and elimination of the input switches. However,
as both DT- and CT- signals are involved, the mathematical analysis (and consequently the
synthesis) of CT- Ms becomes much more difficult than in the case of DT- Ms.
Both theoretical and practical issues associated to CT- Ms have been addressed in
several monographs [Bree01][Cher00][Enge99][Shoa95][Rodr03]. Their claimed pros can
be summarized as:
• Extra anti-aliasing filter can be avoided, or at least, the required specifications of

the front-end AAF can be relaxed. Instead the CT loop filter H s can be exploited
to this purpose as will be explained in more detail in Section 1.4.4.
• Less impact of errors caused during sampling operation. This is a consequence of

the fact that sampling is not realized at the input, where its error cannot be attenu-
ated, but within the modulator loop. Indeed, one of the main benefits is avoiding
the use of sampling switches, which among other advantages, allows loop filters to
operate with low voltage supply. On the contrary, sampling switch-on resistance is
an important limiting factor in SC implementations, and as the supply voltage
reduces with technology downscaling, making necessary the use of circuit tech-
niques like clock boosting, that introduce additional parasitics.
• No “settling” error at the loop filter circuitry. In DT circuits, signals must settle to
their steady-state values according to dynamic features of the circuitry [Rio06].
Complete settling requires infinite time. In practice settling process must last until
the influence of the circuit time-constants becomes negligible. In contrast, CT-
M present larger operation speed. This is inherent to the operation of CT cir-
cuits, where circuit dynamics is not a parasitic (as it happens for DT circuits), but
a design primitive.
• No sampling of the k T C (thermal) noise at the input capacitors a by-product

of the location of the sampling operation. Therefore, the in-band noise power is
lower than in DT- Ms where a large amount of thermal noise is fold back into the
signal band, constituting a fundamental resolution limit [Ortm06].
• Reduced digital noise coupling since switching process is attenuated by the action
of the modulator feedback, in the same way as for the quantization noise.
On the other hand, the main cons of CT- Ms are the following:
• Very involved dynamic due to the combination of non-linearity, continuous-time

and discrete-time signals.This makes the mathematics of the CT- M system
much more complicated than for DT- Ms, which has a natural connection with
their circuit-level implementation, through the use of the Z-transform of the finite
difference equations describing the behavior of the system.
• Larger impact of circuit non-linearities. This is inherent to CT circuits. These cir-

cuits require voltage-to-current transformation, and this yields nonlinear errors.
These errors may have significant impact, particularly those appearing at the very
input because they are not attenuated by the modulator feedback loop.
• Time constant tuning is needed for correct loop filtering. This is also inherent to CT
circuits where time constants are given as the product of two un-correlated param-
eters.
• Time uncertainty ( or clock “jitter”) plays a significant role because it maps

directly onto errors in the feedback signal y t . This is not the case of DT imple-
mentations, which thanks to their sample-data nature, presents relaxed sensitivity
to timing variations or delays within the loop filter, both of which constitute a
strong limitation in CT- Ms [Ortm06].
1.4.1 Approximated linear analysis of CT- Ms
In order to understand basics and fundamental concepts of the signal processing in CT-
Ms, let us consider the conceptual block diagram shown in Fig. 1.10. For the analysis
that follows, it will be considered that the feeback DAC has a gain of approximately unity in
the signal band†2. Under this assumption and considering a linear model for the quantizer,
the modulator in Fig. 1.10(a) can be transformed into the one depicted in Fig. 1.10(b).
ui uo û o
x H s y
B-bit
fs
S/H
DAC
(a)
ui uo û o g sh t b g
x g1 H s q y
Ts
fs
g' 1 Eq
(b)
Figure 1.10: (a) Conceptual block diagram of a CT- M. (b) Simplified model.
†2. The effect of actual DAC waveform will be analysed in next section.
A basic analysis of Fig. 1.10(b) shows that the frequency transform of the modulator
output and the loop filter input are respectively given by:
U i = g 1 X f – g' 1 Y f
(1.21)
Y f = Eq f + gq B f
where E q f and B f are respectively the frequency-domain transform of the quantization

error, e t , and the quantization input, b t .
On the other hand, the sampling operation can be mathematically expressed as:
b t = û o t g sh t (1.22)
where the operator stands for the convolution, û oˆ t is the sampled version of the
integrator output, û o t , given by:
uô t = u o nT s t – nT s (1.23)
n
and g sh t is the impulsive response of the S/H block, given by:
1 0 t Ts
g sh t = (1.24)
0 t Ts t 0
where T s is the sampling time.
Applying the Fourier-transform of (1.23) and (1.24) and replacying the result in (1.22),
we obtain that:
B f = sinc fT s U o f – nf s (1.25)
n
where sinc x sin x x . Note that, in those cases where M » 1 , fT s « 1 and hence,
2 4
2 4
sinc fT s 1 – ------ f f s + --------- f f s 1 (1.26)
6 120
Assuming a band-limited input signal, i.e the input frequency, f i 0 B w , and

neglecting the spectral components of y t above f s 2 , it can be shown that:
Y f S TF f X f + N TF f Eq f (1.27)
where
g1 gq H f 1
S TF f = --------------------------------- N TF f = --------------------------------- (1.28)
1 + g' 1 g q H f 1 + g' 1 g q H f
which are the same expressions as those obtained in (1.11) with g 1 = g' 1 = g q = 1 .
1.4.1.1 First-order CT- M
As discussed earlier, the loop filter must be designed such that H f within the
signal band. The simplest CT function that verifies this condition is:
1
H f = ------------- (1.29)
2 jf
where stands for the time constant of the circuit implementing H f . Thus, replacing
H f in (1.27) and (1.28) gives:
g1 gq 2 jf
Y f = -------------------------------- X f + -------------------------------- E q f (1.30)
g' 1 g q + 2 jf g' 1 g q + 2 jf
Assuming g 1 = g' 1 and g q = 1 g 1 and taking the limit of the above expression for
f 0 , the Fourier transform of the modulator output can be written as:
Y f X f + 2 jf Eq f (1.31)
that corresponds with the Fourier Transform of the input signal plus a shaped version of the
quantization error.
The in-band noise can be derived from (1.13) and (1.31), giving:
2 B w 2 – arctg Bw 2
P Q = ---------- ------------------------------------------------------------------- (1.32)
12f s
It is usually a common situation in CT- Ms to make T s = 1 f s [Ortm06],

because this maximizes the performance of the modulator. Fig. 1.11 illustrates this by plot-
ting the SNR vs. in a second-order ( L = 2 ) CT- M, for different values of the oversam-
pling ratio. Note that, the maximum value of the SNR is achieved when T s . Taking this
into account and assuming the Taylor series expansion for M » , the above expression can
be simplified as:
2 3 5 2 2
M– M – 1 3 M + 1 5 M
P Q = ------ -------------------------------------------------------------------------------------------------------------------------- ------ ----------- (1.33)
12 12 3M 3
which corresponds to the in-band noise power of a M with L = 1 and B = 1 .
1.4.1.2 Second- and Lth-order CT- M
The above approximated analysis can be extended to 2nd- and Lth-order CT- Ms. Let
us consider the modulator in Fig. 1.12(a), which implements a 2nd-order loop filter. Assum-
ing that f s = 1 , g q = 1 g 2 g' 1 and that H f has the same expression as (1.29), the fre-
quency transform of the modulator output can be written as:
100
90 M=128
80
70 M=64
SNR (dB)
60
M=32
50
40
30
20
10
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Ts
Figure 1.11: SNR vs. in a 2nd-order CT- M for different values of M.
x y
H s H s S/H
g1 g2
g' 1 g' 2
(a)
x y
H s H s H s S/H
g1 g2 g3
g' 1 g' 2 g' 3
(b)
Figure 1.12: Generic single-loop CT- Ms. (a) 2nd-order. (b) Lth-order.
g1 2
Y f = ------ X f + 2 jf f s E q f (1.34)
g' 1
In a more general case of a Lth-order loop filter like the one shown in Fig. 1.12(b), the
following expression is obtained:
g1 L g1 L
Y f ------ X f + 1 H f E q f = ------ X f + 2 jf Eq f (1.35)
g' 1 g' 1
Following the same procedure as in Section 1.4.1.1, the in-band noise power can be
obtained, giving the same result as in (1.9).
1.4.2 DT-to-CT equivalence and the impulse-invariant transformation
The above analysis assumed that M » 1 and an ideal DAC impulsive response. How-
ever, in a CT- M the output signal must be transformed from DT- to CT- in the feedback
loop. This signal reconstruction is very critical and has a significant impact on the overall
behaviour of the modulator [Shoa95]. There are a pleyade of DAC waveforms that can be
used in CT- Ms. Fig. 1.13 shows a survey of the different possibilities including the
nomenclature used for the feedback waveforms extracted from [Ortm06]. Among others
the most commonly used DACs incorporate rectangular feedback pulses of basically three
types: Non-Return-to-Zero (NRZ) (Fig. 1.13(a)), Return-to-Zero (RZ) (Fig. 1.13(b)) and
Half-delay Return-to-Zero (HRZ) (Fig. 1.13(c)). Their inpulsive response can be written as:
1 p1 Ts t p2 Ts
DAC t = (1.36)
0 ioc
and their corresponding Laplace S-transform is given by:
p1 = 0 p2 = 1 for NRZ
– sp 1 T s – sp 2 T s
e –e p1 = 0 p2 = 1 2 for RZ
DAC s = ---------------------------------------- (1.37)
s
p1 = 1 2 p2 = 1 for HRZ
Let us consider the above transfer function for the DAC and the basic block diagram of
a CT- M shown in Fig. 1.10. Because of the presence of a S/H inside the loop, the overall
(open) loop filter of the modulator is indeed a DT function as it illustrated in Fig. 1.14. Note
that, as the signal travels across the open loop path, it is first transformed into a CT signal
by the DAC. Assuming the DAC shapes in (1.36) the following feedback waveform is
obtained per each period,
y t = y n p DAC t = y n u t – p1 n TS – u t – p2 n TS (1.38)
where u denotes the unit step waveform and p 1 and p 2 are given in (1.37) for the
three basic DAC shapes. After this transformation, the signal shaped by the CT filter H s ,
which in Laplace domain can be expressed as,
–s p1 TS –s p2 TS
e------------------------------------------------------
–e
Z s = H s - (1.39)
s
Finally, the signal z t is sampled, which in time domain can be expressed as:
z n = z t t – n TS (1.40)
n=0
DAC t DAC t DAC t

1 1 1
NRZ RZ HRZ
Ts t Ts 2 t Ts 2 Ts t
(a) (b) (c)
DAC t DAC t DAC t

1 1 1
td t1 Ts t td t1 Ts t td t1 Ts t
(d) (e) (f)
DAC t DAC t DAC t

1
1 1
Ts t td t1 Ts t td t1 Ts t
(g) (h) (i)

Figure 1.13: Common DAC feedback impulse responses [Ortm06]. Rectangular wave-
forms: (a) Non-Return-to-Zerod (NRZ); (b) Return-to-Zero (RZ); (c) Half-Return to Zero
(HRZ). Decaying waveforms: (d) Linear decaying; (e) Quadratic decaying; (f) Exponen-
tial decaying, Swiched-Capacitor Resitor (SCR). Other waveforms: (g) Cosine. (h) Non-
linear slope. (i) Linear slope.
where is the Dirac delta. By combining previous expressions, the transfer function
of the overall feedback path is calculated as:
–1
H z = Z L DAC s H s t – n TS (1.41)
n=0
where Z stands for the Z-transform operator, L stands for the Laplace-trans-
form operator.
Based on the equivalent DT loop filter transfer function shown in (1.41), the most usual
procedure to design CT- Ms consists of, first, matching this equivalent filter with a refer-
ence DT loop filter chosen to fulfil specs; then, solving for the coefficients of the CT filter;
and finally implementing this filter by circuits. Careful choice of the CT filter structure is
needed to have sufficient degrees of freedom to implement the reference DT loop filter
[Enge99].
1.4.3 Direct synthesis method
An alternative method for the design of the loop filter uses the desired NTF as a starting
point, just in the same manner as for the DT case. Usually, an inverse Chevychev distribu-
tion of the NTF zeroes is considered because it has advantages in terms of SNR and stability
[Risb94]. Once the desired NTF has been chosen, the necessary loop filter can be derived
from the linearized model [Bree01]. As an illustration, Fig. 1.15(a) shows a third-order sin-
gle-loop CT- M which has been synthesized using a direct synthesis method [Ortm06].
The scaling coefficients, k i , have been obtained considering a Chebyshev type II distribu-
tion of NTF zeroes, giving k 1 k 2 k 3 = 0.51, 0.97, 1.95,0.04/ k 2 k 3 . The corre-
x x1 t x1 n yn
fs
H s
DAC s
x = 0
E z = 0
yn y t x1 t x1 n
DAC s fs
X1 z
H s H z = -------------
Y z
Figure 1.14: Equivalent DT transfer function in CT- Ms.

sponding output spectrum is shown in Fig. 1.15(b), considering a sampling frequency of

f s = 100MHz , a NRZ DAC waveform and a 3-bit quantizer.
There are two major drawbacks to the direct synthesis method:
• Previous knowledge of discrete time modulators is not reused. This rises questions
about stability.
• Simulations are harder due to the fact that every simulation has to be done in con-
tinuous time.
The above reasons have prompted that most implemented CT- M ICs are synthesized
using a DT-to-CT method, including both single-loop and cascade M architectures
[Bree04]. However, as demonstrated in this thesis, using the direct synthesis method, more
robust and efficient cascade architectures can be obtained as compared to DT-to-CT trans-
formation.
k1 k2 k3
x t -------
- -------
- -------
- y n
sT s sT s sT s B-bit
fs
DAC
(a)
–20
–40
–60
–80
Magnitude (dB)
–100
–120
–140
–160
–180
–5 –4 –3 –2 –1 0
10 10 10 10 10 10
(b) Normalized frequency (f/fs)
Figure 1.15: 3rd-order CT- M with Chebyshev loop filter approximation [Ortm06]. (a)
Block diagram. (b) Output spectrum.
1.4.4 Implicit anti-aliasing filtering
As stated previously, CT- Ms have the advantage of including an implicit AAF. This
property has been analytically demonstrated in previous works [Cand85][Shoa95], and can
be explained as follows. Let us consider the conceptual diagram of a CT- M in
Fig. 1.14(a). This block diagram can be transformed in the one shown in Fig. 1.16(a), in
which the loop filter and the implicit S/H block are realocated across the summation point
and placed in front of the CT- M and the feedback loop filter. Note that the resulting For-
ward Filter (FF), FF s , is not necessarily identical to the Feedback loop filter, LF s .
This is a direct consequence of the fact that in a CT- M, the input signal is CT and the out-
put signal is DT. Therefore, it is not possible to define a straight Z-domain or S-domain STF
[Cand85][Shoa95][Ortm06].
The block diagram shown in Fig. 1.16(a) reveals that, as was discussed in previous sec-
tions, a CT- M behaves as a DT- M due to the sampling operation in the feedback path,
but with an additional CT Forward Filter, FF s . So, the corresponding STF frequency
response can be obtained from the block diagram in Fig. 1.16(b). From this figure, the AAF
can be approximately expressed as [Shoa95]:
FF j
F AAF = -------------------- (1.42)
j
FF e
j
where FF j is the FF filter of the CT- M and FF e its DT equivalent. The above
equation shows that the AAF-behaviour can be defined for different loop filter characteris-
tics, i.e low-pass, band-pass, etc [Ortm06].
x1 n
x t y n
FF s fs
DAC s
fs LF s
(a)
1 x n FF z -
x t FF s --------------- ----------------------- y n
FF z 1 + LF z
F AAF fs
(b)
Figure 1.16: (a) Equivalent representation of a CT- M and (b) Implicit AAF.
As an illustration, the aliasing behaviour of a 2nd- and 3rd-order CT- Ms shown in

Fig. 1.17 is discussed. The original CT FF filter for both architectures is given by:
fs 2 fs 3
FF 2nd-ord s = k in --- FF 3rd-ord s = k in --- (1.43)
s s
x k in I1 s I2 s y
B-bit
fs
–k1 –k2
DAC
FF s LF s
x k in I1 s I2 s y
B-bit
fs
–k1 –k2
I1 s I2 s DAC
(a)
x k in I1 s I2 s I3 s y
B-bit
fs
–k1 –k2 –k3
DAC
LF s
x k in I1 s I2 s I3 s y
B-bit
fs
FF s
–k1 –k2 –k3
I1 s I2 s I3 s DAC
(b)
Figure 1.17: Implicit AAF in: (a) 2nd-order CT- M- (b) 3rd-order CT- M.
and the equivalent DT FFs are:
–1 2 –1 3
z z
FF 2nd-ord z = k in ---------------- FF 3rd-ord z = k in ---------------- (1.44)
–1 –1
1–z 1–z
Inserting the above expressions in (1.42) and after a few simplifications we obtain the
AAF transfer function for the 2nd- ( L = 2 ) and 3rd-order ( L = 3 ) CT- M, given by:
–j L
fs j 1–e f L
F AAF = ------------------------------------------
- sin c ----- (1.45)
–j fs
e
which consists of the well-known sinc-function, defined as sin c x sin x x . The effect
of AAF is better illustrated by simulations as shown in Fig. 1.18, where the output spectra
of a 2nd-order DT- and CT- Ms are plotted considering two input sinewave signals, one
in-band and the other out-of-band. It can be noted the effect of the implicit AAF in the CT-
M, causing a notable attenuation (almost 60dB) of the aliased signal, as compared to the
DT case.
1.5 DT-to-CT synthesis methods and basic CT- M architectures
As stated in previous section, most CT- Ms are synthesized starting from an equiva-
lent DT- M that fullfils the required specifications and applying a DT-to-CT transforma-
tion. The most common transformation method is the impulsive-invariant explained in
0 0
DT- M Aliased signal CT- M

– 20 – 20
Aliased
Input Input signal
– 40 – 40
Signal Signal
Magnitude (dB)
Magnitude (dB)
– 60 – 60
– 80 – 80
– 100 – 100
– 120 – 120
– 140 – 140
0 2 4 6 0 2 4 6
10 10 10 10 10 10 10 10
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 1.18: Antialiasing filtering in 2nd-order CT- Ms for an input signal at fin=1kHz
and a "non-desired" signal at fs 5kHz with fs=1MHz. (a) DT. (b) CT.
Section 1.4.2. This method allows the design of a CT loop filter, which together with a spe-
cific DAC transfer function, DAC s , exactly matches the noise-shaping behaviour of the
original DT loop filter. Thus, for given specific M architecture, the DT-to-CT transfor-
mation can be done using (1.41) for the corresponding loop filter [Ortm06]. Most DT loop
filters can be divided into partial fractions of type, 1 z – z k , for the low-pass case, and of
2 2
type, 1 z + z k , for the band-pass case. For that reason, it is very useful to know the S-Z
equivalents of basic LP and BP Z-domain transfer functions as summarized in Table 1.1
[Cher00][Ortm06], where rectangular DAC waveforms are considered. Based on the equiv-
alence of basic transfer functions, more complex loop filter transfer functions can be syn-
thesized as will be illustrated later on.
In addition to the above-mentioned impulse-invariant transformation method, there are

other, less-usual, DT-to-CT transformation methods that have been used to synthesize CT-
Ms: the modified Z-transformation [Shoa95][Abus02] and the state-space representation
method [Schr96][Olia03]. Both methods are summarized below.
Table 1.1:DT-CT equivalence with rectangular DAC waveform
Z-domain S-domain
–1
z fs
--------------- -----o- where o = ---------------
-
1–z
–1 s p2 – p1
–2 2
z 1s + o fs 1 fs p1 + p2 – 2
----------------------2- --------------------- where = ---------------
-; = --- ---------------------------------
-
–1 o 1
1–z s p2 – p1 2 p2 – p1
2 2
fs 1 fs p1 + p2 – 3
–3 2 o = ---------------
-; 1 = --- ----------------------------------
-
z 2s + 1s + o p2 – p1 2 p2 – p1
----------------------3- --------------------------------------- where
1–z
–1 s 1 f s p 2 p 2 – 9 + p 1 p 1 – 9 + 4p 1 p 2 + 12
2 = ------ -------------------------------------------------------------------------------------------------
-
12 p2 – p1
Bandpass CT- Ms
–1 –1
z 1–z
-------------------------------
–2
- (NRZ)
1+z
2 –1 2 –2
1 – ------- z – ------- z
2 2
--------------------------------------------------------------
-
1+z
–2 o s
-----------------
-
2 2
(RZ) s + o
2 2
------- z – 1 – 1 – ------- z – 2
2 2
---------------------------------------------------------------
–2
1+z
(HRZ)
1.5.1 Modified Z-transformation method
The modified Z-transform method is based on the general modified Z-transform, that
allows to calculate the DT system behaviour at all instants of time. Thus, in order to find out
the equivalent CT loop filter for a certain modulator architecture with a certain feedback
DAC pulse shape, the DT loop filter transfer function is computed and compared with the
original DT loop filter function, similarly to the case of impulse invariant method, giving
the following equivalence [Ortm06]:
H z = Z mi H s DAC s (1.46)
i
where m i is the characteristic parameter of the modified Z-transform. The value of m i is
normalized to the sampling period and bounded between, 0 m i 1 , whereas the extremes
0 confirm to the previous sample instant and 1 to the next [Ortm06]. Thus, assuming a rec-
tangular DAC waveform, (1.46) can be expressed as:
m1 Ts s m2 Ts s
H s e H s e
H z = Re ----------- ------------------ – Re ----------- ------------------ (1.47)
s Ts s s Ts s
i z–e i z–e
where m 1 = 1 – t d T s ; m 1 = 1 – t d + T s ; t d and are, respectively, the time delay

and pulse width of the DAC waveform; p i are the poles of H s s and Re x stands for
the residue of x [Shoa95][Abus02].
Generally speaking, for every time instant in which the CT loop filter changes its
behaviour, an additional delay factor is introduced. This is the role played by coefficients
m 1 and m 2 in (1.47). As an illustration of the modified Z-transformation, Table 1.2 shows
several usual examples of S-domain transfer functions and their corresponding modified
transforms [Ortm06].
Table 1.2:DT-CT equivalence Using Modified Z-Transform
S-domain Zm-domain equivalent
1 mT Ts
----
2
----------s- + -----------------
-
s z–1 z–1
2
– s k mT s
1 -
------------------- 1- ----------
1- e
--- – --------------------
-
s s + sk sk z – 1 –sk T s
z–e
2
1- T m2 2m + 1 2
---
3
----s- ----------- + ------------------ + ------------------
s 2 z–1 z–1
2
z–1
3
– s mT
1 1 s k mT s – 1 sk Ts k s
----------------------
- e
2 ---2- ----------------------
- + -----------------
- + -------------------------
s s + sk sk z–1 z–1
2 – s k Ts
z–e
1.5.2 State-space representation method
Let us consider the conceptual block diagram shown in Fig. 1.14. Using the impulse-
invariant transformation [Proa98], the DT equivalent of the loop filter transfer function can
be written as:
n L–1 z L–1 + + n1 z + n0
H z = -------------------------------------------------------------------------------------------- (1.48)
L
dL z + d L – 1 z L – 1 + + d1 z + d0
where n i and d i are function of the coefficients of the original CT modulator loop filter,
H s . Therefore, N TF z can be derived from (1.48) as:
L L–1
1 dN z + dN – 1 z + + d1 z + d0
N TF z = --------------------- = ---------------------------------------------------------------------------------------------------------------------------------------------- =
1+H z L
dL z + dL – 1 + nL – 1 z L – 1 + + d1 + n1 z + d0 + n0
(1.49)
– 1 – L–1 –L
dL + dL –1 z + + d1 z + d0 z
= -------------------------------------------------------------------------------------------------------------------------------------------------------------
– L–1 –L
dL + dL – 1 + nL – 1 z –1 + + d1 + n1 z + d0 + n0 z
Fig. 1.19 shows the transpose of the Direct II implementation of (1.49) [Proa98]. This
block diagram does not have any direct correspondence with the physical implementation
of the modulator and is only used to represent the relationship between the input e n , out-
put q n and state variables of N TF z . This formulation is known as the state-space repre-
sentation of N TF z and can be implemented by the block diagram in Fig. 1.20, which is
described by the following finite difference equations [Proa98]:
e(n)
d0 d1 d2 dL-1
dL dL dL dL
v1 v2 vL
z -1
z -1
z -1 q(n)
n0+d0 n1+d1 n2+d2 nL-1+dL-1
dL dL dL dL
Figure 1.19: Transpose of the Direct II implementation of NTF(z).
v n+1 0 v n 0
e n –1
q n
p0 z g0
F0
Figure 1.20: State-space representation of NTF(z).
v n + 1 0 = F0 v n 0 + p0 e n
(1.50)
T
q n = g0 v n 0+e n
where F 0 is the state matrix, v n 0 is the L 1 state vector, p 0 and g 0 are L 1 vectors,
respectively given by:
n0 + d0
0 0 0 0 – ----------------
-
dL
n1 + d1 n
1 0 0 0 – ----------------
- ----0-
dL dL
0
n2 + d2 n
0 1 0 0 – ----------------
- ----1- 0
F0 = dL p0 = – dL g0 = (1.51)
n3 + d3
0 0 1 0 – ----------------
- 1
dL nL – 1
-----------
dL
nL – 1 + dL – 1
0 0 0 1 – ------------------------------
dL
Equation system (1.50) can be solved recursively to find the relation between the initial
state v 0 0 , previous inputs e k , current input e n and output q n of the system
[Proa98].
1.5.3 Basic CT- M architectures
The DT-to-CT transformation methods described in previous sections have been used
extensively to synthesize a number of CT- M architectures. Indeed, practically any given
DT- M topology reported in literature can be transformed into its CT- M counterpart by
using any of these DT-to-CT methods. However, describing every DT topology and its cor-
responding CT transformation is beyond the scope of this thesis and it can be found in a
number of monographs and books [Abus02][Cher00][Ortm06][Shoa95].
1.5.3.1 Single-quantizer lowpass CT- M architectures
We will start the review of basic CT modulator architectures with the single-loop sec-
ond-order topology shown in Fig. 1.21(a). This modulator uses FE integrators with a Z-
domain transfer function given by:
–1
z
I z = ---------------- (1.52)
–1
1–z
The open loop filter transfer function of the M in Fig. 1.21(a) defined as the trans-
fer function from the quantizer output to the quantizer input, is given by [Ortm06]:
2 a2 a1 a2
LF z = – a 2 I z – a 1 a 2 I z = – ----------- – ------------------ (1.53)
z–1 z–1 2
Considering the S-Z transformations given in Table 1.1 and assuming a NRZ DAC wave-
form, it is easy to show that the DT-to-CT transformation of (1.53) is given by:
2
a1 a2 fs f
LF s = – a 2 – ----------- --- – a 1 a 2 ----s- (1.54)
2 s s
2
One possible implementation of the open loop filter in (1.54) is shown in Fig. 1.21(b),
where I s = f s s is the CT integrator transfer function, and g i , are the feedback coeffi-
cients given by:
a1 a2
g 1 = g 1' = a 1 a 2 ; g 2 = a 2 – ----------- (1.55)
2
From (1.54) and (1.55), the CT loop filter yields:
2
fs fs
H s = LF s = – g 2 --- – g 1' ----- (1.56)
s s
2
whose scaling coefficients can be chosing such that the CT- M in Fig. 1.21(b) behaves
x g in
+ a1 I z
+ a2 I z y
(a)
B-bit
fs
DAC
x g in
+ I s
+ I s y
(b)
B-bit
fs
g 1' g2
DAC
Figure 1.21: Second-order M. (a) DT block diagram. (b) CT equivalent.

exactly as its DT counterpart in Fig. 1.21(a). This is illustrated in Fig. 1.22 that represents
the output spectra of both modulators and the scaling coefficients proposed in [Marq98]
have been used.
It is important to note that, the transfer function found in (1.56) and its associated mod-
ulator architecture, varies with the DT-to-CT transformation method and the DAC wave-
form used. Thus, for a general rectangular DAC waveform, the corresponding feedback
coefficients of a 2nd-order and a 3rd-order CT- Ms are given by [Ortm06]:
·
2
----- + p 1 + p 2 – 2
a1 a2 a1 a2 a1
2nd-order g 1' = ----------------- ; g 2 = ----------- ---------------------------------------
p2 – p1 2 p2 – p1
·
2-
---- + p1 + p2 – 3 (1.57)
a1 a2 a3 a1 a2 a3 a1
g 1' = ----------------- ; g 2 = ----------------- ---------------------------------------
3rd-order p2 – p1 2 p2 – p1
a 1 a 2 a 3 p1 p1 – 9 + p2 p2 – 9 + 4p1 p2 + 6 a1 p1 + p2 + 12 a1 1 a2 + a1 – 1
g 3 = ----------------- ----------------------------------------------------------------------------------------------------------------
-
12 p2 – p1
Alternatively, if a modified Z-transformation is used and considering a SCR DAC (see

Fig. 1.13(f)), with an impulsive response given by:
–tp s + 1 DAC
– st d 1---------------------------------------------
–e
DAC s = e - (1.58)
s + 1 DAC
where t p = t 1 – t d . Then, the resulting coefficients of Fig. 1.21(b) are [Ortm06]:
0 0
– 20 – 20
– 40 – 40
– 60 – 60
Magnitude (dB)
Magnitude (dB)
– 80 – 80
– 100 – 100
– 120 – 120
ydt
– 140 – 140 yct
– 160 – 160
– 180 – 5 0 – 180 –5 0
10 10 10 10
Frequency (Hz) Frequency (Hz)
(a) (b)
Figure 1.22: Output spectra of the modulators in Fig. 1.20. (a) DT (b) CT.
a1 a2 Ts
g 1' = ----------------------------------------------------------
Mod2-SCR –Ts 2 DAC
DAC 1 – e
–Ts 2 (1.59)
DAC
a 2 – a 1 T s + 2a 1 DAC + 2T s 1 – e
g 2' = --------------------------------------------------------------------------------------------------------------------------
Mod2-SCR –Ts 2 2
DAC
DAC 1 – e
Theoretically, the above described methodology could be used to synthesize an arbi-

trary Lth-order lowpass†3 CT- M. However, it is well-known that for those Ms with
–1 L
L 2 , and particularly those with a pure differentiator NTF i.e FIR filters with 1 – z
transfer function, are prone to unstability [Adam97]. For that reason, alternative high-order
single-quantizer DT- Ms topologies have been proposed in literature [Nors97][Enge99].
Fig. 1.23 shows the most usual high-order CT- M topologies†4 including the so-called
interpolative M (Fig. 1.23(a)) proposed by Lee and Sodini [Lee87]; cascade of integra-
tors with feedforward summation and local resonator feedbacks (Fig. 1.23(b))[Abus02];
and the cascade of integrators with distributed feedback and distributed input paths
(Fig. 1.23(c)) [Abus02] [Nors97][Schr05].
Most of the high-order topologies, like the ones shown in Fig. 1.23, are based on the use
of several feedback and/or feedforward transmission of the signals in the modulator loop in
order to implement IIR NTFs with multiple zeroes and poles. These zeroes and poles can be
distributed using either a Butterworth or Chebychev filter approximation such that the in-
band noise power is minimized.
An important drawback of the high-order CT- Ms shown in Fig. 1.23 is the increased
complexity of the analog circuitry. Therefore, in order to optimize the stability-resolution
trade-off, most high-order CT- Ms are synthesized directly in the CT domain instead of
applying a DT-to-CT transformation method. In any case, the strategies followed to pre-
clude from instabilities leads to lower values of DR as compared with what can be obtained
according to the ideal values in (1.17) [Rio06].
1.5.3.2 Cascade CT- M architectures
A well-known alternative to circumvent instabilities while obtaining high-order noise

shaping consists of using the so-called MASH (multi-stage noise-shaping) Ms, often
referred to as cascade or multi-stage Ms [Marq98][Rodr03][Nors97]. This architecture is
conceptually depicted in Fig. 1.24. Each stage, consisting of a single-loop CT- M (typi-
cally either second or first order), modulates a signal that contains the quantization error
†3. Bandpass CT- Ms have NTF with zeroes at different frequencies from DC. For that reason, addi-
tional design considerations need to be accounted as will be described in Section 1.5.3.3.
†4. The interested reader can read the equivalence between CT- and DT- high-order topologies in a
number of papers and monographs. Particularly detailed description can be found in [Abus02].
BL
B2
B1
AL
x I s I s I s
y
A2 B-bit
fs
A1
A0
DAC
(a)
1 2
x I s I s I s I s I s
a1 a2 a3 a4 a5
y
B-bit
y fs
DAC
(b)
x
b1 b2 b3 b4 b5
y
I s I s I s I s I s
B-bit
fs
a1 a2 a3 a4 a5
y
DAC
(c)
Figure 1.23: Illustrating high-order single-quantizer CT- Ms. (a) Lee-Sodini (Interpola-
tive) topology. (b) Cascade of integrators with feedforward summation and local resonator
feedbacks (5th-order topology). (c) Cascade of integrators with distributed feedback paths
(5th-order topology).
generated in the previous stage. Once in the digital domain, the stage outputs are processed
and combined by the cancellation logic so that only the quantization error of the last stage
remains. Also, this error is shaped by a transfer function whose order equals the sum of the
respective orders of all the stages in the cascade [Rio06].
The principle underlying cascade Ms can be a priori extensible to whatever number

of stages. However, in practice, it is well-known that the number of stages and conse-
quently the order of the modulator is limited by circuit non-idealities, particularly mis-
match. This error causes incomplete cancellation of low-order quantization errors at the
modulator output [Rio06]. This effect known as noise leakage is especially critical in
cascade CT- Ms because of their higher sensitivity to circuit element tolerances. This
explains the very few reported cascade CT- Ms ICs reported so far [Bree04].
However, the increased demand for wideband ADCs has prompted the interest in cas-
cade CT- Ms in order to implement high-order noise-shaping with low oversampling
ratios whereas guaranteeing stability [Olia03][Ortm06]. Most published proposed synthesis
methods based on applying a DT-to-CT transformation to an equivalent well known
cascade DT- M. However, as will be demonstrated in this thesis, the use of DT-to-CT syn-
thesis methods yields an increase of the analog circuit complexity, with the subsequent pen-
alty in silicon area, power consumption, and sensitivity to parameter variations. Indeed,
more efficient cascade CT- M architectures can be shown if a direct synthesis method is
obtained [Tort06].
As a matter of example, in the following, the DT-to-CT transformation of a cascade 2-1

DT- Ms shown in Fig. 1.25(a) will be described [Ortm06]. To do such a transformation it
is needed to take into account not only the loop filter transfer function of the i-th stage, LF i ,
but also the inter-stage loop filter transfer functions, LF ij , representing the transfer function
from the output of preceding stages to the input of the quantizer of the following stages.
Thus, the corresponding expressions for the DT LFs of the modulators in Fig. 1.25(a) are
the following:
E1(z)
x(s) y (z) Cancellation
CT M1 1 CL1 Logic
E2(z) E2(z)
y (z)
CT M2 2 yo(z) x2(s) +
CL2
.. F(s)
y2(z)
.. .. . y2(s)
DAC
. . Em(z) To next stage
y (z)
CT Mm m CLm
Figure 1.24: Conceptual block diagram of a cascaded CT M.

q1 2
LF 1DT z ----- = – a 1 a 2 I z – a 2 I z
y1
q2
LF 2DT z ----- = – a 3 I z (1.60)
y2
q2
LF 12DT z ----- = g 1 LF 1DT – b 1 c 1 a 3 I z
y1
x
+ a1 I z
+ a2 I z
q1 y1
CL1
B-bit
Digital Cancellation Logic

DAC y
+ g1
c1
b1
+ a3 I z
q2 y2
CL2
B-bit
DAC
(a)
x
+ I s
+ I s
y1
CL1
B-bit
fs
Digital Cancellation Logic
k1 k4 k2
DAC y
k5
k6
+ I s
y2
CL2
B-bit
fs
k3
DAC
(b)
Figure 1.25: Cascade 2-1 M. (a) DT. (b) CT equivalent.

Assuming a NRZ DAC waveform, and taking into account the S-Z equivalences given
in Table 1.1, the corresponding CT LFs are obtained, giving:
2
a1 a2 fs 1 a2 2 – a1 fs
LF 1CT s = – ---------------- – --- -----------------------------
s
2 2 s
a3 fs
LF 2CT s = – --------- (1.61)
s
3 2
c 1 a 3 f s c 1 a 3 1 a 1 – 1 f s c 1 a 3 b 1 + 1 3 – 1 2a 1 f s
LF 12CT s = – ---------------- – ------------------------------------------- – ---------------------------------------------------------------------
s
3
s
2 s
To get a functional CT- M topology that satisfies (1.61) while keeping identical dig-
ital Cancellation Logic (CL) as its corresponding DT counterpart (Fig. 1.25(a)), every state
variable (integrator output) and DAC output must be connected to the integrator input of the
ulterior stages in the cascade [Ortm01]. This increases the number of analog components
needed, leading to the CT- M topology shown in Fig. 1.25(b), which at least ideally,
behaves equivalently to its DT counterpart [Ortm06].
1.5.3.3 Bandpass CT- M architectures
BandPass Ms (BP- Ms) are a particular class of Ms that place the zeroes of
NTF in a given bandwidth around an Intermediate Frequency (IF) location, usually named
notch frequency, f n . Therefore, BP- Ms differ from their LP counterparts in that the loop
filter is of bandpass type instead of lowpass type as illustrated in Fig. 1.26
[Schr89][Gail89]. This has an obvious application in the front-end of wireless communica-
tion systems. Indeed, BP- Ms are very suited for the implementation of ADCs in such
systems because, compared with lowpass ADCs, BP- Ms do not need to digitize the
whole Nyquist band (from DC to f s ) (see Fig. 1.26). Instead, they digitize just the signal
band, thereby requiring much less power consumption to obtain similar dynamic range
[Enge99][Rosa02]. In addition, IF A/D conversions allows to move great part of the signal
0
B
w
-20
-40
Relative Magnitude (dB)
x y -60
fn -80
th
2L -BPF 6th Order BP
-100
4th Order BP
DAC -120
2nd Order BP
-140
0 0.1 0.2 fn 0.3 0.4 0.5
Relative Frequency
Figure 1.26: Conceptual block diagram of a BP- M and its output spectrum.
processing from the analog domain to the digital domain, including: quadrature mixing,
channel selection, gain control and demodulation. This results in robust Radio Frequency
(RF) receivers with high degree of programmability and adaptability to a number of stand-
ard specifications.
BP- Ms share much in common with their LP counterparts, except for the obvious
difference that the quantization noise is suppressed around f n instead of DC. A common
choice is using f n = f s 4 , i.e just in the middle of the Nyquist band. It can be shown that
this location optimizes the trade-off between antialiasing filtering and image-reject filtering
in digital wireless transceivers [Rosa02][Rodr03].
The design and analysis of BP- Ms is the same as that of LP- Ms, but considering
bandpass loop filters instead of lowpass loop filters. Indeed, it can be shown that the main
figures of merits, i.e in-band noise power, DR, SNR, SNDR have the same expressions as
the ones obtained in Section 1.3.2 [Rodr03]. In practice, it means that a BP- M can be
synthesized by replacing integrators by resonators in the modulator loop filter. These reso-
nators may be implemented either as DT circuit techniques or CT techniques, the latter giv-
ing rise to the so-called CT BP- Ms Section [Nors97][Cher00][Rosa02][Shoa95].
Since Schreier and Snelgrove proposed the idea of BP modulation in 1989 [Schr89],
a number of CT BP- M ICs have been published [Enge99] [Tort06][Hsu00][Schr06].
Similarly to lowpass modulators, CT BP- Ms can be synthesized either using a direct syn-
thesis method or any of the DT-to-CT synthesis methods described in previous sections. In
the case of a DT-to-CT transformation is used, DT resonators are transformed into CT reso-
nators using S-Z equivalences shown in Table 1.1. As a matter of example, Fig. 1.27(a)
shows the block diagram of a 4th-order CT BP- M. This modulator is equivalent to the
DT modulator shown in Fig. 1.27(b) and their in-loop resonators have a resonant fre-
quency†5 at f n = f s 4 . This translates in an output spectrum with a noise shaping like the
one shown in Fig. 1.27(c). Note that the architecture in Fig. 1.27(a) uses multiple feedback
loops including two different DAC waveforms RZ and NRZ each one with separately
feedback coefficients. This is needed to obtain similar noise-shaping than that of the DT
BP- M in Fig. 1.27(b) because it allows to use resonator transfer functions of the type
2 2
s s + , which are easier to realize through Gm-C circuits than the CT filters resulting
from the impulsive-variable transformation method [Shoa95][Cher00].
1.6 Circuits and Errors
In previous sections, CT- Ms have been analysed from an ideal point of view. In prac-
tice, such an ideal performance is degraded as a consequence of the error mechanisms asso-
ciated to their circuit implementation. These errors can be divided into two main categories
[Cher00][Ortm06]:
†5. One advantage of CT resonators is that they can implement continuously-tunable resonant frequen-
cies, which allows the corresponding BP- Ms to have a programmable frequency band [Shoa90].
x 2 s - 2 s - y
----------------------------- -----------------------------
2 2 2 2 S/H
s + 2 s + 2
g g
1h 2h
HRZ DAC
g g
4r 2r
RZ DAC
(a)
–2 –2
x –z –z
---------------------
y
--------------------- –2
–2
1+z 1+z
g g
1 2
DAC
(b)
-50
-100
0.1 0.15 0.2 0.25 0.3 0.35 0.4
(c)
Figure 1.27: 4th-order Bandpass CT- M. (a) Block diagram. (b) Equivalent DT Block
diagram. (c) Output spectrum.
• Building-block errors, which are the non-ideal effects derived from the CT- M
loop filter implementation such as finite opamp DC gain (in the case of RC-active
integrators), integrator time-constant error, integration incomplete transient
response, circuit element tolerances, non-linearities (specially at the input front-
end Gm-C integrators), circuit noise, etc.
• Architectural timing errors, namely: quantizer metastability, excess loop delay and
clock jitter error.
As a consequence of these non-idealities, the effective resolution of any CT- M archi-

tecture is reduced as compared to the ideal values presented in previous sections. In some
conditions, and particularly in the case of timing errors, the performance of CT- Ms may
become totally degraded.
The rest of the Annex analyses the impact of main non-idealities and non-linearities
affecting the performance of CT- Ms. To this purpose, their main building blocks will be
described first.
1.7 CT Integrators
CT integrators are the most important and critical building blocks of CT- Ms
[Ortm06]. These circuits constitute the basic elements of the modulator loop filter of low-
pass CT- Ms. Moreover, they can be combined to build resonators in order to implement
bandpass CT- Ms.
There are four practical CT integrator structures conceptually depicted in

Fig. 1.28[Tsiv94]: active-RC integrators (Fig. 1.28(a)); Gm-C (Fig. 1.28(b)); MOSFET-C
(Fig. 1.28(c)) and active Gm-C or Gm-MC (Fig. 1.28(c)). From an ideal point of view, all
these implementation have the same transfer function, given by:
y---------
s- 1
I s = ----- (1.62)
x s s
where is the integrator time constant, which is the product of the resistive and capacitive
elements of the CT integrator as shown in Fig. 1.28.
In practice, the behaviour of the CT integrator implementations in Fig. 1.28 is different,

involving a number of trade-offs. Thus, active-RC integrators have the advantages of better
linearity and larger signal swing, whereas Gm-C integrators usually can operate at higher
VC
–x C –x C
(a) (c)
= RC R ch = R ch C
R y y
C
x gm y x gm
C C
(b) = ------ (d) = ------
C gm y gm
VC VC
Figure 1.28: Alternative circuit techniques for the implementation of CT Integrators: (a)
Active RC. (b) Gm-C. (c) MOSFET-C. (d) Gm-MC.
frequencies with less power consumption. MOSFET-C integrators, which allow a continu-
ous time-constant tunability, present a poor linearity and indeed, have been much less used
in practical CT- M implementations [Ortm06]. Among others, most frequently used
implementations of CT- Ms include either active-RC integrators or Gm-C integrators or a
combination of both types of integrators. The following subsections sum up the most impor-
tant characteristics of these CT integrator topologies.
1.7.1 Gm-C Integrators
As illustrated in Fig. 1.28(b), Gm-C integrators are based on the connection of a

transconductance element and a capacitor. The input voltage, x , is multiplied by the
transconductance, g m , giving rise to a current which drives the load capacitance, C . The
resulting ideal transfer function is given by:
gm
I s = ------ (1.63)
sC
Gm-C integrators can be easily tuned and are specially suitable for low-voltage applica-
tions. Their main limitation is caused by the non-linearity in the voltage-to-current conver-
sion of the transconductor element, which forces in some applications to replace the front-
end integrator with an active-RC (which can be much more linear) while the remaining inte-
grators in the loop filter are implemented using Gm-C. Alternative strategies to improve lin-
earity in Gm-C integrators are based on the combination of fully differential topologies with
source degeneration. The prize to pay is an increase of the power consumption [Tsiv94].
Another important limitation of Gm-C integrators is their high sensitivity to parasitic

capacitances, C p as illustrated in Fig. 1.29. This capacitance alters directly the integrator
time constant, modifying (1.63) as:
gm gm
I s = ------ I s = ------------------------ (1.64)
sC s C + Cp
The effect of C p can be reduced by including a virtual ground, which is implemented

by an operational amplifier as shown in Fig. 1.28(d). The resulting integrator, called active
Gm-C or Gm-MC integrator, is more robust against parasitic capacitances connected at the
amplifier input because only small voltage fluctuations are produced thanks to the action of
the virtual ground. Moreover, smaller values of C can be implemented because the effec-
x gm y
C Cp
VC
Figure 1.29: Gm-C integrator with parasitic capacitance, Cp.
tive capacitance is amplified by the Miller effect of the opamp. However, the opamp is an
active element and therefore, increases the power consumption as compared to simple Gm-
C integrators.
Gm-C integrators can be used to build resonators†6 as illustrated in Fig. 1.30. Resona-
tors are basic building blocks which can be used to implement bandpass CT- Ms and low-
pass CT- Ms with NTF zeroes at different frequencies than DC. In the case of the
resonator in Fig. 1.30, the resonant frequency, f n , is given by:
1 g m2 g mR
f n = ------ -------------------
- (1.65)
2 C1 C2
which can be electronically tuned by g mR [Rabi99].
1.7.2 Active-RC integrators
Another alternative of CT integrator implementation that has been used in plenty of CT-
M ICs is the well-known active-RC integrator, conceptually shown in Fig.1.28(a), whose
ideal transfer function is given by:
1
I s = ---------- (1.66)
sRC
This integrator is more robust than Gm-C topologies against capacitor parasitics in part
due to the virtual ground. Besides, it achieves high linearity provided that the input resistor,
R , responsible for the V/I conversion is linear enough. Another source of distorsion
comes from the non-linear amplifier transfer function, which can be reduced by increasing
the value of R at the prize of increasing thermal noise [Ortm06]. This trade-off can be obvi-
vi g m1
g m2
C1
C2 vo
g mR
Figure 1.30: Conceptual schematic of a Gm-C based resonator.

†6. Gm-C based resonators can be also implemented by a transconductor driving a LC tank, instead of a
simple capacitor. Both monolithic and off-chip inductors have been used for their implementation
involving different design trade-offs among silicon area, resonant frequency accuracy, quality factor,
etc. [Geer02][Schr06].
ously solved by increasing the bias current in order to reduce the power dissipation.
The main concern of active-RC integrators is their lower speed as compared to open-
loop Gm-C integrators. Nevertheless, and depending on the application, active-RC can be a
good choice to solve the trade-off among linearity, speed, power consumption and thermal
noise. Indeed, one might think of the very demanding restrictions imposed to the opamp
Gain-BandWidth (GBW), this specification is notably relaxed as compared to the Discrete-
Time (DT) case, for instance in a Switched-Capacitor (SC) integrator. Indeed, it can be
shown that the ideal integrator unity-gain frequency,
1
f u = --------------- (1.67)
2 RC
can be chosen to be approximately equal to the sampling frequency, f s , which leads to a

much more relaxed design (in terms of power dissipation) as compared to the DT case,
where the typical requirement is f u 5f s .
In order to take advantage of the benefits of both active-RC and Gm-C integrators, the
most common situation in practice (particularly in CT- Ms targeting medium-high resolu-
tion within medium bandwidths) consists of including a front-end active-RC integrator
while the remaining integrators are implemented by using Gm-C techniques.
1.8 Building-block errors
As pointed out in Section 1.6, CT- M errors can be classified into two main catego-
ries: building-block errors and timing errors. This section is focused on the former ones,
that are responsible for the increase of in-band noise power and/or harmonic distortion in
the modulator. In order to analyse the impact of a non-ideal (linear) building-block errors,
the following procedure is commonly followed [Mede99][Ortm06]:
• Obtain an integrator†7 equivalent circuit considering the non-ideal effect under

study.
• Analyse the impact of the non-ideality on the integrator transfer function, I s ,

such that I s I s , with being the error vector including all non-ideal var-
iables included in the integrator equivalent circuit.
• In order to compute the effect of on a Lth-order CT- M, integrator transfer

functions are replaced with I s , and a linear model of the quantizer is consider
to get the non-ideal NTF, NTF s L .
†7. Similar study is followed for resonators in the case of BP- Ms [Rosa02].
• NTF s L is integrated within the signal band in order to obtain the In-Band-
Noise (IBN) power, also represented as P Q , given by:
2
IBN PQ ---------- NTF f L df (1.68)
12f s
Signal band
which, after some approximations can be explicitly shown as a function of and

the modulator parameters, i.e B L M . Note that, once P Q is known, the corre-
sponding non-ideal DR and SNR can be obtained.
The above procedure can be mathematically formulated as:
IBN M B L
I s I s NTF s L SNR M B L (1.69)
...
The detailed description of the above formulation for each CT- M building-block
non-ideality is beyond the scope of this annex, and can be found in a number of manu-
scripts†8. Instead, a summary of the most significant effects is described below, starting
with the well-known effect of integrator leakage.
1.8.1 Integrator leakage
The ideal model for the active-RC integrator shown in Fig. 1.28(a) assumed an infinite
value for opamp DC gain, i.e A DC . However in practice, a finite value A DC must be
considered and the integrator transfer function of Fig. 1.28(a) is modified as:
1
I s A = -------------------------------------------------- (1.70)
DC
Active-RC A DC + s 1 + A DC
where = RC and A 1 A DC stands for the error due to finite DC gain, which obvi-
DC
ously becomes zero when A DC . Note that, as a consequence of this error, the integra-
tor presents losses or leakage when s 0 . For that reason, this error is commonly referred
to as leakage error [Mede99].
In the case of Gm-C integrators, leakage error is caused by finite output resistance as
illustrated in Fig. 1.31, whose transfer function is given by:
†8. The interested reader can find a in-depth description of the effect of building-block errors (mainly
considering active-RC implementations) on the performance of CT- Ms in [Ortm06]
1
I s A = ----------------------- (1.71)
DC
Gm-C A DC + s
where = C g m and A = g out g m , with g out being the finite output conductance.
DC
Note that both expressions (1.70) and (1.71) are quite similar. Indeed, multiplying both the
numerator and denominator of (1.70) by 1 – A , and assuming that A « 1 , we
DC DC
obtain the following transfer function:
1– A 1– A
DC DC
I s A = ---------------------------------------------------------------------------
- ----------------------
- (1.72)
DC
Active-RC 2 A + s
A 1– A + s 1– A DC
DC DC DC
that is the same as (1.71) except for a gain error, given by 1 – A . Therefore, the impact
on a single-loop lowpass CT- M†9 is approximately the same considering both integrator
DC
circuit implementations.
Following the analytical procedure described earlier, it can be shown that the IBN
degraded by A in a single-loop L-th order CT- M with NRZ feedback DAC is
DC
approximately given by [Gerf03]:
2L L 2i 2 L – i
2 A DC A DC L L–1 L–i+1
PQ A ----------------- ----------- + -------------------------------------------------------------------------------- (1.73)
12k 1 g q M
DC 2 2 2i + 1
2i + 1 M i!
i=1
where g q is the quantizer gain and k 1 is the feedback scaling coefficient of the front-end
integrator. Note that, the above expression approximates the ideal in-band noise power if
A DC 1 M exactly the same as happens in DT CT- Ms. This result is illustrated in
Fig. 1.32, that shows the impact of finite DC gain on the SNR in a 2nd-order CT- M for
different values of M .
It can be noted from (1.73) and Fig. 1.32 that the values required for A DC are not very
x gm y
g out C
Figure 1.31: Conceptual Gm-C integrator with finite output resistance.
†9. In the case of bandpass CT- Ms, the modulator loop filter is based on resonators instead of integra-
tors. Therefore, integrator gain errors affect the resonator transfer function, and hence, the corre-
sponding NTF of the resulting bandpass CT- M. In this case, the differences between (1.70) and
(1.71) may result in different NTFs and, therefore, different impact of the finite DC gain error on the
IBN of the bandpass CT- M [Cher00][Rosa02].
demanding in practice. However as also happens in the case of DT- Ms this is not the
case of cascade CT- Ms. In this case, if the integrator leakage is considered, the NTFs of
the different stages in the cascade are modified and their quantization errors are incom-
pletely cancelled in the digital domain, so that the non-ideal parts of the quantization noise
leak into the overall modulator output [Rio06], causing an increase in the in-band noise
power which can be expressed as [Ortm06]:
L–1
PQ A PQ + PQ A – PQ (1.74)
DC ideal DC ith-stage_ideal
cascade ith-stage
i=1
which corresponds to the ideal IBN of the cascade modulator plus the non-ideal parts due to
integrator leakage of the IBN in all previous stage in the cascade.
In the same way as happens with DT- Ms, sensitivity of cascade CT- Ms to leakage
error is higher than in the case of single-loop architectures. For instance, in a cascade 2-1-1
3
the required DC gain for the front-end stage integrators is A DC M in contrast to
A DC M required for a single-loop 2nd-order CT- M. The requirements for the subse-
2
quent stages in the cascade are more relaxed than the front-end stage, being A DC M and
A DC M , for the second- and third stages, respectively.
1.8.2 Integrator gain error
Integrator gain error is caused by technology process variations of the integrator time
constant†10, , which yield to a modification of the ideal integrator transfer function given
by:
1 1
I s = ----- I s = ------------------------ 1 – I s (1.75)
s s 1+
85
80
75
SNR (dB)
70
65
60
55
50
0 20 40 60 80 100 120 140 160 180 200
Finite DC gain
Figure 1.32: Effect of finite DC gain on the SNR of a 2nd-order CT- M.
†10.For this reason, this error is sometimes named time-constant error [Cher00].
where = , stands for the time-constant tolerance error.
In the case of DT implementations, the integrator gains are mapped into capacitor
ratios, with variations typically lower than 0.1% in modern technology processes [Rio06].
However, in CT circuit realizations, time constants are mapped into resistor-capacitor prod-
ucts or transconductance-capacitor products, respectively for active-RC and Gm-C imple-
mentations. These products can present variations in the order of = 20-30% , which
represents a critical limiting factor, particularly in the case of cascade topologies [Ortm06].
Following the procedure described at the beginning of this section, the IBN degradation
caused by integrator gain errors can be calculated, yielding the following expression for a
L-th order single-loop CT- M:
L L
2L 2
1 1 1 (1.76)
PQ --------------------------- -----------------------------
- ---------------------- = PQ ----------------------
SL 12 2L + 1 k 2 g 2 M 2L + 1 2 ideal 2
1 q i=1
1– i = 1
1–
i i
where is the time constant error of the i-th integrator. Note that, although decreases
the modulator performance, the modulator still shows the same order shaping as the ideal
one, and hence, realistic values of can be tolerated. However, this is not the case of cas-
cade CT- Ms, where the impact of is very critical, severely degrading the performance
of the modulator.
Although there have been some attempts to analyse the impact of on the perform-
ance of cascade CT- Ms, calculations become enormously sophisticated. For instance,
Ortmanns et al. [Ortm06] show that the IBN degraded by time constant errors in a Lth-order
cascade CT- M is approximately given by:
2L i 2
1 - ----------------------------
i 1
PQ --------------- ---------------------------------- +
Cascade K–1 12 2L i + 1 2 2 2L i + 1
k1 gq M
di i i
i=1
(1.77)
K–1 2L i 2 L
2
1 - ---------------------------- ---------------------------------
i 1 1-
+ --------------- - ----- – 1
K–1 12 2L i + 1 2 2 2L i + 1
i=1 k1 gq M i=1 i
di i i
i=1
where K is the number of stages in the cascade, d i is the inter-stage gain coefficient and L i
and i are the order and the time constant error of the i-th stage, respectively.
Instead of using such complicated and not always so precise and usable expres-
sions, many authors evaluate this effect by means of MonteCarlo simulations using behav-
ioural models [Tort06].
The impact of is much more critical in cascade CT- Ms, which are severely more
sensitive to variations in the practical values of circuit element tolerances than their single-
loop counterparts. This fact explains why there are very few reported cascade CT- M ICs
[Bree04][Bree07]. Indeed, cascade CT- Ms cannot be implemented without some kind of
compensation techniques, such as on-chip tuning [Shoa97][Xia04][Xia04] and/or digital
calibration [Bree04][Ortm05]. The use of these strategies may mitigate the effect of element
tolerances, albeit mismatches still remains. These techniques can be combined with proper
synthesis methods in order to obtain more robust cascade CT- M topologies as demon-
strated in this thesis.
1.8.3 Integrator transient response Finite GBW and Slew-Rate
As CT- M loop filters are operating in the CT domain, their transient response is not
so extrictly limited to be settled within a finite time slot usually half of the clock signal
period as it is for the DT- Ms. Thus, non-dominant integrator poles and their cause,
finite Gain-BandWidth (GBW) product, is more than an issue in DT circuitry than it is in
CT ones [Cher00]. Indeed, from a general point of view, it can be said that non-dominant
integrator poles degrade the loop stability of the entire modulator by pushing the modulator
poles closer to the imaginary axis. Therefore, this non-ideal effect must be taken into
account in order to optimize the design in terms of power dissipation and speed, even in the
case of CT- Ms, in spite of their less sensitivity to this error. This is particularly critical in
high-speed applications, where 2nd-order (two-pole) models should be considered in the
design process. In this case, the analysis becomes mathematically too complex, thus requir-
ing the use of time-domain simulations using precise behavioural models like that presented
in [Ruiz05].
A number of approaches have been reported to analyse the impact of GBW in the per-
formance of CT- Ms [Ortm06]. Among others, the work proposed by Ortmanns, Gerfers
et al. [Ortm04] gives more accurate results using a comprehensive model for active-RC
based CT- Ms. This work is summarized in next subsection. The interested reader can
find more detailed description in [Ortm04].
1.8.3.1 Effect of finite GBW
Let us assume that the operational amplifier in Fig. 1.28(a) has a single-pole transfer
function given by:
A DC
A s = --------------------------- (1.78)
s
----------------- +1
opamp
where opamp is the dominant pole of the amplifier and GBW A DC opamp is the gain-
bandwidth product. Considering the above opamp transfer function, it can be shown that the
transfer function of an active-RC integrator with n A input paths is given by [Ortm04]:
1- ---------------
GBW
I s GBW ---- - (1.79)
s ------
s
+1
p
where
nA
GBW
GBW
--------------------------------------
-, p = GBW + f s kl (1.80)
nA
l=1
GBW + f s kl
l=1
and k l is the scale coefficient of lth-path .
Note that, neglecting the effect of the opamp pole, p , the impact of GBW is approxi-
mately the same as that of the integrator gain error, , and therefore, its effect on the mod-
ulator IBN is given by (1.76)-(1.77), by properly replacing with GBW .
If the effect of p is not neglected, the calculus of IBN due to GBW becomes
extremely complex. Instead of doing such a complicate mathematical analysis, the authors
in [Ortm04] propose a behavioural model in which GBW can be divided into two errors:
finite integrator gain error and an excess loop delay in the modulator. This model is illus-
trated in Fig. 1.33 for a single-loop 2nd-order modulator. The feedback delays, Di , are
given by:
– p2 f s 2 2 – p1 f s
– p2 f s 1–e
1----------------------------
–e p1 – p2 1 – e
D1st = - ; D2nd = ---------------------------------------------------------------------------------------------- (1.81)
p2 p1 p2 p1 – p2
where pi are the poles resulting from (1.80) for the different integrators [Ortm04].
One of the benefits of this model is that it allows to compensate for finite GBW error using
similar techniques as for the excess loop delay error which will be discussed in next sec-
tions.
1.8.3.2 Slew Rate, SR
Another effect of the finite integrator transient response is the finite Slew Rate (SR),
Rs C Rv C
x
A1 s A2 s y
fs
R1 R2
kS + fs kv + fs
x GBW1
--- --------------------------
- GBW2
--- --------------------------
- y
s s 1+1 s s 2+1 fs
k1 k2
DAC
x kS + fs kv + fs
-----------------------------------------------------
- --- GBW1 --- GBW2 y
s 1+1 s 2+1 s s fs
k1 k2
-----------------------------------------------------
- --------------------------
-
s 1+1 s 2+1 s 2+1
DAC
kS + fs kv + fs
x --- GBW1 --- GBW2 y
s s fs
D2nd D1st
DAC
Figure 1.33: Modeling finite GBW as extra loop delays [Ortm04].

defined as the maximum integrator output rate due to the limited current used to charge the
integrating capacitor. In the case of CT integrators, the maximum SR can be mathematically
expressed as:
dv o
SR max = = f s V in (1.82)
d t max max
where v o is the output voltage and V in is the maximum input signal amplitude of the
max
integrator. Considering an isolated integrator, V in is mainly limited by the bias current,
max1.34. In this case the input-output DC
I B , of the differential input pair, as illustrated in Fig.
characteristic of the transconductor can be formulated as:
–IB va – IB
i va = v a 2I B – va – IB va – IB (1.83)
IB va IB
where is the large-signal transconductance of the transistor and V in = IB .

max
Similarly to GBW, the effect of SR in CT- Ms is less critical than in the case of DT-
Ms even if single-bit quantization is used†11. However, due to the strong dependence
of SR on the exact waveforms of the different signals involved in the dynamics of a CT-
M, the analysis of the impact of SR becomes mathematically too complex and designers
usually relay on simulations to get the required SR specifications in a given design
[Ortm06]. As an illustration, Fig. 1.35 shows the impact of SR on a Gm-C 2nd-order single-
bit CT- M. Note that, in addition to increase in-band noise, harmonic distortion appears in
the output spectrum of the modulator due to the strong non-linearity introduced by limited
SR.
i i+ – i-
i+ i-
IB
gm
va
– IB IB va
–IB IB
(a) (b)
Figure 1.34: (a) Input-output DC characteristic of a (b) Differential transconductor.
†11.Multi-bit quantization reduces integrator input/output swings, thus attenuating the effect of SR.
1.8.4 Non-linear errors

CT- Ms suffer from harmonic distortion caused by non-linear circuit errors. These
errors are a direct consequence of the non-linear characteristics of CMOS integrated
devices, namely: transistors, resistors and capacitors. In the same way as happens with other
circuit non-ideal effects, the most critical building blocks are those placed at the modulator
front-end basically the first integrator because the errors caused by the remaining blocks
in the modulator loop are attenuated by the gain of previous ones. Thus, considering only
the influence of the front-end integrator, there are several sources of non-linearity which
must be taken into account by designers. As illustrated in Fig. 1.36, main non-linear errors
in CT active-RC integrators are caused by voltage-dependency of the amplifier DC gain,
integrator resistances and capacitors, which can be mathematically expressed as [Ortm06]:
2
C = f C v out C nom 1 + C V1 v out + C V2 v out
2
R = f r v in R nom 1 + R V1 v in + C V2 v in (1.84)
2
A DC = f A v out A DCnom 1 + A V1 v out + A V2 v out
0
-20
-40
-60
Magnitude (dB)
-80
-100
-120 SR = 45V s
-140
f s = 20MHz
-160
f i = 1kHz
-180 Ideal
-2002
10 103 104 105 106 107
Frequency (Hz)
Figure 1.35: Illustrating the effect of SR on a Gm-C 2nd-order CT M.
C = f C v out
g m = f g v in
m
R = f r v in
v in v in
v out
v out
C = f C v out
A DC = f A v out
(a) (b)
Figure 1.36: Non-linear error sources in: (a) Active-RC integrator (b) Gm-C integrators.
In the case of Gm-C integrators, the main source of non-linearity is associated to the V/I
conversion process carried out by the non-linear transconductance, given by [Bree01]:
k 3
i v in = v in 2I B – v in g m v in g m v in + g m v in (1.85)
k 1 3
k=1
Among others, non-linear V/I conversion (implemented by either the input resistor in
active-RC integrators or the input transconductance in Gm-C implementations) is the most
limiting factor degrading the linearity of CT- Ms because its associated harmonic distor-
tion adds directly to the input signal and is subsequently digitized [Bree01][Ortm06].
Assuming a fully-differential circuit implementation of Fig. 1.36(b) and that M » 1 , it

can be shown that the third-order harmonic distortion at the output of CT- Ms due to non-
linear V/I conversion is given by [Bree01]:
gm
2
THD HD 3 --------3- V i (1.86)
gm
1
where V i is the modulator input amplitude.
The above expression can be used to approximately predict the harmonic distortion due
to the non-linear V/I operation, which in the end, constitute the ultimate limiting factor of
the linearity of a Gm-C CT- M based ADC. Thus, in order to quantify the effect of non-
linear errors in CT- Ms, most authors make use of simulations either using behavioural
or transistor-level models [Leuc01]. Recently, Sankar et al. proposed an analytical model
for the non-linearity of CT integrators which can be used to both purposes: simulation and
mathematical analysis [Sank07]. Fig. 1.37 illustrates this model for a Gm-C (Fig. 1.37(a))
and an active-RC (Fig. 1.37(b)) integrator. Basically, the model consists of replacing the
ideal transfer function of a CT integrator by the following one:
I s NL = f x I s ideal (1.87)
where
3
x – g3 4g m x
f x = (1.88)
3 3
x – 2g 3 g m 2 + g m R x
Using this model, the authors in [Sank07] demonstrate that non-linear CT integrators
cause not only harmonic distortion but also an increase of the in-band noise power.
v in + – o
f x --------- v out
s
v DAC
3
i out = g m v d – g 3 v d C
1 gm
iout
v in
R vd v out
R
v in iout
C
R vd
R v out
v DAC
v DAC
(a) (b)
Figure 1.37: Behavioral model of non-linearity in CT integrators [Sank07].

(a) Gm-C integrator. (b) Active-RC integrator.
1.8.5 Circuit noise
Circuit noise constitutes the ultimate limiting factor of any M [Mede99]. It is well
known that this noise is originated by two physical mechanisms in CMOS circuits: thermal
and flicker noise [Gray93]. Thus, practical designs must take into account the contribution
of these noise sources generated by all M building blocks. Among others, those blocks
connected to the input node of the modulator basically the front-end integrator and the
corresponding feedback DAC are the most important contributors because their noise is
added directly to the input signal, thus appearing with no filtering at the output spectrum of
the modulator, and increasing the in-band noise [Rosa02].
In the case of CT- Ms, all high-frequency noise components are filtered before they
are sampled, because sampling process takes place at the input of the quantizer. Therefore,
the remaining aliased noise components are attenuated by the corresponding noise shaping
[Ortm06]. This is an advantage of CT- Ms as compared to their DT counterparts, where
circuit noise is sampled at the input, causing aliased noise sources to increase the in-band
noise power. This phenomenon gives rises to the well-known KT C noise in SC Ms
[Mede99].
Taking into account the above considerations, the analysis of electrical noise in CT-
Ms is very simple and consists of obtaining the input-referred (unsampled) equivalent
noise source. This calculus depends on the particular circuit-level implementation of the
CT- M and, in the more general case, yield to the analysis of the input-referred noise in a
CT integrator. This analysis beyond the scope of this thesis can be found in many man-
uscripts and books dealing with the design of analog CMOS circuits [Gray93]. As an illus-
tration, Fig. 1.38 shows the main noise sources in an active-RC CT- M together with the
equivalent circuit needed to calculate the input referred noise. In this case, the in-band noise
power is given by [Ortm06]:
4n e th 8K f n e f B w
P Noise 32KTB w R + -------------------- + ------------------- ln ------- (1.89)
3g mOTA 2
C ox WL fu
where n e th and n e f stand for the thermal and flicker noise excess factors, g mOTA is the
amplifier input transconductance, K f is a flicker noise technology parameter.
1.9 Excess loop delay
Ideally, the feedback DAC output in a

CT- M should respond immediately to the out comp
quantizer clock edge. However, in practice,
there is a delay due to the finite transient
response of the DAC circuitry. This delay out DAC
illustrated in Fig. 1.39 is often referred to d
as excess loop delay, and mathematically t
expressed as a fraction of the sampling
period, d = d T s , where 0 d 1.
Figure 1.39: Step response of the DAC.
The excess loop delay error introduces additional poles that increase the order of both
the signal and noise transfer functions S TF and N TF which may lead to an unstable
behaviour of the resulting CT- M. The analysis of this effect is mathematically complex,
and indeed there has been different approaches reported to find a close-form expression of
the stability conditions [Cher99a][Roma00][Ortm06]. Some studies are based on analysing
the equivalent DT- system and then make a DT-to-CT transformation [Cher99a][Ortm06].
Here, a direct CT methodology is followed as proposed in [Roma00] considering two
cases studies: 1st- order and 2nd- order single-loop CT- Ms.
2
vn R
Z RZ C
2
vn R
R
v in
2 Ideal OTA v out
v n OTA
2
v n DAC
R DAC
– v REF
Figure 1.38: Main noise sources in active-RC integrators [Ortm06].
1.9.1 Error analysis
Thus, in the case of a 1st-order CT- M with excess loop delay, it can be shown that
the S-transform of the output is approximately given by [Roma00]:
g g T G s H s
q 1 s H 1
Y s = -------------------------------------------------------------------------------------------------- X s + -------------------------------------------------------------------------------------------------- E s (1.90)
– ds – ds
1 + g g' T G s H s e 1 + g g' T G s H s e
1 1 s H 1 1 s H
– sT s
1–e
where H s = I s = 1 s and G H s = --------------------- is the S-transform of the S/H cir-
s
cuit.
– sT s
Considering M » 1 , then e 1 – sT s and (1.90) can be simplified into:
gq g1 s
Y s ---------------------------------------------------------
- X s + ---------------------------------------------------------
-E s (1.91)
g q g' 1 + 1 – d g q g' 1 s g q g' 1 + 1 – d g q g' 1 s
In this case, the stability of the modulator can be guaranteed if we assume that a quan-
tizer gain of g q = 1 d g' 1 , thus nuling the zeroes of S TF and N TF .
This is not the case of a 2nd-order CT- M, where the excess loop delay modifies the
S-transform of the modulator output as follows:
g g g 2
q 1 2
------------------------------------------------------------------------------------------------------------- s - E f(1.92)
- X f + ----------------------------------------------------------------------------------------------------------------
Y f
2 – ds – ds 2 – ds – ds
s + g g 'g e + g g' s e s + g g 'g e + g g' s e
q 1 2 q 2 q 1 2 q 2
Assuming M » 1 and applying the Ruth-Hurwitz’s stability criterion, it can be shown

that a 2nd-order CT- M is stable in the presence of excess loop delay if and only if the fol-
lowing condition is satisfied:
g' 2
d
------------ (1.93)
g' 1 g 2
The above condition has been obtained considering a linearized, additive noise model
for the quantizer. Considering a non-linear model, a simulation-based analysis demonstrates
that the stability condition in (1.93) is modifies as:
g' 2
d
---------------
- (1.94)
2g' 1 g 2
Int. Output (V) 0.5

(a) 0
-0.5
= 0
d
-1
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
2
Int. Output (V)
1
(b)
0
-1
= 1
d
-2
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
5
Int. Output (V)
(c)
0
-5 = 1.5
d
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
Time(s)
Figure 1.40: Unstable behavior due to excess loop delay in a 2nd-order LP CT- M.
(a) d = 0 . (b) d = 1 . (b) d = 1.5 .
The above result has been verified by simulation results. This is illustrated in Fig. 1.40,
that shows the time response of the front-end integrator in a 2nd-order CT- M for a 1-kHz
input tone with half-scale amplitude. It is shown how, as d is increases, the amplitude of
the integrator output increases, becoming unstable for d = 1.5 , which is in close agree-
ment with the theoretical stability condition d 1 in this example.
Excess loop delays causes similar degradation in different modulator architectures, i.e.
single-loop, cascade, lowpass, bandpass, etc. As an illustration, Fig. 1.41 shows the impact
of excess loop delay in multi-feedback CT-BP Ms†12. As a consequence of the poles
introduced by d 0 , the noise-shaping transfer functions, S TF and N TF , are modified,
thus increasing the in-band noise power as illustrated in Fig. 1.41(c). This effect becomes
specially critical in telecom applications, in which large values of d d 0,4 in the
example of Fig. 1.41(b)-(c) may eventually make CT-BP Ms unstable.
Mathematically speaking, complex analyses are required to obtain the stability condi-
†12.This architecture uses different types of DACs each with separately feedback coefficients to
obtain similar noise-shaping than that of its corresponding DT-BP M. This strategy allows us to use
2 2
resonator transfer function of the type s s + , which are easier to realize through g m C circuits
than the CT filters resulting from a DT-to-CT transformation.
x 2 s 2 s y
------------------------------ ------------------------------
2 2 2 2 S/H
s + 2 s + 2
Resonator Resonator Comparator out
g g comparator
1h 2h
HRZ DAC
out
g g DAC
4r 2r d
RZ DAC t
(a)
0
2
1
0 -50
-1
-2 d
= 0,1
-100 d = 0,1
1st-Resonator Output Amplitude (V)
500 550 600 650 700 750 800 850 900 950 1000 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Relative Magnitude (dB)

0
2
1
0 -50
-1
-2 d = 0,2 -100 d = 0,2
500 550 600 650 700 750 800 850 900 950 1000 0.1 0.15 0.2 0.25 0.3 0.35 0.4
10 0
5
0 -50
-5
d
= 0,4
-100 d = 0,4
-10
500 550 600 650 700 750 800 850 900 950 1000 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (#Ts) Frequency / Sampling Frequency
(b) (c)
Figure 1.41: Excess loop delay. a) DAC time response in CT-BP Ms. Effect on: b)
Transient response of first resonator. c) Modulator output spectrum.
tion in most common CT- M architectures. Instead of that, simulation-based analyses are
normally used to know the critical value of d leading to instability. Indeed, the simulation-
based analysis presented in [Cher99a] demonstrates that, in the more general case of a Lth-
order (bandpass) CT- M, the critical value of d is approximately given by:
1
d
--------------------------------------- (1.95)
critical H f
out-of-band
where H f is the loop-filter transfer function.
1.9.2 Excess-loop-delay compensation techniques
In order to palliate the effect of excess loop delay, a number of compensation tech-
niques have been reported in the open literature [Bena97] [Cher99a][Kell08][Ortm06].
Among others, the most commonly used strategies are based on the use of additional feed-
back DACs with their corresponding tunable scaling coefficients in order to cancel out
the additional poles of N TF [Cher99a]. This technique is illustrated in Fig. 1.42 for a 2nd-
x k in I1 s I2 s y
B-bit
fs
* *
–k1 –k2
DACNRZ
*
–kh
DACHRZ
Figure 1.42: 2nd-order CT- M with additional feedback DAC to compensate for
the excess loop delay [Ortm06].
order single-loop architecture, where an additional HRZ DAC is used [Ortm06]. The com-
pensation scaling coefficient can be determined by matching the actual open-loop LF trans-
fer function with the ideal one. This calculation detailed in [Ortm06] can be done in the
Z-domain yielding to the following relationships among ideal and real feedback coeffi-
cients:
* * 3k 1 d *
LF ideal = LF non-ideal k 1 = k 1 k 2 = -------------- + 2k 2 k h = k 1 d + 2k 2 (1.96)
2
*
where k i are the scaling feedback coefficients of the compensated modulator, while k i are
the coefficients of the original (ideal) modulator.
An interesting and robust implementation based on the strategy described above was
proposed by Yan and Sánchez-Sinencio [Xia04] and is illustrated in Fig. 1.43. As shown in
Fig. 1.43(a), this technique consists in adding one extra feedback DAC (labelled DAC_B)
which is connected from the output to the input of the internal quantizer, together with an
additional half clock cycle delay. The clock timing diagram is shown in Fig. 1.43(b). The
half-delay latch placed in front of DAC_B holds the data when clock (CLK) is low, whereas
when CLK is high, it simply works as a digital buffer, and any change at the input propa-
gates instantly to the output. In this way, the operation of the modulator is not affected even
if the excess loop delay of the internal ADC varies from zero to nearly one clock period
[Xia04]. The main benefit of this technique is that it reduces the impact of excess loop delay
without adding any extra feedback coefficient which needs some kind of calibration, as
explained above†13.
†13.Indeed the excess-loop-delay compensation technique proposed in [Xia04] is the strategy most com-
monly used by reported CT- M ICs, and it has been used in the designs presented in this thesis.
The above strategies compensate for the excess loop delay in the analog part of the CT-
M. Recently, alternative solutions have been proposed to cancel out this error in the dig-
ital domain. This is the case of the digital cancellation technique proposed by Fontaine et al.
[Gail89] illustrated in Fig. 1.44, where a digital feedback loop is inserted after the internal
quantizer and the analog coefficients are modified to produce an N TF almost equivalent to
the ideal delay-free loop filter. A half-clock-delay latch is also used to relax the comparator
speed and to provide maximum isolation of the quantizer from DAC switching events.
All these techniques together with other ones proposed in literature have been recently
compared in an excellent paper by M. Keller et al. [Kell08], in terms of their impact on
SNR, DR, output swing and dynamic requirements of both single-loop and cascade CT-
M architectures. In conclusion, it can be said that in present designs, excess loop delay is
an error that must be taken into account, but their effect can be controlled by using proper
design and architecture techniques. This non-ideal timing effect is particularly critical in
high speed applications, where CT- Ms are more appropriate than their DT- counterparts.
x H s y
B-bit
(a) fs
DAC_A DAC_B
z-1/2 z-1/2
Extra DAC to compensate

excess loop delay error
S/H
Flash ADC Edge trigered

(b)
DAC_A
Level trigered
DAC_B
Figure 1.43: Excess-loop-delay cancellation technique presented in [Xia04].

x
Extra Digital loop to
compensate for excess
b1 b2 b3
loop delay
I s I s I s y
B-bit
g
CLK
a1 a2 a3
DAC Latch
Figure 1.44: Digital compensation of excess loop delay [Gail89].

1.10 Comparator metastability
Previous analyses assume an ideal quantizer except for the inherent quantization error.
In practice, quantizers are implemented by flash ADCs, in which non-ideal effects are
mainly caused by comparator errors, namely: offset and hysteresis [Bose88]. As for the case
of DT- Ms, the impact of comparator errors is attenuated by the gain of the of the com-
plete loop filter and hence, they can be considered negligible as compared to building-block
errors [Mede99]†14.
Nevertheless, although comparator offset and hysteresis are less critical than other CT-
M errors, they must be taken into account in high-performance applications, particularly
when high-resolution is required and multi-bit quantization is used [Ortm06]. In this case,
there is a trade off among static resolution (limited by offset and hysteresis) and transient
response of the comparators, which becomes severely degraded by the exponentially
increased input capacitance with the number of bits. Moreover, the flash architecture
requires a reference resistor ladder. Thus, in order to reduce the effect of capacitor
feedthrough from the comparators into the reference ladder, the resistors need to be small,
thus increasing the power dissipation [Ortm06]. In order to circumvent this multiple trade-
off among offset, hysteresis, speed and power dissipation, some authors propose alternative
solutions to implement high-resolution quantizers by using tracking quantizer [Dorr05] or
successive approximation ADCs [Sami02].
In addition to the errors caused by the comparator, the quantizer operation is degraded
by two timing-induced errors, namely: clock jitter and comparator metastability. The former
discussed in Section 3.6 has a little impact on the resolution of the modulator. The latter
caused by the signal dependency of the quantizer delay is particularly critical in the case
of CT- Ms, and can be considered as a variable excess loop delay analysed in previous
section but associated to the quantizer block instead to the DAC transient response†15.
Comparator metastability is illustrated in the electrical simulation shown in Fig. 1.45

(a) [Cher99]. This phenomenon consists of the variation of the comparison time with the
input signal, v i . Ideally, the time delay depicted in Fig. 1.45(a) should be independent on
the input signal. However, as a consequence of the finite comparator gain, there is a depend-
ence of the comparison time with the input signal amplitude. This dependence can be math-
ematically expressed as [Cher99]:
d1
d m = d 0 + --------- (1.97)
a
vi
†14.The interested reader can find more details about the effect of comparator errors on the performance
of Ms in [Bose88].
†15.As metastability is a quantizer-induced error, its effect is less critical than excess loop delay, which
directly affects the loop filter transfer function.
(a) (b)
Figure 1.45: Illustrating comparator metastability.
(a) Electrical simulation of comparison time vs. input signal amplitude.
(b) Effect on a 2nd-order CT- M [Cher99].
where d 0 stands for the comparison time delay for large input signal amplitudes and a is an
adjustable parameter. The effect of this signal-dependent delay is illustrated in Fig. 1.45(b)
for a 2nd-order CT- M, showing a severe increase of the in-band noise power as com-
pared to considering a constant time delay.
The effect of metastability is relatively easy to circumvent by including latches between

the quantizer and the feedback DAC. Clocking each latch stage on the opposite clock phase
from the previous stage gives the previous stage a good deal of time to settle. The price to
pay is the additional delay introduced in the feedback loop [Cher00]. Indeed, the effect of
metastability is a critical issue as the clock frequency increases and the timing errors
become limiting factors. However, the use of multiple latches has been demonstrated very
effective even for sampling frequencies in the GHz range. This is the case of the 2nd-order
CT- M reported in [Enge99], where a 2-GHz clock signal is used. As illustrated in
Fig. 1.46, the modulator in [Enge99] uses a comparator based on two latches. However,
additional latches are used to synchronize the last latch’s output transitions with the sam-
pling clock times. These additional latches can reduce comparator’s metastability. The
number of latches vary depending on a number of practical issues. Thus, for typical process
parameters, 3-latch solution is adequate to meet the metastability specification. However, to
meet the metastability specification over all process corners, a 5-latch comparator is neces-
sary [Enge99].
1.11 Clock jitter error
The performance of CT- Ms may becom largely impacted by time uncertainties in the
clock-signal edges illustrated in Fig. 1.47(a) commonly referred to as clock jitter
[Cher00]. Clock jitter occurs at those points within the modulator architecture where signals
are transformed from the CT- domain to the DT- domain and vice versa, i.e at the S/H and
reconstruction DAC, respectively as illustrated in Fig. 1.47(a). The error introduced by the
gm
DAC
DAC
Latch Latch Latch Latch Latch
Pre-amplifier DAC
Driver
Clock
Figure 1.46: 2-GHz 2nd-order CT- M architecture with multiple latches to reduce
metastability [Enge99].
tj
fS clock
x +
a Y
y
Loop Filter H s
DAC
tj
clock
1 1 0 1 0
DT DAC CT DAC q
NRZ
jitter
q t
t
RZ
b c
Figure 1.47: Clock jitter in CT-Ms. (a) Main jitter error sources. (b) 1-bit RZ vs.
NRZ CT DAC waveforms.(c) DT vs. CT feedback DAC waveforms.
S/H is attenuated within the signal band by the modulator noise-shaping effect, and can
hence be neglected. However, the jitter error at the DAC illustrated in Fig. 1.47(b) for a
NRZ and RZ 1-bit waveforms occurs without attenuation at the input node, thereby limit-
ing modulator accuracy. The reason why CT- Ms are more sensitive to clock jitter than
DT- Ms is illustrated in Fig. 1.47(c), where typical SC waveform is compared to a CT
current-mode waveform. In the SC case, most of the charge transfer occurs at the start of the
clock period, so that the amount of charge lost due to a timing error is relatively small. By
contrast, in the CT case, charge is transferred at a constant rate over a clock period, and so
charge loss from the same timing error is a larger proportion of the total charge [Veld03].
Jitter analysis of high-speed CT- Ms has attracted significant interest in technical lit-
erature [Zwan96][Olia98][Tao99][Cher00][Bree01][Olia03][Hern04] [Chan06] [Redd07]
[Vasu09]. Most studies have addressed only the case of modulators with single-bit quantiz-
ers and RZ DACs whereas a much smaller number of studies have been focused on modula-
tors employing multi-bit quantizers and NRZ DAC waveforms [Hern04][Redd07]. This
may be due to the fact that analysis of these multi-bit NRZ waveforms is mathematically
more complex than their RZ counterparts. As a consequence, designers willing to use these
waveforms have to rely on inexact semi-empirical estimations based on simulation results
[Cher00][Hern04][Xia04], whereas very little has been done in the theoretical area
[Redd07].
Despite the lack of theoretical coverage, multibit quantizers and NRZ DACs are appeal-
ing for practical usage because they have low sensitivity to jitter. Many of the recently
reported prototypes for medium-to-high resolutions (11-14bit) and large signal bandwidths
(1-15MHz) employ either multi-bit quantizers, or NRZ DACs, or both [Moya03][Pato04].
This thesis is basically aimed at bridging the gap between theory and practice by providing
an analytical coverage of jitter error in multi-bit CT- Ms with NRZ DACs. As compared
to both the effect of the modulator loop filter transfer function and that of the input signal
are covered herein. The state-space formulation is used to derive closed-form relations
between jitter error, sampling frequency, modulator specifications (resolution and signal
bandwidth), circuit topology (loop filter transfer function and number of bits of the internal
quantizer) and input signal parameters (amplitude and frequency). This state-space formula-
tion is general, architecture-independent, and can be applied to any kind of CT Ms either
cascade or single-loop.
The study described in this thesis highlights effects that are significant for medium-to-
high-frequency applications like the ones targeted in this thesis. As the number of bits of the
internal quantizer increases, the signal-dependent term dominates over the modulator-
dependent term, as it would be expected, since the quantizer approaches the ideal case with
no quantization error. As a consequence, lowering the sampling frequency might increase
the impact of jitter instead of decreasing it as has been assumed up to now. In fact, it is
found that for a given set of modulator specifications, there is an optimum value for the
sampling frequency that minimizes the in-band noise power dominated by jitter.
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!
ANEXO 2: PRINCIPALES PUBLICACIONES SOBRE LOS

TRABAJOS RECOGIDOS EN LA TESIS DOCTORAL
RESUMEN
Este anexo incluye cinco publicaciones del doctorando que constituyen la principal aportación a su
trabajo de tesis doctoral. Tres de ellas han sido publicadas en revistas internacionales indexadas con
índice de calidad relativo en “Journal Citation Reports” (JCR) en la categoría de “Electrical & Electronic
Engineering”. Las otras dos publicaciones se corresponden con artículos presentados en el congreso
“IEEE International Symposium on Circuits and Systems (ISCAS)”, que es el principal congreso
organizado por la sociedad “Circuits and Systems” del IEEE, al que acuden habitualmente más de 1000
expertos en el área de Microelectrónica, y más concretamente de circuitos y sistemas - directamente
relacionado con la temática de esta tesis doctoral. En todos los casos, las publicaciones han sido aceptadas
tras ser sometidas a un proceso de revisión por pares.
Las referencias completas de las publicaciones incluidas son las siguientes:
- R. Tortosa, J.M. de la Rosa, F.V. Fernández, A. Rodríguez-Vázquez: “A New High-Level

Synthesis Methodology of Cascaded Continuous-Time ΣΔ Modulators,” IEEE Transactions on
Circuits and Systems-lI: Express Briefs, vol.53, pp. 739-743, August 2006. (ISSN: 1057-7130).
- R. Tortosa, J.M. de la Rosa, F.V. Fernández, A. Rodríguez-Vázquez: “Clock jitter error in multi-
bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform,”
Microelectronics Journal, vol. 39, pp. 137-151, January 2008. (ISSN: 0026-2692).
- R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez-Vázquez and F.V.

Fernández: “Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time
Sigma-Delta Modulators,” ETRI Journal, vol.30, no. 4, pp. 535-545, August 2008. (ISSN: 1225-
6463).
- R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Design of a 1.2-V

Cascade Continuous-Time ΣΔ Modulator for Broadband Telecommunications,” Proceedings of
2006 IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 589-592, May 2006. (ISBN: 0-
7803-9390-2).
- R. Tortosa, A. Aceituno, José M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “A 12-

bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator,” Proceedings of 2007
IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2007. (ISBN: 1-4244-0921-
7).
!
!
PUBLICACIÓN 1
Título de la Publicación: A New High-Level Synthesis Methodology of Cascaded

Continuous-Time ΣΔ Modulators
Autores: Ramón Tortosa, José M. de la Rosa, Francisco V. Fernández, Angel Rodríguez-
Vázquez
Tipo de publicación: Revista internacional indexada con indice de calidad relativo
Nombre de la revista: Transactions on Circuits and Systems-II: Express Briefs
Editorial: IEEE
ISSN: 1057-7130
Indice de impacto: 0.922
Referencia completa de la publicación:
R. Tortosa, J.M. de la Rosa, F.V. Fernández, A. Rodríguez-Vázquez: “A New High-Level
Synthesis Methodology of Cascaded Continuous-Time ΣΔ Modulators,” IEEE Transactions on
Circuits and Systems-lI: Express Briefs, vol.53, pp. 739-743, August 2006.
RESUMEN
Este artículo propone un método eficiente para la síntesis de moduladores ΣΔ en cascada

implementados mediante técnicas de circuito de tiempo continuo. El método propuesto se basa
en la síntesis de la cascada completa directamente en el dominio del tiempo continuo, en lugar de
aplicando una transformación discreta-a-continua a un modulador de tiempo discreto
equivalente, como se había hecho anteriormente a esta publicación.
Además de posibilitar una distribución óptima de los ceros del filtro del lazo, la metodología
propuesta conduce a arquitecturas más eficientes en términos de la complejidad de la circuitería
analógica, del consumo de potencia y de la robustez frente a los errores del circuito.
!
AUGUST 2006 VOLUME 53 NUMBER 8 ITCSFK (ISSN 1057-7130)
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 8, AUGUST 2006 739
A New High-Level Synthesis Methodology of

Cascaded Continuous-Time Modulators
Ramón Tortosa, José M. de la Rosa, Senior Member, IEEE, Francisco V. Fernández, and
Angel Rodríguez-Vázquez, Fellow, IEEE
Abstract—This brief presents an efficient method for syn-

thesizing cascaded sigma–delta modulators implemented with
continuous-time circuits. It is based on the direct synthesis of
the whole cascaded architecture in the continuous-time domain
instead of using a discrete-to-continuous time transformation as
has been done in previous approaches. In addition to placing the
zeroes of the loop filter in an optimum way, the proposed method-
ology leads to more efficient architectures in terms of circuitry
complexity, power consumption and robustness with respect to
circuit errors.
Index Terms—Analog–digital conversion, continuous-time
sigma–delta ( ) modulation.
I. INTRODUCTION .
Fig. 1. Conceptual block diagram of a cascaded CT-
C ONTINUOUS-TIME (CT) sigma–delta modulators

( s) are suited to analog-to-digital (A/D) interfaces
in submicrometer CMOS [1]. Although most s employ
This brief presents a direct synthesis method for cascaded
architectures. On the one hand, this method yields better placing
discrete-time (DT) circuits, CT techniques are applicable to of the noise transfer function zeroes and poles. On the other
broadband data communication systems due, among other fea- hand, it reduces the number of analog components. Thus, more
tures, to their intrinsic anti-aliasing filtering and their suitability robust and efficient architectures are obtained than when using
for fast operation with low power consumption [2], [3]. DT-to-CT transformation. The method is illustrated in this brief
Compared to DT- s, a drawback of CT modulators is through the synthesis of a 2-1-1-1 cascaded CT- for 12-bit
their higher sensitivity to some circuit errors, namely: clock at 40-MS/s.
jitter, excess loop delay and time constant tolerances [2], [3]. II. CASCADED CT MODULATORS
Among other things, the impact of these errors influences the
choice of the architecture. Particularly, most reported CT- Fig. 1 shows the conceptual block diagram of a -stage
s ICs employ single-loop topologies [4], [5] to circumvent the cascaded CT- . Each stage, consisting of a single-loop
larger impact of tolerances on cascaded architectures. However, CT- (typically either second or first order), modulates
some recent contributions demonstrate that cascaded CT- a signal that contains the quantization error generated in the
ICs are feasible and well suited to broadband applications [6]. previous stage. Once in the digital domain, the stage outputs
This is significant because cascaded architectures have larger are processed and combined by the cancellation logic so
modularity and less stability problems than their single-loop that only the quantization error of the last stage remains. Also,
counterparts for the same filtering order. this error is shaped by a transfer function whose order equals
Different authors have addressed the synthesis of high-order the sum of the respective orders of all the stages in the cascade.
cascaded CT- s [7]–[9]. In all cases, the proposed methods Cascaded CT- s are typically synthesized from equiva-
are based on applying a DT-to-CT transformation to an equivalent lent DT systems and use the same digital cancellation logic [8]
DT topology that fulfils the required specifications. In most cases, as the DT prototype. This DT-to-CT equivalence can be guaran-
the use of such transformation yields an increase of the analog teed because at each stage the corresponding feedback transfer
circuit complexity, with the subsequent penalty in silicon area, function from the quantizer output to the quantizer input is of
power consumption, and sensitivity to parameter variations. discrete-time nature [2]. Assuming a rectangular impulsive re-
sponse at the digital-to-analog converter (DAC), this equivalent
Manuscript received May 13, 2005; revised October 26, 2005. This work was
DT loop filter transfer function is calculated as [10], [11]
supported by the Spanish Ministry of Science and Education (with support from
European Regional Development Fund) under Contract TEC2004-01752/MIC.
This paper was recommended by Associate Editor H. Hashemi.
The authors are with the Institute of Microelectronics of Seville (IMSE),
National Microelectronics Center (CNM-CSIC), 41012 Seville, Spain (e-mail:
jrosa@imse.cnm.es). (1)
Digital Object Identifier 10.1109/TCSII.2006.875310
1057-7130/$20.00 © 2006 IEEE

740 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 8, AUGUST 2006
where stands for the -transform, is the inverse Laplace

transform, is the DAC transfer function, and
(4)
represents the transfer function from to the input of the th

quantizer [see Fig. 2(b)].
Using the notation , the
output of each stage is given by
(5)
and the output of the modulator can be written as
(6)
The cancellation logic transfer function is calculated by
annulling the quantization errors of the first stages. This
Fig. 2. Cascaded 2-1-1 CT architecture obtained (a) from an equivalent gives
DT , and (b) using the proposed method.
where is the sampling frequency; ;

; , and are, respectively, the time (7)
delay and pulsewidth of the DAC waveform; are the poles of where the cancellation logic transfer function of the last stage,
and stands for the residue of . , can be chosen to be the simplest form that preserves
To get a functional CT- whose cancellation logic coin- the required noise shaping.
cides with that of the original DT- , every state variable Note that the design equations (2)–(7) do not only take into
and DAC output must be connected to the integrator input account the single-stage loop filter transfer functions , but
of the ulterior stages in the cascade [8]. This increases the also the inter-stage loop filter transfer functions .
number of analog components (transconductors, amplifiers, The latter are CT integrating paths appearing only when the
and DACs) needed. For instance, Fig. 2(a) shows a cascaded modulator stages are connected to form the cascaded and
2-1-1 CT- obtained from an existing DT- [12]. must be included in the synthesis methodology to obtain a func-
Note that eight scaling coefficients and their corre- tional modulator with a minimum number of inter-stage paths.
sponding signal paths are needed to connect the different stages Therefore, the following systematic procedure can be pro-
of the modulator. As a counterpart, if the CT- is directly posed for the synthesis of cascaded CT s.1
synthesized by following the technique in this brief, the number • First, the poles of the single-loop transfer functions
of integrating paths can be reduced—see Fig. 2(b). are optimally placed in the signal bandwidth for
given specifications. The poles of the individual stages can
III. PROPOSED METHODOLOGY be placed such that the overall pole distribution within the
signal bandwidth is equivalent to that proposed in [13].
Let us consider the more general case of the -stage cascaded
• Secondly, each individual stage is optimized following
CT- shown in Fig. 1. The overall output is given by
a similar procedure as the one proposed in [14], that is,
numerator coefficients in are optimized to maximize
the resolution while maintaining the system stability. This
(2)
process is carried out entirely in the CT domain and no
equivalence to an existing DT modulator needs to be con-
where and denote, respectively, the output and sidered. Once are defined, , are automatically
the cancellation transfer function of the th stage. determined by the inter-stage integrating paths as outlined
If the modulator input is set to zero, the output of each in Fig. 2(b).
stage can be written as • Thirdly, once the individual stages are designed, (7) is used
to obtain the cancellation transfer functions.
1In this procedure, the modulator order, oversampling ratio, and number of
(3) bits of internal quantizers are assumed to be determined for the given specifica-
tions from well-known expressions [1].
TORTOSA et al.: METHODOLOGY OF CASCADED CT MODULATORS 741
For illustration, the 2-1-1 CT- of Fig. 2(b) was synthe-

sized using (2)–(7) to achieve 16-bit resolution in a 750-kHz
bandwidth, with a sampling frequency of 48 MHz (oversam-
pling ratio ) [12]. For simplicity, in order to facilitate
the comparison of the performance of both modulators in Fig. 2,
the coefficients of the first stage are taken
to be equal in both systems and are obtained from a DT-to-CT
transformation of the first stage of the DT- in [12]. The
rest of the coefficients in Fig. 2(b) are chosen such that the time
constant of the integrators is the inverse of the sampling fre-
quency . In summary
(8)
Thus, the single-loop and inter-stage transfer functions are
(9)
and the cancellation logic transfer functions can be calculated
using (7)–(9). Considering a nonreturn-to-zero (NRZ) DAC, the
following are obtained: Fig. 3. Effect of mismatch on the SNR of a cascaded 2-1-1 CT obtained:
(a) from an equivalent DT , and (b) from the proposed method.
each point of these surfaces, 150 simulations were carried out

using random variations with the corresponding standard devi-
(10) ations. The value of the SNR loss represented in Fig. 3 stands
where is chosen to have three zeroes at dc, corresponding for the difference between the ideal SNR, i.e., with no param-
to the zeroes contributed by the first three integrators. eter variation, and the SNR with 90% of the 150 simulations
To compare the robustness of both modulators in Fig. 2, the above it. It is shown that the lower analog component count
effect of mismatch on the signal-to-noise ratio (SNR) was simu- in Fig. 2(b) is reflected in a lower variance of the modulator
lated using SIMSIDES—a SIMULINK-based time-domain be- coefficients, leading to better behavior in terms of sensitivity to
havioral simulator for s [15]. For this purpose, maximum mismatch.
values of mismatch were estimated for a 0.18- m CMOS tech- The same reasoning can be applied to the requirements in
nology. On the one hand, capacitor mismatch lower than terms of dc gain of the transconductors. Since the number of
1% are standard in modern technologies. On the other hand, transconductors connected to the same node is higher in the pre-
MOS transconductance mismatch is related to drain cur- vious method, the equivalent impedance associated with these
rent mismatch by the following expression: nodes tends to be lower and the requirement in terms of the in-
dividual transconductor output impedance is higher. Therefore,
(11) a higher dc gain is needed. Fig. 4 illustrates this point. Note that
the SNR-peak starts dropping at a dc gain 5 dB higher in the
In the case of the 0.18- m technology addressed, assuming typ- case of the system designed following the previous method. For
ical transistor sizes and a maximum spacing between transis- high dc gains, the two curves collide because the effect of this
tors of 1500 m, a maximum is obtained. Then, error becomes negligible.
taking into account that in a linearized transconductor, a min-
imum of 4 transconductance elements are used and that the IV. SYNTHESIS EXAMPLE
tuning circuit introduces an additional error, maximum values As an application of the proposed methodology, the 2-1-1-1
of are expected. cascaded CT shown in Fig. 5 was synthesized to achieve
Both modulators in Fig. 2 were simulated considering a 12-bit resolution within a 20-MHz signal bandwidth. In order
– implementation. The results are shown in Fig. 3, where to fulfill these specifications without being limited by the clock
the SNR loss is represented as a function of and . For jitter error, the sampling frequency, , and the number of bits of
742 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 8, AUGUST 2006
TABLE I
MODULATOR DESIGN VALUES
Fig. 4. Effect of dc gain on the SNR-peak.

to cancel the effect of finite gain-bandwidth product (GB) of the
front-end opamp, due to the fact that this error can be modelled as
an integrator gain error [5]. All the other transconductors could
be tuned in order to keep the time constant unchanged
over variations. In this case, the single-loop and inter-stage
transfer functions are
(12)
where
Fig. 5. Cascaded 2-1-1-1 CT .
(13)
the internal quantizers (and DACs), , must be properly chosen.
In the case of a fifth-order modulator like the one shown in and coefficients , , and are given by
Fig. 5, the in-band jitter noise power is minimized for
240 MHz and [16].
Another critical source of error in CT s is the excess (14)
loop delay. As shown in [17], this error can be compensated for
by adding an extra feedback branch between the output and the These coefficients are found through an iterative simulation-
input to the quantizer ( in Fig. 5) and two D-latches. By based process that optimizes the first stage of the modulator in
adding this extra branch with the appropriate gain, the loop im- order to maximize the SNR while maintaining stability. The out-
pulse response is exactly the same as that of the original. This come of this process—done entirely in the CT domain—is sum-
extra feedback term can be easily included in the calculation marized in Table I. This table includes the values of loop filter
of the cancellation logic by modifying appropriately the coefficients, (implemented as transconductances) as well as
transfer functions. In practice, this extra feedback branch will the capacitances, , and resistances, obtained from the opti-
only affect the cancellation logic if the input to other stages is mization process. The expressions of , can be obtained from
tapped at quantizer inputs or if the last stage includes a second (7) and (12), giving
DAC. In a practical implementation it might be advantageous to
make programmable [5].
Considering the factors above, the 2-1-1-1 architecture in Fig. 5
was synthesized using the methodology described in Section III.
The first stage is formed by a resonator which has its pole placed
at , minimizing the quantization noise transfer
function in the signal bandwidth, . Resistor variations can
be tuned out using a combination of a discrete rough tuning of
the resistors ( , and ) and a continuous fine tuning of
the transconductors and . This tuning can be also used (15)
TORTOSA et al.: METHODOLOGY OF CASCADED CT MODULATORS 743
TABLE II Fig. 7, where the signal-to-noise-plus-distortion ratio (SNDR)

NONIDEALITIES CONSIDERED IN THE SIMULATION is plotted as a function of the input signal amplitude.
V. CONCLUSION
This brief presents a new methodology for synthesizing cas-
caded continuous-time s. The resulting circuits are less
complex and more robust than those obtained with conventional
methodologies. Examples supported by realistic behavioral sim-
ulations are given to validate the presented approach.
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!
PUBLICACIÓN 2
Título de la Publicación: Clock jitter error in multi-bit continuous-time sigma-delta

modulators with non-return-to-zero feedback waveform
Autores: Ramón Tortosa, José M. de la Rosa, Francisco V. Fernández, Angel Rodríguez-
Vázquez
Nombre de la revista: Microelectronics Journal
Editorial: Elsevier
ISSN: 0026-2692
R. Tortosa, J.M. de la Rosa, F.V. Fernández, A. Rodríguez-Vázquez: “Clock jitter error in
multi-bit continuous-time sigma-delta modulators with non-return-to-zero feedback waveform,”
Microelectronics Journal, vol. 39, pp. 137-151, January 2008.
RESUMEN
Este artículo presenta un estudio detallado del error de “jitter” del reloj en moduladores ΣΔ de
tiempo continuo con DAC NRZ. Se demuestra que la potencia de ruido en la banda de la señal
causada por el jitter puede despomponerse en dos componentes fundamentales: una que depende
la función de transferencia del filtro del lazo del modulador y la otra que depende de la amplitud
y la frecuencia de la señal de entrada. Esta última componente, no considerada en estudios
anteriores, permite predecir de forma precisa la pérdida de resolución ocasionada por el error de
“jitter”, mostrando efectos que habían sido tenidos en cuenta en los estudios reportados con
anterioridad a esta publicación, y que son especialmente críticos en aplicaciones de
telecomunicaciones de banda ancha. El estudio que se presenta en este artículo se fundamenta en
la formulación espacio-estado, lo que hace que el análisis sea general y aplicable a cualquier
topología de moduladores tanto en cascada como de lazo simple. Como resultado del mismo se
obtienen ecuaciones de diseño para la potencia del ruido integrado en banda como para la
relación señal ruido. Dichas ecuaciones de pueden utilizar para optimizar las prestaciones del
modulador en relación a las especificaciones a conseguir con un consumo de potencia y una
potencia del error de “jitter” minimos. Como validación del análisis se presentan simulaciones en
el dominio del tiempo de diversas arquitecturas de moduladores con aplicación en VDSL.
!
Tesis Doctoral. Ramón Tortosa Navas
ARTICLE IN PRESS 109
Microelectronics Journal 39 (2008) 137–151

www.elsevier.com/locate/mejo
Clock jitter error in multi-bit continuous-time sigma-delta modulators

with non-return-to-zero feedback waveform
Ramón Tortosa, José M. de la Rosa!, Francisco V. Fernández, Angel Rodrı́guez-Vázquez
Departamento de Electrónica y Electromagnetismo, Instituto de Microelectrónica de Sevilla (IMSE), Centro Nacional de Microelectrónica (CNM), Consejo
Superior de Investigaciones Cientı´ficas (CSIC), Universidad de Sevilla, Edificio CICA-CNM, Avda Reina Mercedes S/N, 41012 Sevilla, Spain
Received 29 November 2006; received in revised form 18 September 2007; accepted 4 October 2007
Available online 26 November 2007
Abstract
This paper presents a detailed study of the clock jitter error in multi-bit continuous-time SD modulators with non-return-to-zero
feedback waveform. It is demonstrated that jitter-induced noise power can be separated into two main components: one that depends on
the modulator loop-filter transfer function and the other dependent on input signal parameters, i.e. amplitude and frequency. The latter
component, not considered in previous approaches, allows us accurately to predict the resolution loss caused by jitter, showing effects
not taken into account previously in literature despite the fact that they are especially critical in broadband telecom applications.
Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop
architectures. Closed-form expressions are derived for in-band error power and signal-to-noise ratio that can be used to optimize
modulator performance in terms of jitter insensitivity. Time-domain simulations of several modulator topologies (both single-loop and
cascade) intended for VDSL application demonstrate the validity of the presented approach.
r 2007 Elsevier Ltd. All rights reserved.
Keywords: Analog-to-digital conversion; Continuous-time SD modulation; Clock jitter
1. Introduction transformed from the CT-domain to the DT-domain and

vice versa, i.e., at the sample-and-hold and reconstruction
Nowadays, the increasing demand for ever faster analog- digital-to-analog converter (DAC), respectively. The error
to-digital converters (ADCs) in broadband communication introduced by the sample-and-hold is attenuated within the
systems has boosted the interest in continuous-time (CT) signal band by the modulator noise-shaping effect, and can
sigma-delta modulators (SDMs). These modulators have hence be neglected. However, the jitter error at the DAC
intrinsic anti-aliasing filtering and the potential to operate occurs without attenuation at the input node thereby
at higher sampling rates and with lower power consump- limiting modulator accuracy.
tion than their discrete-time (DT) counterparts [1,2]. Jitter analysis of high-speed CT SDMs has attracted
However, CT SDMs are more sensitive than DT SDMs significant interest in technical literature [1–7]. Most studies
to some circuit non-idealities. Particularly, their perfor- have addressed only the case of modulators with single-bit
mance in high-speed applications is largely impacted by quantizers and return-to-zero (RZ) DACs whereas a much
time uncertainties in the clock-signal edges, commonly smaller number of studies have been focused on modula-
referred to as clock jitter [1]. Clock jitter occurs at those tors employing multi-bit quantizers and non-return-to-zero
points within the modulator architecture where signals are (NRZ) DAC waveforms. This may be due to the fact that
analysis of these multi-bit NRZ waveforms is mathemati-
!Corresponding author. Tel.: +34 955 056666; fax: +34 955 056686. cally more complex than their RZ counterparts. As a
E-mail addresses: tortosa@imse.cnm.es (R. Tortosa),
consequence, designers willing to use these waveforms have
jrosa@imse.cnm.es (J.M. de la Rosa), pacov@imse.cnm.es to rely on inexact semi-empirical estimations based on
(F.V. Fernández), angel@imse.cnm.es (A. Rodrı́guez-Vázquez). simulation results [1,7,8]. To the best of the authors’
0026-2692/$ - see front matter r 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2007.10.005
138 R. Tortosa et al. / Microelectronics Journal 39 (2008) 137–151
knowledge, only the work in [7] addresses the case of NRZ

DACs. However, in [7] some effects are not considered + y(n)
Loop Filter
which, as shown in this paper, might become critical in x(t)
− G(s)
medium-to-high-frequency applications.1
y(t)
Despite the lack of theoretical coverage, multi-bit
quantizers and NRZ DACs are appealing for practical DAC
usage because they have low sensitivity to jitter. Many of
the recently reported prototypes for medium-to-high Fig. 1. Conceptual block diagram of a single-loop CT SDM.
resolutions (11–14 bit) and large signal bandwidths
(1–15 MHz) employ either multi-bit quantizers, or NRZ
DACs, or both [9,10]. This paper is basically aimed at 2. Modeling clock jitter error in CT RDMs with NRZ DACs
bridging the gap between theory and practice by providing
an analytical coverage of jitter error in multi-bit CT SDMs Fig. 1 shows the conceptual block diagram of a single-
with NRZ DACs. As compared to [7] both the effect of the loop CT SDM.2 The loop filter is CT and a CT-to-DT
modulator loop-filter transfer function and that of the transformation is performed at the sampler placed after
input signal are covered herein. this filter.3 An inverse transformation, DT-to-CT, is
We use state-space formulation [11] to derive closed- performed at the DAC to obtain the CT feedback signal
form relations between jitter error, sampling frequency, y(t) from the modulator output y(n).4 Jitter occurs at the
modulator specifications (resolution and signal band- points where these two transformations take place. On one
width), circuit topology (loop-filter transfer function and hand, the error introduced at the sampler is subject to the
number of bits of the internal quantizer) and input signal same processing (assuming linear models) as the quantiza-
parameters (amplitude and frequency). This state-space tion noise, and hence pushed out-of-band by the modulator
formulation is general, architecture-independent, and can noise-shaping effect. As a consequence its contribution
be applied to any kind of CT SDMs either cascade or within the signal band can be neglected. On the other hand,
single-loop. the error associated with the DAC directly adds to the
The study described in this paper highlights effects not input signal and therefore makes a significant contribution
covered by previous approaches; effects that are signifi- within the signal band.
cant for medium-to-high-frequency applications. As the Let us focus on the DAC jitter error. Fig. 2 illustrates
number of bits of the internal quantizer increases, the how this error occurs in the time domain for RZ and NRZ
signal-dependent term dominates over the modulator- multi-bit DAC feedback waveforms. Assume in both cases
dependent term, as it would be expected, since the that the DAC output is a current, IDAC, and that the time
quantizer approaches the ideal case with no quantiza- uncertainty caused by jitter is represented by DT(n). This
tion error. As a consequence, lowering the sampling time uncertainty produces a corresponding uncertainty in
frequency might increase the impact of jitter instead the total charge associated with the nth clock period,
of decreasing it as has been assumed up to now. In fact,
it is found that for a given set of modulator specifica- DQðnÞ ffi DI DAC ðnÞ DTðnÞ, (1)
tions, there is an optimum value for the sampling frequency
that minimizes the in-band noise power dominated by where DIDAC(n) represents the amplitude of the signal
jitter. transition at the edge of the period. Note in Fig. 2 that,
This paper is organized as follows. Section 2 describes a since the output signal IDAC in a RZ DAC goes to zero at
model for the jitter effect on CT SDMs, with emphasis on each clock cycle, signal transition amplitudes are larger for
those architectures using NRZ DACs. Section 3 applies the RZ, DIDAC(n)|RZ$IDAC(n), than for NRZ DACs,
state-space formulation to derive closed-form expressions DIDAC(n)|NRZ$IDAC(n)%IDAC(n%1). Also, as the number
for the in-band noise power and the signal-to-noise ratio of bits in the quantizer increases, |DQ(n)| decreases for
dominated by the jitter error. Section 4 compares those NRZ DACs but remain practically unchanged for RZ
expressions with previous approaches. Finally, Section 5 DACs.
shows several time-domain simulations of different mod- A DAC output waveform with jitter can be represented
ulators using both single-loop and cascade topologies in as the sum of an unjittered output waveform and a stream
order to validate the theoretical predictions given by the 2
Note that Fig. 1 is a conceptual representation of a generic single-loop
presented approach. CT SDM. However, the analysis presented here is still valid for other
architectures, like high-order cascade topologies. Indeed, the results of this
study have been incorporated into a new system-level synthesis
methodology for cascade CT SDMs [12], which has been recently applied
1
Basically, jitter error contains two terms: one associated with the input to the design of a cascade 3–2 (4-bit) CT SDMs [13].
3
signal and the other associated with the modulator loop transfer function. In DT modulators the sampler is at the input and all signals in the loop
However, the work in [7] takes only into account the loop filter are DT.
4
dependency in order to optimize the design of the loop filter in terms of In order to simplify the notation, y(nTs) is written as y(n) with Ts being
jitter. the sampling period.
R. Tortosa et al. / Microelectronics Journal 39 (2008) 137–151 139
∆IDAC(n)
∆IDAC(n)
IDAC
IDAC
Ts Ts
∆T(n) ∆T(n)
Time Time
Fig. 2. Feedback DAC pulse shaping: (a) RZ DAC and (b) NRZ DAC.
of pulses with amplitude DIDAC(n) and width DT(n)—often term Dxn can be simplified as
!
referred to as jitter error sequence [1]. In the case of a NRZ dxðtÞ!!
Dxn ffi T s ¼ Aoi T s cos½oi ðn % 1ÞT s & (7)
DAC, the jitter error sequence can be related to the dt ! t¼ðn%1ÞT s
modulator output signal by [14]
and hence,
DTðnÞ T 2s A2 o2i
!ðnÞ ffi ½yðnÞ % yðn % 1Þ& , (2) EfðDxn Þ2 g ffi T 2s A2 o2i Ef½cos oi ðn % 1ÞT s &2 g ¼ .
Ts 2
where Ts is the sampling period. Assuming that DT(n) (8)
corresponds to a stationary process with zero mean and Regarding the second term in (6), the following
standard deviation sDT, the power of the jitter error signal approximate expression is derived in Appendix A:
" #
can be expressed as EfðDqn Þ2 g ffi E ðZ %1 ½ð1 % z%1 ÞN TF ðzÞ eðzÞ&Þ2
s2DT X 2FS
P! ¼ Ef!ðnÞ2 g ¼ Ef½yðnÞ % yðn % 1Þ&2 g, (3) ¼
T 2s 12pð2B % 1Þ2
Z p
! !
) !ð1 % e%jo ÞN TF ð1 % e%jo Þ!2 do, ð9Þ
where E{.} represents the mathematical operator expecta-
0
tion [15].
The following definition will be used: where XFS is the full scale, B is the number of bits of the
internal quantizer, NTF(z) is the noise transfer function and
yðnÞ ¼ xðnÞ þ qðnÞ, (4) e(z) is the Z-transform of the quantization error.
From (3), (8) and (9), we obtained
i.e., the output y(n) can be mathematically expressed as the $ %
combination of the input signal x(n) and an error signal sDT 2
P! ffi
q(n).5 Using (4), E{[y(n)%y(n%1)]2} is expanded as follows: Ts
Z !
2 2
A oi X 2FS 1 p !! !
%jo !2
Ef½yðnÞ % yðn % 1Þ&2 g ) þ %jo
ð1 % e ÞN TF ðe Þ do ,
2f 2s 12ð2B % 1Þ2 p 0
¼ Ef½xðnÞ % xðn % 1Þ&2 g
Ef½qðnÞ % qðn % 1Þ&2 g % 2Ef½xðnÞ % xðn % 1Þ& ð10Þ
)½qðnÞ % qðn % 1Þ&g. ð5Þ where fs*1/Ts is the sampling frequency.
Depending on the actual modulator topology, the
Assuming that x(n) and q(n) are uncorrelated, (5) can be integration in (9) and hence the calculation of the second
simplified to: term in (10) may become too involved. Instead, E{(Dqn)2}
can be calculated analytically by using the state-space
Ef½yðnÞ % yðn % 1Þ2 &g ffi Ef½xðnÞ % xðn % 1Þ&2 g formulation shown in the next section. State-space
þ Ef½qðnÞ % qðn % 1Þ&2 g ¼ EfDxðnÞ2 g þ EfDqðnÞ2 g, ð6Þ formulation provides a framework to study all types of
modulators. Most important, it allows the study of jitter-
where Dxn*x(n)%x(n%1) and Dqn*q(n)%q(n%1). induced noise in the time domain and extract the noise
The equation above contains two terms. The first one autocorrelation function [6].
depends on the input signal. Considering a sinewave input
signal of amplitude A and angular frequency oi ¼ 2pfi, this 3. State-space formulation
5
Note that, for the sake of simplicity, a unity signal transfer function
(STF) has been assumed in Eq. (4). Considering that a common situation Let us consider the conceptual block diagram in Fig. 1.
in practice is that |STF| ¼ 1 within the signal bandwidth, this assumption Using the impulse-invariant transformation [16], the
can be used without loss of generality in the presented analysis. DT equivalent of the loop-filter transfer function can be
written as e(n)
d0 d1 d2 dL-1
nðL$1Þ zðL$1Þ þ & & & þ n1 z þ n0 dL
v1
dL dL dL
GðzÞ ¼ , (11) v2 vL
d L z þ d ðL$1Þ zðL$1Þ þ & & & þ d 1 z þ d 0
L
z-1 z -1
z-1 q(n)
n0+d0 n1+d1 n2+d2 nL-1+dL-1

where ni and di are function of the coefficients of the
dL dL dL dL
original CT modulator loop filter, G(s). Therefore, NTF(z)
can be derived from (11) as
Fig. 3. Transpose of the Direct II implementation of NTF(z).
1
N TF ðzÞ ¼
1 þ GðzÞ
d N zL þ d N$1 zL$1 þ & & & þ d 1 z þ d 0
¼ v(n+1)0 v(n)0
d L zL þ ðd L$1 þ nL$1 ÞzL$1 þ & & & þ ðd 1 þ n1 Þz þ ðd 0 þ n0 Þ e(n) q(n)
d L þ d L$1 z$1 þ & & & þ d 1 z$ðL$1Þ þ d 0 z$L p0 z–1 g0
¼ .
d L þ ðd L$1 þ nL$1 Þz$1 þ & & & þ ðd 1 þ n1 Þz$ðL$1Þ þ ðd 0 þ n0 Þz$L
ð12Þ F0
Fig. 3 shows the transpose of the Direct II implementa-
tion of (12) [15]. This block diagram does not have any Fig. 4. State-space representation of NTF(z).
direct correspondence with the physical implementation of
the modulator and is only used to represent the relation-
ship between the input e(n), output q(n) and state variables Equation system (13) can be solved recursively to find
of NTF(z). The so-called state-space representation of the relation between the initial state vð0Þ0 , previous inputs
NTF(z) can be implemented by the block diagram in e(k), current input e(n) and output q(n) of the system [15].
Fig. 4, which is described by the following finite difference This gives
equations [15]: n
qðnÞ ¼ g0 T & F 0 & vð0Þ0
vðn þ 1Þ0 ¼ F 0 & vðnÞ0 þ p0 & eðnÞ,
X
n$1
n$k$1
qðnÞ ¼ g0 T & vðnÞ0 þ eðnÞ, ð13Þ þ g0 T & F 0 & p0 & eðkÞ þ eðnÞ. ð15Þ
k¼0
where F0 is the state matrix, vðnÞ0 is the L ' 1 state vector,
p0 and g0 are L ' 1 vectors, respectively, given by
2 3.1. Expectation value of (Dqn)2
n0 þ d 0 3
0 0 0 ... 0 $
6 dL 7 To compute the power of the jitter error from (2) it is
6 7
6 n1 þ d 1 7 necessary to derive the mathematical expectation of (Dqn)2,
6 7
6 1 0 0 ... 0 $ 7 given by
6 dL 7
6 7
6 n2 þ d 2 7
6 7 EfðDqn Þ2 g ¼ Ef½qðnÞ $ qðn $ 1Þ)2 g
6 0 1 0 ... 0 $ 7
F0 ¼ 6 dL 7, ¼ 2½EfqðnÞ2 g $ EfqðnÞqðn $ 1Þg), ð16Þ
6 7
6 n3 þ d 3 7
6 0 0 1 ... 0 $ 7 2
where the fact that E{q(n) } ¼ E(q(n$1) ) has been taken 2
6 7
6 dL 7 into account.
6... ... ... ... ... ... 7
6 7 It is demonstrated in Appendix B that E{(Dqn)2} is given
6 7
4 nL$1 þ d L$1 5 by
0 0 0 ... 1 $
dL
2 n0 3 EfðDqn Þ2 g
!
6 dL 7 2 T
X
L X
L l$1 $1 $1
k $ lk l j
6 7 ¼ 2EfeðnÞ g 1 $ ḡ & p̄ þ gk pk gj pj ,
6 n1 7 1 $ l$1 $1
k lj
6 7 k¼1 j¼1
p0 ¼ $6 7
6 d L 7,
6 ... 7 ð17Þ
6 7
4 nL$1 5 where L is the order of NTF, li are the eigenvalues of F 0
dL and gi and pi are, respectively, the elements of
2 3
0 ḡT ¼ g0 T & T̄ and p̄ ¼ T $1 & p0 , being T̄ the matrix of the
6 7 eigenvectors of F0.
6 0 7
6 7 Taking into account that
g0 ¼ 6 7 . ð14Þ
6...7
4 5 X 2FS
EfeðnÞ2 g ¼ . (18)
1 12ð2B $ 1Þ2
Expression (17) can be rewritten as

b2 s2 + b1 s +b0 y(n)
2 X 2FS x(t)
+
EfðDqn Þ g ¼ cðḡ; p̄; l̄; LÞ, (19) − s (s2 +!p2)
6ð2B $ 1Þ2
y(t)
where
DAC
L X
X L l$1 $1 $1
k $ l k lj
cðḡ; p̄; l̄; LÞ ¼ 1 $ ḡT % p̄ þ gk pk gj pj . Fig. 5. Conceptual block diagram of a 5-bit third-order single-loop CT
k¼1 j¼1 1 $ l$1 $1
k lj SDM.
(20)
The above expression gives a direct method to calculate Table 1

E{(Dqn)2}, and hence Pe from the eigenvalues of a L ' L Loop-filter coefficients of the modulator in Fig. 5
matrix, which involves the summation of L2 terms,
Coefficient Value, 2b Value, 4b Value, 6b
normally with Lo5.
24 25
b0 7.4 ' 10 2.4 ' 10 3.2 ' 1025
3.2. In-band noise power and signal-to-noise ratio b1 5.3 ' 1016 9.7 ' 1016 1.8 ' 1017
b2 3.3 ' 108 4.2 ' 108 5.0 ' 108
op 9.7 ' 107
Replacing (9) with (19) in (10), the jitter noise power is
given by
! "
s2DT T 2s A2 o2i X 2FS
P! ¼ 2 þ cðḡ; p̄; l̄; LÞ . (21) the jitter term to obtain the total in-band noise Pin-band ¼
Ts 2 6ð2B $ 1Þ2 Pe_band+PQ_band.6
Taking into account that DT(n) is a Gaussian random Note that in (22) and (25) the primary time uncertainty
process, and that Dyn([y(n)$y(n$1)] is not correlated with error (sDT)2 is multiplied by two different factors which
DT(n), the error power computed using (21) can be added together define the hereinafter called Jitter Ampli-
assumed to be a white noise source at the input of the fication Factor, namely:
modulator. Therefore, the in-band noise power can be ) the signal-dependent term (SDT), that depends on the
written as input signal parameters A and oi, and sampling
! 2 2 "
A oi X 2FS f s frequency:
P!_band ¼ ðsDT Þ2 Bw þ cðḡ; p̄; l̄ % LÞ , (22)
fs 3ð2B $ 1Þ2
where Bw is the signal bandwidth. A2 o2i
SDT ¼ (26)
The in-band noise power sets the accuracy which the fs
modulator can attain. This accuracy can be alternatively
formulated in terms of SNR, ) and the modulator-dependent term (MDT), that depends
A 2 on the modulator topology parameters B, XFS and
SNRjitter ( . (23) c(g,p,l,L), and sampling frequency:
2P!_band
Depending upon whether the in-band noise power is
X 2FS f s
dominated only by the jitter terms or also includes the MDT ¼ cðḡ; p̄; l̄; LÞ. (27)
quantization error noise power one obtains, respectively, 3ð2B $ 1Þ2
A2 Note also that the latter term increases with fs while the
SNRjitter ¼ 10 log ! ",
A2 o2 X2 f s former decreases with fs. This suggests that a value can be
2Bw ðsDT Þ2 f i þ FS cðḡ; p̄; l̄; LÞ
s 3ð2B $1Þ 2 found that minimizes the jitter amplification factor.
(24) Consider for illustration the third-order single-loop CT
SDM depicted at conceptual level in Fig. 5. Several
SNR modulators with different numbers of bits in the internal
quantizer (2b, 4b and 6b) have been studied. Table 1 shows
A2
¼ 10 log ! 2 2 ", the values of the loop-filter coefficients as well as the
X2 R Bw # #2 X2 f s
FS #N TF ðf Þ# df þ 2Bw ðsDT Þ2 A oi þ FS cðḡ; p̄; l̄; LÞ
3f s ð2B $1Þ2 0 f
s 3ð2B $1Þ2 position of the pole and Table 2 shows the values of gi, pi
and li, obtained from the state-space formulation. Fig. 6
ð25Þ
where SNRjitter corresponds to the case dominated by jitter, 6
The quantization noise power is given by the well-known expression,
and SNR corresponds to the more general case where an X2 R Bw # #
PQ_band ¼ 6f FS #N TF ðf Þ#2 df :
uncorrelated quantization noise term PQ_band is added to ð2B $1Þ2 0
s
plots the jitter amplification factor, together with its two means that improvement in the in-band noise power
constitutive terms, STD (common to all modulators) and would be possible by lowering the sampling frequency
MDT, as a function of fs for fi ¼ Bw ¼ 20 MHz. down to a certain value below which noise power starts
Several conclusions can be drawn: to raise again. In any case, dependency of jitter-induced
noise on sampling frequency is reduced significantly
with respect to the previous case.
" For the modulator with a 2 bit internal quantizer, jitter " In the case of a 6-bit internal quantizer, the jitter
sensitivity is completely dominated by the modulator- amplification factor is dominated by the input signal-
dependent term. In this case, lowering the sampling dependent term in most of the range under study.
frequency (while keeping constant Bw) yields an " Note also that for the cases with 4 and 6 bit internal
improvement in the in-band noise power. quantization, there is an optimum value of fs that
" In the case of the modulator with a 4-bit internal minimizes the in-band jitter noise power and hence,
quantizer, even though in the higher range of sampling maximizes SNR. Generally speaking, whenever jitter is
frequency jitter-induced noise is still dominated by the the main limiting factor of a multi-bit CT SDM with
modulator-dependent term, in the lower range the term NRZ DAC, obtaining the minimum value of the jitter
dependent on the input signal becomes dominant. This amplification factor provides a convenient criterion for
deciding loop-filter parameters, sampling frequency and
the number of bits in the internal quantizer for given
Table 2
specifications.
Values of gi, pi and li for the modulator in Fig. 5
Coefficient Value, 2b mod. Value, 4b mod. Value, 6b mod.
l̄ 0.031 #0.222 0.183

0.457+j0.497 0.123+j0.815 #0.635+j0.377 kin 1/4
0.457#j0.497 0.123#j0.815 #0.635#j0.377 kin
1 k2 1
p̄ #3.048 #2.807 #1.195 Tss Ts s k1 1/4
k1 k3
0.146#j0.64 #0.352#j1.37 #1.883#j7.541
0.146+j0.64 #0.352+j1.37 #1.883+j7.541 k2 1
ḡ 0.7 0.811 0.586 DAC k3 3/8

0.82 0.765 0.856
0.82 0.765 0.856
Fig. 7. Block diagram of a single-bit second-order CT SDM.
x107 x107
3.5 11
10
Jitter Amplification Factor 2b
3 9
8
2.5
MDT 2b 7
6
V2Hz
V2Hz
2
Jitter Amplification Factor 4b
5
Jitter Amplification Factor 6b 4

1.5
SDT 3
MDT 4b
1 2
MDT 6b
1
0.5
0
180 200 220 240 260 280 300 320 340
fs (MHz)
Fig. 6. Jitter components vs. fs for the modulator in Fig. 5. Note that the right vertical scale applies to the modulator with 2 bit quantization and the left
scale to the rest of the cases.
4. Comparison with previous approaches operation of multi-bit CT SDMs with NRZ DACs. Among
other things, this improved insight helps designers to better
The main interest of the analysis carried out in this paper understand the impact of the input signal on the jitter error
lies in the availability of simple, yet accurate, analytical balance. As was shown in Fig. 6, different design regions
expressions for the jitter-induced in-band noise power. can be defined based on the relative importance of the
These expressions help designers to gain an insight into the terms (26) and (27). It was also illustrated how, under
certain conditions, jitter-induced noise could increase with
decreasing sampling frequency. This therefore limits the
80 Equation 34, [3] bandwidth that can be effectively achieved in practice.
Equation 30
Equation 31
78 [7]
Simulated
76
Table 3
Loop-filter coefficients of CT SDMs in Fig. 9
SNR (dB)
74 CT SDM1 CT SDM2 CT SDM3
72 kin 1.5 2 1.6

kfb !1.5 !2 !1.6
kg1 1 1 1.6
70
kr !0.1 !0.37 !0.24
kg2 0.6 1 –
68 kg3 0.5 1.2 –
Quantization error-dominated Jitter-dominated
kff1 1 1 1
66 kff2 0.5 1 –
0 5 10 15 20 25 30 kin2 – – 1
Clock jitter standard deviation !"T (ps) Kfb2 – – !1
pffiffiffiffiffiffiffi
Poles o1 ¼ 0; o2 ¼ 3=52pBw
Fig. 8. Comparison of theory and simulations for the modulator of Fig. 7.
kff1
kff 2
x(t) kin kg1

1 1 1
kg2 kg3 y(n)
Tss T ss T ss
kfb kr
DAC
kff1
x(t) kin
1 1
kfb T ss kg1 Tss
kr
Cancellation Logic
DAC
y(n)
kin2
1
Tss
kfb2
DAC
Fig. 9. Multi-bit NRZ CT SDMs under study: (a) third-order single-loop and (b) cascade 2-1.
However, in spite of the practical relevance of such a limit, single-bit second-order CT SDM of Fig. 7 with fi ¼ Bw, an
this effect has not been addressed in previous analysis. input amplitude of 80% of the reference level, fs ¼ 40 MHz
Coverage provided by previous analyses, especially those and an oversampling ratio M"fs/(2Bw) ¼ 64.
in [3,7], are appropriate whenever the modulator term In this case, the modulator-dependent term is more than
dominates the jitter amplification factor. This is generally one thousand times higher than the signal-dependent term.
the case with single-bit quantization where E{(Dqn)2} In other words, jitter sensitivity in this modulator is
dominates due to the much greater value of the quantiza- completely dominated by E{(Dqn)2}, making jitter-induced
tion step D. Let us consider for illustration purposes the noise power practically independent of the input signal.
Table 4
T
Values of F 0 , g0 T and p0 T for the CT SDMs in Fig. 9
CT SDM1 before diagonalization CT SDM1 after diagonalization
T
2 3 2 3
F0 0 0 #0:208 #0:328 0 0
6 7 6 0 0:664 # j0:438 0 7
4 1 1 #0:198 5 4 5
0 1 1:001 0 0 0:664 # j0:438
! " ! "
g0 T 0 0 1 #0:562 0:853 0:853
! " ! "
p0 T #1:208 2:744 #1:94 3:503 0:016 # j0:184 0:016 þ j0:184
CT SDM2 before diagonalization CT SDM2 after diagonalization
T
2 3 2 3
F0 0 0 #0:112 0:122 þ j0:39 0 0
6 7 6 7
4 1 1 #4:675e # 3 5 4 0 0:122 # j0:39 0 5
0 1 #0:423 0 0 #0:667
! " ! "
g0 T 0 0 1 0:81 0:81 0:959
! " ! "
p0 T #1:112 2:636 #3:064 1:476 þ j1:722e # 3 1:476 # j1:722e # 3 #5:69
CT SDM3 (1st stage) before diagonalization CT SDM3 (1st stage) after diagonalization
T # $ " #
F0 0 #0:705 #0:543 þ j0:64 0
1 #1:087 0 #0:543 # j0:64
T
! " ! "
g0 0 1 0:766 0:766
! " ! "
p0 T 0:295 #2:728 #1:781 # j1:813 #1:781 þ j1:813
Table 5
Simulated vs. theoretical predictions of E{(Dq(n)2)}
Modulator fi (MHz) A (V) Clock jitter (ps) Simulated (10#2 V2) Theory (10#2 V2)
CT SDM1 2.197 0.3 10 12.2 16

CT SDM1 8.79 0.3 10 12.1 16
CT SDM1 17.58 0.3 10 12.2 16
CT SDM1 8.79 0.1 10 11.2 16
CT SDM1 8.79 0.2 10 14.1 16
CT SDM1 8.79 0.3 20 12.2 16
CT SDM1 8.79 0.3 30 12.2 16
CT SDM2 2.197 0.3 10 1.21 1.2
CT SDM2 8.79 0.3 10 1.23 1.2
CT SDM2 17.58 0.3 10 1.50 1.2
CT SDM2 8.79 0.1 10 1.25 1.2
CT SDM2 8.79 0.2 10 1.22 1.2
CT SDM2 8.79 0.3 20 1.23 1.2
CT SDM2 8.79 0.3 30 1.23 1.2
First stage CT SDM3 2.197 0.3 10 0.81 0.87
-20
Magnitude (dB)
1.9 MHz input frequency
-40 19 MHz input frequency
-60
-80
0 10 20 30 40 50 60 70 80
0 -95 19 MHz 1.9 MHz
-100
-20
Magnitude (dB)
-105
-40
-110
-60
-80
-100
0 10 20 30 40 50 60 70 80
Frequency (MHz)
Fig. 10. Effect of jitter error on the output spectra of (a) CT SDM1 and (b) CT SDM2.
Under these conditions, the equations derived in this paper is negligible, the maximum resolution is calculated from
provide similar predictions to the expressions reported in (24) as
[3] for single-bit quantization, which is recalled here for !
comparison, fs
! SNRMAX ¼ 10 log
8p s2DT B2w
2
1 !
SNRjitter ¼ 10 log (28)
16Ms2DT B2w ¼ 10 log
M
, ð29Þ
4p2 s2DT B2w
and the analysis presented in [7]. This is illustrated in Fig. 8.
On one hand, the curves at the top right-hand side depict the where we have assumed that fi ¼ Bw. This is a limit valid
predictions made by the simplified expressions (24) and both for single-loop and cascade CT SDMs.7 This is also
(28), respectively, showing good agreement. On the other valid for any type of loop filter, since (29) is independent of
hand, the bottom curves depict the predictions made by the the particular loop filter.
previously shown Eq. (25) and by the analysis in [7], as well Note that exactly the same expression is obtained for DT
as the estimations made by simulations. The agreement is SDMs [17]. In these modulators, this limit is established by
quite good. Fig. 8 also shows that within the region where the input sampler. In CT SDMs it is introduced by the
the resolution is dominated by jitter the agreement between feedback DAC. In fact, (29) reveals a limit that applies to
simplified and complete SNR estimations is reasonable. any ADC, not only to those based on SD modulation, and
As the signal-dependent term becomes first significant that is that no converter, when clocked with an imperfect
and eventually dominant, previous analyses fail to produce signal, can perform better than an ideal sampler clocked
proper predictions. In the next section, it will be shown that with the same signal.
when the oversampling ratio is reduced and the number of In summary, the analysis in this paper provides a more
bits increased (as happens in broadband applications where detailed coverage of practical design choices with applica-
the combination of high input bandwidth and technology tion in broadband while at the same time serves as an
limitations imposes a low oversampling ratio) behavior in extension to previous studies, covering cases not included
terms of jitter sensitivity is not well described by previous in them.
approaches, while expressions derived in this study closely
match modulator performance. 7
In these cascade architectures, jitter-induced noise introduced in the
At the limit when the SNRjitter is fully dominated by the first stage is not affected by later stages since they process only
signal-dependent term and the modulator-dependent term quantization errors.
5. Validation and application to VDSL

56
Fig. 9 shows two CT SDMs used as illustrative case
studies in this section. Fig. 9(a) is a third-order single-loop 54
and Fig. 9(b) is a cascade 2-1 topology. Both architectures
employ feed-forward stabilization and incorporate a feed- 52
Peak SNR (dB)

back coefficient kr to move one of the poles to an optimum
position. In this section the results of the analysis in this 50
paper are compared to those obtained through detailed
time-domain behavioral simulation using SIMSIDES, a 48
SIMULINK-based simulator for SDMs [18]. Calculated, fin=1.9 MHz
46 Calculated, fin=10.5 MHz
The modulators in Fig. 9 have been synthesized Calculated, fin=19 MHz
following the methodology described in [12] for VDSL Simulation, fin=1.9 MHz
44 Simulation, fin=10.5 MHz
application with Bw ¼ 20 MHz. Three different cases are Simulation, fin=19 MHz
considered: [7], no input signal dependency
42
0 5 10 15 20 25 30
" CT SDM1: Fig. 9(a) with fs ¼ 400 MHz and B ¼ 2; Clock jitter standard deviation !"T (ps)
" CT SDM2: Fig. 9(a) with fs ¼ 160 MHz and B ¼ 5;
" CT SDM3: Fig. 9(b) with fs ¼ 160 MHz and B1 ¼
B2 ¼ 5, 61
60
where B1 and B2 are the number of bits in the quantizer in
the first and second stage of Fig. 9(b), respectively. Table 3 59
shows the values of the loop-filter coefficients, ki, and the
Peak SNR (dB)
58
position of the poles for the three cases mentioned above.
An optimum distribution of NTF zeros has been adopted 57
as described in [19]. Table 4 shows the values of
T 56
F 0 ; g0 T and p0 T also for these three cases. Calculated, fin=1.9 MHz
Table 5 compares the values of E{(Dqn)2} extracted from 55
Calculated, fin=10.5 MHz
Calculated, fin=19 MHz
simulations with those calculated using (19). Note that the Simulation, fin=1.9 MHz
Simulation, fin=10 MHz
simulated E{(Dqn)2} are independent of the input signal 54
and clock jitter, as predicted by (19). Fig. 10 shows several 53
[7], no input signal dependency
simulated output spectra of cases CT SDM1 (Fig. 9(a)) and

0 5 10 15 20 25 30
CT SDM2 (Fig. 9(b)) corresponding to different values of fi
Clock jitter standard deviation !"T (ps)
and sDT ¼ 25 ps. Note that in Fig. 10(a), the in-band noise
power does not depend on fi, in agreement with what is
predicted by Hernandez et al. [7]. However, as B increases 70
from 2 to 5, the modulator-dependent term in (22) 68
decreases and hence, the in-band noise becomes dominated
by the signal-dependent term as illustrated in Fig. 10(b). 66
This effect is better shown in Fig. 11, where the SNR-
64
Peak SNR (dB)
peak of the modulators in Fig. 9 is plotted vs. sDT for

several values of fi, showing simulation results and 62
theoretical predictions. For comparison purposes, predic-
60
tions given by Hernandez et al. [7] are also included. Note
that simulated and theoretical data match very well when 58 Calculated, fin=4 MHz
Calculated, fin=12 MHz
the combined effect of signal- and modulator-dependent Calculated, fin=19 MHz
56
jitter noise is taken into account. Simulation, fin=4 MHz
Note that in Fig. 11(a), due to the fact that fs and D are 54 Simulation, fin=19 MHz
large, the jitter amplification factor is dominated by the [7], no input signal dependency
modulator-dependent term, meaning that the SNR is 52
0 5 10 15 20 25 30
practically independent of the input signal. However, when
Clock jitter standard deviation !"T (ps)
B is increased and fs is decreased in order to improve jitter
insensitivity, the resolution improves for low input Fig. 11. SNR vs. sDT for different values of fi: (a) CT SDM1, (b) CT
frequencies, whereas for higher input frequencies this SDM2, (c) CT SDM3.
improvement is considerably reduced as shown in
Fig. 11(b). The same behavior is obtained in Fig. 11(c),
where jitter sensitivity is dominated by the first stage. It is e(n)

important to note that this dependence on input signal,
even though it might not be important in low bandwidth x(t) + y(n)
G(s)
applications, can become dominant in broadband commu-
nications where the input frequency is high and designers !T(n)
resort to multi-bit implementations with low oversampling Ts
ratios. + DAC
z-1
6. Conclusions
Fig. 12. Clock jitter model used in the mathematical derivations.
The effect of clock jitter error on multi-bit CT SDMs
with NRZ DAC has been analyzed. Based on the use of
state-space formulation, easy-to-compute closed-form ex-
pressions have been derived for the in-band noise power assumption G(s) can be replaced by G(z) which is the DT
and signal-to-noise ratio. This study extends the applica- equivalent calculated through the impulse-invariant trans-
tion range of the derived expressions as compared with formation [16]. The equation governing the modulator is
! "
previous approaches. It provides mathematical tools to DTðzÞ %1
separate the two components of jitter-induced noise. It xðzÞ þ $ ð1 % z ÞyðzÞ % yðzÞ
Ts
provides means that allow the designer to quantify how the
&GðzÞ þ eðzÞ ¼ yðzÞ. ð30Þ
modulator is going to be affected by jitter and facilitates
the design optimization process. This optimization can be Taking into account that y(z)(x(z)+q(z), the following
performed using (20) as a figure of merit in an iterative equation is easily derived:
method. Furthermore, for low oversampling ratios, this ! "
DTðzÞ %1 GðzÞ
study makes it possible to find out an optimum solution in qðzÞ % $ ð1 % z ÞqðzÞ
Ts 1 þ GðzÞ
terms of jitter sensitivity by using (24), where all modulator # $
parameters, including modulator filter, sampling frequency ðDTðzÞ=T s Þ $ ð1 % z%1 ÞxðzÞ GðzÞ % xðzÞ
¼
and quantizer number of bits can be used to find a 1 þ GðzÞ
minimum in the in-band noise power. Predictions have eðzÞ
been confirmed by time-domain simulations of several CT þ . ð31Þ
1 þ GðzÞ
SDMs for VDSL application.
In order to determine E{[q(n)%q(n%1)]2}, the equation in
(31) is multiplied by z%1 and subtracted from itself, giving:
Acknowledgments ! "
DTðzÞ ð1 % z%1 ÞGðzÞ
ð1 % z%1 ÞqðzÞ % $ ð1 % z%1 ÞqðzÞ
This work has been supported by the Spanish Ministry Ts 1 þ GðzÞ
# $
of Science and Education (with support from the European %1 %1
ðDTðzÞ=T s Þ $ ð1 % z ÞxðzÞ ð1 % z ÞGðzÞ
Regional Development Fund) under contract TEC2004- ¼
1 þ GðzÞ
01752/MIC.
ð1 % z ÞxðzÞ ð1 % z%1 ÞeðzÞ
%1
% þ . ð32Þ
1 þ GðzÞ 1 þ GðzÞ
Appendix A. Calculation of E{Dq(n)2}
The expected value of both sides is calculated, starting
It is proved herein that a good approximation of with the term to the left of the equal sign:
E{Dq(n)2} can be calculated taking into account only &% ! ! "
DTðzÞ
quantization error. This approximation simplifies enor- E Z %1 ð1 % z%1 ÞqðzÞ % $ ð1 % z%1 ÞqðzÞ
Ts
mously any further analysis but needs justification since it "' 2
)
is not necessarily applicable to every feedback system. It is ð1 % z%1 ÞGðzÞ
& ¼ Ef½qðnÞ % qðn % 1Þ*2 g
shown that in the particular case of SD converters, it is a 1 þ GðzÞ
valid approximation and leads to accurate predictions. (% !% ' "'2 )
%1
According to (2), the effect of clock jitter can be modeled as DTðzÞ ð1 % z ÞGðzÞ
þE Z %1 $ ð1 % z%1 ÞqðzÞ
shown in Fig. 12. Ts 1 þ GðzÞ
For simplicity,8 the input to the modulator x(t) is & !! "
DTðzÞ
approximated by an ideally sampled version x(n). With this % 2E ½qðnÞ % qðn % 1Þ*Z %1 $ ð1 % z%1 ÞqðzÞ
Ts
%1
"(
8
The exact continuous-time signal can be used together with inverse ð1 % z ÞGðzÞ
& . ð33Þ
Laplace and Z transforms making the analysis much more complicated. 1 þ GðzÞ
Since it is demonstrated above that input signal has no significant effect on
the calculation of E[q(n)%q(n%1)]2, the exact analysis does not contribute Since DT(n) is a random signal with zero mean, it can
anything and the approximation makes the analysis much simpler. be proven that the last term in (33) is zero. Considering
that where the fact that DT(n) is a random signal with zero
! ! mean has been used to drop one of arising terms. Using the
! GðzÞ ! ! !
! ! ! ! (34) approximation in (34), an upper bound for the second-last
!1 þ GðzÞ! ¼ STF ðzÞp1
term in (38) can be evaluated:
an upper bound for the second-last term in (33) can be (" $ %#2 )
%1
estimated: DTðnÞ %1 ð1 % z ÞGðzÞ
E ½xðnÞ % xðn % 1Þ( & Z
(" $" # %#2 ) Ts 1 þ GðzÞ
DTðzÞ ð1 % z %1
ÞGðzÞ (" #2 )
E Z %1 & ð1 % z%1 ÞqðzÞ DTðnÞ
Ts 1 þ GðzÞ pE %1
½xðnÞ % xðn % 1Þ( & Z ½1 % z ( %1
(" $" # %#2 ) Ts
DTðzÞ &"
pE Z %1 %1
& ð1 % z ÞqðzÞ ð1 % z Þ %1 DTðnÞ
Ts ¼E ½xðnÞ % xðn % 1Þ(
&" Ts
DTðnÞ #2 )
¼E ½qðnÞ % qðn % 1Þ( DTðn % 1Þ
Ts % ½xðn % 1Þ % xðn % 2Þ(
#2 ) Ts
DTðn % 1Þ ($ % )
% ½qðn % 1Þ % qðn % 2Þ( DTðnÞ 2
Ts ¼ 2E Ef½xðnÞ % xðn % 1Þ(2 g ffi s2DT A2 o2in ,
(" # ) Ts
DTðnÞ 2 ð39Þ
¼ 2E Ef½qðnÞ % qðn % 1Þ(2 g
Ts
where the same approximation as in (8) has been used.
5Ef½qðnÞ % qðn % 1Þ(2 g. ð35Þ The last part of this demonstration consists of proving
that the last term in (39) satisfies the relation:
Therefore, the term to the left of the equal sign in (32)
(" $ % #2 )
can be approximated by ð1 % z %1
ÞeðzÞ
&"$ % s2DT A2 o2in 5E Z %1 . (40)
DTðzÞ 1 þ GðzÞ
EZ %1 ð1 % z%1 ÞqðzÞ % & ð1 % z%1 ÞqðzÞ
Ts
%1
%#2 ) The proof starts with the definition of NTF(z):
ð1 % z ÞGðzÞ ("
) ffi Ef½qðnÞ % qðn % 1Þ(2 g. ð36Þ $ %1
% #2 )
1 þ GðzÞ %1 ð1 % z ÞeðzÞ
E Z
1 þ GðzÞ
The term on the right-hand side of (32) can be Z
approximated following a similar procedure. First, taking X 2FS 1 p !! !2 ! !2
¼ 2p
ð1 % e%jo Þ! !N TF ðe%jo Þ! do
into account that x(z) is restricted to the signal band where B
12ð2 % 1Þ 0
G(z)-N, the following approximation can be applied: Z
X 2FS 1 p ! ! ! !
!ð1 % e%jo Þ!2 !N TF ðe%jo Þ!2 do.ð41Þ
4 2p
1 % z%1 B
12ð2 % 1Þ 2pBw =f s
xðzÞ ffi 0 (37)
1 þ GðzÞ
Using the fact that the out of band gain of NTF(e%jo) is
leading to the following approximation: greater than one, a lower bound for (41) can be estimated,
80 2hDTðzÞ i (" $ % #2 )
< & ð1 % z %1
ÞxðzÞ ð1 % z%1 ÞGðzÞ %1
@ %1 4 T s %1 ð1 % z ÞeðzÞ
E Z E Z
: 1 þ GðzÞ 1 þ GðzÞ
Z
%#2 ) 2
X FS 1 p ! ! X 2FS
ð1 % z%1 ÞxðzÞ ð1 % z%1 ÞeðzÞ 4 !ð1 % e%jo Þ!2 do ffi
% þ 12ð2B % 1Þ2 f s p 2pBw =f s 6ð2B % 1Þ2
1 þ GðzÞ 1 þ GðzÞ
80 2hDTðzÞ i 2A2
< & ð1 % z %1
ÞxðzÞ ð1 % z%1 ÞGðzÞ X ð42Þ
T s 3ð2B % 1Þ2
ffi E @Z%1 4
: 1 þ GðzÞ
using the fact that the integral in (42) is ffi2p for MX4 and
%#2 )
ð1 % z%1 ÞeðzÞ that the maximum input amplitude is ApXFS/2. Now the
þ following relation can be easily shown to hold even for
1 þ GðzÞ
(" extreme values of clock jitter and input signal,
$ %1
%#2 )
DTðnÞ %1 ð1 % z ÞGðzÞ
¼E ½xðnÞ % xðn % 1Þ( & Z 2A2
Ts 1 þ GðzÞ B 2
bs2DT o2i A2 , (43)
(" $ %# ) 3ð2 % 1Þ
2
ð1 % z%1 ÞeðzÞ
þE Z %1 , ð38Þ B ¼ 5, sDT ¼ 30 ps and fi ¼ 30 MHz, the first term (43) is
1 þ GðzÞ
more than 20 times the second term.
Using Eqs. (39), (42) and (43) in (38), the following EfqðnÞqðn $ 1Þg
conclusion can be drawn:
¼ EfeðnÞ2 g
! " !
EfðDqn Þ2 g ffi E ðz$1 ½1 $ z$1 &N TF ðzÞeðzÞÞ2 T
X
n$1
T n$k$1 T n$2$k
Z p * g0 ( p0 þ g0 ( F 0 ( p0 ( g0 ( F 0 ( p0 .
X 2FS # #
¼ #ð1 $ e$jo ÞN TF ðe$jo Þ#2 do. ð44Þ
k¼0
B
12pð2 $ 1Þ 0 2 ð48Þ
2
Note that E{q(n) } and E{q(n)q(n$1)} depend on the
time instant, n. However, it is demonstrated next that for a
Appendix B. Mathematical expectation of [q(n)]2 in stable
stable modulator, i.e., a system with a NTF having all poles
systems
inside the unit circle, the value of E{q(n)2} is independent
of time, provided that a reasonable number of samples is
In order to derive an expression for E{(Dqn)2}, it will be
used to derive (48). In order to demonstrate this, let us
assumed in (15) that the initial state, vð0Þ0 , is zero. A non-
consider the state-space representation of NTF(z) shown in
zero initial state would lead to expressions of the form
Fig. 4, which can be described by the finite difference
E{constant ( e(n)} which are zero by definition. With this,
equations in (13).
E{(Dqn)2} and E{q(n)q(n$1)} can be written, respectively,
After diagonalization, the equation system in (13) can be
as
expressed as
EfqðnÞ2 g vðn þ 1Þ ¼ F̄ ( vðnÞ þ p̄ ( eðnÞ,
( !
X
n$1
¼E g0 T ( F 0
n$k$1
( p0 ( eðkÞ þ eðnÞ qðnÞ ¼ ḡT ( vðnÞ þ eðnÞ, ð49Þ
k¼0
!) where vðnÞ is the state vector of the diagonalized system
X
n$1
n$1$j and F̄ ; p̄ and ḡ are, respectively, given by
* g0 T ( F 0 ( p0 ( eðjÞ þ eðnÞ
k¼0 2 3
l1 0 ... 0
n$1 X
X n$1
n$k$1 n$1$j 6 7
¼ g0 T ( F 0 ( p0 ( g0 T ( F 0 ( p0 ( EfeðkÞeðjÞg 6 0 l2 . . . 0 7
$1 6 7
k¼0 j¼0 F̄ ¼ T ( F 0 ( T̄ ¼ 6 7,
6... ... ... ...7
X
n$1 4 5
n$1$k
þ g0 T ( F 0 ( p0 ( EfeðkÞeðnÞg 0 0 . . . lL
k¼0 2 3
p1
X
n$1
þ g0 T ( F 0
n$1$k
( p0 ( EfeðjÞeðnÞg þ EfeðnÞ2 g, ð45Þ 6 7
6 p2 7
6 7
j¼0 p̄ ¼ T $1 ( p0 ¼ 6 7,
6...7
4 5
EfqðnÞ $ qðn $ 1Þg pL
( ! h i
Xn$1
n$1$k ḡT ¼ g0 T ( T̄ ¼ g1 g2 ... gL , ð50Þ
T
¼E g0 ( F 0 ( p0 ( eðkÞ þ eðnÞ
j¼0
!) where T̄ is the matrix formed by the eigenvectors of F̄ , lj
X
n$2
n$2$j
T
* g0 ( F 0 ( p0 ( eðjÞ þ eðn $ 1Þ are the eigenvalues and L is the order of the modulator.
j¼0 h Once F 0 has been i2 diagonalized, the matrix product
n$1$k
n$1 X
X n$2
n$1$k n$2$j
g0 T ( F 0 ( p0 can be written as
¼ g0 T ( F 0 ( p0 ( g0 T ( F 0 ( p0 ( EfeðkÞeðjÞg h i2 h i2
n$1$k n$1$k
k¼0 j¼0 g0 T ( F 0 ( p0 ¼ ḡT ( T $1 ( F 0 ( T̄ ( p̄
X
n$1
&
þ g0 T ( F 0
n$1$k
( p0 ( EfeðkÞeðn $ 1Þg $ %n$k$1 '2
T $1
k¼0
¼ ḡ ( T ( F 0 ( T̄ ( p̄
X
n$2
n$2$j h i2 X
L X
L
þ g0 T ( F 0 ( p0 ( EfeðjÞeðnÞg ¼ ḡT ( F̄
n$1$k
( p̄ gi pi gj pj lin$1$k ln$1$k . ð51Þ
j
j¼0
i¼1 j¼1
þ EfeðnÞeðn $ 1Þg. ð46Þ
Taking into account (51), the summation in (47) can now
Considering that E{e(k)e(j)} ¼ 0 for k6¼j, (45) and (46) be expressed as
are, respectively, simplified into: n$1 h
X i2 X
L X
L X
n$1
n$1$k
! g0 T ( F 0 ( p0 ¼ gi pi gj pj lin$1$k ln$1$k .
n$1 h
X i2 j
2 2 T n$1$k k¼0 i¼1 j¼1 k¼0
EfqðnÞ g ¼ EfeðnÞ g 1 þ g0 ( F 0 ( p0 , (47)
k¼0 (52)
Let us define the partial sums as Finally, from (16), (59) and (60), the following relation is
obtained:
X
n"1
S nij ¼ ln"1"k
i ljn"1"k . (53) EfðDqn Þ2 g
k¼0
¼ 2EfeðnÞ2 g
!
Multiplying (53) by l"1 "1
i lj and subtracting from the X
L X
L l"1 "1 "1
k " lk l j
T
original, the following expression is obtained: & 1 " ḡ % p̄ þ gk pk gj p j . ð61Þ
k¼1 j¼1 1 " l"1 "1
k lj
S nij " l"1 "1 n"1 n"1

i lj S nij ¼ li lj " l"1 "1
i lj
ln"1
i ln"1
j " l"1 "1
i lj
) S ijn ¼ . ð54Þ References
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i lj
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If the system is stable, |li|o1, and hence Sijn has a finite ulators for High-Speed A/D Conversion, Kluwer Academic Publish-
limit given by ers, Dordrecht, 2000.
[2] L. Breems, J.H. Huijsing, Continuous-Time Sigma-Delta Modulation
l"1 "1
i lj
for A/D Conversion in Radio Receivers, Kluwer Academic Publish-
lim S ijn ¼ " . (55) ers, Dordrecht, 2001.
n!1 1 " l"1 "1
i lj [3] E.J. van der Zwan, A 0.2-mW CMOS SD modulator for speech
coding with 80 dB dynamic range, IEEE J. Solid-State Circuits 31
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modulators with delayed return-to-zero feedback. In: Proceedings
last summation in (52) can be expressed as of the 1998 IEEE International Conference on Electronics, Circuits
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n"1 l"1 "1
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[5] H. Tao, L. Toth, J.M. Khoury, Analysis of timing jitter in bandpass
ln"1"k
i ljn"1"k ¼ " . (56) sigma-delta modulators, IEEE Trans. Circuits Syst.-II 46 (1999)
k¼0 1 " l"1 "1
i lj 991–1001.
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Syst.-II 50 (2003) 31–37.
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! Modelling and optimization of low-pass continuous-time sigma-delta
2 2
X
L X
L l"1 "1
k lj
modulators for clock jitter noise reduction, in: Proceedings of the
EfqðnÞ g ¼ EfeðnÞ g 1 " gk pk gj pj 2004 International Symposium on Circuits and Systems, vol. 1,
k¼1 j¼1 1 " l"1 "1
k lj pp. 1072–1075.
[8] S. Yan, E. Sánchez-Sinencio, A continuous-time SD modulator with
(57) 88-dB dynamic range and 1.1-MHz signal bandwidth, IEEE J. Solid-
State Circuits 39 (2004) 75–86.
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Following a similar procedure, it can be proved that A 700/900 mW/channel CMOS dual analog front-end IC for VDSL
E{q(n)q(n"1)} is given by with integrated 11.5/14.5 dBm line drivers, in: Proceedings of the 2003
IEEE International Solid-State Circuits Conference, 2003,
pp. 416–417.
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! Pötscher, M. Clara, A 70-mW 300-MHz CMOS continuous-time SD
L X
X L
l"1
2
¼ EfeðnÞ g ḡ % p̄ " T
gk pk gj pj k
. ð58Þ ADC with 15-MHz bandwidth and 11 bits of resolution, IEEE J.
k¼1 j¼1 1 " l"1 "1
k lj
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[11] R. Scherier, B. Zhang, DS modulators employing continuous-time
circuitry, IEEE Trans. Circuits Syst.-II 43 (1996) 324–332.
With this, expressions in (47) and (48) can be re-written [12] R. Tortosa, J.M. de la Rosa, F.V. Fernández, A. Rodrı́guez-Vázquez,
as A new high-level synthesis methodology of cascaded continuous-time
SD modulators, IEEE Trans. Circuits Syst.-II (2006) 739–743.
! [13] R. Tortosa, A. Aceituno, J.M. de la Rosa, A. Rodrı́guez-Vázquez,
X
L X
L l"1 "1
k lj F.V. Fernández, A 12-bit@40MS/s Gm-C cascade 3-2 continuous-
EfqðnÞ2 g ¼ EfeðnÞ2 g 1 " gk pk gj pj ,
k¼1 j¼1 1 " l"1 "1
k lj
time sigma-delta modulator, in: Proceedings of the 2007 International
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(59) pp. 1–4.
[14] L. Risbo, SD Modulators-stability and design optimization, Ph.D.
Dissertation, Technical University of Denmark, 1994.
EfqðnÞqðn " 1Þg [15] J.G. Proakis, D.G. Manolakis, Digital Signal Processing. Principles,
! Algorithms and Applications, Prentice-Hall, Englewood Cliffs, NJ,
X
L X
L
l"1 1998.
2 T k
¼ EfeðnÞ g ḡ % p̄ " g k pk gj pj . ð60Þ [16] O. Shoaei, Continuous-time delta-sigma A/D converters for high
k¼1 j¼1 1 " l"1 "1
k lj speed applications, Ph.D. Dissertation, Carleton University, 1995.
[17] B.E. Boser, B.A. Wooley, The design of sigma-delta modulation analog- LINK-based time-domain behavioral models, IEEE Trans. Circuits
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[18] J. Ruiz-Amaya, et al., High-level synthesis of switched-capacitor, [19] R. Schreier, An empirical study of high-order single-bit delta-sigma
switched-current and continuous-time SD modulators using SIMU- modulators, IEEE Trans. Circuits Syst.-II 40 (1993).
!
PUBLICACIÓN 3
Título de la Publicación: Systematic Design of High-Resolution High-Frequency Cascade

Continuous-Time Sigma-Delta Modulators
Autores: Ramón Tortosa, Rafael Castro-López, José M. de la Rosa, Elisenda Roca, Angel
Rodríguez-Vázquez and Francisco V. Fernández
Nombre de la revista: ETRI Journal
Editorial: Electronics Telecomunications Research Institute
ISSN: 1225-6463
R. Tortosa, R. Castro-López, J.M. de la Rosa, E. Roca, A. Rodríguez-Vázquez and F.V.
Fernández: “Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time
Sigma-Delta Modulators,” ETRI Journal, vol.30, no. 4, pp. 535-545, August 2008.
RESUMEN
Este artículo presenta una metodología “top-down/bottom-up” para sistematizar el diseño e

implementación de moduladores ΣΔ en cascada realizados mediante la técnica de circuito de
tiempo continuo. Las características más destacadas de la metodología propuesta son las
siguientes:
a) Modelado de comportamiento flexibles, que pueden ser aplicados en distintas etapas del
proceso de síntesis “top-down”.
b) Síntesis directa en el dominio del tiempo continuo para minimizar la complejidad de la

circuitería y la sensibilidad a los errores de tolerancia de sus principales elementos.
c) Exploración arquitectural basada en la optimización y el conocimiento.
d) Uso de frentes Pareto-óptimos para reducir las iteraciones de rediseño.
La aplicabilidad de esta metodología se ilustra y valida mediante el diseño de un modulador ΣΔ

en cascada de tiempo continuo en una tecnología CMOS de 130nm, con una tensión de
alimentación de 1.2V, con resolución efectiva de 12 bits y 20 MHz de ancho de banda.
!
Systematic Design of High-Resolution High-Frequency

Cascade Continuous-Time Sigma-Delta Modulators
Ramón Tortosa, Rafael Castro-López, J.M. de la Rosa, Elisenda Roca,

Ángel Rodríguez-Vázquez, and F.V. Fernández
This paper introduces a systematic top-down and I. Introduction

bottom-up design methodology to assist the designer in the
implementation of continuous-time (CT) cascade sigma- The ever shrinking minimum feature size of CMOS
delta ( modulators. The salient features of this technologies has triggered a revolution in integrated designs,
methodology are (a) flexible behavioral modeling for from application-specific integrated circuits to entire systems
optimum accuracy-efficiency trade-offs at different stages on a single chip. Notwithstanding, a critical design productivity
of the top-down synthesis process, (b) direct synthesis in lag has been reported [1]. With a productivity growth rate of
the continuous-time domain for minimum circuit 21%, compared to a 58% complexity growth rate, design cost
complexity and sensitivity, (c) mixed knowledge-based and is increasing rapidly. Taking into account the ever demanding
optimization-based architectural exploration and time-to-market pressures, this picture is clearly worrisome. For
specification transmission for enhanced circuit analog and/or mixed-signal design the situation is even worse
performance, and (d) use of Pareto-optimal fronts of for many reasons, the most significant being the lack of
building blocks to reduce re-design iterations. The commercial computer-aided design tools and methodologies to
applicability of this methodology will be illustrated via the efficiently support the analog design.
design of a 12-bit 20 MHz CT modulator in a 1.2 V The design methodology described in this paper tries to
130 nm CMOS technology. reduce this design gap for a class of circuits, namely,
continuous-time (CT) cascade sigma-delta ( ) modulators
Keywords: modulators, mixed-signal interfaces for (conceptually shown in Fig. 1), although some of the
wireless/wireline communications, design automation. techniques and tools presented are applicable to other classes.
The choice of this circuit class has been driven by the demands
of new generations of high-speed wireless and wireline
communication terminals, which require broadband analog-to-
digital converters capable of digitizing 20 MHz wideband
signals with effective resolution over 12 bits and with
Manuscript received Aug. 1, 2007; revised June 16, 2008; accepted June 27, 2008. minimum power consumption. Although most reported
This work was supported by the Spanish Ministry of Science and Education (with support
from the European Regional Development Fund) under Contracts TEC2004-01752/MIC and
modulators have been implemented using discrete-time (DT)
TEC2007-67247, and by Consejería de Innovación, Ciencia y Empresa, Junta de Andalucía circuits, the increasing demand for broadband data
under Contract TIC-2532. communication systems has motivated the use of CT
Ramón Tortosa (email: castro@imse.cnm.es) was with CSIC-IMSE-CNM, Sevilla, Spain,
and is currently with Analog Devices, Ireland. techniques. In addition to showing an intrinsic anti-aliasing
Rafael Castro-López (phone: +34955056666), email: castro@imse.cnm.es), J.M. de la Rosa filtering, CT modulators can potentially provide faster
(email: jrosa@imse.cnm.es), Elisenda Roca (email: eli@imse.cnm.es), Ángel Rodríguez-
operation with lower power consumption than their DT
Vázquez (email: angel@imse.cnm.es), and F.V. Fernández (email: pacov@imse.cnm.es) are
with CSIC-IMSE-CNM and University of Sevilla, Spain. counterparts [2], [3].
ETRI Journal, Volume 30, Number 4, August 2008 Ramón Tortosa et al. 535
E1(z) b) A High-level topological synthesis method directly in the

Cancellation logic continuous-time domain (described in section IV)
x(s) y1(z) c) Efficient behavioral simulator with variable levels of
CT M1 CL1
modeling accuracy for architectural synthesis, specification
E2(z) transmission, and hierarchical verification (described in
section V)
y2(z)
CT M2 CL2 yo(z) d) Global and local optimization core for topology
exploration and specification transmission (described in
section II)
Em(z)
e) Specification transmission driven by bottom-up
ym(z)
information flow in the form of Pareto-optimal fronts
CT Mm CLm (described in section VI)
The design of a 12-bit 20 MHz CT modulator in a 1.2 V

E2(z) 130 nm CMOS technology is used in section VII as an
illustrative example of each step.
x2(s) F(s) y2(z)
y2(s)
II. Systematic Design Methodology
DAC
To next stage Synthesis of high-speed CT modulators is a complex task

which requires systematic design methods and customized
Fig. 1. Conceptual block diagram of a cascade CT modulator. tools. The objective of the synthesis process is to design a CT
modulator able to meet the performance specifications,
In spite of their advantages, CT modulators are more with minimum power consumption and minimum occupation
sensitive than DT modulators to some circuit errors, namely, of silicon area.
clock jitter, excess loop delay, and technology parameter The synthesis procedure is schematically shown in Fig. 2. In
variations [2]. The latter are especially critical for the the three main stages of this design flow, design space
realization of cascaded architectures. This explains the use of exploration and specification transmission rely on the
single-loop topologies in most reported silicon prototypes [4]- interaction of some kind of performance evaluator (such as
[6]. Although single-loop CT topologies have potentially lower equations and behavioral simulation with models at some level
sensitivity to technological process variations than cascade CT of abstraction) with an optimizer. The cornerstones of this
topologies, the possibility of avoiding stability problems in the process are an adequate formulation of a cost function, which
latter make them especially appealing for high-resolution, high quantifies the degree of compliance of the design with the
signal bandwidth operation. targeted performance; a fast yet accurate method to evaluate
Most developments in systematic design methods and tools the cost function; and an efficient technique to generate the
have focused on DT modulators [7]-[13], probably due to next movement over the design space.
their widespread use, but also due to their easier design. First, The optimization core used has two steps. In the first step,
developments of methods and tools for CT modulators global optimization techniques are applied, whereas
have addressed specific problems, such as efficient deterministic techniques are applied for local optimization in
behavioral simulation [12], [14], [15] or topological synthesis the second step [18]. Our experience is that adaptive simulated
by discrete-time to continuous-time transformation [16], annealing algorithms are more efficient for global optimization
eventually with coefficient scaling using simulation of ideal addressing some specific design constraints, whereas other
modulators [17]. popular global optimization algorithms, such as evolutionary
This paper introduces a complete design methodology to algorithms, are more powerful to explore trade-offs between
assist the designer in the implementation of CT cascade performance specifications.
modulators. The main components of this systematic The optimization problem is mathematically stated as
methodology, introduced in section II, are the following: minimize yoi (x), 1 i P
subject to yrj (x) Yrj or yrj (x) Yrj , 1 j R,
a) Performance modeling of dominant error sources at the
modulator level (described in section III) where yoi(x) stands for the value of the i-th design objective
536 Ramón Tortosa et al. ETRI Journal, Volume 30, Number 4, August 2008
Goal: SNR
1 Parameters: L, B, OSR
Architectural Architectural exploration

synthesis
Optimization
core
Topological synthesis
Goal: define topology using
the direct synthesis method 2
Behavioral Optimization Sub-block Behavioral

High-level sizing simulation core POFs verification
Goal: SNR 3
Parameters: non-idealities of
blocks (see table 1)
Circuit-level Electrical Full electrical

Optimization
sizing simulation simulation
core
Goal: address building block performances

Parameters: device sizes and values
Fig. 2. Synthesis procedure.
(that is, to minimize power consumption); yrj(x) is the value of and the technology process information. The methodology starts
the j-th design constraint (that is, an SNR larger than 70 dB); Yrj by an architectural exploration, which basically tries to obtain
is the targeted value of such design specification; and x is the candidate architectures, defined by the order of the modulator L,
vector of design variables. Design objectives, constraints, and the number of bits of the quantizer(s) B, and the oversampling
variables depend on the optimization task at hand. For instance, ratio M, which allows a certain SNR specification to be obtained.
block non-idealities (such as amplifier gain) are design This architectural exploration is performed by using analytical
variables for high-level sizing, but they are design constraints expressions that model the dominant error sources limiting the
for circuit-level sizing. It is important to highlight the difference achievable SNR, in combination with the optimization core
between a constraint and a design objective. Constraints define previously outlined. The modeling of these error sources will be
the set of valid designs (also called the feasible design space), discussed in section III. The output of this architectural
whereas design objectives, such as power consumption or area exploration is a set of candidate architectures that can potentially
occupation, characterize the optimality of the design and show meet the modulator performance specifications.
the trade-off between valid solutions. The sizing engine carries The following step is the topological synthesis, that is, the
out the optimization by using a single cost function. For those definition of the cascade architecture, the intra- and inter-stage
points of the design space that do not satisfy the design loop filter transfer functions, and the cancellation logic
constraints, the cost function is defined as functions. A direct synthesis method in the CT domain is used
here instead of the more conventional DT to CT transformation
( x) max w j log( yrj / Yrj ) , of an equivalent DT topology. The direct topological synthesis
method is described in section IV.
where wj is the weight associated to the j-th constraint. For The input to the high-level sizing stage is the structural
those points of the feasible design space, the cost function is description of the topology being synthesized. The subsequent
defined as automated sizing process uses the behavioral simulator (see the
( x) ( yoi ) wi log( yoi ) , non-idealities considered in section V) together with global
i
optimization procedures to find out the maximum values of
where wi is the weight associated with the i-th design non-idealities of the different building blocks that can be
objective. tolerated while still meeting the modulator performance
The inputs to the architectural synthesis stage (see Fig. 2) are specifications. At this level, power consumption estimates are
required performance specifications of the CT modulator much more detailed as relationships with each building block
specifications can be established [7]. The modulator Here, XFS is the full-scale of the quantizer, B is the number of
performance with the transmitted building block specifications bits of the quantizer, fs is the sampling frequency, NTF(.) is the
is then verified under all operating conditions (process, noise transfer function, and BW is the signal bandwidth.
temperature, and supply variations) by using the behavioral However, in practice, the error power contains terms due to
simulator (section V). If this verification shows that some quantization error power enlargement, digital-to-analog
performance specification degrades beyond certain limits, the converter (DAC) non-linearities, capacitor mismatching,
high-level synthesis and/or the architectural synthesis are thermal noise, clock jitter, finite amplifier gain, incomplete
performed again under harder constraints. amplifier settling, and so on. Therefore, the in-band error
The last step of the synthesis procedure is the sizing of the power becomes
building blocks. The inputs to the circuit-level sizing stage are the
performance requirements for each building block (for instance, P Pq Pq P thermal P jitter P DAC P settling ... (3)
DC gain and bandwidth of amplifiers, or hysteresis and offset for
comparators). This sizing is performed by combining an Unlike other types of modulators, a dominant error
electrical simulator with the global optimization procedure source in high-speed CT modulators is the error power due to
previously outlined [18]. The implementation of the optimization clock jitter. For this reason, closed-form modeling of the
core is flexible enough to incorporate valuable design knowledge influence of jitter is of paramount importance. The error power
of each building block. At the optimization level, design due to clock jitter in CT modulators with non-return-to-zero
knowledge brings knowledge of the feasibility space. This limits (NRZ) DACs can be expressed as in [19] as
the exploration space and makes the synthesis process more
efficient, thereby enhancing the optimization results. A2 i2 2
X FS fs
P jitter Bw ( T )2 B
g , p, , L , (4)
With all blocks sized, a final verification of the complete 2 fs 6(2 1) 2
modulator at the electrical level at a limited number of
operating conditions is performed, namely, at the nominal point where A and i are the amplitude and frequency of the input
and a few critical process corners. This verification is signal, and (g p L is a function arising from the
complemented by a more exhaustive verification (all process, state-space representation of the noise transfer function of the
temperature, and supply variations) at the behavioral level with modulator and depends on the modulator order. It can be seen
information extracted at the electrical level. Performance that it has two terms. The first term depends on the modulator
degradations beyond tolerable margins induce redesign input and decreases with the sampling frequency, and the other
iterations at the circuit and/or modulator levels. depends on the modulator architecture and increases with
sampling frequency.
III. High-Level Performance Modeling and Architectural For illustration’s sake, Fig. 3 represents the two terms in
Exploration brackets in (4) for a 5-bit third-order modulator with a 20 MHz
input frequency as a function of the sampling frequency. Notice
As shown in section II, design space exploration and that there is a frequency range dominated by the signal-
specification transmission rely on the iterative interaction dependent term and another range dominated by the
between a global optimizer and a fast performance evaluator. modulator-dependent term. Therefore, there is an optimum
At a high level of abstraction, modulator performance is sampling frequency which minimizes the in-band jitter noise
modeled by a set of closed-form equations, which are relatively power and, hence, maximizes the SNR.
inaccurate but carry essential information on the design The use of the dominant error power terms in (3) (shown in
parameters dominating the system behavior. The signal to (2) and (4)) in combination with the optimization core allows
noise ratio of a modulator is given by candidate architectures to be extracted (each represented by a
A2 / 2 triad of values of order, number of bits, and oversampling ratio
SNR , (1) {L, B, M}) with better performance in terms of distribution of
P
the noise transfer function (NTF) zeroes and insensitivity to
where A represents the magnitude of the input signal, and P clock jitter.
represents the in-band error power. Ideally, the in-band error Usually, several triads are considered for later stages for
power only contains the quantization noise P q: several reasons. First, the modeling equations are very
2 approximate and, therefore, there is no guarantee that the
X FS BW 2
p q NTF ( f ) df . (2) selected architecture will continue to meet the performance
B
6 f s (2 1) 2 0
specifications when more accurate models containing the
×10
7 subsequent design steps.
2.5
0.22 j 0.55
0.22 j 0.55
2.0
0.79 IV. Topological Synthesis
1.5 0.66 j 0.39
p 0.66 j 0.39
Cascade CT modulator architectures are usually
V2 Hz
Jitter amplification factor

4.464 synthesized by first synthesizing a modulator with the same
1.0
0.74
performance specifications in the DT domain and then applying
Signal-dependent
0.5
term g 0.74 a DT to CT transformation that keeps the same digital
0.87 cancellation logic [16]. However, obtaining a functional CT
Modulator-dependent term
0
modulator from this transformation and keeping the cancellation
120 140 160 180 200 220 240 260 280 300
logic requires every state variable and DAC output to be
fs (MHz)
connected to the integrator input of subsequent stages as Fig. 4
Fig. 3. Jitter vs. sampling frequency for a third-order CT shows for a 2-1-1 architecture. This means a larger number of
modulator.
analog components (transconductors and amplifiers), which
translates into larger area, higher power consumption, and higher
E1(z) sensitivity to circuit tolerance.
x(s) To avoid this, we have developed a synthesis method
kin1 kg1
1
1
Tss
CL1 directly in the continuous-time domain which we will present
Tss
kfb1 kfb2 in this section. Let us consider the general case of a cascaded
y1(s) y1(z)
DAC CT modulator with m stages as shown in Fig. 1. Let us
kg2 E2(z) denote the transfer function from yi(s) to the input of j-th
kg3 1
y0(z) quantizer as
CL2
kg4 Tss
q j ( s)
kfb3 y2(s) y2(z) Fij Fij ( s) . (5)
DAC yi ( s)
kg5
E3(z)
kg6 The synthesis method starts by optimally placing the poles of
kg7 1 CL3 the single-loop transfer functions Fij(s) at the positions which
kg8 Tss
kg9
minimize the NTF in the signal bandwidth [21]. Their
kfb4 y3(s) y3(z) numerators are obtained by combining behavioral simulation
DAC
with the optimization core. Starting from the nominal values
Fig. 4. Diagram of a 2-1-1 CT modulator using a DT-to-CT required to place the zeros of the corresponding NTF, the
transformation. modulator performance is optimized in terms of dynamic range
and stability. For this purpose, these coefficients are varied in a
range around their nominal values in order to maximize the
non-idealities of the particular physical implementation are
SNR while maintaining stability. Then, transfer functions Fij(s)
used. The optimal architecture is the one that, meeting the
are automatically determined by the inter-stage integrating
performance constraints, minimizes objectives like power
paths.
consumption or area occupation. Exploration criteria at the
If the modulator input, x(t), is set to zero, it can be shown that
architectural level include considerations like order
the output of each stage yk(z) can be written as
minimization, minimization of oversampling ratio to avoid
infeasible sampling frequencies in terms of power Ek ( z ) k 1 1
I 1 Z{ [ H DAC Fik ] nTs }
consumption, and minimization of the number of bits in the yk ( z ) 1
, (6)
quantizer to avoid the use of linearization techniques [4], [19]. 1 Z{ [ H DAC Fik ] nTs }
Therefore, the power or area minimization criteria that can be

where Z stands for the Z-transform, and -1 is the inverse
considered at this level are of qualitative nature; therefore, any
Laplace transform.
ranking of candidate architectures may suffer significant
The output yo of the modulator can be written as
changes when progressing through the synthesis process.
However, this is not very critical at this stage because the m m Ek ( z ) k 1 1
I 1Z { [ H DAC Fik ] nTs }
desired result is just a set of candidate topologies which will be yo yk CLk CLk , (7)
1
1 Z{ [ H DAC Fik ] nTs }
pruned when more detailed models are considered in k 1 k 1
where CLk(z) represents the partial cancellation logic transfer V. Behavioral Modeling and Simulation
function of the k-th stage.
The partial cancellation logic transfer functions can be Specification transmission and verification require performance
calculated by imposing the cancellation of the transfer function evaluation mechanisms with much higher accuracy than that
of the first m-1 quantization errors Ek(z) in (7). This gives provided by approximate equations such as (2) to (4).
Moreover, this performance evaluation is frequently performed
1
Z{ [ H DAC Fkm ] nTs }CLm ( z ) within an iterative optimization process; therefore, simulation
CLk ( z ) 1
, (8) efficiency is critical for the synthesis process.
1 Z{ [ H DAC Fmm ] nTs }
Because modulators are strongly non-linear sampled-
where the partial cancellation logic transfer function of the last data circuits, simulation of their main performance
stage, CLm(z) can be chosen to be the simplest form that specifications has to be carried out in the time domain. Due to
preserves the required noise shaping. By using this method, the their oversampling nature, long transient simulations are
2-1-1 architecture in Fig. 5 is synthesized. The circuitry is necessary to evaluate their main figures of merit. Therefore,
significantly less complex than that shown in Fig. 4. Another transistor-level simulations yield excessively long computation
positive consequence is better sensitivity to parameter tolerances. times. An appropriate trade-off between simulation accuracy
and efficiency is accomplished by using behavioral simulation.
In this approach, the modulator is partitioned into sub-blocks
E1(z)
(integrators, quantizers, and so on), which are modeled by a set
x(s)
kin1 kg1 of equations, containing the main sub-block functionality and
1 1
CL1 the most important non-idealities. For the implementation
Tss Tss
kfb1 kfb2 platform, we selected Matlab/Simulink [22].
y1(s) y1(z)
DAC Behavioral models of the continuous-time building blocks
are described by a set of continuous-time state-space equations
E2(z)
kin2 which are integrated by Matlab solvers. To increase simulation
y0(z)
1 CL2 efficiency, we make extensive use of S-functions [23]. This
Tss
kfb3 mechanism allows non-idealities to be modeled by embedding
y2(s) y2(z) C-code routines instead of interconnecting numerous Simulink
DAC
elementary blocks. The basic building blocks modeled in the
kin3 E3(z) behavioral simulator as well as its non-idealities are
1 summarized in Table 1.
CL3
Tss
kfb4 The developed toolbox includes several libraries of CT
y3(s) y3(z) building blocks (integrators and resonators) considering
DAC
different circuit implementations: gm-C, gm-MC, active-RC,
Fig. 5. Diagram of a 2-1-1 CT modulator using direct and MOSFET-C. Examples of the application of this
synthesis. behavioral simulator to synthesis and verification can be found
in section VII.
Table 1. Basic building blocks and non-idealities modeled in the VI. High-Level Sizing Using POFs
behavioral simulator.
Block Non-idealities As stated in section II, the combination of the behavioral

Finite and non-linear gain, dynamic simulator in section V with the optimization tool allows the
limitations (parasitic capacitors, one- and high-level sizing of the modulator to be efficiently
Integrators two-pole transconductor model), thermal performed, that is, getting the maximum non-idealities of the
noise, finite output swing, linear input building blocks which can be tolerated while meeting the
range, offset.
modulator specifications.
Resonators Non-idealities associated to the integrators
This high-level specification transmission has some
Comparators Offset, hysteresis, signal-dependent delay drawbacks. First, there is no information a priori about the
Integral non-linearity, gain error, offset, realizability of the building blocks with the transmitted
Quantizers/DACs
jitter, excess loop delay
specifications, and this may induce redesign iterations.
Secondly, even if the specifications are realizable, the results
illustration’s sake, Fig. 6(a) shows the trade-offs between dc-

gain, gain-bandwidth (GB) product, and power for the
0.025
folded-cascode operational amplifier shown in Fig. 7 in a
0.020 130 nm CMOS technology. This Pareto-optimal front was
Power (W)
0.015 generated by combining a genetic algorithm [27] with an

0.010 electrical simulator. Projection on the XY plane in Fig. 6(b)
0.005 makes it easy to visualize the best trade-off between dc gain
and GB that the circuit at hand can achieve. Pareto fronts
900 usually have higher dimensionality including all
700 100 110
500 90 specifications of interest of the building block, which allows
300 80
70
GB (MHz) 100 60
40 50 a0 (dB) exploration of the trade-off among them, including the power
(a) and area budget.
Although Pareto fronts can also be used to directly provide
900 the sizes of the building blocks (each point in the Pareto front
800
represents a design point), in our case, we have used them only
700
to guarantee the feasibility of specifications and to provide
GB (MHz)
600
estimates of area and power for higher hierarchical levels. The
500
400
reason is that Pareto fronts are usually generated by using
300 evolutionary algorithms, where a population of individuals
200 evolves towards the best performance trade-offs. Therefore, the
100 number of points of the Pareto fronts is necessarily limited [26].
40 50 60 70 80 90 100 110
Restricting the search space to those points would lead to
a0 (dB) suboptimal solutions; therefore, better results are obtained if
(b) circuit sizing using the statistical optimization techniques
Fig. 6. (a) Gain/GB/power Pareto-optimal hypersurface for a discussed in section II is applied with the circuit specifications
cascode operational amplifier and (b) gain/GB projection. obtained in the high-level sizing.
Pbias1 VII. Case Study

Pbias2
The objective specifications for the CT modulator are 12
CM bits with 20 MHz signal bandwidth for a wireline
Pbias1 Pbias1
communication application, to be implemented in a 130 nm
Pbias1 Out + VCM Out -
CMOS technology. As a result of the different steps of the
Out - Out + architectural exploration process, several fifth-order (L=5)
Vin+ Vin-
cascade modulators were selected: 2-1-1-1, 2-2-1, and 3-2
CMFB
topologies. Only the topology which is retained for the final
synthesis steps is conceptually shown in Fig. 8 (a). It consists of
CM
a 2-2-1 topology and is clocked at fs=240 MHz (M=6) with
CMFB circuit
Nbias2 B=4 and NRZ DACs in all stages in order to minimize the
CMFB
effect of jitter.
The intra- and inter-stage transfer functions Fij can be written
Fig. 7. Front-end operational amplifier. as
b11s b10 b21s b20 b30
may be suboptimal in terms of area or power consumption due F11 ( s ) 2 2
, F22 ( s ) 2 2
, F33 ( s) ,
(s p1 ) (s p2 )
s
to an inappropriate balance among the specifications (9)
demanded for different building blocks. b20b30 b10b20b30
F23 ( s ) , F13 ( s ) ,
Specification transmission can be made more efficient if s( s 2 2
p2 ) s(s 2 2
p1 )( s
2 2
p2 )
Pareto-optimal fronts of candidate architectures are available.
These fronts represent trade-off hypersurfaces between the where p1,2 denotes the optimal placement of the pole
different types of circuit performance [24]-[26]. For frequencies. Coefficients bij in (9) are found through a
b10b20b30
Resonator 1
n10 n14 3 3 2 2
x(s) + F11(s) CL1 p1 p2 ( p2 p1 )
Quant 1 3 3 3 3
y1(s) [Ts ( p1 p2 p1 p2 ) p1 sin(Ts p2 ) p 2 sin(Ts p1 )],
DAC
2b10b20b30
n11 n13 3 3 2 2
p1 p2 ( p2 p1 )
Resonator 2
+ CL2 + yo(z) 3 3
F22(s) [Ts ( p2 p1 p2 p1 )(cos(Ts p1 ) cos(Ts p 2 )))
Quant 2
y2(s) 3
DAC p 2 sin(Ts p1 )(1 cos(Ts p 2 ))
3
p1 sin(Ts p 2 )(1 cos(Ts p1 ))],
Intergrator 2b10b20b30
+ F33(s) CL3 n11 n13 3 3 2 2
Quant 3 p1 p2 ( p2 p1 )
y3(s) Cancellation logic
3 3
DAC [Ts ( p1 p2 p1 p 2 )(1 2cos(Ts p1 )cos(Ts p 2 )))
(a) 3
p1 sin(Ts p 2 )(1 2cos(Ts p1 ))
kffo 3
p 2 sin(Ts p1 )(1 2cos(Ts p 2 ))],
Rin C1 kff1 b20b30

n20 n22 3
[Ts p2 sin(Ts p 2 )],
x(s) kg2
C2 p2
CL1
b20b30
Rr kg1 n21 3
[sin(Ts p2 ) Ts p 2 cos(Ts p 2 )], (10)
DAC2 CLK p2
D D
DAC1 latch latch
where Ts=1/fs is the sampling period.
kff2 CLK CLK
Figure 8 (b) shows the conceptual circuit implementation of
kff3 the modulator. The results of the optimization process are
kg3 kg4 summarized in Table 2, which includes the values of loop filter
C3 yo(z)
CL2 coefficients, ki (implemented as transconductances) and the
kin2
C4
DAC2
capacitances, Ci, used in the modulator.
CLK
kr3 D D The modulator was high-level sized. That is, the system-level
DAC1 latch latch
specifications (12-bit at 20 MHz) were mapped onto building-
CLK CLK block specifications using global optimization for design
C5
CL3 parameter selection, Pareto-optimal fronts of the sub-blocks
kin3 kg5 and behavioral simulation for evaluation. The result of this
CLK
DAC4 sizing process is summarized in Table 3, showing the
maximum (minimum) values of the non-idealities (at the
(b)
building block level) that can be tolerated to fulfil the required
Fig. 8. (a) Conceptual diagram of the 2-2-1 modulator and (b) modulator performance. Notice that not all non-idealities that
circuit implementation. were presented in Table 1 are listed in Table 3. In this table,
only specifications for those non-idealities that have a
simulation-based optimization process that optimizes the significant impact on the modulator performance are collected.
dynamic range, starting from nominal values required to place Thermal noise of amplifiers, for instance, is not critical for the
the zeroes of the corresponding NTF. For this purpose, these design at hand (it is usually less critical than the integrator’s
coefficients are varied in a range of up to 20% around their thermal noise from the RC elements, whose in-band noise
nominal values in order to achieve the maximum SNR while power, in this case, is around 85 dB). The building blocks,
maintaining stability. The partial transfer functions CLk(z) can including a front-end opamp, loop filter transconductors,
be calculated from (8), yielding the expressions quantizers, and DACs are designed by applying a cell-level
sizing tool [18]. Due to space limitations, only the synthesis
CL1 z 1 (n14 n13 z 1
n12 z 2
n11z 3
n10 z 4 ), results of the front-end opamp sizing are shown here.
The schematic of the front-end operational amplifier used
CL2 z 1 ( n22 n21 z 1
n20 z 2 ) (1 2cos(Ts p1 ) z
1
z 2 ),
together with its common-mode feedback circuit is shown in
1
CL3 (1 2cos(Ts p1 ) z z 2 ) (1 2cos(Ts p2 )z
1
z 2 ), Fig. 7. It is a fully differential folded-cascode topology with gain
Table 2. Loop filter coefficients of the modulator. -20
Rin=Rfb=1 k Rr1=5 k C2=2.25 pF -40

C1=C3=6 pF C4=C5=0.75 pF kg1=500 µA/V
-60
kg3=kg5=kff1=kff3=kin3=200 µA/V kin2=800 µA/V
Magnitude (dB)
-80
kg2=kg4=kr2=kff2 =100 µA/V kff0 =158 µA/V
-100
-120
Table 3. High-level sizing of the modulator.
-140
Front-end DC gain> 68 dB, GB> 580 MHz, Phase margin> 60 , BW =20 MHz
opamp Differential output swing> 0.5 V -160
105 106 107 108
Comparator offset <20 mV, Comparator hysteresis<20 mV, Frequency (Hz)
Flash
Comparator resolution time< 1 ns,
quantizers Ladder unit resistance=220 Fig. 10. Output spectrum of the modulator.
DC gain> 50 dB, Differential input amplitude> 0.3 V,
Loop 0
Differential output amplitude> 0.3 V,
transconductors Third-order non-linearity< -56 dB
-20 f1 =1.49 MHz
Current standard deviation< 0.15% LSB, -40 f2 =2.02 MHz
Current-
Finite output impedance> 12 M ,
steering DACs Settling time<500 ps -60
Magnitude (dB)
-80
-100
Table 4. Electrical performance of the front-end opamp.
-120
GB 600 MHz -140
DC gain 71 dB -160
BW =20 MHz
Phase margin 80 -180 4
10 105 106 107 108
Parasitic input capacitance 0.36 pF
Frequency (Hz)
Parasitic output capacitance 0.4 pF
Fig. 11. Output spectrum from a two-tone input signal test.
Differential output swing 0.7 V
Power consumption 20 mW
boosting. After a simulator-in-the-loop optimization process, the
resulting sized circuit achieves the electrical performance shown
in Table 4. A similar sizing is applied for the other building blocks.
The modulator performance before and after layout generation
has been extensively verified. Figure 9 shows the layout of the
modulator. The total occupied area is 2.33 mm2 (pads included)
Integrators with a power dissipation of 70 mW from a single 1.2 V supply
Capacitors
voltage. As an illustration, Fig. 10 shows the output spectrum for
an input sine-wave with -6.5 dBV amplitude and 1.76 MHz
Transimpedance
DACs s frequency. The maximum signal-to-(noise+distortion) ratio
(SNDR) is 80 dB (about 13 bits). These results correspond to a
full electrical-level post-layout simulation (thermal noise is
Clock
gen Loop-flter included in the simulation). Due to the long simulation time, this
latches Transconductor
DEM type of verification is only feasible for a limited set of simulation
conditions. A more exhaustive verification (including process,
Quantizers
supply, and temperature variations) is performed by using the
behavioral simulator with data obtained from the electrical
simulation of the building blocks. This allows, for instance, the
application of Monte Carlo simulation to evaluate the influence
Fig. 9. Layout of the modulator (with pads). of mismatch on performance deviations. In the present case,
even in the worst-case mismatch, a maximum SNDR larger than ICs, vol. 25, no. 3, Mar. 2006, pp. 597-607.
74 dB is obtained. [12] J. Ruiz-Amaya et al., “High-Level Synthesis of Switched-
Finally, Fig. 11 shows the results from a two-tone input signal Capacitor, Switched-Current and Continuous-Time
test. The performance degradation due to the third-order Modulators Using SIMULINK-Based Time-Domain
intermodulation distortion (IM3) is well below the required Behavioral Models,” IEEE Trans. Circuits And Systems I, vol.
resolution. 52, no. 9, Sept. 2005, pp. 1795-1810.
[13] O. Yetik et al., “A Coefficient Optimization and Architecture
VIII. Conclusion Selection Tool for Modulators in MATLAB,” Proc. Design,
Automation and Test in Europe Conf., 2007, pp. 16-20.
This paper has presented a complete design methodology [14] K. Francken et al., “A Behavioral Simulation Tool for
supporting the design of CT modulators. An appropriate Continuous-Time Delta-Sigma Modulators,” Proc. IEEE/ACM
combination of design knowledge, behavioral simulation, Int. Conf. Computer-Aided Design, 2002, pp. 234-239.
synthesis methods, and optimization tools eases the complex [15] G. Gielen et al., “An Analytical Integration Method for the
design of these high-performance modulators. Simulation of Continuous-Time Delta/Sigma Modulators, IEEE
Trans. Computer-Aided Design of ICs, vol. 23, no. 3, Mar. 2004,
pp. 389-399.
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[2] J.A. Cherry and W.M. Snelgrove, Continuous-Time Delta-Sigma [17] H. Aboushady et al., “Automatic Synthesis and Simulation of
Modulators for High-Speed A/D Conversion, Kluwer, 2000. Continuous-Time Sigma/Delta Modulators,” Proc. Design,
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Modulation for A/D Conversion in Radio Receivers, Kluwer, [18] F. Medeiro et al., “Global Design of Analog Cells Using Statistical
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IEEE J. Solid-State Circuits, July 2004, pp. 1056-1063. Continuous-Time Modulators with NRZ Feedback
[5] M. Moyal et al., “A 700/900 mW/Channel CMOS Dual Analog Waveform,” Proc. IEEE Int. Symp. Circuits and Systems, 2005, pp.
Front-End IC for VDSL with Integrated 11.5/14.5 dBm Line 3103-3106.
Drivers,” Proc. IEEE Int. Solid-State Circuits Conf., 2003, pp. [20] S. Yan and E. Sánchez-Sinencio, “A Continuous-Time
416-417. Modulator with 88-dB Dynamic Range and 1.1-MHz Signal
[6] L.J. Breems, R. Rutten, and G. Wetzker, “A Cascaded Bandwidth,” IEEE J. Solid-State Circuits, Jan. 2004, pp. 75-86.
Continuous-Time Modulator with 67 dB Dynamic Range in [21] R. Schreier, “An Empirical Study of High-Order Single-Bit Delta-
10-MHz Bandwidth,” IEEE J. Solid-State Circuits, Dec. 2004, pp. Sigma Modulators,” IEEE Trans. Circuits and Systems II, Aug.
2152-2160. 1993, pp. 461-466.
[7] R. del Río et al., CMOS Cascade Sigma-Delta Modulators for [22] http://www.mathworks.com
Sensors and Telecom: Error Analysis and Practical Design, [23] “Simulink 6 Writing S-functions,” MathWorks Inc., 2007 [On-line:
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[8] F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez, Top- [24] G. Stehr, H. Graeb, and K. Antreich, “Performance Trade-Off
Down Design of High-Performance Sigma-Delta Modulators, Analysis of Analog Circuits by Normal Boundary Intersection,”
Kluwer, 1999. Proc. ACM/IEEE Design Automation Conf., 2003, pp. 958-963.
[9] K. Francken and G. Gielen, “A High-Level Simulation and [25] T. Eeckelaert, T. McConaghy, and G. Gielen, “Efficient
Synthesis Environment for Delta/Sigma Modulators,” IEEE Multiobjective Synthesis of Analog Circuits Using Hierarchical
Trans. Computer-Aided Design of ICs, vol. 22, no. 8, Aug. 2003. Pareto-Optimal Performance Hypersurfaces,” Proc. Design,
[10] P. Malcovati et al., “Behavioral Modeling of Switched-Capacitor Automation and Test in Europe, 2005, pp. 1070-1075.
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[11] H. Tang and A. Doboli, “High-Level Synthesis of Delta/Sigma Sequential Quadratic Programming,” Proc. Design, Automation
Modulator Topologies Optimized for Complexity, Sensitivity and and Test in Europe Conf., 2007, pp. 75-80.
Power Consumption,” IEEE Trans. Computer-Aided Design of [27] K. Deb et al., “A Fast and Elitist Multiobjective Genetic Algorithm:
NSGA-II,” IEEE Trans. Evolutionary Computation, vol. 6, no. 2, Elisenda Roca received the physics and PhD
Apr. 2002, pp. 182-197. degrees from the University of Barcelona, Spain,
in 1990 and 1995, respectively. From November
Ramón Tortosa received the BSc degree from 1990 to April 1995, she worked at IMEC,
the University of Valencia, Spain in 1999. He Leuven, Belgium, in the field of infrared
joined Motorola SPS in Ireland, where he detection aiming to obtain large arrays of CMOS
worked in the development of transceiver chips compatible silicide Schottky diodes. Since 1995,
for GPRS in both the baseband filters and RF she has been with the IMSE-CNM-CSIC, Seville, Spain, where she
circuits groups. From 2002 to 2007, he was with holds the position of tenured scientist. Her research interests are centered
the Instituto de Microelectronica de Sevilla, on the design of CMOS vision systems on-chip (VSoC) with integrated
where his main research area was high speed continuous-time sigma high dynamic range sensors, and modeling and design methodologies for
delta modulators. In 2007, he joined Analog Devices in Ireland, where analog integrated circuits. She has been involved in several research
he is currently working as a team leader and main designer in the projects with various institutions including Commission of the EU, ESA,
development of low-voltage and low-power temperature sensors. His and ONR-NICOP. She has also co-authored more than 50 papers
research interests include low-power data converters and sensors. published in international journals, books, and conference proceedings.
Rafael Castro-López received the "Licenciado Ángel Rodríguez-Vázquez received the PhD
en Física Electrónica" degree (MS degree in degree in physics-electronics in 1983. He is a full
electronic physics) and the "Doctor en Ciencias professor of electronics at the University of Seville
Físicas" (PhD degree) from the University of and the Head of Innovaciones Microelectro'nicas
Seville, Spain, in 1998 and 2005, respectively. S.L. (AnaFocus). He founded and headed the
Since 1998, he has been working at the Institute High-Performance Analog and Mixed-Signal
of Microelectronics of Seville (CSIC-IMSE- VLSI Circuits research unit of the Institute of
CNM) of the Spanish Microelectronics Center. His research interests lie Microelectronics of Seville (IMSE-CNM). His team made significant
in the field of integrated circuits, especially design and computer-aided contributions to the application of chaotic dynamics to communications,
design for analog and mixed-signal circuits. He has participated in several including the design and production of the first world wide chaos-based
national and international R&D projects and co-authored more than 40 communication MoDem chips. Some 30 high-performance, state-of-the-
international scientific publications, including journals, conference papers, art mixed-signal chips were successfully designed by his team during the
book chapters and the book Reuse-Based Methodologies and Tools in the last 15 years. He has authored/edited eight books, around 40 book chapters,
Design of Analog and Mixed-Signal Integrated Circuits (Springer, 2006). and more than 400 articles. He has served as an editor, associate editor, and
Dr. Castro is also currently teaching at the University of Seville where he guest editor for various IEEE and non-IEEE journals. He has received a
joined the Department of Electronics and Electromagnetism. number of international awards and was elected Fellow of the IEEE for his
contributions to the design of chaos-based communication chips and
J. M. de la Rosa received the "Licenciado en neuro-fuzzy chips. He is an IEEE Fellow.
Física Electrónica" (Electronics Physics) degree
in 1993 and the "Doctor en Ciencias Físicas" F.V. Fernández received the physics-electronics
(PhD) degree in 2000, both from the University degree from the University of Seville in 1988 and
of Seville, Spain. Since 1994, he has been his PhD degree in 1992. In 1993, he worked as a
working at the Institute of Microelectronics of postdoctoral research fellow at Katholieke
Seville (IMSE-CNM, CSIC) of the Spanish Universiteit Leuven (Belgium). Since 1995, he
Microelectronics Center. He is also with the Department of Electronics has been an associate professor with the Dept. of
and Electromagnetism at the School of Engineering of the University of Electronics and Electromagnetism of University
Seville, where he is an associate professor. His main research interests are of Seville. He is also a researcher at CSIC-IMSE-CNM. His research
in the field of mixed-signal integrated circuits, especially pipeline and interests lie in the design and design methodologies of analog and mixed-
sigma-delta analog-to-digital converters, including analysis, behavioral signal circuits. He has authored or edited three books and has co-authored
modeling and design automation of such circuits. He has participated in more than 100 papers in international journals and conferences. He is
several national and European R&D projects and has co-authored over currently the Editor-in-Chief of Integration, the VLSI Journal (Elsevier).
90 international scientific publications, including journal and conference He regularly serves on the program committees of several international
papers, books, and book chapters. conferences. He has also participated as a researcher or main researcher
in several national and European R&D projects.
!
PUBLICACIÓN 4
Título de la Publicación: Design of a 1.2-V Cascade Continuous-Time ΣΔ Modulator for

Broadband Telecommunications
Autores: Ramón Tortosa, José M. de la Rosa, Angel Rodríguez-Vázquez and Francisco V.
Fernández
Tipo de publicación: Artículo en congreso internacional con proceso de revisión por pares
Nombre del congreso: IEEE International Symposium on Circuits and Systems (ISCAS)
Editorial: IEEE
ISBN: 0-7803-9390-2
R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Design of a 1.2-V
Cascade Continuous-Time ΣΔ Modulator for Broadband Telecommunications,” Proceedings of
2006 IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 589-592, May 2006.
RESUMEN
Este artículo presenta el diseño de un modulador ΣΔ de tiempo continuo en cascada con

cuantización multi-bit para sistemas de telecomunicación de banda ancha. La arquitectura del
modulador ha sido sintetizada directamente en el dominio del tiempo continuo en lugar de
utilizando una transformación discreta-continua a un modulador de tiempo discreto equivalente.
Este método resulta en una arquitectura más eficiente en términos de conformado de ruido,
consumo de potencia y sensibilidad a las tolerancias de los elementos de circuito analógicos.
El diseño del circuito, realizado en una tecnología CMOS de 130nm, se fundamenta en una
metodología CAD “top-down/bottom-up” que combina simulación con optimización estadística
en diferentes niveles de abstracción de la jerarquía del sistema. El consumo de potencia estimado
es de 60mW, considerando una única tensión de alimentación de 1.2V y una frecuencia de
muestreo de 240MHz. Los resultados de simulación demuestran que el modulador puede
alcanzar una resolución efectiva de 80dB (13-bit) en un ancho de banda de 20MHz.
!
Design of a 1.2-V Cascade Continuous-Time ZA

Modulator for Broadband Telecommunications
Ramon Tortosa, Josef M de la Rosa, Angel Rodriguez- Vazquez and Francisco V Fernandez
Instituto de Microelectronica de Sevilla - IMSE-CNM (CSIC)
Ed. CICA-CNM, Avda. Reina Mercedes s/n, 41012- Sevilla, SPAIN
Phone: +34 95 5056666, Fax: +34 95 5056686, E-mail: {tortosaljrosalangellpacov}@imse.cnm.es
Abstract - This paper presents the design of a continuous-time stages include 4-bit internal quantization and
multibit cascade 2-2-1 LA modulator for broadband telecom Non-Return-to-Zero (NRZ) Digital-to-Analog Converter DAC
systems. The modulator architecture has been synthesized in order to attenuate the clock jitter [8]. The modulator has been
directly in the continuous-time domain instead of using a dis- synthesized directly in the continuous-time domain and no cal-
crete-to-continuous time transformation. This method results ibration is used to compensate for mismatch and element toler-
in a more efficient modulator in terms of noise shaping, power ances. Circuit design, realized in a 0.13[tm CMOS technology
consumption and sensitivity to circuit element tolerances. The and nominal 1.2-V supply voltage, has been optimized from
design of the circuit, realized in a 0.13,um CMOS technology, is system-level to building-block level in order to achieve the
based upon a top-down CAD methodology which combines required specifications with minimum power dissipation. Sim-
simulation and statistical optimization at different levels of the ulation results demonstrate that the presented circuit can digi-
modulator hierarchy. The estimated power consumption is tize 20MHz signals with 13-bit resolution when clocking at
60mW from a 1.2-V supply voltage when clocked at 240MHz. 240MHz.
Simulation results show 80-dB effective resolution within a
20-MHz signal bandwidth. t1 II. DESIGN CONSIDERATIONS
I. INTRODUCTION The modulator in this paper was designed to cope with an
Modern broadband telecommunication applications, like effective resolution over 12bit within a 20-MHz signal band-
Yery high-rate D.igital Subscriber Line (VDSL) and Power Line width. Ideally, these specifications can be achieved by different
Communication (PLC), demand Analog-to--.igital Convertes - combinations of modulator order, L, number of bits of the
C targeication
12-1 4bit reslu-t
o
aticonversonvraters internal quantizer(s), B, and oversampling ratio, M. However,
MSampes/sec
12
MS/s)tTradlutionallythnerseispeci
40-80 MSamples/second (MS/s). Traditionally, these specifica-
ra in practice, there are some important limiting factors preclud-
L, B ,MItids
in rmuigsm L hs iiain
tions have been achieved with Nyquist-rate ADCs, using pipe-
line or folding/interpolation topologies, because of the
ing fro usingso es{ traias.
prohibitive sampling frequencies required by *A Modulators High-order single-loop topologies may not be feasible for
prohibiMivesa[.oering
uouMs-Tim (CT)Howeve
i thequlstfewyeairsed us Circuit
nsteadeofDiscretfe-imare of Conulatin
t
the mentioned specifications because of stability issues.
For
o
that reason, only cascade architectures made up of sec-
uous-Time (CT) instead of Discrete-Time (DT) circuit tech-(DT)
tgswr osdrd
niques are making possible for RAMs to digitize (1 -15 MHz )
on-re n is-re
n High values of B force to use linearization techniques [3]

site ofof14
signals
In spite achitrevingspotentallyufasteroperation
achieving potentially faster operation withlor
with digital calibration [2] in order to control the nonlinearity
lowerofteDCudinhem uloredbclop
power consumption, CT RAMs are more sensitive than DT
'.Mscircuiterros,namely:lockjitterndtechnLarge
tosome
EAMs to some circuit errors, namely: clock jitter and technol- values of M lead to unfeasible sampling frequencies
in terms of ower consumption.
ogy parameter variations [5]. The latter are specially critical for p p
the realization of cascade architectures what explains the very * Last but not least, clock jitter is an ultimate limiting error
ththst eadesdfo h eybgnigo h
few ItegrtedCrcuis (Is) reorte up t now[4].that has to be addressed from the very beginning of the
Re centestudiesdeostretore efficintae.
Recent studies demonstrate that more efficient ccascade CT .^^ design process. fact,
In as demonstrated in [8], the in-band
noise power caused by jitter error can be minimized by
EAMscan e sntheize by sin a drec synhess
[6]. This method allows to reduce the number of analog com- mehodproper
selection
prorsleo
ofB,the of B, the sampling frequency, f and the
ponents and to efficiently place the zeroes/poles of the noisemak tor loop fther
transfer function, thus yielding to more robust architectures
than usiga
DT-o-CT trasformaton
Takine onsideraentA ione wab
[7].an exhaustive exploration of different LAM loop filters was
thansisg
This paper reptorCT thedsfo
pap reports tignand
the design and electrical implementa-
electricalimplemen done using SIMSIDES [10] in order to find out the optimum
{ L,B,MItid osmto,dsrbto
ntrso oe
tion of a cascade CT LAM. The modulator architecture com- L B M}t
prises three stages. The first two stages are a second-order of the Noise Transfer Function (NTF) zeroes and insensitivity
topology whereas
+--1- 1 -----the
1 last stage
1-+ +--
uses a first-order
--,+--A- 1--
-,- 91+- All
loop filter. A11 to clock jitter. As a result,
tocokjte.A eut the it-re (L
h fifth-order L = 55 ) cascade
acd
LAM, conceptually shown in Fig.1, was selected. It consists of
ti1. This work has been supported by the Spanish Ministry of Science and Education a'-- oooy 20H (M 6,wt
lce t
(with support from the European Regional Development Fund) under contract B =4 and NRZ DAC in all stages in order to minimize the
TEC2004-01752/MIC.
0-7803-9390-2/06/$20.00 ©C2006 IEEE 589 ISCAS 2006

effect ofjitter, that according to [8], must be below 3ps rms.

The modulator in Fig.1 can be synthesized from an equiv- -blob2____
alent DT LAM. However, in order to get a functional CT LAM p10 14 3 3 2 2
while keeping the Cancellation Logic (CL) of the original DT 3 3 3 3
LAM, every state variable and DAC output must be connected Ts((0pI p2- p(i p2)+±P sin(T p2) - 6p2sin(Tjo31)]
to every integrator input of later stages [7]. The number of inte- n -2b lOb20b30
grating paths, and hence of analog components, can be reduced ( P2(0p2 - ( PI)
if the whole cascaded LAM is directly synthesized in the CT 3 - cos(Tsop9)) 3
domain as proposed in [6]. In this paper we have selected the 3 3
latter methodology, which does not only take into account the p2sin(Tiop1)(1 ± cos(Tpop2)) -psin(T p29(1 + cos(Tsopl))]
single-stage loop filter transfer functions (Fii), but also the , = - 2blob2Ob3 (3)
inter-stage loop filter transfer functions (Fij, i j1). The latter, Opl(op2(0p2-(0p)
defined as the transfer function from y1 to thej-th quantizer (p13p2)(1 + 2 cos(To3p ) cos(T,o32))±
[T (opI2-
(see Fig. 1), are continuous-time integrating paths appearing ±23 sinT T o 3 sin To )±2cos To
only when the modulator stages are connected to form the cas- PI p2)(1 + 2 cos(Ts pI)) - p2 S( s 2 sp2))]
caded LAM and must be included in the synthesis methodology n n [T -
to obtain a functional modulator with minimum number of Op2
inter-stage paths. _-2b3b
For the modulator in this paper, the following Fi were 321 22 [sin(Tso,2) - Ts(o,2cos(Ts(,2)]
synthesized:
b1ls + blo b21s + b2 b 111. MODULATOR IMPLEMENTATION
F1I(s) = 2 2 F22(S) 33(S) -S Fig.2 shows the conceptual circuit implementation of the
(s + cop1) (s + cp2) modulatort2. An RC-active front-end integrator is chosen for
b1ob20b30 b2Ob3 ( its better linearity whereas the rest of integrators are Gm-C
F13(s) = 2+ 2 2 2 F23(S) 2 2 [2][3]. The 4-bit quantizers were implemented using a flash
s(s cop )(s + cop2) s(s + cop2) ADC made up of a resistive ladder and 15 regenerative compa-
where Ts = I /fs is the sampling period and op ,2 are the rators. DACs were implemented by current-steering topolo-
pole frequencies. Coefficients b in (1) are found through an gies. An extra feedback branch between the output and the
iterative simulation-based process that - starting from nominal input to the quantizer (DAC2 in Fig.2) and two D-latches is
values required to place the zeroes of the corresponding NTF - kffo
optimizes the modulator performance in terms of dynamic
range and stability. For this purpose, these coefficients are var- Rinc,
ied in a range of up to ±20% around their nominal values in x(s) Ih L
order to achieve the maximum Signal-to-Noise Ratio (SNR)
while keeping stability. The partial CL transfer functions can be kg,
calculated from (1) [6]: CLK
CL1 = z-l(n4+ n3z'I+ n z2 + nz-3 + n0z-4) D D
CL2 =z-(n22+n2IZI +n20z-2).(1 -2cos(TsPI)Z-I +Z-2) (2) k

CL3 =(I -2cos(TsopI)z +±z2) (1 -2cos(Tso)p2z- ±Z2)
I
1 f2
where coefficients n are given by:

Resonatorli
x(s) + )
11(s J CL1 y
QuantliC
yi(s) DAC2
F , Ifs k.
Y() DAC
F2() f (Z) CLK CLKCL|
Iontgator24
t1 <<
}m }/ ~~~~~~~~~~~~~~~Figure
2. Modulator implementation.
ly(s)
y3sDAC anclQtioLogc3 t2. Although the modulator has been implemented using fully-differential circuitry,
~~~~
Figure 1. Conceptual diagram of the 2-2-1 modulator. a single-ended schematic is shown here for the sake of simplicity.
590
employed in the first two stages in order to compensate for the 1.2-V supply voltage. The LAM building blocks were conven-
effect of excess loop delay [2]. The first two stages are formed iently selected and sized according to the system-level specifi-
by a resonator which has its poles placed at an optimum posi- cations. Among the others, the most critical subcircuits are the
tion, minimizing NTF in the signal bandwidth, Bw [9]. Resistor opamps and the transconductors, described below.
variations can be tuned out using a combination of a discrete
rough tuning of the resistors (R and Rr ) and a continuous nt-end operational amplifier
fine tuning of the transconductors kffl and kgi. This tuning Fig.3 shows the schematic of the front-end operational
can be also used to cancel the effect of finite Gain-Bandwidth amplifier together with its common-mode feedback circuit. It is
product ( GB ) of the front-end opamp, due to the fact that this a fully differential telescopic cascode topology with gain boost-
error can be modelled as an integrator gain error [3]. All the ing. Note that p-type input scheme has been considered in order
other transconductors can be tuned in order to keep the time to cancel the body effect in PMOS devices - one of the mech-
constant Clgm unchanged over C variations. anisms for substrate noise coupling. One of the major limita-
Table I. sums up the outcome ofthe optimization process - tions of this topology is the output swing. However, this is not
entirely done in the CT domain as described in previous sec- a problem in this modulator where proper system-level design
tion. This table includes the values of loop filter coefficients, ki reduces the front-end integrator output signal range to 0.3V.
(implemented as transconductances) as well as the capaci- Table III sums up the simulated performance of the circuit.
tances, Ci, and resistances, R. used in the modulator. B Transconductors
The modulator was high-level sized, i.e, the system-level B. ofutors
specifications (12-bit@20-MHz) were mapped onto build-
ing-block specifications using statistical optimization for
Oneofthe mainelimitationsrin
open-loop Gm-C integrators
is their poor linearity. In order to tackle this problem, the
design parameter selection and behavioral simulation for eval- transconductor shown in Fig.4, based on a quadratic term can-
uation [10]. The result of this sizing process is summarized in cellation, is proposed. High-speed operation is achieved by
Table II, showing the maximum (minimum) values of the cir-
cuit error mechanisms that can be tolerated in order to fulfil the
using only feed-forward paths and by adding capacitors
which introduces a high frequency zero that extends the fre-
(Cfr)
required modulator performance. The data in this table are the quency range of operation. This transconductor can be turned
starting point of the electrical design described in next section. through the bias current, itune, In order for the tuning to be
effective, each transconductance in the modulator is formed by
a parallel connection of unitary transconductors of 100tA/V
The modulator has been designed in a 0.13[tm 1-poly each. Multiple MonteCarlo simulations have been done during
8-metal logic CMOS process. Metal-insulator-Metal capacitors the design process in order to take into account the impact of
were used because of their good matching and linearity proper- mismatch on the linearity ofthis circuit. Table IV shows a sum-
ties. The estimated power dissipation is 60mW from a single mary of the electrical performance.
Pbi.1 0
TABLE I. LooP FILTER COEFFICIENTS OF THE YAM bP I2

Rin =RR - kQ; Rri 5 kQ,7
C1 C3 =6 pF P~ Pi
C2 2.25 pF C4 =C5 0.75 pF pOuL vl [Q4 -
kg, 500 itA/V k1~ 800 itA/V Out+~
kg 3 kg =
kf kfJ- =
k,k 3 -200 ItANV"L k 0J,
kg2 =
kg4 k,2 kff2 100 itAN C
kfjo 158 itAN-
CMIFB circuit
TABLE 11. HIGH-LEVEL SIZING OF THE Y-AM ias2 CMFB - '
Front-end opamp - _
(GB >50 MHz
DC Gain >68 dB Figure 3. Front-end operational amplifier.
Phase Margin >600
Parasitic Input Capacitance <0.4 pF TABLE III. ELECTRICAL PERFORMANCE OF THE FRONT-END OPAMP
Parasitic Output Capacitance <0.5 pF GB 600 MHz
Diff. Output Swing >0.5 V DC Gain 71 dB
Transconductors Phase Margin 800
L)(J (Jamn >50) dB Parasitic input capacitance 0.36 pF
Diff. Input Amplitude 0.3 V Parasitic output capacitance 0.4 pF
Diff. Output Amplitude 0.3 V Differential output swing 0.7 V
Third-order non-linearity >56 dBV Power consumption 20mW
591
0)~~~~~~~~~~~~~~~~~~T
.5 0
- b-4 --Figure 6. Effect of mismatch on the SNR.

Figure 4. Transconductor schematic.
a MonteCarlo analysis of 150 simulations was carried out. The
V. SIMULATION RESULTS value of the SNR represented in the vertical axis of Fig.6 is
The modulator was simulated considering the electrical obtained by 9000 of the simulations for each case of CGgm and
performance described above. As an illustration, Fig.5 shows ~c*c Note that even in the worst-case mismatch, the resolution
the output spectrum for an input sinewave of -6.5-dBV ampli- is above the specified (74-dB ).
tude and 1 .76-MHz frequency. The maximum Sig- CONCLUSIONS
nal-to-(Noise+Distortion) Ratio (SNDR) is 80 dB (_ 13 bits ).
In addition to the design issues discussed in previous sec- The design of a 1.2-V, 0.13[pm CMOS 13-bit@20-MHz
tions, the effect of circuit tolerances and component mismatch, cascade CT-SAM has been presented. The modulator architec-
especially critical in cascade CT RAMs, has been taken into ture has been directly synthesized in the continuous-time
account. The first one can be controlled in this circuit by using domain, thus optimizing their performance in terms of circuit
tuning of time constants. However mismatch error still complexity, power consumption and sensitivity with respect to
remains. In order to evaluate the impact of this error on the per- mismatch. In the time of writing this paper, the circuit is being
formance of the modulator, maximum values of mismatch were laid out for fabrication and it is expected that measured results
estimated for a 0.13[pm CMOS technology. The results of this will be available at the symposium.
analysis are shown in Fig.6 where the SNR is represented as a REFERENCES
function of the standard deviation of the transconductances [1] A. Rodriguez-Vazquez, F. Medeiro and E. Janssens (Editors): CMOS
(Ggm) and capacitances
g
(GCs)- For each point ofthese surfaces,' 2 Telecom
Yan, E.Data Converters. Kiuwer,
[2] ~~~~~~~~~~~~~~~~S.
Sainchez-Sinencio: 2003.
"A Continuous-Time LA Modulator With
88-dB Dynamic Range and 1. 1-MHz Signal Bandwidth". IEEE Jour-
TABLE IV. ELECTRICAL PERFORMANCE OF THE TRANSCONDUCTOR nal of Solid-State Circuits, pp. 75-86, January 2004.
____________________________________ - 5 dB - [3] 5. Paton, A. Di Giandomenico, L. Hernandez, A. Wiesbauer, T. Pot-
DC Gain 58___dB scher and M. Clara: "A 70-mW 300-MHz CMOS Continuous-Time LA
Diff. Input Amplitude -0.3 V -ADC With 15-MHz Bandwidth and 11 Bits of Resolution". IEEE Jour-
Diff Output Amplitude C 03 V nal J.ofSolid-State
C4[4] L. Breems, R. Circuits,
Rutten pp.
and 1056-1063,
G. Wetzker:July"A2004.
Cascaded Continu-
HD3 -57 dB ous-Time LA Modulator with 67dB Dynamic Range in 10-MHz Band-
stnaddvain.
Transconductance standard
Transconductance gg
dev1ahon, 6g7/gm <1.500/° width".
DecemberIEEE 2004. Journal of Solid-State Circuits, pp. 2152-2 160,
Power consumption -350MW -
[5] J.A. Cherry and W.M. Snelgrove: Continuous-Time Delta-Sigma Mod-
_______________________________ ulators for High-SpeedAAD Conversion. Kluwer, 2000.
_____
____________________________[6] R. Tortosa,
r rFdez: J.M. de la Rosa, A. Rodriguez-Vaizquez and F.V. Fernain-
"A Direct Synthesis Method of Cascaded Continuous-Time
-20 Sigma-Delta Modulators". Proc. of the 2005 International Symposium
V. SIMULATIONRESULTS Mon Circuits and Systems, pp. 5585-5588, May 2005.
a
-40 | X ! v[7] M. O rtmanns, F. Gerfers, and Y Manoli"On
: the Synthesisof Cas-
performance described above. As anillustraticaded Continuous-Time Sigma-Delta Modulators". Proc. of the 2001
moupu
ad-60s 1 IEEEInt. Symposium on Circuits and Systems, pp. 419-422, May 2001.
n
e
R
C[8] R. Tortosa, J.M. de la Rosa, A. Rodriguez-VNzquez and F.V. Fernan-
-80
Inaddition tothedesignissuesdiscussedinprevioussec- dez: "Analysis of Clock Jitter Error in Multibit Continuous-Time HA
tions,
effect ofcircuittolerancesandcomponentmismatch,
the ccModulators With NRZ Feedback aveftrm". Proc.
e of the 2005 Inter-
enational Symposiu.m on Circuits nd Systems, pp. 3103-3106, May
ac
120nt.im
tunngof costnt-1. II hlednf oa i t t
Del
by sin
[9] R. Schreier: "An Empirical Study of High-Order Single-Bit
ta-Sigma Modulators". IEEE Trans. on Circuits and Systems-II,pp.
-140\ Xl AI,, tl formance of them r, 461-466, August 1993.
m m
ve[10]J. Ruiz-Amaya, J.M. de la Rosa, F.V. Fernandez, F. Medeiro, R. del
thestndadlevatin fterasco
functionof Rio, B. Perez-Verdu and A. Rodriguez-Voazquez: "High-Level Synthe-
016C
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Frequency (Hz)
siS of Switched-Capacitor, Switched-Current and Continuous-Time LA
Modulators Using SIMULINK-Based Time-Domain Behavioral Mod-
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592
!
PUBLICACIÓN 5
Título de la Publicación: A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-

Delta Modulator
Autores: Ramón Tortosa, Antonio Aceituno, José M. de la Rosa, Angel Rodríguez-Vázquez and
Francisco V. Fernández
Tipo de publicación: Artículo en congreso internacional con proceso de revisión por pares
Nombre del congreso: IEEE International Symposium on Circuits and Systems (ISCAS)
Editorial: IEEE
ISBN: 1-4244-0921-7
R. Tortosa, A. Aceituno, José M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “A
12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator,” Proceedings of
2007 IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2007.
RESUMEN
Este artículo presenta el diseño a nivel de transistor en una tecnología CMOS de 130nm de un
modulador ΣΔ de tiempo continuo en cascada. La topología del modulador se ha sintetizado
directamente en el dominio del tiempo continuo, y consiste en una etapa de tercer orden
conectada en cascada con una etapa de segundo orden. Ambas etapas se han implementado
mediante integradores Gm-C y utilizan un cuantizador de 4 bits. El efecto de la no linealidad del
DAC se compensa mediante la implementación de un algoritmo DEM (de “Dynamic Element
Matching”).
El consumo estimado de potencia del circuito es de 70mW considerando una única fuente de
alimentación de 1.2V y una señal de reloj de 240MHz. Se presentan simulaciones eléctricas
realizadas en Cadence-SPECTRE que validan el funcionamiento del modulador a nivel de
transistor, mostrando una resolución efectiva de 12 bits en un ancho de banda de 20MHz.
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RZTR7[8>ZT8
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#?'-&0.Q"&!""%&",=;?I"+C&"-="/*.;;I&*%&,?-#&/'*#*/.;&,.#/0"+ RJA F&0.-&!""%&='"-"%#"+3&J0"&,?+);.#?'&.'/0*#"/#)'"&0.-
=.'#-&?B&#0"&/*'/)*#3&J0"&/?,=;"#"&,?+);.#?'&?//)=*"-&.%&.'".&?B !""%& +*'"/#;I& -I%#0"-*H"+& *%& #0"& /?%#*%)?)-A#*,"& +?,.*%& .%+
O3\\&,,O&1=.+-&*%/;)+"+:&.%+&#0"&"-#*,.#"+&=?$"'&+*--*=.#*?% *,=;","%#"+& )-*%<& M,AR& *%#"<'.#?'-C& XA!*#& B;.-0& ().%#*H"'-
*-&^2&,_"B'?,&.&-*%<;"&43OAV&-)==;I&Q?;#.<"3& .%+&TLc&/)''"%#&-#""'*%<&DSR-&*%&.;;&-#.<"-3&J0"&/0*=&0.-&!""%
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+*-#?'#*?%& ;*,*#-& #0"& ,.@*,),& 8*<%.;A#?A1T?*-"aD*-#?'#*?%: LEKELETRE8
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U.'.,"#"' UA#I="&/";; TA#I="&/";; (>B'!8;&%9;'/-,'CD'E-F<)%'G<,%)%;;'6-99=><.(&<->;C&==3&4\A4]C&h)%"
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4
!
ANEXO 3: OTRAS PUBLICACIONES SOBRE LOS TRABAJOS

RECOGIDOS EN LA TESIS DOCTORAL
RESUMEN
Este anexo incluye una serie de artículos publicados por el doctorando en conferencias
internacionales, todas ellas vinculadas al trabajo de investigación desarrollado en esta tesis
doctoral y publicadas por entidades de reconocido prestigio internacional como son IEEE, IEE
(hoy IET) y SPIE, sometidas al proceso de revisión por pares.
Las publicaciones incluidas son las siguientes:
- R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Cascade Continuous-

Time ΣΔ Modulators With Reduced Number of Analog Components – Application to VDSL,”
Proc. of 2005 IEE Conf. on Advanced A/D and D/A Conversion Techniques and Their
Applications (ADDA), pp. 233-238, Limerick, Irlanda, Julio 2005. (ISBN: 0-86341-542-3).
- R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Analysis of Clock Jitter
Error in Multibit Continuous-Time ΣΔ Modulators with NRZ Feedback Waveform,” Proc. of 2005
IEEE Int. Symposium on Circuits and Systems (ISCAS), pp. 3103-3106, Kobe, Japón, Mayo 2005.
(ISBN: 0-7803-8834-8).
- R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “A Direct Synthesis

Method of Cascaded Continuous-Time Sigma-Delta Modulators,” Proc. of 2005 IEEE Int.
Symposium on Circuits and Systems (ISCAS), pp. 5585-5588, Kobe, Japón, Mayo 2005. (ISBN: 0-
7803-8834-8).
- R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Continuous-Time

Cascaded Sigma-Delta Modulators for VDSL: A Comparative Study,” Proc. of 2005 SPIE
Microtechnologies for the New Millenium – VLSI Circuits and Systems Conf., pp. 59-70, Sevilla,
Mayo 2005. (ISBN: 0-8194-5832-5).
- R. Tortosa, A. Aceituno, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Design of

a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator,”
Proc. of 2006 IEEE/IFIP Int. Conf. on Very Large Scale Integration (VLSI-SoC), pp. 267-271,
Niza, Francia, Octubre 2006. (ISBN: 3-901882-19-7).
- R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “A

Design Tool for High-Resolution High-Frequency Cascade Continuous-Time ΣΔ Modulators,”
Proc. of 2007 SPIE Microtechnologies for the New Millenium – VLSI Circuits and Systems Conf.,
Maspalomas (Gran Canaria), Mayo 2007. (ISBN: 9780819467188).
!
CASCADE CONTINUOUS-TIME Σ∆ MODULATORS WITH

REDUCED NUMBER OF ANALOG COMPONTENTS −
APPLICATION TO VDSL
R.Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández
Instituto de Microelectrónica de Sevilla, IMSE (CNM-CSIC)
Edif. CNM-CICA, Avda. Reina Mercedes s/n, 41012 Sevilla, SPAIN
Phone: +34 955056666, FAX: +34 955056686, E-mail: jrosa@imse.cnm.es
Abstract tectures than using a DT-to-CT transformation. As an applica-

tion, the proposed methodology is used to find optimum CT
This paper describes new cascaded continuous-time Σ∆ modu-
Σ∆Ms for Very high-rate Digital Subscriber Line (VDSL).
lators intended to cope with VDSL specifications. These mod-
Three fifth-order cascade topologies are synthesized: 2-1-1-1,
ulators have been synthesized using a new methodology that is
2-2 and 3-2. These Σ∆Ms are designed for 12-bit@20-MHz
based on the direct synthesis of the whole cascaded architec-
specifications and their performances are compared in terms
ture in the continuous-time domain instead of using a dis-
of time-domain simulations that take into account critical error
crete-to-continuous time transformation as has been done in
mechanisms like mismatch and clock jitter error.
previous approaches. This method allows to efficiently place
the zeroes/poles of the loop-filter transfer function and to re- 2. Direct synthesis of cascade CT Σ∆Ms
duce the number of analog components, thus leading to more
efficient topologies in terms of circuitry complexity, power Fig.1 shows the conceptual block diagram of a m-stage cas-
consumption and robustness with respect to circuit parasitics. caded CT Σ∆M. Each stage, consisting of a single-quantizer
CT Σ∆M, re-modulates a signal containing the quantization
1. Introduction error generated in the previous stage. Once in the digital do-
main, the outputs, y i , of the stages are properly processed and
Although most reported Sigma-Delta Modulators (Σ∆Μs)
combined (by the cancellation logic) in order to cancel out the
have been implemented using Discrete-Time (DT) circuits, the
quantization errors of all the stages, but the last one in the cas-
increasing demand for broadband data communication sys-
cade. This latter error appears at the overall modulator output
tems has motivated the use of Continuous-Time (CT) circuit
shaped by a function of order equal to the summation of the
techniques. In addition to show an intrinsic antialiasing filter-
orders of all the stages.
ing, CT Σ∆Ms provide potentially faster operation with lower
power consumption than their DT counterparts [1][2]. Howev- Cascade CT Σ∆Ms are normally synthesized from equivalent
er CT Σ∆Ms are more sensitive than DT Σ∆Ms to some circuit (well-known) DT systems and use the same digital cancella-
errors, namely: clock jitter, excess loop delay and technology tion logic [7]. This DT/CT equivalence can be guaranteed be-
parameter variations [1][2]. The latter are specially critical for cause the overall open loop transfer function of each stage in
the realization of cascade architectures. This has forced the Fig.1 is in fact a DT system [1]. However, in order to get a
use of single-loop topologies in most reported silicon proto-
types even thought low oversampling ratios ( < 12 ) are needed E1(z)
[3][4], whereas very few cascaded CT Σ∆M Integrated Cir- x(s) y (z)
CT Σ∆M1 1
Cancellation
CL1 Logic
cuits (ICs) have been reported [5].
E2(z)
The need to achieve medium-high resolutions ( > 12bits )
y (z)
within high signal bandwidths ( > 20MHz ) while guaranteeing CT Σ∆M2 2 yo(z)
stability, has prompted the interest in proper methods for the
CL2
..
synthesis of high-order cascade CT Σ∆Ms [6]-[8]. These .. .. .
methods are based on applying a DT-to-CT transformation to . .Em(z)
an equivalent DT topology that fulfils the required specifica- y (z)
tions. In most cases, the use of such a transformation is nor- CT Σ∆Mm m CLm
mally translated into an increase of the analog circuit com-
plexity with the subsequent penalty in silicon area, power con-
E2(z)
sumption and sensitivity to parameter tolerances.
x2(s) F(s) y2(z)
This paper presents a direct synthesis method of cascaded CT +
Σ∆Ms which, dispensing with the DT-to-CT equivalence, y2(s)

makes it possible to reduce the analog circuitry complexity DAC
To next stage
and place the zeroes/poles of the quantization noise transfer
function in an optimal way, thus yielding to more robust archi- Figure 1. Conceptual block diagram of a cascaded CT Σ∆M.
functional CT Σ∆M while keeping the cancellation logic of the k–1

original DT Σ∆M, every state variable and DAC output must –1
Ek ( z ) + Z L [ H D F ik ] yi ( z )
be connected to the integrator input of later stages [7]. This in- nT s
creases the number of analog components, i.e transconductors, i=1
y k ( z ) = -------------------------------------------------------------------------------------------
- (2)
amplifiers and DACs. As an illustration, Fig.2(a) shows a cas- –1
caded 2-1-1 CT Σ∆M obtained from an existing DT Σ∆M [9]. 1 – Z L [ H D F kk ]
nT
s
Note that at least eight scaling coefficients ( k g2 – 9 ) and their
–1
corresponding signal paths are needed to connect the different where Z stands for the Z-transform , L is the inverse
stages of the modulator. The number of integrating paths can Laplace transform, H D ≡ H DAC ( s ) is the transfer function of
be reduced − as illustrated in Fig.2(b) − if the whole cascaded the DAC, and
Σ∆M is directly synthesized in the CT domain.
Input Quantizer j
For that purpose, let us consider the more general case of the F ij ≡ F ij ( s ) = ----------------------------------------- (3)
yi ( s )
m-stage cascaded CT Σ∆M shown in Fig.1. The overall out-
represents the transfer function from y i ( s ) to the input of j-th
put, y o , is given by:
quantizer.
m
Using the following notation
yo(z ) = y k ( z )CL k ( z ) (1)
–1
k=1
Z km ≡ Z L ( H D F km ) (4)
nT
s
where y k ( z ) and CL k ( z ) represent respectively the output
and partial cancellation logic transfer function of the k-th the output of each stage is given by:
stage. k–1
Ek ( z ) Z ik y i ( z )
If the modulator input, x ( t ) , is set to zero, the output of each y k ( z ) = ----------------- + ------------------
- (5)
1 – Z kk 1 – Z kk
stage can be written as: i=1
and the output of the modulator can be written as:
x(s) kin1 kg1 E1(z)
1 1 m m k–1
Tss Tss CL1 Ek 1
kfb1 kfb2 yo = y k CL k = ----------------
- + ----------------- Z ik y i CL k (6)
1 – Z kk 1 – Z kk
y1(s) y1(z)
DAC k=1 k=1 i=1
kg2 E2(z) The partial cancellation logic transfer functions ( CL k ) can be
kg3 1 yo(z) calculated by imposing the cancellation of the transfer func-
CL2 tion of the first m – 1 quantization errors E k ( z ) in (6). This
kg4 Tss
(a) kfb3 gives:
y2(s) y2(z)
DAC
kg5 –1
kg6 E3(z) – Z L [ H D F km ] CL m ( z )
nT
kg7 1 – Z km CL m s
kg8 Tss
CL3 CL k ( z ) = ------------------------ = -------------------------------------------------------------------------- (7)
kg9 1 – Z mm –1
1 – Z L [ H D F mm ]
kfb4 y3(s) y3(z) nT s
DAC
E1(z) where the partial cancellation logic transfer function of the last
x(s) kin1 kg1
1 1 stage, CL m ( z ) , can be chosen to be the simplest form that pre-
Tss Tss CL1 serves the required noise shaping.
kfb1 kfb2
y1(s) y1(z) Note that the design equations (1)-(7) do not only take into ac-
DAC
count the single-stage loop filter transfer functions ( F ii ), but
kin2
E2(z) also the inter-stage loop filter transfer functions ( F ij, i ≠ j ).
1 yo(z) The latter are continuous-time integrating paths appearing
(b) Tss CL2
kfb3 only when the modulator stages are connected to form the cas-
y2(s) y2(z) caded Σ∆M and must be included in the synthesis methodolo-
DAC gy to obtain a functional modulator with minimum number of
kin3 E3(z) inter-stage paths.
1
Tss CL3 Therefore, the following procedure can be used in a systematic
kfb4
y3(s) y3(z) methodology for the synthesis of cascaded CT Σ∆Ms:
DAC
• First, the poles of single-stage transfer functions ( F ii ( s ) )
Figure 2. Cascaded 2-1-1 CT Σ∆M architecture obtained (a) from an equiva-
lent DT Σ∆M (b) using the proposed method. are optimally placed in the signal bandwidth for given
specifications. This process is carried out entirely in the CT

18
domain and no equivalence to an existing DT modulator
needs to be imposed.
(dB)
16
Loss (dB)
• Second, once the individual stages are designed and 14
SNRLoss
optimized, cancellation logics are calculated using (7). (a)
12
SNR
For illustrative purposes, the 2-1-1 CT Σ∆M of Fig.2(b) was
10
synthesized using (1)-(7) to achieve 16-bit resolution in a
750-kHz bandwidth, with a sampling frequency of 48MHz 8
2.5
(oversampling ratio, M = 32 ) [9]. For simplicity, in order to σgm(%)

2
1.5 0.6
0.4
0.2 0
0.8 σc(%)
facilitate the comparison of the performance of both modula- 1 1
tors in Fig.2, the coefficients of the first stage

( k in1, k g1, k fb1, k fb2 ) are taken to be equal in both systems
14
and are obtained from a DT-to-CT transformation of the first
SNR Loss (dB)

12
stage of a DT Σ∆M in [9]. The rest of coefficients in Fig.2(b) 10
are taken such that the time constant of the integrators is the (b)
8
inverse of the sampling frequency ( T s = 1 ⁄ f s ):
6
k in1 = – k fb1 = 1 ⁄ 4 ; k fb2 = – 3 ⁄ 8

(8) 4
2.5
k g1 = k in2 = – k fb3 = k in3 = – k fb4 = 1 2
0.2
0
1.5
σgm(%) 0.6
0.4
Hence, the single-loop and inter-stage transfer functions are 1 1

0.8
σc(%)
given by:
Figure 3. Effect of mismatch on the SNR of a cascaded 2-1-1 CT Σ∆M
3T s 1 obtained from: (a) an equivalent DT Σ∆M; (b) proposed method.
– -------- s + ---
8 4 –1
F 11 = ------------------------------ F 22 = F 33 = -------- tion, and the SNR with 90% of the 150 simulations above it. It
( sT s )
2 sT s
is shown that the lower analog component count in Fig.2(b) is
(9) reflected in a lower variance of the modulator coefficients,
3T s 1
– -------- s + --- leading to a better behaviour in terms of sensitivity to mis-
8 4 –1 match.
F 13 = ------------------------------ F 23 = ---------------
4 2
( sT s ) ( sT s )
3. Application to VDSL
and the partial cancellation logic transfer functions can be cal-
culated using (7)-(9). Considering a Non-Return-to-Zero As an application of the synthesis methodology proposed in
(NRZ) DAC, the following cancellation logics are derived: previous section, three 5th-order cascaded CT Σ∆Ms, shown
–1 in Fig.4, were synthesized to cope with VDSL specifications:
z –1 –2 –3
CL 1 = ------- ( 7 + 29 z – 7z – 5z ) 12-bit resolution within a 20-MHz signal bandwidth. In order
48 to fulfil these specifications without being limited by the clock
–1 –1 –1 2 (10) jitter error, the sampling frequency, f s , and the number of bits
CL 2 = z ( 1 + z ) ( 1 – z )
of the internal quantizers (and DACs), B , must be properly
–1 3 chosen. In the case of 5th-order modulators like those shown
CL 3 = 2 ( 1 – z )
in Fig.4, the in-band jitter noise power is minimized for
where CL3 is chosen to have three zeroes at DC, correspond- f s = 240MHz and B = 4 [11].
ing to the zeroes contributed by the first three integrators. Another critical source of error in CT Σ∆Ms is the excess loop
In order to compare the robustness of both modulators in delay. As shown in [12] this error can be compensated by add-
Fig.2, the effect of mismatch on the Signal-to-Noise Ratio ing an extra feedback branch between the output and the input
( SNR ) was also simulated using SIMSIDES, a SIM- to the quantizer (DAC2 in Fig.4) and two D-latches. By adding
ULINK-based time-domain behavioural simulator for Σ∆Ms this extra branch with the appropriate gain, the loop impulse
[10]. For this purpose, maximum values of mismatch were es- response is exactly the same as that of the original. This extra
timated for a 0.13 µm CMOS technology and both modulators feedback term can be easily included in the calculation of the
in Fig.2 were simulated considering a Gm-C implementation. cancellation logic. In a practical implementation it could be
The results are shown in Fig.3 where the SNR loss is repre- advantageous to make DAC2 programmable [4].
sented as a function of the standard deviation of the transcon- Considering the factors above, the CT Σ∆Ms in Fig.4 were
ductances ( σ gm ) and capacitances ( σ C ). For each point of synthesized using the methodology described in Section 3,
these surfaces, 150 simulations were carried out using random taking into account the following considerations:
variations with the standard deviation given in the diagrams.
The value of SNR loss represented in Fig.3 stands for the dif- • The first stage of the 2-1-1-1 architecture (Fig.4(a)) is
ference between the ideal SNR , i.e with no parameter varia- formed by a resonator which has its poles placed at
Rin C1 kff ω p = 2π 7 ⁄ 9 B w , in order to minimize the quantization

x(s)
Rfb C2
kg2 Noise Transfer Function (NTF) in the signal bandwidth,
− B w . Resistor variations can be tuned out using a
CL1
+
Rr kg1 combination of a discrete rough tuning of the resistors
DAC2 CLK
( R in , R fb and R r ) and a continuous fine tuning of the
D D
DAC1 Latch Latch transconductors k ff and k g1 . This tuning can be also used to
cancel the effect of finite Gain-Bandwidth product ( GB ) of
CLK CLK
C3 kg3 the front-end opamp, due to the fact that this error can be
CL2 modelled as an integrator gain error [4]. All the other
kin2
(a) kfb2 yo(z)
transconductors could be tuned in order to keep the time
DAC3
CLK
constant C ⁄ g m unchanged over C variations.
C4 • An additional resonator has been used in the 2-2-1
CL3
kin3
kg4 architecture (Fig.4(b)), in order to optimally distribute the
kfb3
CLK poles of NTF [13].
DAC4
C5
• The 3-2 modulator shown in Fig.4(c) includes a first stage
kin4
CL4 which consists of an integrator and a resonator. This
kg5
kfb4 topology allows the same optimum pole positioning as in the
CLK
DAC5 2-2-1 modulator with one less stage. However, stability
problems might arise that compromise the modulator
x(s)
Rin performance.
Rfb
−
C2
kg2
Table 1 shows the transforms of F ij ( s ) and cancellation log-
CL1
+ ics CL i of the modulators in Fig.4, obtained using the formu-
kg1
Rr
DAC2 CLK
lation described in previous section. Coefficients n ij − not ex-
D D
plicitly shown in Table 1 for simplicity − are function of the
DAC1 Latch Latch loop filter coefficients. These coefficients are obtained from a
CLK CLK
simulation-based procedure that − starting from nominal val-
kff2
ues required to place the zeroes of the corresponding NTF −
(b)
kin2 kg3 kg4 yo(z) optimizes the modulator performance in terms of dynamic
C3
CL2 range and stability. For this purpose, loop filter coefficients are
kfb2
C4 varied in a range of up to ± 20% around their nominal values
DAC2 CLK
kr2 in order to achieve the maximum Signal-to-Noise Ratio (SNR)
D D
DAC1 Latch Latch while keeping stability.
CLK CLK The outcome of the optimization process − entirely done in the
C5
CL3
CT domain − is summarized in Table 2. This table includes the
kin3
kg5 values of loop filter coefficients, k i (implemented as transcon-
kfb3
CLK ductances) as well as the capacitances, C i , and resistances, R i
DAC4
obtained from the optimization process.
kff1
kff2
4. Simulation results
C1
Rin
x(s) kg1 kg3
The modulators in Fig.4 were simulated using SIMSIDES
kg2 C3
Rfb − C2
CL1
[10]. Fig.5 shows the ideal output spectra of the modulators
+ when clocked at f s = 240 MHz . It can be observed the effect
kr1
DAC2 CLK of the resonators poles distributed within the signal band-
D D width.
(c) DAC1 Latch Latch
yo(z)
In addition to the ideal performance described above, the ef-
CLK CLK
kff3 fect of most critical limiting factors has been taken into ac-
kg4 kg5 count in the high-level design. Two critical limiting factors in
C4 C5
CL2 cascaded Σ∆Ms, and particularly in their CT implementation,
kin2
are circuit tolerances and component mismatch. The first one
kfb2 CLK
kr2
DAC2 can be controlled by using tuning of time constants [3][4] or
DAC1
D
Latch
D
Latch digital calibration [5]. However mismatch error still remains.
In order to evaluate the impact of this error on the perform-
CLK CLK ance of the modulators in Fig.4, maximum values of mismatch
Figure 4. Cascaded CT Σ∆Ms synthesized for VDSL: (a) 2-1-1-1; (b) 2-2-1;
were estimated for a 0.13 µm CMOS technology considering a
(c) 3-2. Gm-C implementation. The results of this analysis are shown
in Fig.6 where the SNR is represented as a function of the stan- lustration, Fig.7 shows the output spectra of the modulators
dard deviation of the transconductances ( σ gm ) and capaci- taking into account the non-idealities listed in Table 3. The ef-
tances ( σ C ). For each point of these surfaces, a MonteCarlo fective resolution is ≅ 13.4 bits and ≅ 13.2bits for the
analysis of 150 simulations was carried out. The value of the modulators in Fig.4(b) and (c), respectively.
SNR represented in the vertical axis of Fig.6 is obtained by
90% of the simulations for each case of σ gm and σ C . Note Conclusions
that even in the worst-case mismatch, the resolution is above It has been shown that more efficient cascade CT Σ∆Ms can
the specified ( 72-dB ). be generated if their design is directly done in the CT domain.
Several architectures have been synthesized and designed to
Finally, the modulators in Fig.4(b)-(c) were high-level sized, achieve VDSL system requirements: 12-bit@20MHz . Behav-
i.e, the system-level specifications ( 12-bit@20-MHz ) were ioural time-domain simulations considering their most critical
mapped onto building-block specification using statistical op- limiting factors validate the presented approach.
timization for design parameter selection, and behavioural
simulation for evaluation. The results of this sizing process are Acknowledgments
summarized in Table 3, showing the maximum (minimum) This work has been supported by the Spanish Ministry of Sci-
values of the circuit error mechanisms that can be tolerated in ence and Education (with support from European Regional
order to fulfil the required modulator performance. As an il- Development Fund) under contract TEC2004-01752/MIC.
Modulator Function Transforms Cancellation logics
4 3 2
–1 n 14 z + n 13 z + n 12 z + n 11 z + n 10
Z ( L ( H D F 14 ) ) = --------------------------------------------------------------------------------
3 2
- –1 –1 –2 –3 –4
nT
( z – 1 ) ( z – 2 cos ( T s ω p ) z + 1 ) CL 1 = – z ( n 14 + n 13 z + n 12 z + n 11 z + n 10 z )
2
– ( z + 4z + 1 )- 1 –1 –1 –2 –1 –2
–1
Z ( L ( H D F 24 ) ) = --------------------------------- CL 2 = --- z ( 1 + 4z – z ) ( 1 – 2 cos ( T s ω p ) z + z )
nT 3 6
2-1-1-1 (z – 1 )
1 –1 –1 –1 –1 –2
–1 –( z + 1 ) CL 3 = --- z ( 1 + z ) ( 1 – z ) ( 1 – 2 cos ( T s ω p ) z + z )
Z ( L ( H D F 34 ) ) = ---------------------2- 2
nT
2 (z – 1 ) –1 2 –1 –2
CL 4 = ( 1 – z ) ( 1 – 2 cos ( T s ω p ) z +z )
–1 –1
Z ( L ( H D F 44 ) ) = -----------
nT z–1
3 2
–1 n 14 z 4 + n 13 z + n 12 z + n 11 z + n 10 CL 1 = – z –1 ( n 14 + n 13 z
–1
+ n 12 z
–2
+ n 11 z –3 + n 10 z –4 )
Z ( L ( H D F 13 ) ) = ----------------------------------------------------------------------------------------------------------------------------------------
2 2
nT
( z – 1 ) ( z – 2 cos ( T s ω p1 ) z + 1 ) ( z – 2 cos ( T s ω p2 ) z + 1 )
CL 2 = – z –1 ( n 22 + n 21 z –1 + n 20 z – 2 ) ⋅
2
2-2-1 –1 n 22 z + n 21 z + n 20 ( 1 – 2 cos ( T s ω p1 ) z –1 + z –2 )
Z ( L ( H D F 23 ) ) = ---------------------------------------------------------------------------
2
-
nT
( z – 1 ) ( z – 2 cos ( T s ω p2 ) z + 1 ) CL 3 = ( 1 – 2 cos ( T s ω p1 ) z –1 + z –2 ) ⋅
–1 –1 ( 1 – 2 cos ( T s ω p2 ) z –1 + z –2 )
Z ( L ( H D F 33 ) ) = -----------
nT z–1
3 2
n 14 z 4 + n 13 z + n 12 z + n 11 z + n 10 –1 –2 –3 –4
–1
Z ( L ( H D F 12 ) ) = ---------------------------------------------------------------------------------------------------------------------------------------- CL 1 = – z – 1 ( n 14 + n 13 z + n 12 z + n 11 z + n 10 z )
nT 2 2
( z – 1 ) ( z – 2 cos ( T s ω p1 ) z + 1 ) ( z – 2 cos ( T s ω p2 ) z + 1 )
3-2 CL 2 = ( 1 – 2 cos ( T s ω p1 ) z –1 + z –2 ) ( 1 – z ) ⋅
–1
–1 n 21 z + n 20
Z ( L ( H D F 22 ) ) = -----------------------------------------------------------
2 ( 1 – ( n 21 + 2 cos ( T s ω p2 ) )z – 1 + ( 1 – n 20 )z –2 )
nT
( z – 2 cos ( T s ω p2 ) z + 1 )
Table 1: Summary of the characteristics of the cascaded CT Σ∆Ms designed using the proposed method.
2-1-1-1 Modulator 2-2-1 Modulator 3-2 Modulator

R in = R fb = 2 kΩ ; R r = 8.2 kΩ R in1 = Rfb1 = 2 kΩ ; R r1 = 9 kΩ Rin1 = R fb1 = 2 kΩ
C 1 = 1.875 pF C 2…5 = 0.75 pF C 1 = 1.875 pF C 2…5 = 0.75 pF C 1 = 10 pF C 2…5 = 1 pF
k g1 = 150 µS k g2 = 48 µS k g1 = 166 µS k g2 = 30 µS k g1 = 312 µS k g2 = 130 µS
k g3…5 = 20 µS k ff = 60 µS k g3 = 200 µS k g4 = 46 µS k g3 = 26 µS k g4 = 182 µS
k in2…4 = k fb 2…4 = 180 µS k g5 = 20 µS k r2 = 13 µS k g5 = 104 µS k ff1 = 208 µS
k ff1 = 63 µS k ff2 = 112 µS k ff2 = 78 µS k ff3 = 130 µS
k in2 = k fb2 = 100 µS k in2 = k fb2 = 130 µS
k in3 = k fb3 = 180 µS k r1 = 208 µS k r2 = 26 µS
Table 2: Loop filter coefficients of the modulators in Fig.4.

References Solid-State Circuits, Vol. 39, pp. 1056-1063, July 2004.

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[10]J. Ruiz-Amaya, J.M. de la Rosa, F. Medeiro, F.V. Fernández, R. del Río, B.
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Magnitude (dB)
-80
(a) -100
for the High-Level Synthesis of Discrete-time and Continuous-Time Σ∆
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Symp. Circuits and Systems, Vol V., pp. 97-100, 2004.
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10
4
10
5
10
6
10
7
10
8 Circuits and Systems. Accepted for its publication.
Frequency (Hz) [12]S. Yan, E. Sánchez-Sinencio: “A Continuous-Time Σ∆ Modulator With
0
88-dB Dynamic Range and 1.1-MHz Signal Bandwidth”. IEEE Journal of
-20
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-40
[13]R. Schreier: “An Empirical Study of High-Order Single-Bit Delta-Sigma
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Magnitude (dB)
-80
(b) -100 Front-end opamp Fig. 4(b) Fig. 4(c)

-120
-140 GB >600 MHz >600 MHz

-160
DC Gain >70 dB >60 dB
-180
-200
Phase Margin 60º 60º
4 5 6 7 8
10 10 10
Frequency (Hz)
10 10
Parasitic Input Capacitance <0.2 pF <0.2 pF
0
-20
Parasitic Output Capacitance <0.2 pF <0.2 pF
-40 Diff. Output Swing >0.5 V >0.5 V
-60 Transconductors
Magnitude (dB)
-80
DC Gain >50 dB >60 dB
(c) -100
-120
Diff. Input Amplitude 0.3 V 0.4 V
-140 Diff. Output Amplitude 0.3 V 0.4 V
-160
Third-order non-linearity >56 dBV >53 dBV
-180
-200
10
4
10
5
10
6
10
7
10
8 Table 3: High-level sizing of the modulators in Fig.4(b) and Fig.4(c).
Frequency (Hz)
0
Figure 5. Ideal output spectra of the cascaded CT Σ∆Ms in Fig.4: (a) -20
2-1-1-1. (b) 2-2-1. (c) 3-2.
-40
Magnitude (dB)
85 -60
(a) -80
90% SNR
80
-100
(a)
-120
-140
75
1
1.5 1 -160 5 6 7 8
0.5 10 10 10 10
σgm(%) 2 0
Frequency (Hz)
0.5
1 σc(%)
2.5 0 0
-20
88 -40
86
(b) -60
Magnitude (dB)
84
90% SNR
-80
82
(b)
80 -100
78
-120
76
1
-140
1.5 1
0.5
0 -160
σ gm(%) 2
0.5
1 σc(%)
2.5 0 10
5
10
6
10
7
10
8
Frequency (Hz)
Figure 6. SNR loss vs. mismatch for: (a) 2-2-1 CT Σ∆M. (b) 3-2 CT Σ∆M. Figure 7. Output Spectra for: (a) 2-2-1 CT Σ∆M. (b) 3-2 CT Σ∆M.
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A design tool for high-resolution high-frequency cascade continuous-

time modulators
R. Tortosa, R. Castro-López, J.M. de la Rosa, A. Rodríguez-Vázquez and F V. Fernández

Instituto de Microelectrónica de Sevilla (CSIC and Universidad de Sevilla)
Edificio CICA. Avda. Reina Mercedes s/n, E-41012- Sevilla, Spain
Tel.: +34 955 056 666. Fax: +34 955 056 686
E-mail: {tortosa, castro, jrosa, angel, pacov}@imse.cnm.es
ABSTRACT
This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cas-
cade modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy-
efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time
domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architec-
tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology
will be illustrated via the design of a 12 bit 20 MHz CT modulator in a 1.2V 130nm CMOS technology.
Keywords: Continuous-time modulators, high-resolution high-frequency data converters, design automation, CAD
1. INTRODUCTION
The ever shrinking minimum feature size of CMOS technologies has triggered a revolution in integrated designs, from
application-specific integrated circuits (ASICs) to entire systems on a single chip (SoCs). Notwithstanding, a critical design
productivity lag has been reported [1]: with a productivity growth rate of 21%, compared to a 58% complexity growth rate,
design cost is increasing rapidly. Taking into account the ever demanding time-to-market pressures, this picture is clearly
worrisome. For analog and/or mixed-signal (AMS) design the situation is even worse because of many different reasons,
the most significant being the lack of commercial CAD tools and methodologies to efficiently support the analog design.
The design methodologies and tools in this paper try to reduce this design gap for a class of circuits: Continuous-Time (CT)
cascade modulators (conceptually shown in Fig.1), although some of the techniques and tools presented are applicable
to other classes. The selection of this circuit class has been driven by the demands of new generations of high-speed
wireless/wireline communication terminals, which require broadband Analog-to-Digital Converters (ADCs) capable of
digitizing 20-MHz wideband signals with effective resolutions over 12 bits and with minimum power consumption.
Although most reported modulators have been implemented using Discrete-Time (DT) circuits, the increasing demand
for broadband data communication systems has motivated the use of CT techniques. In addition to showing an intrinsic
antialiasing filtering, CT modulators provide potentially faster operation with lower power consumption than their DT
counterparts [2],[3].
In spite of their mentioned advantages, CT modulators are more sensitive than DT ones to some circuit errors, namely:
clock jitter, excess loop delay and technology parameter variations [2]. The latter are specially critical for the realization
of cascaded architectures. This explains the use of single-loop topologies in most reported silicon prototypes [4][5],
whereas very few experimental results of cascaded CT modulators have been reported [6]. Although single-loop CT
topologies have potentially a smaller sensitivity to technological process variations than cascade CT topologies, the
possibility to avoid stability problems in the latter make them specially appealing for high-resolution high signal bandwidth
operation.
This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time cascade sigma-
delta modulators. The main components of this systematic methodology, introduced in Section 2, are:
a) Performance modeling of dominant error sources at modulator level (Section 3).
b) Efficient behavioral simulator with variable levels of modeling accuracy for architectural synthesis, specification
transmission and hierarchical verification (Section 3).
E1(z)
x(s) y (z) Cancellation
CT M1 1 CL1 Logic
E2(z)
E2(z)
y (z)
M2 2 yo(z)
CT CL2
.. x2(s) F(s) y2(z)
.
+
.. .. y2(s)
. . Em(z)
To next stage
DAC
y (z)
CT Mm m CLm
Figure 1: Conceptual block diagram of a cascade CT M.
c) A high-level topological synthesis method in the continuous-time domain (Section 4).

d) Global and local optimization core for topology exploration and specification transmission (Section 5).
The design of a 12 bit 20 MHz CT sigma-delta modulator in a 1.2V 130nm CMOS technology is used as illustrative
example of each step in Section 6.
2. SYSTEMATIC SYNTHESIS METHODOLOGY

Synthesis of high-speed continuous-time modulators is a complex task which requires systematic design methods and
customized tools. The objective of the synthesis process is to get a CT modulator able to meet the objective performance
specifications, with a minimum power consumption and a minimum occupation of silicon area.
The synthesis procedure, schematically shown in Fig.2, starts by an architectural exploration, which basically tries to obtain
candidate architectures, defined by the order of the modulator, L, the number of bits of the quantizer(s), B, and the
oversampling ratio, M, which allows to obtain a certain SNR specification. This architectural exploration is performed by
using analytical expressions which model the dominant error sources limiting the achievable SNR. The modeling of these
error sources will be discussed in Section 3.
Architectural exploration
Architectural Architectural refinement Optimization core

synthesis
Topological synthesis
High-level Behavioral verification

Behavioral simulation Optimization core
sizing
Circuit-level Full electrical

Behavioral simulation Optimization core simulation
sizing
Figure 2: Synthesis procedure

The output of this architectural exploration is a set of candidate architectures that are potentially capable of meeting the
modulator performance specifications. Frequently, more than one architecture is considered for later stages for several
reasons:
• The modeling equations are very approximate and, therefore, there is no guarantee that the selected architecture
will continue to meet the performance specifications when more accurate models containing the non-idealities
of the particular physical implementation are used.
• The optimal architecture is that which, meeting the performance constraints, minimizes objectives like power
consumption or area occupation. Exploration criteria at the architectural level include considerations like order
minimization, minimization of oversampling ratio to avoid infeasible sampling frequencies in terms of power
consumption and minimization of number of the bits in the quantizer to avoid the use of linearization tech-
niques [4] or digital calibration [7]. As can be observed, power or area criteria at this level are of a qualitative
nature and, therefore, any ranking of candidate architectures performed may suffer significant changes when
progressing through the synthesis process.
The set of candidate architectures is refined using very simple functional models combined with optimization. The
simulation is performed at the functional block level as no topology has been synthesized yet.
The following step is the topological synthesis, i.e., the definition of the cascade architecture, the intra- ant inter-stage loop
filter transfer functions and the cancellation logic functions. A direct synthesis method in the continuous-time domain is
used here instead of the more conventional discrete-time to continuous-time transformation of an equivalent discrete-time
topology. The direct topological synthesis method is described in Section 4.
Then, an accurate behavioral simulation is used with the global optimization procedures to find out the maximum values
of non-idealities of the different building blocks which can be tolerated while still meeting the modulator performance
specifications. At this level, power consumption estimates are much more detailed as relationships with each building block
specifications can be established [8]. Exhaustive verification under different operating conditions is performed using
accurate behavioral simulation. If a consequence of this verification, some performance specification degrades beyond
certain limits, the high-level synthesis and/or the architectural synthesis are performed again under harder constraints.
Specification transmission can be made more efficient if Pareto-optimal fronts of candidate architectures are available.
These fronts represent trade-off hypersurfaces between the different circuit performances [9],[10]. For illustration´s sake,
Fig.3(a) shows the trade-offs between dc-gain, gain-bandwidth product (GB) and power for a cascode operational
amplifier. Projection on the XY plane allows to easily visualize the best trade-off between dc gain and GB that the circuit
at hand can achieve. Although not easily visualized, Pareto fronts have usually higher dimensionality: all specifications of
interest of the building block. Pareto fronts make high-level exploration more efficient and allow to get better designs as
there is information at the modulator level on which are the achievable specifications of each sub-block as well as which
is the power and area budget for them.
The last step of the synthesis procedure is the sizing of the building blocks. This sizing is performed by combining an
electrical simulator with the global optimization procedures described in Section 5. The implementation of the optimization
core is flexible enough to incorporate valuable design knowledge of each building block. At the optimization level, design
knowledge brings knowledge of the feasibility space, limiting, therefore, the exploration space and making the synthesis
process more efficient and/or enhancing the optimization results.
With all blocks sized, a final verification of the complete modulator at the electrical level at a limited number of operating
conditions is performed. This verification is complemented by a more exhaustive verification at the behavioral level with
information extracted at the electrical level. Performance degradations beyond tolerable margins induce redesign iterations
at the circuit and/or modulator levels.
3. PERFORMANCE MODELING AND SIMULATION

As shown in Section 2, design space exploration and specification transmission rely on multiple performance evaluations,
with different levels of abstraction and accuracy. At a high level of abstraction, modulator performance is modeled by a set
of closed-form equations, relatively inaccurate, but with essential information on the design parameters dominating the
system behavior. The signal to noise ratio of a modulator is given by:
2
A 2
SNR = ------------- (1)
P
× 108
8
GB (Hz)
Pow(W) 7
GB (Hz) A0 (dB)
0
50 55 60 65 70 75 80 85 90 95 100
A0 (dB)
(a) (b)
Figure 3: (a) Gain / GB / Power Pareto-optimal hypersurface for a cascode operational amplifier; (b) Gain / GB projection.
where A represents the magnitude of the input signal and P represents the in-band error power. Ideally, the in-band error
power only contains the quantization noise P q :
2 Bw
X FS 2
P q = ------------------------------ N TF f df (2)
B 2
6f s 2 – 1 0
being X FS the full-scale of the quantizer, B the number of bits of the quantizer, f s the sampling frequency and B w the
signal bandwidth. However, in practice, the error power contains terms due to: quantization error power enlargement, DAC
non-linearities, capacitor mismatching, thermal noise, clock jitter, finite amplifier gain, incomplete amplifier settling, etc.
Therefore, the in-band error power becomes:
P = P q + P q + P thermal + P jitter + P DAC + P settling + (3)
A dominant error source in high-speed continuous-time modulators is the error power due to clock jitter. For this reason,
closed-form modeling of the influence of jitter is object of special attention. The error power due to clock jitter in CT
modulators with non-return-to-zero (NRZ) Digital-to-Analog Converters (DACs) is [11]:
2 2 2
2 A i X FS f s
P jitter = B w T
------------- + -------------------------
- g p L (4)
2f s B 2
6 2 –1
where A and i are the amplitude and frequency of the input signal, g p L is a function arising from the state-
space representation of the noise transfer function of the modulator and depends on the modulator order. It can be seen that
it has two terms: one which depends of the modulator input and decreases with the sampling frequency and another one
which depends on the modulator architecture and increases with sampling frequency.
The use of the dominant error power terms in eq. (3) (shown in eqs. (2) and (4)) allows to extract candidate triads{ L , B ,
M } with better performance in terms of distribution of the Noise Transfer Function (NTF) zeroes and insensitivity to clock
jitter.
Topology refinement, specification transmission and verification require performance evaluation mechanisms with much
higher accuracy than that provided by approximate equations like (2)-(4). Moreover, as this performance evaluation is
frequently performed within an iterative optimization process, simulation efficiency is critical for the synthesis process.
modulators are strongly non-linear sampled-data circuits, and hence, simulation of their main performance
specifications has to be carried out in the time domain. Due to their oversampling nature, this means that long transient
simulations are necessary to evaluate their main figures of merit. Therefore, transistor-level simulations yield excessively
long computation times. An appropriate trade-off between simulation accuracy and efficiency is accomplished by using
behavioral simulation. In this approach, the modulator is partitioned in a set of building blocks which are modeled by a set
of equations, containing the main block functionality, as well as the most important non-idealities. The selected
implementation platform has been Matlab/Simulink [12] due to its wide extension, powerful data processing tools and
flexibility to build block libraries.
Behavioral models of the continuous-time building blocks, are described by a set of continuous-time state-space equations
which are integrated by Simulink solvers. To increase simulation efficiency, we make extensive use of S-functions [13].
This mechanism allows to model non-idealities by embedding C-code routines instead of interconnecting numerous
Simulink elementary blocks. The basic building blocks modeled in the behavioral simulator, as well as its non-idealities
are summarized in Table 1.
Table 1: Basic building blocks and non-idealities modeled in the behavioral simulator
Block Non-idealities
Finite and non-linear gain, dynamic limitations (parasitic capaci-
Integrators tors, one- and two-pole transconductor model), thermal noise,
finite output swing, linear input range, offset.
Resonators Non-idealities associated to the integrators.
Comparators Offset, hysteresis, signal-dependent delay
Quantizers
Integral non-linearity, gain error, offset, jitter, excess loop delay.
/DACs
The developed toolbox includes several libraries of CT building blocks (integrators and resonators) considering different
circuit implementations: gm-C, gm-MC, active-RC and MOSFET-C. As an illustration, let us consider, for instance, the
gm-C integrator depicted in Fig.4(a). The ideal behavior of this circuit is described by the following differential equation:
d
gm vi t + ii t = C vo t (5)
dt
where v i t is the input voltage, i i t is the input current (provided by the feedback DAC block), and v o t is a state
variable, which can be integrated by the Simulink solvers very efficiently.
ii +
ii t ii t
vo t va t vo t
vi gm vo
vi t gm vi ro Cp C v i t g ma v i t ra C ro C C
C a gm va t p
-
(c) First Stage Second Stage

(a) (b)
Figure 4: (a) gm-C integrator and equivalent circuit with (b) a one-pole model and (c) a two-pole model.
Fig.5 shows the complete model of a real gm-C integrator including their most significant error mechanisms, namely: input-
referred thermal noise PSD ( S in ), output voltage saturation ( v i max ), non-linear transconductance (modeled as
g m = g mo 1 + g mnl1 v i + g mnl2 v i2 ) and the transient response. The latter is especially critical in high-speed applications.
For that purpose, both a single-pole and a two-pole models have been considered in the behavioral simulator, by using the
equivalent circuits shown in Fig.4(b) and (c), respectively.
#define gm(S) ssGetSFcnParam(S,0)

#define C(S) ssGetSFcnParam(S,1)...
static void mdlInitializeSizes (SimStruct *S)

/*Size and number of inputs, outputs, states ...*/
{ ssSetNumSFcnParams(S, N_PARAMS);
Input voltage ssSetNumContStates(S, 2);
vi ssSetNumDiscStates(S, 0);
ssSetNumInputPorts(S, 2);...
}
static void mdlInitializeSampleTimes(SimStruct *S)
NO vi vi
YES /* It sets the sample time (continuous) */
max ?
{ ssSetSampleTime( S, 0,
CONTINUOUS_SAMPLE_TIME);
ssSetOffsetTime ( S, 0, 0.0);
vi = vi max g m = g mo 1 + g mnl1 v i + g mnl2 v i2 }
static void mdlDerivatives(SimStruct *S)
/* It solves the state-variables equations */
{ real_T *dx= ssGetdX(S);
Calculate equivalent S f = ---------
4kT real_T *x = ssGetContStates (S);
thermal noise in 3g m real_T gm = *mxGetPr(gm(S));...
dx[0]=-1/ra/Ca*x[0]+gma/Ca*vi;
dx[1]=-go/(C+Cp)*x[1]+gm/(C+Cp)*x[0]+1/(C+Cp)*iin;
Transient response }
static void mdlOutputs (SimStruct *S, int_T tid)
/* It computes the output of the S-function */
End { real_T*y= ssGetOutputPortRealSignal (S, 0);
real_T*x= ssGetContStates (S); ...
y[0] = x[1] ;
}
(a) (b)
Figure 5: Complete gm-C integrator model: (a) Flow diagram of the computation model and (b) excerpt of the corresponding
S-function.
These models are included in the corresponding S-function through a set of state-variable equations. As an illustration,
Fig.5(b) shows the main parts of the S-function corresponding to a two-pole model of a gm-C integrator. In this case, the
transient response is modeled as:
dv a
–1 ra Ca 0 g ma C a 0
dt va vi
= gm 1 + 1 (6)
dv o ----------------
- – --------------------------- v o 0 ----------------- i
C + Cp ro C + Cp C + Cp i
dt
with v a t and v o t being the state variables.

Examples of the application of this behavioral simulator can be found in Section 4 and Section 6.
4. TOPOLOGICAL SYNTHESIS
Cascaded continuous-time modulator architectures are usually synthesized by first synthesizing a modulator with
the same performance specifications in the discrete-time domain and then applying a discrete-time to continuous-time
transformation that keeps the same digital cancellation logic [14]. However, obtaining a functional continuous-time
modulator from this transformation and keeping the cancellation logic requires every state variable and DAC output to be
connected to the integrator input of subsequent stages as Fig.6 shows for a 2-1-1 architecture. This means a larger number
of analog components (transconductors and amplifiers), which translates into larger area, power consumption and larger
sensitivity to circuit tolerances. This sensitivity is illustrated in Fig.6(b), which shows the SNR loss as a function of the
standard deviation of the transconductances ( gm ) and capacitances ( C ).
x(s) kin1 kg1 E1(z)

1 1
Tss Tss CL1 18
kfb1 kfb2
y1(s) y1(z) 16
DAC
(dB)
Loss(dB)
kg2 E2(z) 14
1 yo(z)
Loss
kg3
Tss CL2
SNR
12
kg4
SNR
kfb3 y2(s) y2(z) 10
DAC
kg5 8
kg6 E3(z) 2.5

2
0.2 0
kg7 1 (%) 1.5 0.6
0.4
kg8 Tss CL3 gm 1 1

0.8
c
(%)
kg9
kfb4 y3(s) y3(z)
(a) DAC (b)
Figure 6: Cascade 2-1-1 CT modulator architecture obtained from an equivalent DT modulator and effect of mismatch on
the SNR.
To avoid this, we have implemented a synthesis method directly in the continuous-time domain. Let us consider the general
case of a cascaded CT modulator with m stages shown in Fig.1 and let us denote:
Input Quantizer j
F ij F ij s = ----------------------------------------- (7)
yi s
the transfer function from y i s to the input of j-th quantizer.
The synthesis method starts by optimally placing the poles of the single-loop transfer functions F ii s . Their numerators
are refined by combining behavioral simulation with an iterative simulation process, which starting from the nominal
values required to place the zeros of the corresponding Noise Transfer Function (NTF), optimizes the modulator
performance in terms of dynamic range and stability. For this purpose, these coefficients are varied in a range around their
nominal values in order to maximize the Signal-to-Noise Ratio (SNR) while keeping stability. Then, F ij s are
automatically determined by the inter-stage integrating paths.
If the modulator input, x t , is set to zero, it can be shown that the output of each stage y k z can be written as:
k–1
–1
Ek z + Z L H DAC F ik yi z
nT s
i=1
y k z = -------------------------------------------------------------------------------------------------
- (8)
–1
1–Z L H DAC F kk
nT s
–1
where Z stands for the Z-transform , L is the inverse Laplace transform.
The output y o of the modulator can be written as:
k–1
–1
m m
Ek z + Z L H DAC F ik yi z
nT s
i=1
-------------------------------------------------------------------------------------------------
- CL k
yo = y k CL k = (9)
–1
k=1 k=1 1–Z L H DAC F kk
nT s
where CL k z represent the partial cancellation logic transfer function of the k-th stage.
The partial cancellation logic transfer functions can be calculated by imposing the cancellation of the transfer function of
the first m – 1 quantization errors E k z in (9). This gives:
–1
–Z L H D F km CL m z
nT s
CL k z = -------------------------------------------------------------------------- (10)
–1
1–Z L H D F mm
nT s
where the partial cancellation logic transfer function of the last stage, CL m z , can be chosen to be the simplest form that pre-
serves the required noise shaping.
Using this method the 2-1-1 architecture in Fig.7(a) is synthesized. As can be observed, the circuitry is significantly less com-
plex than that in Fig.6(a). Another positive consequence is the better sensitivity to parameter tolerances, as the SNR loss in
Fig.7(b) shows for the same transconductor and capacitance mismatches that Fig.6(b)
x(s) kin1 kg1 E1(z)

1 1
Tss Tss CL1
kfb1 kfb2
y1(s) y1(z) 14
DAC
12
E2(z)
SNR Loss (dB)

kin2
1 yo(z) 10
Tss CL2
kfb3 8
y2(s) y2(z)
DAC 6
kin3 E3(z) 4
1 2.5
Tss CL3 2
0
1.5 0.2
kfb4 gm
(%)
0.8
0.6
0.4
1 1 (%)
(a) y3(s) y3(z) (b) c
DAC
Figure 7: Cascade 2-1-1 CT M architecture using the direct synthesis method and effect of mismatch on the SNR.
5. OPTIMIZATION TOOL
Design space exploration and specification transmission rely on the interaction of some kind of performance evaluator:
equations, behavioral simulator (with models at some level of abstraction), with an optimizer. The cornerstones of this
process are: (1) an adequate formulation of a cost function, which quantifies the degree of compliance of the design with
the targeted performance; (2) a fast yet accurate method to evaluate the cost function; and (3) an efficient technique to
generate the next movement over the design space. The second point mainly depends on the performance evaluation
mechanism, which has already been discussed in Section 3.
Optimization algorithms can be classified into local optimization and global optimization ones. Local optimization
algorithms are generally fast but require a good initial guess. Therefore, they are appropriate for fine-tuning of already good
designs, otherwise, they get quickly trapped into a local minimum. Global optimization algorithms do not need a good
initial point as they incorporate mechanism to escape from local minima, at the price of a larger computation time. Global
optimization algorithms include a variety of evolutionary and simulated annealing algorithms with all their derivatives.
The optimization core used here is a two-step one: in the first one, global optimization techniques inspired on simulated
annealing, are applied, while deterministic ones are applied in the second. Unlike conventional simulated annealing
procedures, in which the control parameter commonly named temperature follows a predefined temporal evolution
pattern, the implemented global optimization algorithm dynamically adapts this temperature to approximate a predefined
evolution pattern of the acceptance ratio (accepted movements / total number of iterations). This idea prevents excessively
high temperatures which will make convergence difficult and inappropriately low temperatures which can make the
algorithm to stuck on a local minimum. The amplitude of parameter movements through the design space is also
synchronized with the temperature for improved convergence [15].
For efficiency reasons, the optimization core has been conceived as an independent application whereas the behavioral
simulator runs in Matlab/Simulink. In order to integrate both processes, a special-purpose application has been developed
by using the Matlab engine library [16]. This application is responsible for the communication between the optimization
core and the behavioral simulator so that the optimization core runs in background while Matlab acts as a computation
engine.
6. CASE STUDY
The objective specifications for the continuous-time modulator are 12 bits with 20MHz signal bandwidth for a VDSL
application, to be implemented in a 130nm CMOS technology. As a result of the different steps of the architectural
exploration process, a fifth-order ( L = 5 ) cascade modulator, conceptually shown in Fig.8(a), was selected. It consists
of a 2-2-1 topology, clocked at f s = 240MHz ( M = 6 ), with B = 4 and NRZ DACs in all stages in order to minimize
the effect of jitter.
kff0
Rin C1 kff1
x(s) kg2
C2
CL1
Resonator1
x(s) + F11(s) CL1 Rr kg1
DAC2 CLK
Quant1
y1(s) DAC1
D D
DAC Latch Latch
kff2 CLK CLK
Resonator2
+ F22(s) CL2 yo(z) kff3
Quant2 kg3 kg4

y2(s) C3
CL2 yo(z)
DAC kin2
C4
DAC2 CLK
kr2
Integrator D D
+
F33(s)
CL3 DAC1 Latch Latch
Quant3 CLK
Cancellation Logic CLK
y3(s)
DAC C5
(a) (b) CL3
kin3
kg5
CLK
DAC4
Figure 8: (a) Conceptual diagram of the 2-2-1 modulator and (b) circuit implementation.
The intra- and inter-stage transfer functions F ij are

b 11 s + b 10 b 21 s + b 20 b 30
F 11 s = ------------------------- F 22 s = ------------------------- F 33 s = --------
2
s + p1
2 2
s + p2
2 s
(11)
b 10 b 20 b 30 b 20 b 30
F 13 s = ------------------------------------------------------ F 23 s = ----------------------------
2 2 2 2 2 2
s s + p1 s + p2 s s + p2
where p1,2 stand for the optimal placement of the pole frequencies. Coefficients b ij in (11) are found through an iterative
simulation-based process that starting from nominal values required to place the zeroes of the corresponding NTF
optimizes the modulator performance in terms of dynamic range and stability. For this purpose, these coefficients are varied
in a range of up to 20% around their nominal values in order to achieve the maximum Signal-to-Noise Ratio (SNR) while
keeping stability. The partial CL transfer functions can be calculated from (10), giving the expressions:
–1 –2
CL 1 = z –1 n 14 + n 13 z + n 12 z + n 11 z – 3 + n 10 z – 4
CL 2 = z –1 n 22 + n 21 z – 1 + n 20 z – 2 1 – 2 cos T s p1 z – 1 + z –2
CL 3 = 1 – 2 cos T s p1 z –1 + z –2 1 – 2 cos T s p2 z –1 + z –2
– b 10 b 20 b 30 3 3 3 3
n 10 = n 14 = -----------------------------------------------
3 3 2 2
- Ts p1 p2 – p1 p2 + p1 sin Ts p2 – p2 sin Ts p1
p1 p2 p2 – p1
– 2b 10 b 20 b 30
n 11 = n 13 = -----------------------------------------------
3 3 2 2
-
p1 p2 p2 – p1
[ Ts p2
3
p1 –
3
p2 p1 cos T s p1 + cos T s p2 +
3
p2 sin Ts p1 1 + cos T s p2 –
3
p1 sin Ts p2 1 + cos T s p1 ] (12)
– 2b 10 b 20 b 30
n 12 = -----------------------------------------------
3 3 2 2
-
p1 p2 p2 – p1
3 3 3 3
[T s p1 p2 – p1 p2 1 + 2 cos T s p1 cos T s p2 + p1 sin Ts p2 1 + 2 cos T s p1 – p2 sin Ts p1 1 + 2 cos T s p2 ]
– b 20 b 30
n 20 = n 22 = ------------------
3
- Ts p2 – sin T s p2
p2
– 2b 20 b 30
n 21 = ---------------------
3
- sin T s p2 – Ts p2 cos Ts p2
p2
where T s = 1 f s is the sampling period.

Fig.8(b) shows the conceptual circuit implementation of the modulator. The results of the optimization process are
summarized in Table 2, which includes the values of loop filter coefficients, k i (implemented as transconductances) as well
as the capacitances, C i , used in the modulator.
Table 2: Loop filter coefficients of the modulator.
R in = R fb = 1 k ; R r1 = 5 k , k g1 = 500 A/V
C 1 = C 3 = 6 pF C 2 = 2.25 pF C 4 = C 5 = 0.75 pF k in2 = 800 A/V
k g3 = k g5 = k ff1 = k ff3 = k in3 = 200 A/V k ff0 = 158 A/V
k g2 = k g4 = k r2 = k ff2 = 100 A/V
The modulator was high-level sized, i.e, the system-level specifications (12-bit@20-MHz ) were mapped onto building-
block specifications using statistical optimization for design parameter selection and behavioral simulation for evaluation.
The result of this sizing process is summarized in Table 3, showing the maximum (minimum) values of the non-idealities
(at the building block level) that can be tolerated in order to fulfil the required modulator performance.
The building blocks: front-end opamp, loop filter transconductors, quantizers and DACs are designed using the
methodology described in Section 2. Due to space limitations, only the synthesis results of the front-end opamp sizing are
shown here.
Table 3: High-level sizing of the modulator

Front-End Opamp Flash Quantizers
DC Gain > 68 dB Comparator Offset < 20mV
GB > 580MHz Comparator Hysteresis < 20mV
Phase margin > 60o Comparator Resolution Time < 1ns
Differential output swing 0.5 V Ladder Unit Resistance 220
Loop Filter Transconductors Current-steering DACs
DC Gain > 50dB Current standard deviation < 0.15% LSB
Differential Input Amplitude > 0.3V Finite output impedance > 12M
Differential Output Amplitude > 0.3V Settling Time < 500ps
Third-order non-linearity 56dB
Fig.9 shows the schematic of the front-end operational amplifier used together with its common-mode feedback circuit. It
is a fully differential telescopic cascode topology with gain boosting. After a simulator-in-the-loop optimization process is
applied, the resulting sized circuit has the electrical performances in Table 4. A similar sizing procedure is applied for the
other building blocks.
Table 4: Electrical performances of the front-end opamp
GB 600 MHz
DC Gain 71 dB
Phase Margin 80º
Parasitic input capacitance 0.36 pF
Parasitic output capacitance 0.4 pF
Differential output swing 0.7 V
Power consumption 20mW
Pbias1
Pbias2
CM
Pbias1 Pbias1
Pbias1 Out+ VCM Out-
Out- Out+
Vin+ Vin-
CMFB
CM
CMFB circuit
Nbias2
CMFB
Figure 9: Front-end operational amplifier.
The modulator performance has been verified by exhaustive simulations. As an illustration, Fig.10 shows the output
spectrum for an input sinewave of -6.5-dBV amplitude and 1.76-MHz frequency. The maximum Signal-to-
(Noise+Distortion) Ratio (SNDR) is 80 dB ( 13 bits ). These results correspond to a full electrical-level simulation. This
type of verification is only feasible for a limited set of simulation conditions. A more exhaustive verification is performed
by using the behavioral simulator with data obtained from the electrical simulation of the building blocks. This allows, for
instance, the application of Monte Carlo simulation to evaluate the influence of mismatchon performance deviations. In the
present case, it is obtained that even in the worst-case mismatch a maximum SNDR larger than 74dB is obtained.
ACKNOWLEDGEMENTS
This work was supported by the Spanish Ministry of Science and Education (with support from European Regional
Development Fund) under Contract TEC2004-01752/MIC and FIT-330100-2006-134 SPIRIT Project (“Secured Platform
for Intelligent and Reconfigurable Voice and Data Terminals”), funded by the Spanish Ministry of Industry, Tourism, and
Commerce.
REFERENCES
1. Int. Technology Roadmap for Semiconductors. Editions 2001, 2003, and 2005. [On-line: http://public.itrs.net/].
2. J.A. Cherry and W.M. Snelgrove: Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion.
Kluwer, 2000.
-20
-40
Magnitude (dB)
-60
-80
-100
-120
-140
-160 5 6 7 8
10 10 10 10
Frequency (Hz)
Figure 10: Output spectrum of the modulator.
3. L. Breems and J.H. Huijsing: Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receivers.
Kluwer, 2001.
4. S. Patón, A. Di Giandoménico, L. Hernández, A. Wiesbauer, T. Pötscher and M. Clara: “A 70-mW 300-MHz CMOS
Continuous-Time ADC With 15-MHz Bandwidth and 11 Bits of Resolution”. IEEE Journal of Solid-State
Circuits, pp. 1056-1063, July 2004.
5. M. Moyal, M. Groepl, H. Werker, G. Mitteregger, J. Schambacher: “A 700/900mW/Channel CMOS Dual Analog
Front-End IC for VDSL with Integrated 11.5/14.5dBm Line Drivers”. Proc. IEEE Int. Solid-State Circuits Conf., pp.
416-417, 2003.
6. L. J. Breems, R. Rutten and G. Wetzker: “A Cascaded Continuous-Time Modulator with 67dB Dynamic Range
in 10-MHz Bandwidth”. IEEE Journal of Solid-State Circuits, pp. 2152-2160, December 2004.
7. S. Yan, E. Sánchez-Sinencio: “A Continuous-Time Modulator With 88-dB Dynamic Range and 1.1-MHz Signal
Bandwidth”. IEEE Journal of Solid-State Circuits, pp. 75-86, January 2004.
8. R. del Río, F. Medeiro, B. Pérez-Verdú, J.M. de la Rosa and A. Rodríguez-Vázquez, “CMOS Cascade Sigma-Delta
Modulators for Sensors and Telecom: Error Analysis and Practical Design,” ISBN 1-4020-4775-4, Springer 2006.
9. G. Stehr, H. Graeb and K. Antreich, “Performance Trade-off Analysis of Analog Circuits by Normal Boundary
Intersection,” Proc. Design Automation Conf., pp. 958-963, 2003.
10. T. Eeckelaert, T. McConaghy and G. Gielen, “Efficient Multiobjective Synthesis of Analog Circuits Using
Hierarchical Pareto-Optimal Performance Hypersurfaces,” Proc. Design, Automation and Test in Europe, pp. 1070-
1075, 2005.
11. R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández, “Analysis of Clock Jitter Error in Multibit
Continuous-Time Modulators with NRZ Feedback Waveform,” Proc. IEEE Int. Symp. Circuits and Systems, pp.
3103-3106, 2005.
12. http://www.mathworks.com
13. “Simulink 6 Writing S-functions”, The MathWorks Inc., 2007 [On-line: http://www.mathworks.com].
14. M. Ortmanns, F. Gerfers, and Y. Manoli: “On the Synthesis of Cascaded Continuous-Time Sigma-Delta
Modulators”. Proc. of the 2001 IEEE Int. Symposium on Circuits and Systems, pp. 419-422.
15. F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-Castro, J.L. Huertas and A. Rodríguez-Vázquez,
“Global Design of Analog Cells Using Statistical Optimization Techniques,” Analog Integrated Circuits and Signal
Processing, Vol. 6, No. 3, pp. 179-195, Nov. 1994.
16. “Matlab 7 External Interfaces”, The MathWorks Inc., 2007 [Online: http://www.mathworks.com].
Listado Completo de Publicaciones
Libros y Capítulos de Libro

• A. Rodríguez-Vázquez, R. del Río, J.M. de la Rosa, R. Tortosa, F. Medeiro and B.
Pérez-Verdú: “Sigma-Delta CMOS ADCs: An Overview of the State-of-the-Art”.
Chapter 2 in the Book CMOS Telecom Data Converters (Edited by A. Rodríguez-
Vázquez, F. Medeiro and E. Janssens), Kluwer Academic Publishers, 2003. (ISBN:
1-4020-7546-4).
Artículos en Revistas Internacionales

• R. Tortosa, J.M. de la Rosa, F. V. Fernández and A. Rodríguez-Vázquez: “A New
High-Level Synthesis Methodology of Cascaded Continuous-Time
Modulators,” IEEE Transactions on Circuits and Systems - II: Express Briefs, vol.
53, pp. 739-743, August 2006. (ISSN: 1057-7130).
• R. Tortosa, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-Vázquez: “Clock
Jitter Error in Multi-bit Continuous-Time Sigma-Delta Modulators with Non-
Return-to-Zero Feedback Waveform,” Microelectronics Journal, vol. 39, pp. 137-
151, January 2008. (ISSN:0026-2692).
• R. Tortosa, R. Cástro-Lopez, J.M. de la Rosa, E. Roca, A. Rodríguez-Vázquez and
F.V. Fernández: "Systematic Design of High-Resolution High-Frequency Cascade
Continuous-Time Sigma-Delta Modulators". ETRI Journal, vol. 30, pp. 535-545,
August 2008. (ISSN: 1225-6463).
Artículos en Congresos Internacionales

• R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Analysis
of Clock Jitter Error in Multibit Continuous-Time Modulators with NRZ
Feedback Waveform,” Proceeding of the 2005 IEEE International Symposium on
Circuits and Systems (ISCAS), pp. 3103-3106, Kobe, Japan, May 2005. (ISBN: 0-
7803-8834-8).
• R. Tortosa, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "A
Direct Synthesis Method of Cascaded Continous-Time Sigma-Delta Modulators,”
Proceeding of the 2005 IEEE International Symposium on Circuits and Systems
(ISCAS), pp. 5585-5588, Kobe, Japan, May 2005. (ISBN: 0-7803-8834-8).
• R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández:
"Continuous-Time Cascaded Sigma-Delta Modulators for VDSL: A Comparative
Study,” Proc. of SPIE - Second International Symposium on Microelectronics for
the New Millennium - VLSI Circuits and Systems Conference, pp. 59-70, Sevilla,
May 2005. (ISBN: 0-8194-5832-5).
• R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "Cascade

Continuous-Time Modulators with Reduced Number of Analog Components
Application to VDSL”, Proceeding of Fifth IEE International Conference on
Advanced A/D and D/A Conversion Techniques and Their Applications (ADDA),
pp. 233-238, Limerick, July 2005. (ISBN: 0-86341-542-3).
• R. Tortosa, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: "Design
of a 1.2-V Cascade Continuous-Time Modulator for Broadband
Telecommunications”, Proceeding of the 2006 IEEE International Symposium on
Circuits and Systems (ISCAS), pp. 589-592, May 2006. (ISBN: 0-7803-9390-2).
• R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-
Vázquez: “Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1
Continuous-Time Sigma-Delta Modulator,” Proc. of the 2006 IEEE/IFIP
International Conference on Very Large Scale Integration (VLSI-SoC), pp. 267-
271, Niza, Octubre 2006. (ISBN: 3-901882-19-7).
• R. Tortosa, A. Aceituno, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V.
Fernández: “A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta
Modulator ”. Proceeding of the 2007 IEEE International Symposium on Circuits
and Systems (ISCAS), pp. 1-4, New Orleans, May 2007. (ISBN: 1-4244-0921-7).
• R. Tortosa, R. Castro-López, J. M. de la Rosa, A. Rodríguez-Vázquez and F.V.
Fernández: “A Design Tool for High-Resolution High-Frequency Cascade
Continuous-Time Modulators”. Proceeding of SPIE - Third International
Symposium on Microelectronics for the New Millennium - VLSI Circuits and
Systems Conference, Maspalomas-Gran Canaria, 2-4 May 2007. (ISBN:
9780819467188).
Artículos en “Design of Circuits and Integrated Systems Conference

(DCIS)”
• R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “A New
Method for the High-Level Synthesis of Continuous-Time Cascaded
Modulators”, Proceeding of the 2004 DCIS Conference, pp. 661-666, Bordeaux,
November 2004.
• R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández: “Effect of
Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time
Modulators with NRZ DAC”, Proceeding of the 2005 DCIS Conference,
Lisbon, November 2005.
• R. Tortosa, A. Aceituno, J.M. de la Rosa, F.V. Fernández and A. Rodríguez-
Vázquez: “Design of a 1.2-V 130nm CMOS 12-bit@20MHz Gm-C Cascade 3-2
Continuous-Time Modulator”, Proceeding of the 2006 DCIS Conference,
Barcelona, November 2006.

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UNIVERSIDAD DE SEVILLA

Departamento de Electrónica y Electromagnetismo

Una Contribución al Diseño de Moduladores

Memoria presentada por

RAMÓN TORTOSA NAVAS

para optar al grado de Doctor por la Universidad de Sevilla

Sevilla, abril de 2012

Memoria presentada por

RAMÓN TORTOSA NAVAS

para optar al grado de Doctor por la Universidad de Sevilla

Dr. José Manuel de la Rosa Utrera Dr. Ángel Rodríguez Vázquez

Profesor Titular de Universidad Catedrático de Universidad

Departamento de Electrónica y Electromagnetismo

Anexo 1: Convertidores Sigma-Delta de Tiempo Continuo

Anexo 2: Principales Publicaciones sobre los Trabajos Recogidos

Anexo 3: Otras Publicaciones sobre los Trabajos Recogidos en la

UNA CONTRIBUCIÓN AL DISEÑO DE MODULADORES

Esta tesis doctoral es el resultado de un conjunto de trabajos de investigación encaminados a sistematizar y

1. Introducción y Justificación de la Unidad Temática de esta Tesis Doctoral

A pesar de ello, el ritmo creciente de incorporación de nuevos estándares de comunicación y

La miniaturización de sistemas electrónicos completos a escala nanométrica permite, por una

2. Convertidores Analógico-Digitales: Conceptos básicos y Estado del Arte

Un convertidor analógico-digital (ADC de “Analog-to-Digital Converter”) es un circuito

un ADC, el cual incluye los siguientes componentes: un filtro “anti-aliasing”, un circuito de

x a (t ) x bl (t ) x s,n x c,n y d,n

Como se ilustra en la Fig.1(b), la conversión A/D comprende dos procesos fundamentales:

Las prestaciones, en términos de resolución, velocidad y consumo de potencia pueden

3. Moduladores ΣΔ de Tiempo Continuo

La Fig. 4 muestra el diagrama de bloques conceptual de un ADC ΣΔ concebido para la

Suponiendo un modelo linealizado del cuantizador en la Fig. 4, en el que el error de

Y (z) = STF(z) ⋅ X (z) + NTF(z) ⋅ E(z) (2)

donde X(z) y E(z) representan la transformada Z de la señal de entrada y del error de

donde B y X FS representan respectivamente es el número de bits y el fondo de escala del

cuantizador; y f L , fU denotan los los límites inferior y superior de la banda de la señal.

tipo diferenciadora4, es decir NTF(z) = (1− z −1 ) L , de la expresión en (5) se obtiene que:

donde OSR representa la razón de sobremuestreo.

Ventajas de los Moduladores ΣΔ de Tiempo Continuo

• Mayor velocidad de operación con menor consumo de potencia, propiciada por la

• No necesidad de llaves de muestreo en la entrada, evitando la necesidad de emplear

• Menor impacto del ruido de conmutación, denominado “digital noise” o “switching

Inconvenientes de los Moduladores ΣΔ de Tiempo Continuo

Las principales desventajas y limitaciones de los MΣΔ CT son las siguientes:

• Respuesta dinámica más complicada, debido al procesamiento de señales de tiempo

• Mayor impacto del error debido a la incertidumbre de los instantes de conmutación de la

4. Objetivos de esta Tesis Doctoral

1) Desarrollar una metodología de síntesis y diseño de alto nivel para topologías

3) Encontrar soluciones a nivel de circuito que reduzcan el efecto de los errores no

4) Demostrar la viabilidad del uso de MΣΔ CT en cascada para la digitalización

Propuesta de un Nuevo Método de Síntesis Directa de Moduladores ΣΔ CT en Cascada

El método propuesto se puede aplicar a cualquier topología de MΣΔ CT en cascada, como se

Desarrollo de una Metodología “Top-Down/Bottom-Up” para el Diseño Sistemático de

Como se detalla en la Publicación 3 del Anexo 2 [21], la metodología propuesta combina

Casos de Estudio y Soluciones Circuitales

Esta tesis doctoral representa una contribución al diseño de moduladores ΣΔ (MΣΔ)

• Se ha desarrollado una nueva metodología de diseño de MΣΔ CT en cascada basada en

a la frecuencia y amplitud de la señal de entrada (supuesta ésta sinusoidal). Dichas

• Se han propuesto nuevas arquitecturas de MΣΔ CT en cascada obtenidas mediante la

o La segunda topología es una cascada 3-2, implementada mediante integradores

Ambos moduladores operan con una frecuencia de muestreo de 240MHz y emplean

12bits@20MHz, teniendo un consumo estimado de 70mW. Como ilustración la Fig. 5(d)

ANEXO 1: CONVERTIDORES SIGMA-DELTA DE TIEMPO

Algunas partes de este anexo fueron incluidas en la siguiente publicación de la que el

A. Rodríguez-Vázquez, R. del Río, J.M. de la Rosa, R. Tortosa, F. Medeiro and B. Pérez-

Continuous-time Sigma-Delta Converters