Department of Electrical and Electronics Engineering

YEAR/SEM: II / III DATE: 07.10.2017

TIME: 3 Hrs. MARKS: 100
SUBJECT CODE & TITLE: EE6301 –DIGITAL LOGIC CIRCUITS

Answer ALL Questions.

PART – A (10 x 2 = 20 Marks)
1. Determine (377)10 in Octal and Hexa-Decimal equivalent?
2. Compare the totem-pole output with open-collector output?
3. Give one application each for Multiplexer and Decoder.
4. Show the JK flip flop can be modified into a D flip flop or a T flip flop.
5. Differentiate between Mealy and Moore models.
6. What is a deadlock condition?
7. Draw the block diagram of PLA.
8. Write a VHDL code for 2*1 MUX.

PART – B (5X13=65 marks)

9. a) (i) Implement F= (AB'+A'B) (C+D') with only NOR gates.

(ii) Minimize the following using karnaugh map. Implement the resultant function using NOR
gates only. F(A,B,C,D,E)=П M (2,4,7,9,26,28,29,31)

(Or)
b) Explain the TTL.

10. a) Explain priority encoder and octal to binary encoder.

(Or)
b) Implement full adder circuit using 8:1 multiplexer.
a) Design a counter with the sequence 0,1,3,7,6,4,0.
(Or)
b) Design and implement a synchronous decade counter using T flip-flop. Draw the timing diagram.
11. a) Design a pulse mode circuit with inputs x1, x2, x3 and output z as shown in figure below by
considering the following necessary conditions:
 the output should change from 0 to 1, only for the input sequence x1- x2- x3 occurs,
while z=0
 the output z should remain in 1 until x2 occurs
 use only SR flip flops for the design

(Or)
 b) Design a BCD to Excess 3 code converter and implement using suitable PLA.
15. a) (i) Construct a VHDL module for a JK flip flop.
(ii) Express the expression for arithmetic and logic operations using RTL.
(Or)
b) Write HDL program for full adder and multiplexer.
PART – C (1*15)
16. a)