Session Number 2526

The Coin Detector Circuit

Nghia T. Le
Purdue University

I. Introduction

This paper discusses the design of a Coin Detector Project that utilizes an inductor as an
inductive proximity switch. The project covers basic analog/digital circuits that the
students have learned during the first two years in the Electrical Engineering Technology
Program at Purdue University. Figure 1 below shows the block diagram of the project.

OSCILLATOR

RL ACTIVE PEAK
INSTRUMENTATION RESET
WHEATSTONE BANDPASS AND
AMPLIFIER CIRCUIT
BRIDGE FILTER HOLD

VOLTAGE ONE-SHOT
COMPARATORS CIRCUITS

DECODER/
DRIVER

PLD

DECODER/
DRIVER

Figure 1 – The Block Diagram of the Circuit

In the ready mode, the circuit shows 00 at the seven-segment displays. When a quarter, a
dime, or a nickel passes through the slot, the display becomes 25, 10, or 05 respectively
in a two-second period and it then resets itself to 00.

The project consists of different stages that are manageable as weekly classroom
activities. It helps the students to utilize their knowledge to design and build a working
circuit.
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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
II. Individual Stages of the Circuit

A. The Coin Slot

The design of the coin slot is in Figure 2 below. The material of this slot is non-metallic
so that the value of the inductor on the slot is not affected. The U-shape slot provides a
smooth passage for the coins to roll down the slope. A 33mH inductor is mounted on the
side of the slot via a through hole. The top of the inductor is flush with the inner wall of
the slot.

Figure 2 – The Coin Slot

The characteristics of the core of the inductor change when a coin passes in front of it.
This change results in a decrease of the inductance value. The circuit will exploit this
behavior of the inductor to detect the different coins passing through the slot.

B. The Sine Wave Oscillator

The schematic diagram of the oscillator is in Figure 3 on the next page.

If we let C1 = C 2 = C 3 = C and R3 = R 4 = R, the oscillating frequency of the circuit is:

1 1
f = = = 4.08kHz
2πRC 2π (0.01µF )(3.9kΩ )

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
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Copyright © 2003, American Society for Engineering Education

In designing this oscillator, the students must match three capacitors and two resistors.
After connecting the circuit, the students must carefully tune the rheostat R1 so that
oscillation occurs.

C2
0.01µF C3
VREF 0.01µF

+15V
R3 +15V
7 3.9kΩ
2
LM741 7
3 6 2
4 LM741
R1 3 6
4
1kΩ
22−TURN −15V
R4 −15V
3.9kΩ

R2
3.3kΩ
C1
0.01µF

Figure 3 – The Sine Wave Oscillator

The output waveform of the voltage VREF is in Figure 4 below. This output voltage has its
peak value of 13.5VPEAK and its frequency of 4kHz.

+13.5V

50µV/DIV

-13.5V

Figure 4 – The Output of the Oscillator

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
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Copyright © 2003, American Society for Engineering Education

The output voltage of the oscillator is used as the reference voltage for a RL Wheatstone
Bridge.

C. The RL Wheatstone Bridge

The schematic diagram of this circuit is in Figure 5 below. In the bridge, the inductor L1
is mounted on the coin slot and connected to the circuit via a two-conductor shielded
cable wire. The rheostat R6 is for balancing the bridge. The reference voltage VREF is the
output voltage of the oscillator.

VREF

R6
R5
5kΩ
3.3kΩ
22−TURN

V1 V2

L1 L2
33mH 33mH

Figure 5 – The RL Wheatstone Bridge

When a coin passes in front of the inductor L1, the inductance decreases resulting in an
unbalanced bridge. The difference of the output voltages of the bridge is then amplified
by an Instrumentation Amplifier.

D. The Instrumentation Amplifier

The schematic diagram of the Instrumentation Amplifier is in Figure 6 on the next page.
The input voltages V1 and V 2 of the circuit are the output voltages of the RL Wheatstone
Bridge. In the amplifier, if we let R8 = R 9 = R 10 = R 11 = R 12 = R 13 = R, the closed-loop
gain of the circuit is:

2R 2(15kΩ )
ACL = 1 + = 1+ = 14.6
R7 2.2kΩ

The resistors R8 through R13 in the circuit are precision resistors.

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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
The output voltage V3 of the amplifier has the following peak values:

• When there is no coin passing through, the peak value of the output voltage is
60mV.
• When 25¢ coin passes through, the peak value of the output voltage is 1V.
• When 10¢ coin passes through, the peak value of the output voltage is 0.7V.
• When 5¢ coin passes through, the peak value of the output voltage is 0.25V.

+15V

V1 7
3
LM741
6
2 R13
4
15kΩ, 1%

−15V
+15V

R8 R10
7
15kΩ, 1% 15kΩ, 1% 2
R7
LM741
2.2kΩ R9 R11 3 6
4
15kΩ, 1% 15kΩ, 1% V3

−15V
+15V
R12
7
15kΩ, 1%
2
LM741
3 6
V2 4

−15V

Figure 6 – The Instrumentation Amplifier

The voltage V3 is not a perfect sine wave since we cannot perfectly balance the bridge
and the stray capacitance in the cable also contributes to the presence of some minor
interference. Figure 7 below shows one cycle of the waveform of the voltage V3 when a
25¢ coin passes in front of the inductor L1.

1V

−1V

Figure 7 – The Voltage V 3 for 25¢ Coin

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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
An Active Band Pass Filter is used in the next stage to eliminate the interference and
amplify the signal further.

E. The Active Band Pass Filter

The schematic diagram of the filter is in Figure 8 below.

R16
5.6kΩ

R15 R18
10kΩ 27kΩ

+15V
2
7
R14
5.6kΩ LM741
3 6
V3 4
V4
C5
0.01µF -15V
C4 R17
0.01µF 5.6kΩ

Figure 8 – The Active Band Pass Filter

If we let R14 = R 16 = R 17 = R and C4 = C 5 = C in the filter, the center frequency is:

2 2
f0 = = = 4.02kHz
2πRC 2π (5.6kΩ )(0.01µF )

The Q sensitivity value of the filter is:

2 2
Q= = = 4. 7
 R   27 kΩ 
4 − 1 + 18  4 − 1 + 
 R15   10 kΩ 
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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
The output voltage V4 of the filter is a sine wave whose peak values are:

• When there is no coin passing through, the peak value of the output voltage is
0.7V.
• When 25¢ coin passes through, the peak value of the output voltage is 12V.
• When 10¢ coin passes through, the peak value of the output voltage is 8V.
• When 5¢ coin passes through, the peak value of the output voltage is 3V.

Figure 8 below shows the different responses of the filter.

RESPONSE FOR $0.25

RESPONSE FOR $0.10
RESPONSE FOR $0.05

+12V

+8V

+3V
50µV/DIV

-3V

-8V

-12V

Figure 8 – The Output Waveforms of the Active Band Pass Filter

F. The Peak and Hold Circuit and the Reset Circuit

With the output of the active filter, we are able to distinguish the differences of the coins.
The next stage of the circuit is to convert the peak values of the sine waves into DC
voltages. This task can be accomplished by using the Peak and Hold circuit. The
schematic diagram of this circuit is in Figure 9 on the next page.

When there is no reset signal presence at the input of the Reset circuit, the capacitor C6 is
fully charge and it holds the charge to produce a DC voltage equal to the peak value of
the voltage V4.

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
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Copyright © 2003, American Society for Engineering Education

When the Reset circuit receives a signal, the transistor Q1 acts as a closed switch. The
collector-emitter junction of the transistor behaves as a short circuit providing a path for
the capacitor C6 to discharge through the resistor R21 and the collector-emitter junction.
Under this condition, the Peak and Hold circuit is reset.

The discharging time constant is:

τ = R21C 6 = (560Ω )(10 µF ) = 5.6ms

Therefore, if the reset signal lasts more than 5• (28ms), the capacitor will be fully
discharged and the Peak and Hold circuit is reset. The reset signal comes from the One-
Shot circuit.

R19
100kΩ

+15V
+15V
7
D1 2
7 1N914 LM741 V5
2 3 6
LM741 4
3 6
V4 4
C6 −15V
−15V 10µF

PEAK & HOLD CIRCUIT

R21
560Ω

R20
1kΩ
Q1
RESET SIGNAL
2N3903

RESET CIRCUIT

Figure 9 – The Peak and Hold Circuit and the Reset Circuit

At this part of the project, the output voltage V5 can be:

• 0.7VDC when there is no coin passing through.

• 3VDC when 5¢ passes through.
• 8VDC when 10¢ passes through.
• 12VDC when 25¢ passes through.
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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
 G. The Voltage Comparators

The voltage V5 goes into three Voltage Comparators to produce proper outputs for the
Programmable Logic Device. The schematic diagram of this part of the circuit is in
Figure 10 below. The potentiometer R22 is set so that the voltage at its wiper output to be
1.5V. The potentiometer R23 is set so that the voltage at its wiper output to be 6V. The
potentiometer R24 is set so that the voltage at its wiper output to be 10V.

When there is no coin passing through the slot, the outputs of the Voltage Comparators
are 0V.

When a 5¢ coin passes through, the output V6 is approximately 4V and the remaining
outputs V7 and V 8 are 0V.

When a 10¢ coin passes through, the outputs V6 and V 7 are approximately 4V and the
output V8 is 0V.

When a 25¢ coin passes through, all of the outputs are approximately 4V.

+15V

R22 +15V
10kΩ 1.5V D2 R 25
7 1N914 5.6kΩ
2
LM741 V6
3 6
4
+15V R28
−15V 2.2kΩ

R 23 +15V
10kΩ 6V D3 R26
7 1N914 5.6kΩ
2
LM741 V7
3 6
V4 4
+15V R29
−15V 2.2kΩ

R24 +15V
10kΩ 10V D4 R27
7 1N914 5.6kΩ
2
LM741 V8
3 6
4
R30
−15V 2.2kΩ

Figure 10 – The Voltage Comparators

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
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Copyright © 2003, American Society for Engineering Education

In Figure 11 below shows the digital equivalent of the output voltages of the Voltage
Comparators.

V8 V7 V6
NO COIN 0 0 0
NICKEL 0 0 1
DIME 0 1 1
QUARTER 1 1 1

Figure 11 – The Digital Equivalent of the Output Voltages

As in Figure 11, the output voltage V6 changes its state when any coin passes through the
slot. We can use this voltage as the trigger signal for the One-Shot circuit.

H. The One-Shot Circuits

The One-Shot circuits are used to maintain the seven-segment displays for duration of
time as well as to reset the Peak and Hold circuit. The schematic diagram of the circuit is
in Figure 12 below.
5V

R 31
120kΩ

5V 5V

C7
22µF

16 15 14 13 12 11 10 9
Vcc 1Rext 1Cext 1Q 2Q 2CLR 2B 2A

74221
1A 1B 1CLR 1Q 2Q 2Cext 2Rext GND
1 2 3 4 5 6 7 8

C8
10µF
5V
V6
R32
120kΩ
TO RESET CIRCUIT

5V

Figure 12 – The One-Shot Circuits

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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
The 74221 Dual Monostable Multivibrator IC is used for the One-Shot circuits. When the
input voltage V6 goes from LOW to HIGH, the first one-shot circuit produces a pulse.
The width of this pulse is:

PULSEWIDTH #1 = 0.7C 7 R31 = 0.7(22 µF )(120kΩ ) = 1.85s

This is the time that the outputs V6 through V8 stay at their states when a coin is passing
through the slot. At the end of this time period, the output 1Q of the first one-shot triggers
the second one-shot. The pulse width of the second one-shot is:

PULSEWIDTH #2 = 0.7C8 R32 = 0.7(10µF )(120kΩ ) = 840ms

This pulse is used as the reset signal to the Reset circuit. The duration of this pulse is
much more than the 5• required for the capacitor C6 to be fully discharged.

I. The PLD, the Decoder/Drivers, and the Seven-Segment Display

The Programmable Logic Device in the circuit is the GAL16V8D EEPROM. This device
has 8-bit input and 8-bit output. We use the outputs V 6 through V8 of the Voltage
Comparators as the input bits I/E, I/F, and I/G to the device. The outputs O/a through O/d
are used for the Least Significant Digit and the outputs O/e through O/h are for the Most
Significant Digit. The Truth Table of the inputs and outputs of the device is in Figure 13.

I/H I/G I/F I/E I/D I/C I/B I/A O/h O/g O/f O/e O/d O/c O/b O/a
1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
1 0 0 1 1 1 1 1 0 0 0 0 0 1 0 1
1 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0
1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0
1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1

Figure 13 – The Inputs and Outputs of the GAL16V8D Page 8.1107.11

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
The program for the EEPROM is written using WinCupl as in Figure 14 below.

Figure 14 – The Program for the GAL16V8D

The outputs of the EEPROM are used to feed into two Decoder/Drivers to drive the
Common Anode 7-segment displays. The schematic diagram of the circuit is in Figure 15
on the next page.

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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education
 5V 5V

Vcc 16 220Ω
5V a
IN D b
IN C c
IN B 7446 d
1 CLK Vcc 20 IN A e
2 I/A O/h 19 f

GAL16V8D
3 I/B O/g 18 8 GND g
4 I/C O/f 17 220Ω
5 I/D O/e 16
V6 6 I/E O/d 15 5V 5V
V7 7 I/F O/c 14
V8 8 I/G O/b 13
9 I/H O/a 12
Vcc 16 220Ω
10 GND I/OE 11
a
IN D b
IN C c
IN B 7446 d
IN A e
f
8 GND g
220Ω

Figure 15 – The PLD, the Decoder/Drivers, and the 7-segment Displays

III. Conclusion

The project produces visual indicators for the value of the coin passing in front of the
detection inductor. It consists of different analog/digital circuits that the students have
learned during the first three semesters in the Electrical Engineering Technology Program
of Purdue University. This design gives the students the opportunity to put into practice
the theories and applications they possess. It also enhances their troubleshooting skills.

Bibliography
1. Boylestad, R. L. (1995). Introductory circuit analysis (6th ed.). Ohio: Merrill Publishing.
2. Budak, A. (1974). Passive and active network analysis and synthesis. Boston: Houghton Mifflin.
3. Malvino, A. P. (1999). Electronic Principles (6th ed.). Ohio: Glencoe/McGraw-Hill.

NGHIA T. LE
Nghia T. Le is an Assistant Professor of Electrical Engineering Technology of Purdue University. He
teaches at Purdue University, School of Technology at New Albany, Indiana. He earned his B. S. and M. E.
E. E. degrees from the University of Louisville. He specializes is instrumentation and controls. He can be
reached at: nle1@purdue.edu.
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Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition
Copyright © 2003, American Society for Engineering Education