------- CONTENTS -------

• SPECIFICATIONS ··························2

• CIRCUIT DESCRIPTION ·····················3 .SEMICONDUCTOR DATA ····················7

• EXPLODED VIEW ·14

• PARTS LIST· ·17

• ADJUSTMENT· ·21

• PC BOARD VIEW ·24

• BLOCK DIAGRAM ...........•............ ·31

• CIRCUIT DIAGRAM· ·33

IEbI ALI NCO, INC.

• In the NFM, AM, SSB and CW modes, the second IF signal goes through an IF filter (XF300 and XF301) and is input to pin No. 16 of an IF IC (IC304). A 455 kHz third IF signal converted by the IC's internal mixer is output from pin NO.3 and is filtered of adjacent signals by a ceramic filter (FL301). Thereafter, a switch (0306 and 0309) selects the mode. In the NFM mode, the signal is input to pin No.5, demodulated by IC's intemallimiter amplifier and quadrature detection circuit, and output from pin NO.9 as an AF signal. In the AM mode, the Signal is amplified by an AGC amplifier (0313) and input to pin No. 7 of an IF IC (IC305). It is amplified inside the circuit, demodulated by the detection circuit and output from pin NO.8 as an AF signal. In the SSB mode, the Signal goes through a ceramic filter (FL303) and is amplified by an AGC amplifier (0313) and an IF amplifier (0316). It is then mixed with a carrier signal, which is generated by the BFO circuit (X302 and 0318) and fed through a buffer (0317), demodulated by a balanced modulation circuit consisting of diodes (Q315, 0314 and 0313), and output as an AF signal.

• The AF Signal for each of the modes is selected with a switch (IC308) and amplified by an AF signal amplifier (IC309). It is controlled by an AF mute circuit (0319) and adjusted for volume by an electronic volume (IC306). It is then amplified by an audio amplifier (IC307) and input to the speaker.

3) PLL Synthesizer Circuit

• The signal from a 12.8 MHz crystal (X100) oscillator circuit (0100) is input to a PLL IC (IC1 01) to obtain a 10 MHz reference oscillation signal frequency. The comparison frequency is output from a VCO circuit (Q114, L108, 0104, 0105, 0107 and 0108), amplified by an amplifier (0115,0113 and 0116) and divided by a divider inside the PLL IC. It is then compared against the reference frequency to make the PLL synthesizer.

• The VCO output signal (675 - 1225 MHz) is amplified by a buffer amplifier (0115, 0113 and 0120) and input into the first mixer as the first local oscillator Signal.

• Frequencies of 9 kHz steps or less are varied by the VCXO circuit (X300, 0304 and 0305) of the O/A converter (IC303).

4

CIRCUIT DESCRIPTION

1) Frequency

• Signals in the 0.1 - 449.99 MHz and 1500 - 2000 MHz bands are converted into the 736.25 MHz first IF signal by the first local oscillator signal.

• Signals in the 450 - 1499.99 MHz band are converted into the 275.45 MHz first IF signal by this same first local oscillator signal.

• The first IF signal is converted into the 45.05 MHz second IF signal from the two second local oscillator signals (671.2 and 230.4 MHz) by the second mixer circuit.

• Oepending on the mode, the second IF signal is input to one of the two IF amplifier ICs. In one mode, the second IF signal is mixed with a 34.35 MHz third local oscillator signal and converted into a third IF signal of 10.7 MHz, while in the other, it is mixed with a 44.595 MHz third local oscillator signal and converted into the third IF signal of 455 kHz.

2) Receiver Block Front-End Circuit

• The received signal from the antenna goes through the antenna circuits (0128,0124 and 0125) and is screened by seven band pass filters consisting of several antenna switches (0131,0111,0127,0112, 0126, 0114, 0130, 0115, 0134, 0119, 0135, 0121, 0136, 0122 and 0133) to remove unwanted signals.

• The RF signal is amplified by each of the RF amplifiers 0123 (0.1 - 222 MHz), 0125 (222 - 797 MHz), 0126 (797 - 2000 MHz) and 0118. It is then converted into the first IF signal by the first mixer circuit (T1 01, T100, 0109 and 0116).

• The adjacent signals in first IF signal, the 275.45 MHz IF signal and the 736.25 MHz IF signal are filtered out respectively by the band switch (0110 and 0102), the IF filter (L 113, L 110, L 107 and L 101) and the IF filter (FL 102 and FL 101). Then, the signals are input into the second mixer circuit (0102).

• In the second mixer circuit, the 12.8 MHz reference signal is mixed with either a 230.4 MHz second local oscillator signal (amplified 18 times) or a 691. 2 MHz second local oscillator signal (amplified 54 times) selected by a switch (0101), and is converted into a 45.05 MHz second IF signal.

• In the WFM mode, the second IF signal goes through an IF filter (L301) and is input into pin No. 16 of an IF IC (IC305). A 10.7 MHz third IF signal converted by the IC's internal mixer is output from pin No. 14, filtered of adjacent signals by a ceramic filter (FL302) and input into pin No. 12. Next, it is demodulated by IC's internal limiter amplifier and quadrature detection circuit, and output from pin No. 8 as an AF signal.

3

SPECIFICATIONS

Frequency range 0.1 - 1999.999950 MHz
Radio systems received WFM. NFM. AM. USB. LSB. CW
Frequency steps 50 Hz. 100Hz. 1 kHz. 2 kHz. 5kHz. 6:25 kHz. 9 kHz. 10 kHz. 12.5 kHz. 15 kHz. 20 kHz. 25 kHz,
30 kHz. 50 kHz. 100 kHz. 125 kHz, 150 kHz. 200 kHz. 250 kHz. 500 kHz
Sensitivity AM 0.1- 0.5 MHz 10 IJV(20 dBtJ)
(l'yp.) 0.5 - 5 MHz 1.5IJV( 3.5 dBIJ)
5-30MHz 1 IJV(O dBIJ)
3(} MHz - ,1000 MHz 1 IN(O dBIJ)
(1'kHz30 %rnpcl10dB SIN)
sse O.5~ 5 MHz ns IJV(-6 dBIJ)
5 - 30 MHz 0.251.N(-12 dBIJ)
30 MHz - 1000 MHz 0.5 iJV( -6 dBiJ)
(10 dB SIN)
NFM 5 - 30 MHz 0,35 iJV(-9 dBiJ)
30 - 1000 MHz 0,25 iJV(-12 dBiJ)
1000 - 1300 MHz 1.5 iJV(3.5 dBiJ)
1300 - 1999 MHz 10 iJV(20 dBiJ)
(1 kHz 3.5 kHz 12 dB SINAD)
WFM 30 - 1000 MHz 1.5 iJV(3.5 dBiJ)
(12 dB SINAD)
Memory channels 1200
Search pass mode channels 1000
Priority channel 1
Memory banks 30
Channels per bank 40
Search bands 20
Scan speed Approx. 25 CHlsec
Antenna connector BNC,50n
Power supply 4.8V DC (Ni-Cd)/6V DC (AA dry cell)
External power supply 8 - 15V DC
Rated AF output Min, 100 mW, 10% THD
Power consumption At rated output Approx. 200 mA
Squelched Approx. 140 mA
BS ON Approx. 30 mA
Weight Approx. 320 9
Dimensions 57 x 150 x 27,5 mm (without projections)
Operating -10 - +50°C
temperature range
Frequency stability ±10 ppm 2

19) LCD Diagram

II

~

:H TCP,SEAL Center I II

II

I I

=- n M PMS IVFO <:DO BS = PRIO SKIP~TT Oor m

~ IIIII~IIIIII

111111:111111 111111:111111

I I

• • • • • • • •

II II

NCV1-------------------v~

13

18) Transistor, Diode, and LED Outline Drawings

12

DA204U DAN202U MA742TX MA741WK 1SS295 1SS312
----------- ----------- ----------- ----------- ----------- -----------
XD0130 XD0230 XD0250 XD0252 XD0306 XD0307
----------- ----------- ----------- ----------- ----------- ----------- 1SV231 1SS356 MA111 MA729 U2FWJ44N HVU350
----------- ----------- ----------- ----------- ----------- -----------
XD0260 XD0272 XD0290 XD0291 XD0294 XD0313
----------- ----------- ----------- ----------- ----------- ----------- TA

1 B

2B

2F

4

DTB123YK XP150nx UN9112 UN5212 DTA143ZE DTC143ZE

----------- ----------- ----------- ----------- ----------- -----------

XU0155 XU0172 XU0182 XU0184 XU0185 XU0186

2SC4649 2SC4181 2SC4738 2SC5006 2SC5007 2SC5008

XT0108 XT0149 XT0150 XT0151 XT0152 XT0153

BRPG1201W SML7310MT PG1101F 2SK425 UMC5N

----------- ----------- ----------- ----------- -----------------------

XLOO28 XL0036 XL0045 XE0033 XU0152

"" ~B~'

C2 B2IC1 C2 4.7k BJC1

1l1li

1l1li

2SA1213-Y

XT0088

SB~

B C E E

14) S-S0725SN-2 (XA052S)

Pin Assignment

Block Diagram

.-----------------------------------------------

15) TA75W01FU-2 (XA0349)

~ ~ J

16) TC4W53FU (XA034S)

Pin Assignment

Block Diagram

COMMON

VDD

17) S-S12XXSG (XA035S)

Pin Assignment

Block Diagram

: - - - - - - - - - -- P-aras1tlcdiode- - - - -:

VIN: : VOUT

""'-""""-<3

RL

~-----------------------------:

11

10) TC75S51 F (XA0465)

11) TK11235AM (XA0467) Pin Assignment

N. BYPASS

12) TK11819M (XA0468)

Pin Assignment

13) BU4094BCFV (XA0506)

Pin Assignment

STROBE

o

DATA

CLOCK 01 02 03

VSS

10

Block Diagram VIN

HC

GND N.BYPASS

VOUT

Block Diagram

VIN

Block Diagram

OUTPUT 1 ENABLE

PARALLEL OUTPUT

8) HN58V257 A (XA0462)

Pin Assignment

DE 0
A11
A9
AS
A13
WE
RES
VCC
ROYIBusy
A14
A12
A7
A6
A5
A4
A3 2 A10 CE NC 1/07 1/06 1/05 1/04 1/03 VSS 1/02 1/01 1100 NC AD A1 A2

Block Diagram

VCC
VSS
RES
OE
CE
WE
RES
AD
to
A5 Address
buffer and
A6 latch
to
A14 1100 to 1/07 ROYIBusy

9) TA7792F (XA0464)

9

4) NJM2070MT (XA0210)

-INPUT

NC

OUTPUT

POWER GND

5) TA7806F (XA0267) Pin Assignment

Block Diagram

Z1

6) S-80733SLAXT2 (XA0357) Pin Assignment

Block Diagram

~--------------------------------------------:

, ,

OUT

vss

7) TA31136FN (XA0404)

, '

~--------------------------------------------~

• Parasitic diode

8

SEMICONDUCTOR DATA

1) LC75366M (XA0345)

Pin Assignment

_:+- ........ ~--<>'1j- ~o-t--ORCTl ~ t+---+j -i:----'ORCT2 NC( •••••••

'----- ---~-()RVref

.................... ~ :

I LEVEL SHIFT I

1r

Block Diagram

z

~

LlOdBIN

.---------_ - --.---_ ---_.- .,

NO ~,i::

LCT20>---!_'_: _"'!~' ... :- __ --,:- l::,i ,······-9NC

LVrel

.................... ~ ;

,. _ ------_._.- ---.-----_. __ ...

LCTl

S ....
CE 4
01
~ CONTROL
CL

01 ~ g SHIFT REGISTER I

2) NJU4066BM (XA0095)

{ INIOUT 1 SIG,A OUTIIN

{ OUTIIN 3 SIG,B INIOUT

3) MB1511 (XA0173)

Pin Assignment

o

f--_o.iq,L LATCH

I

Block Diagram

LE

FC LO

eP

BiSW

DO

NO

RIOdBIN

( VOO

( VSS

Clock

_ : Data Signal _ : Conlrol Signal

7

No. Name Pin Name I/O Description H L HiZ Pull UP
32 P43/AD3 DD3 1/0 EEPROM DATA
33 P44/AD4 DD4 1/0 EEPROM DATA
34 P45/AD5 DD5 1/0 EEPROM DATA
35 P46/AD6 DD6 1/0 EEPROM DATA
36 P47/AD7 DD7 1/0 EEPROM DATA
37 P50/A8 A8 0 EEPROM ADRESS
38 P51/A9 A9 0 EEPROM ADRESS
39 P52/A10 A10 0 EEPROM ADRESS
40 P53/A11 A11 0 EEPROM ADRESS
41 P54/A12 A12 0 EEPROM ADRESS
42 P55/A13 A13 0 EEPROM ADRESS
43 VSS GND GND
44 P56/A14 A14 0 EEPROM ADRESS
45 P57/A15 IRES 0 EEPROM LCD RESET
46 P60 STB4 0 STB FOR IC500
47 P61 SHIFT 0 NOT USED
48 P62 OECNT 0 OUT CONTROL IC500
49 P63 ICE 0 CHIP ENABLE EEPROM
50 P64//RD RD I OUT ENABLE EEPROM
51 P65//wR /WE I WRITE ENABLE EEPROM
52 P66/wAIT OPTSTB 0 STB FOR OPTION
53 P67/ASTB OPTCT 0 CONTROL FOR OPTION ON OFF
54 P1001T151T05 RDY I EEPROM STATUS
55 P1011T161T06 OPTDET I OPTION DETECT ON OFF
56 P102 WIDES I ENABLE BAND
57 P103 LOCK I PLL LOCK UNLOCK
58 P301T00 BEEP 0 BEEP
59 P311T01 AFS 0 AMP CONTROL ON OFF
60 P321T02 MUTE 0 MUTE ON OFF
61 P331T11 STB3 0 STB FOR IC300
62 P341T12 STB2 0 STB FOR IC306
63 P35/PCL STB1 0 STB FOR IC103
64 P36/BUZ LE 0 STB FOR IC101
65 P37 BUSLS 0 BUSY LED CONTROL ON OFF
66 P90 DB4 0 DATA LCD
67 P91 DB5 0 DATA LCD
68 P92 DB6 0 DATA LCD
69 P93 DB7 0 DATA LCD
70 P94 E/SCLK 0 ElSCLK LCD
71 P95 RW/SID 110 RW/SID LCD
72 P96 RS/CS 110 RS/CS LCD
73 P120/RTPO DATA 0 DATA FOR 4094
74 P121/RTP1 CLK 0 CLK FOR 4094
75 P1221RTP2 BATSV 0 BATT SAY CONTROL ON OFF
76 P1231RTP3 RFL 0 FILTER CONTROL OFF ON
77 P124/RTP4 RFM 0 FILTER CONTROL OFF ON
78 P125/RTP5 RFH 0 FILTER CONTROL OFF ON
79 P126/RTP6 BARS 0 NOT USED
80 P127/RTP7 IFS 0 IF SWITCH OFF ON
81 VPP GND
82 X2 XTAL MAIN
83 X1 XTAL MAIN
84 VDD VDD
85 XT2 XTAL SUB
86 XT1/P07 XTAL SUB
87 IRESET IRST I RESET CPU
88 POO/INTPOIT1 00 LAMPK I LAMP KEY OFF ON 0
89 P01/1NTP11T101 BRDET I BAT DETECT 0
90 P02/1NTP2 POWK I POWER KEY OFF ON 0
91 P03/1NTP3 MONK I MONITOR KEY OFF ON 0
92 P04/1NTP4 FUNK I FUNCTION KEY OFF ON 0
93 P05/1NTP5 A I ROTARY ENCORDER 0
94 P06/INTP6 B I ROTARY ENCORDER 0
95 AVDD VDD VDD
96 AVREFO VCC VCC
97 P10/ANI0 SaD I sa
98 P11/ANI1 SM I S-METER
99 P121ANI2 JRDET I NOT USED
100 P131ANI3 BATTDET I LOW BAT DETECT 6

P14/AN14- P15/AN15- P16/AN16- P17/AN17- 4

AVSS P130/ANOOP131/AN01 AVREF1 P70/S121RXD - P71/S02rrXD - 1 P721SCK2/ASCK - 1

VSS P20/S11- P21/S01- 1 P221SCK1- 1 P231STB-1 P24/BUSY - 17 P251S10/SBO- 1 P261S00/SB1 - 1

P27/SCKO P80/AO- 1 P81/A1 P821A2- P831A3- 4

7 - P1221RTP2 4 - P121/RTP1 7 - P120/RTPO 7 -P96

71 - P95

70 - P94 -P93

-P92

7-P91 -P90

-P37

- P36/BUZ

- P35/PCL

-- P34ff12

-_ P33rr11

-- P32rr02

-- P31rr01

-- P30rrOO

7 -P103 6 -P102

- P101ff16rr06 4 - P100rr15rr05 -- P67/ASTB

-- P66IWAIT

1 -P651WR

~rrrTr~~~~~~rTI~~rrrTrrrT~~~~~

rc 506

No. Name Pin Name I/O Description H L HiZ Pull UP
1 P14/AN14 CO 0 16KEY MATRIX
2 P15/AN15 CB1 0 16KEY MATRIX
3 P16/AN16 CB2 0 16KEY MATRIX
4 P17/AN17 CB3 0 16KEY MATRIX
5 AVSS GND GND
6 P130/ANOO BARTU 0 NOT USED
7 P131/AN01 VCXOIN 0 VCXO CONTROL
8 AVREF1 VCC VCC
9 P70/S 121RXD RXD . I CLONE RX INPUT
10 P71/S02ITXD TXD 0 CLONE TX OUTPUT
11 P721SCK2/ASCK PCNTS 0 DC DC POWER CONTROL ON OFF
12 VSS GND GND
13 P20/S11 RBO I 16KEY MATRIX OFF ON
14 P21/S01 RB1 I 16KEY MATRIX OFF ON
15 P221/SCK1 RB2 I 16KEY MATRIX OFF ON
16 P23/STB RB3 I 16KEY MATRIX OFF ON
17 P24/BUSY RB4 I 16KEY MATRIX OFF ON
18 P25/S10/SBO RB5 I 16KEY MATRIX OFF ON
19 P26/S00/SB1 SRCHK I SRCH KEY OFF ON
20 P2711SCKO NOVOEDET NOT USED
21 P80/AO AO 0 EEPROM ADRESS
22 P81/A1 A1 0 EEPROM ADRESS
23 P82/A2 A2 0 EEPROM ADRESS
24 P83/A3 A3 0 EEPROM ADRESS
25 P84/A4 A4 0 EEPROM ADRESS
26 P85/A5 A5 0 EEPROM ADRESS
27 PB6/A6 A6 0 EEPROM ADRESS
2B P87/A7 A7 0 EEPROM ADRESS
29 P40/ADO DDO 1/0 EEPROM DATA
30 P41/AD1 DD1 1/0 EEPROM DATA
31 P42/AD2 DD2 I/O EEPROM DATA 5

PC BOARD VIEW

CPU Unit Side A

24

R8 G:,IJ ! 01 ~ CO~

RO,., bd J)

D

(;5S~ C55S'[!]j C5,.[!]]

"""[]) C55G[!]j

C5~.[!]j C555 [!J)

CS3lI[!]j CS3?[!]j C530[!J)

CN!501

10001

C~

Qe

~D

LP~

o

o

i~ bJbJ ~~
i~ ~,

[lfi' [!J)C5SPC"'" IEIJ F.1 a

CS4e ~it

!;1 [!]c5 ••

~ [!J)C5,$

! 1EJl:,45

0503

~

7. NFM sensitivity

• Apply SG=6dBu 1 kHz and 3.5kHz DEV (NFM @). Measure SP terminal. Adjust F1102, FL 101, and L 102 in the RF Unit.

While receiving on f=198.70, using the distortion factor meter oscilloscope, repeat adjustment until obtaining optimum SINAD.

• Apply SG=OdBu 1 kHz and 3.5kHz DEV(NFM CD). Measure SP terminal. Adjust L 113, L 110, L 107, and L 101 in the RF Unit.

While receiving on f=510.03, using the distortion factor meter oscilloscope, repeat adjustment until obtaining optimum SINAD.

8. WFM distortion

• Apply SG=60dBu 1 kHz and 22.5kHz DEV(WFM @). Measure SP terminal. Adjust L305 in the IF Unit.

While receiving on f=198.7, using the distortion factor meter oscilloscope, set distortion factor to minimum and max. AF output to 6%.

9. WFM sensitivity

• Apply SG=10dBu 1 kHz and 22.5kHz DEV(WFM @). Measure SP terminal. Adjust L304 and L309 in the IF Unit.

While receiving on f=198.70, using the distortion factor meter oscilloscope, repeat adjustment until obtaining optimum SINAD.

10. SQ level adjustment

• Apply SG=-3dBu. Measure SP BUSY terminal. Adjust VR302 in the IF Unit.

While receiving on f=198.70(NFM @), adjust on LCD sa level 1, turn VR304 clockwise to close squelch. Then, turn counter-clockwise to open and fix. However, close with sa.

11. NFM S meter adjustment

• Apply SG=25dBu, unmodulated(NFM @). Measure LCD terminal. Adjust VR302 in the IF Unit.

While receiving on f=198.70, turn SG OFF when S meter is full scale. Check S meter does not light up.

12. WFM S meter adjustment

• Apply SG=32dBu, unrnodulated ®, WFM. Measure LCD terminal. Adjust VR301 in the IF Unit.

While receiving on f=198.70, turn SG OFF when S meter is full scale. Check S meter does not light up.

23

ADJUSTMENT

1) Required measuring instruments and tools

1. Digital voltmeter

2. Regulated power supply of 10 V, 1 A or more

3. Oscilloscope

4. Frequency counter

5. External speaker 6.0.1 MHz - 2 GHz SG

7. Audio analyzer

Level meter, distortion factor meter, linear detector

8. Spectrum analyzer

1 m coaxial cable with BNC connector Speaker cable with 3.50 plug

I I

r r

AF GND

Cloning cable with 2.50 stereo plug on both ends

I r I I i II i l___1 _ ____j

NC CLONE GND

Power supply cable for external power supply terminal (For DJG5)

2) Adjustment

All SSG outputs are indicated in EMF. The SP is 8 Q. Output is 50 mW.

Level meter filter must be HPF (30 - 50 Hz) and LPF (10 - 15 kHz).

21

ADJUSTMENT

1) Required measuring instruments and tools

1. Digital voltmeter

2. Regulated power supply of 10 V, 1 A or more

3. Oscilloscope

4. Frequency counter

5. External speaker 6.0.1 MHz - 2 GHz SG

7. Audio analyzer

Level meter, distortion factor meter, linear detector

8. Spectrum analyzer

1 m coaxial cable with BNC connector Speaker cable with 3.50 plug

I I

r r

AF GND

Cloning cable with 2.50 stereo plug on both ends

I r I I i II i l___1 _ ____j

NC CLONE GND

Power supply cable for external power supply terminal (For DJG5)

2) Adjustment

All SSG outputs are indicated in EMF. The SP is 8 Q. Output is 50 mW.

Level meter filter must be HPF (30 - 50 Hz) and LPF (10 - 15 kHz).

21

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8

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