FPR 10 1.lect

Floorplanning, Physical Synthesis,
and Place and Route (Flat)

Version 10.1
Lecture Manual February 3, 2011
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Table of Contents
Floorplanning, Physical Synthesis, and Place and Route (Flat)
iSection 1: Floorplanning, Placement, and Trial Route
Module 1 About This Course .................................................................................... 3

Lab 1-1 Locating Cadence Online Support Solutions
Lab 1-2 Customizing Notification and Search Preferences
Module 2 Encounter Digital Implementation (EDI) Overview .............................. 25
Module 3 Design Import and Customizing the EDI Environment ........................ 39
Module 4 Selecting and Highlighting Objects in the Design ............................... 59
Module 5 Floorplanning the Design ....................................................................... 69

Lab 2-1 Importing a Design
Lab 2-2 Using Bindkeys
Lab 2-3 Tearing Off Menus
Lab 2-4 Clearing the Floorplan
Lab 2-5 Initializing the Floorplan
Lab 2-6 Customizing the Menus
Lab 2-7 Checking the Design
Module 6 Planning Power ..................................................................................... 119
Module 7 Routing Power with Special Route ...................................................... 145

Lab 2-8 Floorplanning a Design
Module 8 Running Detail Placement .................................................................... 157
Module 9 Scan Optimization and Reordering ..................................................... 193
Module 10 Analyzing Route Feasibility with Trial Route ...................................... 205

Lab 3-1 Running Placement
Lab 3-2 Running a Trial Route
2/2/2011 Cadence Design Systems, Inc. iii

iSection 2: Extraction, Timing Analysis, CTS, and Optimization
Module 11 Extracting Parasitics and Analyzing Timing ...................................... 219
Module 12 Multi-Mode Multi-Corner Analysis ...................................................... 253

Lab 4-1 Extracting RC Data
Lab 4-2 Running Timing Analysis and Generating a Slack Report
Module 13 Optimizing and Closing Timing ........................................................... 281
Module 14 Implementing the Clock Tree .............................................................. 311

Lab 4-3 Running Timing Optimization
Lab 4-4 Running Clock Tree Synthesis
Lab 5-1 Extracting and Generating Scale Factors
Module 15 Analyzing Power ................................................................................... 355

Lab 6-1 Running Power Analysis
iv Cadence Design Systems, Inc. 2/2/2011

iSection 3: Detail Routing, ECOs, and Foundation Flows
Module 16 Detail Routing for Signal Integrity, Timing, and Design for Yield ..... 369
Lab 7-1 Routing Critical Nets with Shielding and Spacing
Module 17 Evaluating Routing Problems .............................................................. 413
Module 18 Wire Editing ........................................................................................... 431

Lab 8-1Using the Interactive Wire Editor
Module 19 Preventing and Fixing Signal Integrity Problems .............................. 447
Module 20 Metal Fill ................................................................................................. 465
Module 21 Verification ............................................................................................ 475

Lab 9-1Using the Verify Commands in a Design
Module 22 Engineering Change Order (ECO) ....................................................... 493
Module 23 Writing Out a Design ............................................................................. 517

Lab 10-1Loading a Design for ECO Routing
Module 24 Encounter Database Access Commands ........................................... 525

Lab 11-1 Using the dbGet and dbSet Commands
Module 25 Foundation Flow Scripts ...................................................................... 537

Lab 12-1 Generating and Running the Foundation Flow Scripts
Appendix A Setting Constraints Using SDC ............................................................ 551
Appendix B Pipeline Register Placement ................................................................ 569
Appendix C Encounter Parallel Processing ............................................................ 577
Appendix D Nanometer Design Rule Support ......................................................... 583
Appendix E Implementation Details ......................................................................... 629
2/2/2011 Cadence Design Systems, Inc. v

Floorplanning, Physical Synthesis, and Place and
Route (Flat)
iSection 1: Floorplanning, Placement, and Trial Route

Version 10.1
February 3, 2011
Floorplanning, Physical Synthesis, and Place and Route (Flat), version 10.1 1
2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 2
About this Course
Module 1
February 3, 2011
Course Prerequisites
Before taking this course, you must have basic knowledge of the following:
 Design methodology
 Place and route concepts
ASIC: Application-specific integrated chip
Course Objectives
In this course, you
 Import and floorplan your design
 Place the standard cells and blocks in the design
 Run power planning, power routing, and power analysis.
 Reorder scan chains.
 Analyze routing congestion.
 Extract parasitics and generate timing reports
 Create clock trees
 Optimize and close timing
 Analyze how to optimize routing with technology (LEF) and design files
 Route critical nets with shielding and spacing
 Edit wires using the interactive wire editor
 Analyze and fix routing violations
Course Objectives (continued)
 Report and fix timing and signal integrity violations
 Implement an Engineering Change Order (ECO)
 Explore the Foundation scripts to implement your design
Classroom Course Agenda
Day 1 Day 2
 About this Course  Extracting Parasitics and Analyzing
Timing
 Overview
 Running Multi-Mode Multi-Corner
 Getting Started
Analysis
 Selecting and Highlighting Objects
 Optimizing and Closing Timing
in the Design
 Implementing the Clock Tree
 Floorplanning the Design
 Analyzing Power
 Planning Power
 Routing for Signal Integrity, Timing,
 Routing Power with Special Route
and Design for Yield
 Running Detail Placement
 Evaluating Routing Problems
 Optimizing and Reordering Scan
Chains
 Analyzing Route Feasibility
with Trial Route
Classroom Course Agenda
Day 3
 Editing Wires
 Analyzing and Optimizing for

Signal Integrity
 Implementing Metal Fill
 Verifying the Design
 Implementing an Engineering
Change Order (ECO)
 Writing Out a Design
 Using Encounter Database Access

Commands
 Generating and Running
Foundation Flow Scripts
iLS Course Modules
iSection 1 iSection 2
 About this Course  Extracting Parasitics and
 Overview Analyzing Timing
 Getting Started  Running Multi-Mode Multi-
 Selecting and Highlighting Corner Analysis
Objects in the Design
 Optimizing and Closing Timing
 Floorplanning the Design
 Implementing the Clock Tree
 Planning Power
 Analyzing Power
 Routing Power with Special
Route
 Running Detail Placement
 Optimizing and Reordering Scan
Chains
 Analyzing Route Feasibility
with Trial Route
iLS Course Modules
iSection 3
 Routing for Signal Integrity, Timing,
 Evaluating Routing Problems
 Editing Wires
 Analyzing and Optimizing for Signal

Integrity
 Running Metal Fill
 Running Verification
 Implementing an Engineering
Change Order (ECO)
 Writing Out a Design
 Using Encounter Database Access

Commands
 Generating and Running Foundation
Flow Scripts
Learning Map: Digital Design and Encounter Technology
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Getting Help for Encounter Digital Implementation
There are four ways to get help:
 Cadence Help: Accessing version-specific standalone help
 cdnshelp
 Cadence Online Support: Accessing documents and support

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 Cadence Community: Staying current with tips and tricks

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 http://www.cadence.com/community/blogs
 http://www.cadence.com/cdnlive
 The Encounter commandGetIt standalone utility
Cadence Help
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Documents are available in both HTML and
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 The Help button on forms
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 To access Cadence Help from a Cadence software application, from the menu, choose
Help—Cadence Documentation. The browser displays the document page. After the
document page opens, click the Library button to open the Library window.
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When the Library window appears, navigate to the manual you want by selecting the
specific product, then double-click to open the manual in your browser.
Cadence Online Support (COS)
 Cadence Online Support
(http://support.cadence.com) is a
website that gives you access to
support resources, including the
following documentation for EDI 10.1:
 Encounter User Guide
 Encounter Text Command Reference
 Encounter Timing Closure Guide
 LEF/DEF Language Reference
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engineers
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Searching the Knowledgebase

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14
Using Cadence Online Support
Access Cadence Online

Support
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If you don’t find a solution at the online support site...
Submit Service
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Demo: Cadence Online Support
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 Register for Cadence
Online Support
 Search the
knowledge base
 Submit a service
request
 View your service
request
Registering for Cadence Online Support

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17
Looking Up Commands with CommandGetIT
You can find the options of a particular EDI command by running the
CommandGetIt Tool.
Bring the tool up with your browser:
mozilla $InsPath/lnx86/doc/CommandGetIT/CommandGetIT.html
In this example, searching for “place” will display all commands and options
that contain the place string.
Demo: Looking Up Commands with CommandGetIT
Certificate of Course Completion (Optional)
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 Test your knowledge and understanding
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 To receive a Certificate of Completion, you must complete an online

exam with a score of 75% or more.
 Detailed instructions for obtaining a certificate of completion are
provided at the end of this course.
You can obtain a proof of attendance after attending a Cadence instructor-led course (public,
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Pre and Post Assessments
Pre and post assessments are a way to help you determine what new
knowledge you have gained by completing this course.
 You will take a pre-class assessment at the start of the class.
 You will take a post-class assessment at the end of the class.
 These will have the same set of questions and take about
15 minutes to complete.
 After the Post-Assessment we will go over the questions and answers
in detail.
The expectation is that you will not successfully answer most of the
questions in the pre class assessment, which is expected as you have not
yet completed the class.
Conversely, at the end of the class you should be able to answer correctly
most of the post assessment questions.
Completing the Pre-Class Assessment
1. In a web browser enter: http://exam.cadence.com.
2. Log in to the exam server:
a. Name: your complete email address (example: joe@cadence.com)
b. Group: your company’s email suffix (example: cadence.com)
3. Select the pre-class assessment for this class:
ES Floorplanning, Phys. Synth, Place and Route (Flat) PRE
4. Complete the assessment. You do not need to answer all questions.
5. Click Submit at the bottom of the exam.
Note: You will be given a score but will not be provided with the
answers until you take the post assessment at the end of class.
Lab Exercises
Lab 1-1 Locating Cadence Online Support
Lab 1-2 Customizing Notification and Search Preferences
Encounter Digital Implementation (EDI)
Overview
Module 2
February 3, 2011
Module Objectives
In this module, you
 Describe the flat Encounter® Implementation flow
 Explore the directory structure of the software
 Start the software and run it in both batch and interactive modes
 Explore the log and command files
 Run multi-threaded and distributed CPU models to speed up the

implementation
 Identify the main parts of the Encounter Design Window
 Become familiar with the main features of the Encounter Digital

Implementation (EDI) system
Flat Design Implementation Flow
1 2 3 4 5
Design Initialization
Scan
Design Import Routing Add Metal Fill
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff
Create and Load JTAG/Cell Clock Tree Postroute Physical
Floorplan Placement Synthesis Setup/Hold Fixing Verification
Timing, Mode Pre-CTS Post-CTS Post-SI

Setup Timing Analysis
Setup Fixing Setup/Hold Fixing Setup/Hold Fixing
Timing Timing Timing Timing

Met? Met? Met? Met?
Signoff
Software Installation Directory Structure
 The Encounter binary is located in the following directory path:
<installation_directory>/10.10<subversion>/<binary>/
bin/encounter
 The documentation is installed in the following location:

<installation_directory>/10.10<subversion>/binary/doc
 Tcl scripts for automating various tasks are located at:

<installation_directory>/lnx86/share/fe/gift/scripts/tcl
There are currently 170+ Tcl scripts in the gift directory.

 You can find the installation path, as long as the path is set, by typing
the following in an xterm prompt:
lnx-cadence> which encounter
Starting the Software
1. Open a window (xterm)
This window becomes the input window for Tcl commands after you start the
software.
2. To start a session, enter

encounter
This same window becomes the console for displaying messages from the
software.
The xterm window becomes the console for:
 Outputting messages from the software
 Entering commands or for sourcing a Tcl command file.
Using this window for operations other than to interface with the software will
suspend the session until the operation is completed.
Log and Command Files
The Encounter Digital Implementation system creates two types of files: log
files and command files.
 Default log file name: encounter.log<session#>
 Default command file name: encounter.cmd<session#>
 Custom log file name: encounter -log myfile
Example Command File

Filename: encounter.cmd<session#>
loadConfig dtmf_chip.conf 0
commitConfig
loadFPlan /home/abc/dtmf_chip.fp
placeDesign –prePlaceOpt
checkPlace
timeDesign -preCTS
exit
The gift directory, which is a part of the Encounter Digital Implementation installation,
contains several Tcl scripts that you can use as templates to customize your design flow.
The encounter.cmd<seq#> file contains commands that you have entered in the command
window and the graphical interface. It can be used as a replay file. To run the file, delete the
lines related to configuration and remove the 0 in the loadConfig command.
Use the 1 after the loadConfig command to commit the loaded design. If you specify 0, the
design is not committed.
What Is the Log Viewer?
The Log Viewer is a graphical interface for displaying the Encounter log file
in a separate console. The viewer helps you debug by letting you
 Easily find the information in log files
 Expand/collapse log file contents
 View color-coded messages (ERROR and WARN)
 Run string matching/search/find
 View real time updates as log file changes
 Get direct links to extended help (when available)
Limitation
 The viewer is not available if you start the Encounter software in the
nongraphical mode.
Command that you can use in an xterm window:

viewlog [-file <logFileName>]
Example Log Viewer
Running in Batch Mode
There are two ways to run Tcl commands scripts in batch mode:
 In the Encounter Digital Implementation window, run a set of
commands by entering:
source generateSDF.tcl
 In the C-shell, run a job without displaying the Encounter Digital
Implementation window by entering:
encounter -init generateSDF.tcl
 To start the Encounter Digital Implementation graphical interface after
running the tool in batch mode, you can enter:
win
 Once you start the graphical interface, you can turn it off by entering:
win off
To start the Encounter® platform in 64-bit mode, enter the following command:
setenv CDS_AUTO_64BIT ALL
If you do not use this command, the Encounter platform automatically starts in 32-bit mode.
Using CPU Models to Maximize Resources
There are three CPU models that you can use to maximize your hardware
resources and Encounter licenses in order to save time.
Singlethreaded Multithreaded Distributed
Superthreaded
CPU
CPU CPU CPU
Mem CPU CPU Mem Mem Mem

Shared Memory Network
Distributed: Multiple machines each with a single processor

Multithreaded: Multiple processes on a single machine
Superthreaded: Multiple processors and multiple machines
Multithreaded uses different CPUs on the same machine.

 Pros: Significantly less memory space used (There is no need to duplicate memory
footprint on each machine.)
 Pros: There is no need to wait for machine to be available.
 Cons: Can only utilize CPUs available on that machine
Distributed: uses single CPUs on different machines
 Pros and Cons are reverse of multithreaded
Superthreaded: has multithreaded + distributed
Multithreaded results in:
 Reduction in hardware cost because of less memory used
 Reduction in designer wait time for CPUs
 CPUs/cores per machine are increasing, so cons will be less pronounced.
The conclusion is that superthreaded is better.
Choosing the Appropriate CPU Model
Singlethreaded Multithreaded Distributed
Superthreaded
CPU CPU CPU CPU CPU CPU
Mem Shared Memory Mem Mem Mem
Network
Singlethreaded Multithreaded Superthreaded Distributed

Pros Cons Pros Cons Pros Cons Pros Cons
Easy to Significantly Can only Advantages Single Need to
develop less utilize of both CPU on wait for
and memory CPUs multi- multiple machine to
debug space used; available on threaded machines be
no memory one and available
footprint machine distributed
duplication.
Encounter Digital
No need to Implementation:
No need to The first XL license
wait for wait for
machine to enables 2 CPUs,
machine to each additional XL license
be available be available
enables 3 additional CPUs.
Multithreaded uses different CPUs on the same machine.

 Pros: Significantly less memory space used .(There is no need to duplicate memory
footprint on each machine.)
 Pros: There is no need to wait for machine to be available.
 Cons: Can only utilize CPUs available on that machine
Distributed: uses single CPUs on different machines
 Pros and cons are reverse of multithreaded
Superthreaded: has multithreaded + distributed
Multithreaded results in:
 Reduction in hardware cost because of less memory used
 Reduction in designer wait time for CPUs
 CPUs/cores per machine are increasing, so cons will be less pronounced.
The conclusion is that superthreaded is better.
Specifying Multiple CPU Usage
Use the Multiple CPU Processing form to specify options for multithreading,
distributed processing, and superthreading.
Options – Set Multiple CPU Usage
You can run superthreading using the rsh command, and with LSF, Sun Grid, or RSH
configurations.
The Encounter Digital Implementation Window
Pull-Down
Menus Design Views
Visibility
Toolbar Icons
Selectability
Floorplanning
Icons
Number of Objects selected
Press Autoquery to display

object properties in a pop up Design
Status
Encounter Digital Implementation Features
The Encounter® Digital Implementation system is a full-chip silicon prototyping and
implementation system. It has many built-in advantages, including
 RTL synthesis
 Full gate-level placement
 Open system with industry standard interfaces and ease of use
 Advanced power planner and power analysis
 Fast placement and multithreaded placement on multiple CPUs
 Low-power synthesis and implementation
 Clock tree synthesis (CTS)
 Fast trial routing
 Fast 2.5-D parasitic extraction
 Fast delay and timing analysis using industry-standard timing libraries and
constraint formats
 Fast timing closure using global physical synthesis (GPS)
 Integrated SignalStorm® delay calculation
 Fast timing and signal-integrity-aware detail routing for advanced nodes
Design Import and Customizing the EDI
Environment
Module 3
February 3, 2011
Module Objectives
In this module, you will
 Create a configuration file to import the design files and technology
libraries
 View the design after importing the libraries and design files
 Set up and use bindkeys
 Dock and un-dock submenus
 Saving and restoring workspaces
 Customize the menus
 Check your design after importing files
The Design Implementation Flow
1 2 3 4 5
Scan
Routing Add Metal Fill
Post-CTS Flow
Postroute Flow
Design Import
Pre-CTS Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
Input Files for EDI Flat Implementation
Synthesized Gate-Level Netlist
SDC I/O File Floorplan Clock Tree Spec
Verilog
EDI
Timing Physical Cap Tables

Verilog + Libraries Libraries
DEF+OA/GDSII
Netlist Design Netlist – Verilog (or

OA) Timing Timing Constraint File(s) – SDCs for all modes
Constraints
Floorplan Floorplan File – Encounter Digital
File
Implementation .fp file, DEF file
Timing Timing Libraries – .libs for all sets, all Vts or
Libraries
Clock Tree ECSM
Spec Clock Tree Specification File
LEF LEF Libraries or OA)
Libraries
Scan
Information Scan chain information – Tcl or DEF
Technology Technology Files – Cap Tables and QRC (optional)
I/O Files
Information I/O Pad file (pads or pins)
GDS
SI SI Libraries – CDB (optional)
Libraries
Layer Map GDS Layer Map File (if
using GDS Format)
Importing the Design
File … Floorplan … Place Optimize Clock Route Timing ... Verify ... Tools ...
The Design Import menu selection brings up a form for importing the RTL netlist, or gate-
level netlist and the physical and timing libraries.
Use the Save Design menu command to save your design often.
The saveDesign command lets you write out a hierarchical Verilog® netlist after running
placement (with timing-driven option), scan optimization, clock tree synthesis, and
optimization.
The Encounter® Digital Implementation system supports the OpenAccess database format.
You can use standard C++ as the interface (API) to access and manipulate database objects.
Import Design Form: Basic Options
Use this form to import the design libraries (physical and timing) and the
netlists.
File – Import Design
Enter the Verilog Netlist files.
Specify the LEF file for place and route
Enter the name of the I/O file that contains

information about where the I/Os will be placed
around the core area.
Specify the timing libraries and SDC

constraints in the MMMC View definition
file
What Is a Library Exchange Format (LEF) File?
The LEF file contains layer, via, and macro definitions as in this example.
LAYER m1
TYPE ROUTING ;
WIDTH 0.50 ; Dimension
END m1 “bounding box”
LAYER via
TYPE CUT ;
END via VDD
MACRO NAND_1 Symmetry
FOREIGN NAND_1 0.00 0.00
ORIGIN 0.00 0.00 ;
A B (X, Y, or 90-degrees)
SIZE 4.5 by 12.0 ;
SYMMETRY x y ;
SITE core ;
PIN A Pins
DIRECTION input ; • Direction
PORT Y • Layer
LAYER m1 ; • Form
RECT 6.4 10.0 6.8 10.4 ;
END NAND_1
PIN Y
….. GND
OBS
LAYER via ; reference point
RECT … (typical)
RECT ...
END NAND_1
LEF is the text version of the Virtuoso® abstract cellView. It represents an "abstraction" of the
layout needed for physical implementation. LEF files are typically provided by foundries.
They can be generated from abstracts, which in turn are generated from layouts. The
Cadence® Abstract Generator tool is used to create abstracts. For additional information about
the LEF format, refer to the LEF/DEF Language Reference.
The physical library contains information needed for floorplanning, placement, and global
routing. The semiconductor vendors can provide this information in one or more library files
in the Library Exchange Format (LEF).
Technology information is included in the LEF file:
 Layer names
 Layer widths
 Layer usage
The physical cell and pin names have to match the logical cell and pin names. The cell data
includes:
 External dimensions — bounding box
 Cell pin and port descriptions — direction, layer, location
 Blockage description — obstructions.
For over-the-cell routing, obstructions in the cell tell the router where it cannot route on a
layer. (This is not shown in the picture.)
Symmetry rules specify how to rotate the cell (X, Y, or 90-degrees increment).
Additional details of the LEF format are on the SourceLink® site in the LEF/DEF Language
Reference manual.
Setting Defaults for High-Fanout Nets
File – Design Import
The Exclude Net file is typically used to exclude
Scan Enable and Reset types of signals. This
file speeds up the delay calculation process. If
this file is not specified, the default parameters
on this form are used for all nets that have
greater than 1000 pins.
Gate Delay
Exclude Net File Format 1: <netName> <netDelay> <netOutputTran> <netLoad>

Exclude Net File Format 2: <netName> <netDelay> Driver Delay
Viewing Parameters in the Configuration File (.conf)
####################################################
This file contains the parameters that
# Generated by: Cadence Encounter 10.11
were filled out in the Design Import
# OS: Linux x86_64(Host ID lnx-cadence)
form. After generating it, you can
# Design: DTMF_CHIP modify this ASCII file and load it back
#################################################### into the Design Import form.
global rda_Input
set cwd /home/vinita/FPR_10_1/FPR/work
set rda_Input(import_mode) {-treatUndefinedCellAsBbox 0 -keepEmptyModule 0 }
set rda_Input(ui_netlist) "../verilog/dtmf_chip_ak.v ../verilog/stubs.v"
set rda_Input(ui_netlisttype) {Verilog}
set rda_Input(ui_rtllist) ""
set rda_Input(ui_ilmdir) "" To read in a configuration file, enter:
set rda_Input(ui_ilmlist) "" loadConfig design.conf
set rda_Input(ui_ilmspef) ""
set rda_Input(ui_fmdir) {}
set rda_Input(ui_settop) {1}
set rda_Input(ui_topcell) {DTMF_CHIP}
Displaying the Design after Design Import
Pink module
guides consisting
of standard cells
Core Area
Hard/Custom
Blocks
The module guides follow the hierarchy in the netlist.
Demo: Design Import
Learning Activity: Design Import Errors
You will often see errors or warnings when you read in a design during the
design import step. Knowing what to do about the errors and warnings can
save you time.
Assuming that you are in the initial stages of your design and you are
creating a floorplan. You see the errors and warnings indicating that there
are mismatches between your netlist and your libraries. What should you
do?
Take a few moments to think of answers.
Learning Activity Solution
 In the initial stages of the design, when you are trying to create a
floorplan, you may have mismatches between libraries when your
design elements are not all in sync. It is fine, at this stage of the design
process, to ignore these warnings and errors.
 Errors and warnings can often be ignored in the floorplanning and
prototyping phases of the design process. As you get closer to
converging towards your design goals you will need to analyze the
errors and warnings more closely and fix them. For example, if you are
in the timing closure stage, review any warnings and errors, regarding
cells that do not have timing models.
Customizing Bindkeys
Option – Set Preference
Click Binding Key to bring up

the Binding Key form.
To alphabetically sort key names and action names, click the Key and Action labels in the
Binding Key form shown on the right.
Docking and Undocking Subwindows
 You can dock any sub-window except main artwork window, to the side,
top, or bottom of the display area.
 Click on the dock/undock handle to undock a subwindow
Undocked subwindow
Handle
Default window
Tearing off Menus and Submenus
 You can tear off any menu or submenu and place it anywhere in the design area.
 To tear off a menu or submenu, click on the dotted line that appears at the top of the
menu or submenu, and drag the menu to place it.
 The menu remains on the screen when you release the mouse button.
Saving and Loading a Workspace
 You can save and restore a customized window setting
 The use model is consistent with Virtuoso® for mixed-signal.
 Information like layer control will be saved in a workspace file.
Loading
Workspace
The default search order

to access directories are
current working directory
and your home directory
The default workspace is

loaded automatically when
starting up EDI.
Commands:
saveWorkspace
loadWorkspace
deleteWorkspace
setDefaultWorkspace
Refer to CCR 749410.
In edi10.1, this feature supports saving the layer control information and current display
view as a workspace.
You can save or load the xxx.workspace file at will.
Except GUI, edi10.1 creates four new commands to support workspace.
You could learn detailed information from coming slides.
Customizing the Menu
You can customize the menus, toolbars, status bars and the main window
by running these commands.
 uiAdd – Adds a menu, toolbar, menu item, or tool button
 uiDelete – Deletes a menu, toolbar, or item with <name>
 uiSet – Sets the widget’s property
 uiGet – Returns the current value of the specified property
 uiFind – Returns the widget with the specified property
For details of command usage, please refer to Database Access Reference Manual.
Usage: uiAdd [-help] <name>
-type {main|menu|toolbar|statusbar|submenu|command|check|radio|separator|toolbutton}
[-before <name>] [-checked <true|false>] [-command <string>]
[-disabled <true|false>] [-foreground <string>] [-icon <file>]
[-in <name>] [-label <string>] [-newline <true|false>]
[-tooltip <string>] [-underline <integer>] [-value <string>]
[-variable <string>]
Usage: uiDelete [-help] <name>
Usage: uiSet [-help] <name> [-before <name>] [-checked <true|false>]
[-command <string>] [-disabled <true|false>] [-foreground <string>]
[-geometry <string>] [-icon <file>] [-in <name>] [-label <string>]
[-message <string>] [-newline <true|false>] [-title <string>]
[-tooltip <string>] [-underline <integer>] [-value <string>]
[-variable <string>]
Usage: uiGet [-help] [<name>] [-before | -checked | -children | -command | -disabled | -foreground | -geometry | -icon | -in | -
label | -menu | -message | -newline | -statusbar | -title | -toolbar | -tooltip | -type | -underline | -value | -variable]
Usage: uiFind [-help] [<name>] [-before <name>] [-checked <true|false>]
[-command <string>] [-disabled <true|false>]
[-foreground <string>] [-icon <file>] [-in <name>]
[-label <string>] [-newline <true|false>] [-tooltip <string>]
[-type {main|menu|toolbar|statusbar|submenu|command|check|radio|separator|toolbutton}]
[-underline <integer>] [-value <string>] [-variable <string>]
Checking the Design
 Use checkDesign to detect any missing or inconsistent library and/or
design data. Always run checkDesign after importing a new netlist or
new library as a way to validate the data.
 You can run this command at any stage of a design to check the
following items:
 Physical library
 Timing library
 Placement
 Floorplan
 Netlist
 I/O
 Tie-hi and tie-low pins
 Power and ground pins
Checking the Log File
Check the log file for the following:
 More blackboxes created than what should be in the design
 This means that there are missing Verilog® models. If there is a LEF file for
a module and there is not a Verilog netlist, the software assumes that it is a
blackbox.
 Warnings about missing components in the initial stages of the design
are often not serious.
 For example, you might read in a Verilog netlist and then read in a DEF file
which has some different components that the Verilog netlist.
 In the initial stage, you might only want to preserve the floorplan from the
DEF file, meaning that the mismatch doesn’t matter.
 However, late-stage Verilog versus DEF mismatches could point to a
serious data integrity problem.
Selecting and Highlighting Objects in the
Design
Module 4
February 3, 2011
Module Objectives
 Find and select objects in the design
 Highlight selected objects
 Dim the background
 Preplace instances with the design browser
 Display the schematic with the schematic viewer
Edit Menu
… File Edit …
To select and deselect objects by

type or name.
To highlight and clear the

highlights of selected objects.
Finding and Selecting Objects
Edit—Find/Select Object
You can find and select the
following objects by name:
 Instance Finds clock buffer
instances
 Pin
 Net
 Module
 Instance Group
 Bump
Zoom to and highlight selected
The equivalent Tcl command object
syntax is:
selectObjByProp <objType>
<expression>
The find and search feature

supports the * wildcard.
Selecting Highlighted Objects
Choose Edit – Highlight Selected
Usage Tip:
Visually group highlighted objects into sets
by selecting different colors for the sets
Use the Highlight Selected menu command to highlight the object sets that are selected with
the Find/Select Object form. You can also choose the highlight color.
Dimming the Background
Dim the background of the selected or highlighted objects by using F12.
(3)
(2)
(1)
Usage Tip:
Use this feature to unclutter the view
when editing a wire
1. (Default) Shows selected objects with background not dimmed.

2. (Press F12 once) Shows selected objects with background (nonselected) dimmed at 40%
.
3. (Press F12 again) Shows selected objects with background (nonselected) dimmed at
80%.
Press F12 the third time and it will be back to default mode (no dim).
Tools Menu
Design … Floorplan Place Clock Route Timing … SI … Tools
Opens the Design Browser
Displays the schematic
Design Browser Tool
Tools – Design Browser Select object Deselect Selected
object
Connectivity
Browser Instance Attribute form for
preplacing
Hierarchical Browser
used for viewing:
- Instances
- Nets
- Busses
- Connectivity
- Highlighting objects
- Preplaced instances
Click the plus sign to

expand. Unhighlight object
Highlight object
The connectivity browser shows you what the instances are connected to.
Use the Design Browser to place and move cells or blocks in the design core area.
 Highlight the instance.
 Click the Attribute button (text page with arrow) to display the attribute form.
 In the Attribute form, click the get coord button to preplace the instance.
 Click the Preplaced option.
 Save the floorplan.
Displaying the Schematic
Use the Encounter® Module Schematic Viewer with the Design Browser to explore:
 The connectivity of a hierarchical design
 The relationship of modules and instances
 Design changes, such as CTS, optimization, and ECO.
You can cross-probe from this Schematic Viewer to the Encounter design
window Tools – Schematic Viewer
Floorplanning the Design
Module 5
February 3, 2011
Module Objectives
In this module, you
 Articulate the purpose of floorplanning
 Specify the utilization to derive the core size of the design
 Explore the I/O file format
 Floorplan the design by using floorplanning icons, toolbox and menus
 Edit and cut rows to drive standard cell placement
 Add routing halos to alleviate downstream signal integrity issues
 Run the Automatic Floorplan Synthesis tool to place blocks and
blackboxes in the core area
 Use relative floorplanning to interactively place objects
 Create a floorplan to meet your timing and area constraints, using
guides, soft-guides, regions, and fences
 Explore techniques for reducing die-size
What Are Sites and Rows?
 The site is the minimum unit of placement. It represents a slot where a
cell can be placed
 Rows are locations where the placement tool will place cells.
Rows can be core rows or I/O rows.

 Rows are a multiple of the site definition in the LEF file.
LEF File
Core Rows Standard cells after
placement
What Is Floorplanning?
Definition: Process of deriving the die size,
allocating space for soft blocks, planning
power, and macro placement.
Example: Chip X
With a top-level netlist, you can start to
floorplan the chip. din dout
 Set die size to 10x10 mm2

 Place the IOs: The din, clk, and dout I/Os A C
RAM A1
RAM A0
are shown assigned to the perimeter
 For hierarchical implementation, create
10mm
soft blocks for A, B, and C clk
 Size the blocks A, B, and C B

 Perform power planning
 Perform macro placement

10mm
 Check for early routing congestion
 Check for early block utilization
The Design Prototyping Flow
1 2 3 4 5
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
Floorplan Menu
… Partition Floorplan Power Place…
To change the core utilization

specification and floorplan defaults.
Creates an initial floorplan (including

block placement)
Specify Floorplan Form: Basic
Floorplan – Specify Floorplan
This form lets you modify

floorplanning parameters.
Usage Tip:
Die, I/O, and Core coordinates – You can enter or change box coordinates.
Die Size by Width and Height – You can modify the size (microns).
The Core size can be defined in two ways:
 Core size by Aspect Ratio – Enter H/W ratio and Core Utilization (0.7 is 70%).
or
 Core Size by Width and Height – Enter size in microns.
Core Margins can be defined in two ways:
 Core to Die Boundary
or
 Core to IO Boundary – You can enter Core to I/O dimensions in microns.
Die Size Calculation: Max IO Height is selected with multiheight I/O pad instances.
Floorplan Origin at – Default is at Lower Left or change to Center.
Determining Core and Module Sizes
Encounter® Digital Implementation XL
lets you derive core and module sizes
based on the standard cell utilization.
 Size = (standard cell
area/standard cell utilization) +
(macro area + halo)
 Benefit: Generates more accurate
core and module sizes.
Automatically moves I/O pins to new A1
edge when design boundary is
changed. A2
 Does not move fixed pins.
Design size gets Design size gets

bigger smaller. Pin A1 and A2
are both snapped to the
upper right corner
Specify Floorplan Form: Advanced
This form lets you:

 Select sites.
 Change standard row

configurations.
 Change row spacing.
 Change the default

standard cell row height.
 Set the bottom I/O pad
orientation. The default
orientation is R0.
 Select pad placement
based on I/O rows.
Support for DEF Rows
 The Specify Floorplan
Advanced form contains
options to specify row sites.
 Core area will be filled with
user-specified rows
(otherwise called a user
specified site).
 The tool automatically
creates rows whose widths
are integer multiples of a
specified site.
When adding spacing between rows, use distances that are multiples of the row height to
keep cell pin placements on the routing tracks.
I/O File Format
The I/O file format supports:
 Top level design with pads
 Rectilinear block level design
 I/O ordering that is:

 Clock wise
 Counter clockwise
 Left to right, bottom to top (default)
In this diagram Edge 0, the left-most

edge at y=0, is the
starting point for the
Edge 1
IO assignment
Edge 0
I/O File Example for Pad Placement
version = 3 (inst
io_order = clockwise name = IOPADS_INST/pad2 W
total_edge = 4 offset = 296.1250
space = 1.06 orientation = R0
(inst
place_status = fixed
name = IOPADS_INST/pad1 W
)
offset = 235.0000
orientation = R0
place_status = fixed
)
I/O File Example for Pin Placement
Automatic Floorplan Synthesis
Before Automatic Floorplan
Synthesis
Fence,
Partition, or F1 F2
Power Domain
F3 F4 F5
After Automatic Floorplan

Synthesis Guide inside
fence
Macro inside
fence
Automatic Floorplan
The Automatic floorplan tool places blocks and the Floorplan – Automatic Floorplan – Plan Design
guides that contain the blocks and generates a
quick initial floorplan. The automatic floorplanner is
timing-driven by default.
Use the Automatic floorplan tool for creating
multiple floorplans and test the floorplans to find the
one that gives you the best placement results.
The automatic floorplan tool requires:
 Gate-level netlist
 LEF models for all standard cells, hard
macros, and I/O pads.
 Floorplan file (or DEF file) that contains:
 Die size and core area
 Fixed I/O pads and pins
 Any preplaced hard macros or placement
blockages
 Power stripes and rings (optional)
planDesign
[-refineFPlan]
[-constraints constraint_file]
For explanations of commands and options, refer to the Encounter Text Command Reference.
Automatic Floorplan Seed Selection
Seeds are floorplan objects used by the Automatic Floorplan tool. A seed
can be a hierarchical instance, a hard macro, or an instance group.
The Automatic Floorplan tool relies on selected seeds to analyze data flow
and decide module location. Seeds eventually become guides in the
generated floorplan.
The tool can select seeds automatically, or you can specify them in a
constraint file.
An example of a constraint file:
# A Comment line can be added anywhere in seed file
Module-A
Module-B/B1 Seeds are typically design blocks that represent functional units.
Example: USB controllers, PCI controllers, and FPUs.
HM-1 Automatic Floorplan Synthesis:
•Analyzes the connectivity and location of seeds (design blocks)
Module-C/C1/HM1 •Places the seeds in the core area in a way that minimizes wire
instGrp-1 length and congestion.
instGrp-2
Automatic Seed Selection

By default, the MasterPlan uses the following method in the specified order to automatically
select seeds:
1. Chooses modules that fit an internally calculated size range
2. Chooses large, hard macros as seeds
3. Groups small modules or loose standard cells to meet internally calculated size range
You can also control automatic seed selection by specifying certain setPlanDesignMode
options.
User-specified seed selection:
 You can influence the resulting floorplan by specifying seeds.
 Choose seeds based on information about the module function, size, connectivity,
timing criticality, or any combinations of criteria.
 User-specified seeds do not have to cover the whole design. Automatic seed selection
routine will work on the remaining unspecified seeds.
 User-specified seeds are fed to the MasterPlan through a constraint file by entering this
command:
planDesign -constraint <constraint_file>
Automatic Floorplan Flow
gate constr
netlist LEF DEF/.fp .lib sdc file
Analyze Design
Process Constraint
Select Seed
setPlanDesignMode -congAware
Place Seed
Refine Seed
Power Analysis
Place Macro (IR drop map)
Refine Macro
Finish Floorplan
Floorplan
Creating Multiple Floorplans
 Create multiple alternative floorplans by choosing
Floorplan – Automatic Floorplan – Multi Plan Design.
 The resulting floorplans are ranked by estimated wire length and
congestion criteria.
Usage Tip:
Run Multi Plan Design in
multi-CPU or distributed
processing modes in
order to improve runtime
Learning Activity: Inputs and Outputs
What are the inputs and the output

of the Automatic Floorplan
Synthesis Flow?
Analyze Design
Process Constraint
Select Seed
Place Seed
Refine Seed
Power Analysis
Refine Macro
Finish
Floorplan
gate constr
netlist LEF DEF/.fp .lib sdc file
Analyze Design
Process Constraint
Select Seed
Place Seed
Refine Seed
Power Analysis
Refine Macro
Finish Floorplan
Floorplan
Floorplan Toolbox
You can quickly access commonly used commands
during floorplanning stage with the Floorplan Toolbox.
You can take the following actions: Pan
 View related commands, such as zoom and pan.
 Run interactive commands: shift, align, space,

Shift
rotate, and flip.
 Swap selected objects. Space
Click the icon to bring up the floorplan toolbox.

Align
Rotate
General Floorplanning Tools
Select Objects in the Design Window.
Display the ruler. Use Shift-k to remove last ruler.
To move floorplan objects and I/O pads. Use the Shift key to move
selected multiple objects.
Add placement blockages to block placement of standard cells.

The blockages are either hard, soft, or partial.
Hard: The area cannot be used to place blocks or cells.
Soft: The area cannot be used to place blocks or cells during
placement, but can be used during in-place optimization, clock tree
synthesis, ECO placement, or placement legalization (refinePlace).
Partial: Sets a percentage of the area that is unavailable for
placement.
Routing Blockage to block routing. Can block specified metal
layers and works with Specify Placement Blockage form.
Press u to undo previously implemented commands.
Rectilinear Object Support
 You can cut an object boundary to create a rectilinear object.
 Use the Cut Rectilinear tool icon.
Demo: Creating Rectilinear Objects
Resizing the Floorplan
You can resize the space among floorplan objects in one of the following ways:
 Proportional
 Shift-based
 Congestion-based spacing
Resizes and shifts the floorplan objects by estimating the congestion for the floorplan and
automatically deciding how to resize it
Floorplan – Resize Floorplan
Select Based On Resize Line to specify that the floorplan will be resized based on specified
lines. Resize lines control the areas of floorplan that will be expanded or shrunk. You can
specify coordinates for resize lines, or you can use the Draw button to draw resize lines in
the floorplan area. You can specify resize lines using (x1 y1) (x2 y2)...(xn yn) coordinates.
You can also specify noncontinuous lines by specifying an * for x or y coordinate. For
example, you can specify (x1 y1) (x2 *) (x3 y3) (x4 *). In such cases, the missing
coordinates will automatically be derived.
Click the Draw button to draw resize lines in the floorplan area. For floorplan resize in the x
direction, draw vertical lines. For floorplan resize in the y direction, draw horizontal lines.
To complete a line, press the ESC key. You can draw multiple lines by dragging and clicking
the left mouse button as shown in the following figure. The white lines in the figure are
resize lines.
You can run the following resizing command:
resizeFP
Relative Floorplan Interface
You can use relative floorplanning to
 Place relatively
 Reshape relatively
 Reshape between
 Resize Relatively
 Reshape cover
 Specify layers for preroutes between objects
Relative floorplanning supports multiple levels of undo and redo.

Also, it can save all the executed graphical user interface (GUI) commands
into a script file.
Relative Floorplanning
 You can capture and define the placement relationship of floorplan
objects independently from the actual coordinates in a floorplan.
 You can also resize a module or blackbox based on other floorplan
objects.
Floorplan – Relative Floorplan – Edit Constraint
Relative Constraints
relativePlace ram2p_78kx32/ram0 CORE -relation R
relativePlace ram2p_78kx32/ram0 ram2p_78kx32/ram1
–relation R -xOffset 100 -alignedBy B
relativePlace ram2p_78kx32/ram0 ram2p_78kx32/ram5
–relation B -yOffset 100 -alignedBy L
The Place object inside reference module/group button places a specific object inside the
reference object. The object is placed to the Left, Right, Below, or Above the edge of the
reference object.
If you select the Pre-Route option you can specify the layers on which the routes are created.
You can use the equivalent relativeFPlan command to implement the relative floorplanning
feature.
Relative Floorplan Example: Relative Place
Example
Align by -8 μm Reference object
Inst Inst
Inst1 2 2
10 microns
spacing
10 μm spacing 8 μm Inst1
Place Inst1 with R0 Place Inst1with R90

orientation on the left of orientation at below of
Inst2 by 10 microns Inst2 by 10 micron
spacing, and align Inst1 to spacing, and align Inst1
the top side of Inst2 by -8 to the left side of Inst2 by
microns. 8 microns.
Relative Floorplan Example: Define Array Constraints
Choose Floorplan – Relative Floorplan – Define Array Constraints.
Anchor
object
The array can be moved freely to any

location inside the core area.
Floorplanning Menus
You can shift, align, space, flip, and rotate instances interactively.
Floorplan – Edit Floorplan – Align Floorplan – Edit Floorplan – Shift
Floorplan – Edit Floorplan – Space Floorplan – Edit Floorplan – Flip/Rotate Instances
Creating Rows
The row boundary can
Floorplan – Row – Create Core Row
 Be defined by the core area
or
 Be user-specified
You can overlap rows.
Some limitations include:

 You can only create
horizontal rows.
Cutting Rows
When you cut rows, Floorplan – Row – Cut Core Row
standard cells cannot be
placed in those
locations.
You can cut rows by:
 Selection
 Specified area
 Site name
Rows Outside Core Boundary
Create Rows outside

After Floorplan After Placement the Core Boundary by
choosing Floorplan –
Row – Create Core
Row.
After pin assignment and partition At Partition Block
Placement Blockage Outside Core Boundary
You can create a placement
blockage that extends outside the
core boundary.
The blockage is honored by the
I/O placer.
Rectilinear Blockages
 Rectilinear blockages prevent cell placement and routing at non-rectangular
area.
 The software supports both placement and routing blockages.
 Use Cut Rectilinear widget to change a blockage shape from rectangular to
rectilinear.
 The blockages are honored by the placer and the router.
Rectilinear placement blockage Rectilinear routing blockage

The Context Pop-Up Attribute Viewer
The basic properties of an object are displayed in the Context Pop-up
Attribute Viewer that appears when you hold the cursor over the object.
Options – Set Preference
Viewing a Design
 Floorplan view
Displays the hierarchical module and block guides.
Also displays connection flight lines and floorplan objects. Lets you
floorplan the module guides, blocks, and floorplan objects. Press u to
display the submodules for a selected module guide.
 Amoeba view
Displays the outline of the modules and submodules after placement,
showing physical locality of the module.
 Physical view
Displays the detailed placements of the module blocks, standard cells,
and nets. This view can be displayed after placement is run. You can
view the interconnects after trial route. You can move (edit) standard
cells, blocks, and power/ground objects in the Physical view.
Floorplanning Module Constraints
There are five module constraint types:
 None
A module has the attribute “None” if it is not preplaced in the core design area. A module
can be preplaced by moving it to the core area or by loading in a floorplan file where the
module’s placement is defined.
 Soft Guide (Attribute: SoftGuide)
This module constraint is similar to a guide constraint, except there are no fixed
locations. This provides stronger grouping for the instances under the same soft guide.
Instances within a soft guide are grouped better than without a soft guide.
 Guide (Attribute: Guide)
A module is preplaced in the core design area. The placement program honors the
preplacement.
 Region (Attribute: Region)
A region constraint forces all module instances to be placed within the region, but allows
instances from other modules as well.
 Fence (Attribute: Fence)
A fence constraint forces all instances of the module to be placed within the fence and
does not allow any instances from other modules to be placed inside the fence. A
module becomes a fence when the module is specified as a partition.
Demo: Floorplanning Module Constraints
Instance Placement Status
For blocks, you can change the placement status by choosing
Floorplan – Edit Floorplan – Set Instance Placement Status.
The status can be cover, fixed, placed, or unplaced.
If an object is designated as fixed, no tool downstream will be allowed to move it.

A cover macro is data that is fixed to the floorplan and cannot change, such as power routing
(ring pins) around the core.
The placer understand that CLASS COVER cells have no active devices (such as diffusion
or polysilicon), so the MACRO SIZE statement does not affect the placer, and you do not
need an artificial OVERLAP layer. However, any pin or obstruction geometry in the COVER
cells can affect the pin access checks.
Adding and Deleting Placement Halos
To define a block halo area, complete the following steps:
 Select block(s) in the design display area.
 Choose Floorplan – Edit Floorplan – Edit Halos.
Halo
Block
To reduce congestion around a block, you can add a block halo to prevent the placement of
blocks and standard cells. You can specify block halos for hard macros, blackboxes, or
committed partitions.
Adding and Deleting Routing Halos
Routing Halos can prevent signal integrity issues around blocks. Adding routing
halos prevents long wires from being routed within the halo region.
The NanoRoute® graph-based router treats routing with specified layers in the
routing halo area as a very high cost. The router will do the following:
 Make perpendicular routing connections to pins
 Make no jogs and create no parallel routing in the routing halo area
Not OK
Instance
Block
OK
Not OK
Routing halo on M1 – M4
M1 routing
M2 routing
Clearing the Floorplan
Use this form to delete floorplanning objects.
Floorplan – Clear Floorplan
Specifying Critical Nets with Net Weights
Placement of Instances on Critical Nets
By default, the placement command placeDesign places the instances

connected to the critical nets close together.
Specifying Net Weights for Placement

The specifyNetWeight command is another way to specify what instances
you want placed together. Here you specify the net name, and all instances
connected to the weighted net are placed together.
The default net weighting is 2, and high fanout nets (>75 terms) are not
weighted. The recommended value is a number between 1 and 10.
specifyNetWeight <netName> <wt> ; 512 (highest priority) to 1
(lowest)
Floorplanning Grouping Commands
Use the following Tcl commands in the Encounter window to create
instance groups and placement guides inside and outside the core
boundary:
createInstGroup <groupName> [-guide | -region | -fence

<llx> <lly> <urx> <ury> | -density densityValue
[-AR aspectRatioValue]] [-isPhyHier]
addInstToInstGroup <groupName> ( <hInstName | instName

| groupName> )
To change the logical hierarchy select Floorplan – Generate Regrouped

Netlist
Command: runRCNetlistRestruct
You can infer hierarchy from a flat design by using createInstGroup.

The addInstToInstGroup command tells the placer to place instances specified in this group
close together. These instances can be in the same hierarchy or in different hierarchies.
The -isPhyHier option specifies that the created group is a physical hierarchy. By default, the
created group is not saved back to the netlist.
Finishing the Floorplan
Finishing the floorplan automatically accomplishes the following:
 Adds placement halos on macros.
 Adds placement blockages around macros to reduce potential congestion after
placement.
 Adjusts macro sequence to create “staircase-like” pattern on the side facing
core area.
Floorplan – Automatic Floorplan – Finish Design
Halos added
Placement
Blockages
added
Analyzing the Floorplan
The analyzeFloorplan command estimates total wire length, congestion, and timing. It also
reports design statistics.
There are effort-level switches to let you make tradeoffs between accuracy and run time.
The analyzeFloorplan command can evaluate a floorplan or compare different floorplans.
Choose Floorplan – Automatic Floorplan – Analyze Floorplan.
************************* Analyze Floorplan **************************

Die Area(um^2) : 2532867.08
Core Area(um^2) : 923744.05
Chip Density (Counting Std Cells and MACROs and I/Os): 51.639%
analyzeFloorplan Core Density (Counting Std Cells and MACROs): 49.499%
Average utilization : 19.768%
Number of instance(s) : 5981
Number of Macro(s) :4
Number of I/O Pin(s) : 57
Number of Power Domain(s) : 0
************************* Estimation Results *************************
Techniques for Reducing Die Size
Die-size optimization is an iterative process where you need to run several experiments along
with virtual prototyping to determine the shape and size of the die that will achieve your timing
and routability goals.
Techniques include:
 Considering a non-square die (with an aspect ratio less than or greater than one). The
shape will depend on the amount routing layers that are needed in a particular direction.
 During implementation, start with 70% utilization and run iterative prototyping steps to
analyze the timing and congestion results.
 Run the resize floorplan commands to reduce the size by a step value.
 Save this floorplan and run all the steps through Trial Route and output the target slack and view
the congestion.
 If the slack is met and there is not too much congestion, reduce the size again and repeat the
above steps.
 Increase module utilizations to see if tightening that constraint will adversely impact the size.
 Use partial placement blockages to alleviate local congestion and also to block cell placements
between macros. Blocking placements between macros will alleviate intermacro routing
congestion.
Note: The spaces blocked by using partial placement blockages will allow placement during
optimization.
Lab Exercises
Lab 2-1 Importing a Design
Lab 2-2 Using Bindkeys
Lab 2-3 Tearing Off Menus
Lab 2-4 Clearing the Floorplan
Lab 2-5 Initializing the Floorplan
Lab 2-6 Customizing the Menus
Lab 2-7 Checking the Design
Planning Power
Module 6
February 3, 2011
Module Objectives
 Articulate the purpose of power planning
 Assign global connections for the power and ground nets in your
design
 Create rings and stripes or the global power plan for the floorplan
 Create more complex power structures like rectilinear rings
 Size the vias to conserve routing resources
 Use wire groups to create metal-slotting
 Explore power plan prototyping
What Is Power Planning?
During power planning, you: G V G V
 Create the rings and stripes
for the core and the blocks in
block 3
V
the design
V
block 5
 Define the global power and
G
ground nets and create the
G
power structure that block 2
V
corresponds to the global nets block 4
V
block 1
V
G
G V G V G V
Power Planning
You can add power rings and power stripes to connect blocks and cells to
the power structures.
… Floorplan Power Place…
You must load a LEF file that contains technology information before you add power rings
and power stripes. If the LEF file is not loaded, you cannot select metal layers on the power
planning forms.
Connecting to Global Nets
Choose Power – Connect Global Nets to assign pin and net connections
to global power and ground nets.
Tcl:
globalNetConnect
Add Rings: Basic Tab (Core Rings)
Choose Power – Power Planning –
Add Ring.
Core rings follow the contour of the
core boundary or the I/O boundary.
 You can specify the layers, their
widths, their spacing, and the
offset.
 You can also exclude selected
objects, such as blocks that
typically have their own power
structure.
Load the options file that

you created earlier.
Select Core ring(s) contouring to create core rings that follow either the contour of the core
boundary or the contour around the I/O boundary.
 Select Around core boundary to create core rings that contour around blocks or rows
in the core area of the design.
Use the options in the Ring Configuration panel to either center the ring in the channel
between the core boundary and the I/O area, or offset each side of the ring by a specific
distance from the core boundary.
 Select Along I/O boundary to create core rings that contour the I/O area. Use the
options in the Ring Configuration panel to either center the ring in the channel between
the core boundary and the I/O area, or offset each side of the ring by a specific distance
from the I/O boundary.
 Optionally, select the Exclude selected objects option. This option creates a ring that
does not include the selected objects.
You can select User defined coordinates, then select either Core ring or Block ring and
specify a set of coordinates. This creates a ring that has the same number of corners as the
number of x and y coordinates that you specify.
 You can draw core or block rings anywhere in the core area.
 You need to specify the coordinates and the type of ring (either core or block).
Core Rings on Top of Rows
 Core rings on top of rows are useful when you do not have a dedicated
channel for power between the I/O and core.
 Use negative offset in conjunction with core row contouring.
Add Rings: Basic Tab (Block Rings)
 Block rings are generated
around each block or cluster
of blocks, with the option to
include shared edges.
 You can specify the layers,
and their widths, spacing,
and the offset.
Add Rings: Rectilinear Ring Generation
 You can draw rectilinear rings
anywhere in the design by
specifying coordinates.
 You can also draw rectangular
block rings or core rings by clicking
the mouse in the design area.
X6, Y6 X5, Y5
X4, Y4
X3, Y3
X1, Y1 X2, Y2
Add Rings: Layer Change to Make Connections
Switches layer to avoid short.
Layer change control during
ring extension/merging
 Supports planar rings.
M5 VDD M6 VDD
 Tool automatically
switches layers to
avoid short during ring Block
extensions or merging. M6 VSS
M5 VSS
Core rings
Add Rings: Advanced Tab
 Used for automatic ring
merging capability.
 Merging is completed by using
a user-defined threshold.
 Edges of rings and power
structure are merged if the
distance between the edges
are less than the threshold.
 Legal objects used for
merging are block rings, core
rings, and pad rings.
 Select and deselect edges in the Custom Ring Creation section.

This lets you create rings in any configuration. By default, all edges of the ring are
selected. You can deselect any area for edges you do not want to include.
 Click one or more of the eight stripes (above, below, or to the sides of the ring edges) to
indicate the direction in which you want to extend the ring.
The ring is extended in those areas until encountering a legal target.
 (Optional) Select Create rectangular ring(s) only to prevent the software from creating
rectilinear rings.
If you specify this option, only rectangular rings are created.
 (Optional) Select Use wire group.
This option specifies that multiple wires from the same net be treated as if they are
connected. If you have duplicate wires, it is recommended that you select this
option. By default, wire groups are not used.
 (Optional) Make group vias at ring corners
If selected, this option creates group vias for the wire group corners along with
reinforcement stripes placed in the horizontal and vertical directions. This option
must be used in conjunction with the Reinforcement stripes option and is deselected
by default.
Add Rings: Ring Extension and Exclusion
 You can minimize block rings by
merging edges with other
structures.
 You can customize ring structures
and select segments to create and
extend to existing rings.
Block ring
Core ring
HB1
Add Rings: Around Cluster of Selected Blocks
HB1 HB1 HB1
HB2 HB2 HB2
Case1: Case2: Case 3:

Orthogonal polygon Orthogonal polygon
Rectangular only with shared edges
Use the Advanced Tab addRing –type block_rings
addRing –type block_rings
-around cluster
-around shared_cluster
Add Rings: Use Wire Groups
The Use Wire Groups command lets you create multiple wires for the same
nets with a single command. The nets can contain interleaved bits.
 It is useful for technologies with max width rules.
 It affects core/block rings, stripes, followpins, pad rings, and

connections from power pins to these structures.
Example
Without “Use wire group” option With “Use wire group” option
Wire Group Support
Specify the number of bits of nets by checking the Use wire group button
and updating the Number of bits field while creating rings or stripes.
The Encounter software will internally update its nets field.
It also supports interleaving bits.
Example
 To create two sets of rings for nets VDD VSS, set number of bits = 2.
The rings will be drawn with the pattern VDD VDD VSS VSS.
 For the above example, if you select the Interleaving button then the
stripes will be drawn with the pattern VDD VSS VDD VSS.
Add Stripes
You can create stripes for power and ground nets
by selecting Power – Power Planning – Add
Stripe.
Options
 Set configuration
 Nets – Specify the nets.
 Layer – Specify the layer to use.
 Width – Specify the width of the stripes
that you want to create.
 If the number of widths specified is less
than number of nets specified, then the
last value specified for width is used for
the unmatched nets.
 Spacing – Specify the spacing between
pair of the stripes.
 Set pattern
You can define the distance between each
stripe set and the number of sets.
 Stripe Boundary
You can specify the target of the stripe by
selecting an object for the stripe to connect to,
which enables relative power planning.
Select the Bumps option to generate stripes in relation to bumps.

Over indicates that stripes need to be generated over bumps.
Between indicates that stripes need to be generated between bumps.
Select the Over P/G pins option to generates stripes over power/ground pins in a standard
cell or block.
Add Stripes: Spacing Definitions
Spacing and Set Pattern Definitions
Width a Width b
Spacing
VDD GND VDD GND
Set-to-set distance
Boundary offsets are measured from core boundary edge.

You can improve routability and availability of routing tracks by selecting the
width and spacing as it relates to the routing grid.
Add Stripes: Advanced Tab
Stripe Breaking
 You can omit stripes at block rings so
that the stripes do not go though the
block.
Target Connection Control
 You can allow stripes to jog to connect
to target rings.
 You can merge the stripes with a block
ring if the spacing is less than your
specified amount.
Layer Control for Target Connections
You can allow stripes that connect to pad
and core rings to
 Jog or use straight connections
 Switch layers when the jog length
exceeds a threshold
Wire Groups
 If you use wire groups when creating
rings and you need to connect the
stripes to them, then select the Use
wire group option.
Add Stripes: Break Stripes at Block Rings
Omit Stripes inside block ring OFF Omit Stripes inside block ring ON
Stripes Stripes
Block rings Block rings
Block A Block A
Add Stripes: Merge with Rings
Block rings Stripe Block rings Stripe
Block A Block A
Example 1: merge threshold < a Example 2: merge threshold > a
Via Generation: Control of Via Size
 All power planning commands

resize generated vias.
 You can give the max percentage
of width or height to be scaled
during stripe-ring crossover, ring-
ring crossover or stripe-stripe
crossover.
 By shrinking the size of the via,
more routing resources are
available to the signal or power
routing tool.
 Controlling via sizes can prevent
congestion.
Via Generation with Respect to a Given Point
Via generation with
Fat Pad ring respect to a given point
Target penetration
Stripe point
Via width scaled

Vias without Via width is scaled to 50% from the
scaling to 50%. (Stripe target penetration
metal is not scaled.) point
Metal is also
trimmed.
Demo: Creating Rings and Stripes
Power Plan Prototyping
 In order to save time in the prototyping phase where you are
experimenting with various power plan structures, you can turn off the
DRC checks during the creation of rings, stripes, and vias.
 In the case of vias, the via generation will ignore DRC violations with
nearby objects but will honor enclosure and minimum cut rules.
 Before running power planning commands such as addRing,
addStripe, and editPowerVia, set the following modes:
setAddRingMode –ignore_DRC
setAddStripeMode –ignore_DRC
setViaGenMode –ignore_DRC
Learning Activity: Add Rings
Instead of adding rings interactively, you can use commands to achieve the
same objective.
Using one of the many ways of accessing documentation look up the
command for adding rings.
What command and options would you use to create the following?
1. One VDD Core Ring on M5(V)/M6(H)
2. One VSS Core Ring on M5(V)/M6(H)
3. Widths of 10um
4. Spacing of 1um
Take a few minutes to answer
this question.
Here is the command that you would use to add rings using the
specification provided on the previous slide:
addRing –nets {VDD VSS} –layer_top M6 –layer_bottom M6
–layer_right M5 –layer_left M5 -width_bottom 10
-width_top 10 –width_left 10 –width_right 10
–spacing_top 1 –spacing_bottom 1 –spacing_left 1
–spacing_right 1
Routing Power with Special Route
Module 7
February 3, 2011
Module Objectives
 Articulate the purpose of power routing
 Route power to the standard cells and blocks
 Route areas of the design incrementally with Special Route
 Connect global nets to targets
 Explore the properties in the LEF file that are required for running
Sroute
What Is Power Routing (Sroute)?
 During power routing, you create power routing to the:
 Standard cells (follow pins power routing)
 Blocks
 I/O pads
 Connect the power routes to the global power created during power
planning
Standard Cells
Follow Pins Power Routing
Block
Running Special Route: Basic
Choose Route – Special Route.
Fast Mode Straight Connections
 Modes of operation
 Allow Jogging
 Allow Layer Change
Layer Change Control

 Control the top/bottom layers
used during Special Route.
Block pins connects the power and ground pins of the blocks to rings and stripes.
Pad pins connects the power and ground pins of the power pads into the core power ring.
Pad rings creates pad rings.
Follow pins connects the power and ground pins of the standard cells along the core rows.
The end connections are based on the options you set using the Advanced tab of this form.
By default, the end connections are at the first ring or stripe outside the row.
Special Route: Incremental Capability
Gives you the flexibility to route (through automation) portions of the design
differently than others, without ripping up previously generated routes.
 The Area option lets the router make connections only if the source
ports and target ports are inside the defined area.
 All existing routes are preserved if you use the Area option.
You can incrementally route the full chip or a block.
 If the Delete Existing Route Option is turned on, existing wires in the
specified area will be deleted an re-routed.
Special Route: Area-Based Incremental Routing
Area-based routing Area-based routing
Connect to target inside area Only = OFF Connect to target inside area Only = ON
Target inside the area

Target inside the area
Source ports/pins Source ports/pins
block block
Ring Stripe
Ring Stripe Area defined
Running Special Route: Advanced
Block Pins
Select a target for the

block pin connections
Follow LEF Conventions

Pins are connected exactly as specified in the LEF file. For example, if the LEF file has multiple ports with one
geometry connecting to each port, then one pin per port is connected.
All Pins
All pins on all ports are connected, regardless of how pins are specified in the LEF file.
Pins Facing
Only boundary pins are connected. If you select this option, you can also deselect one or more of the following
options to prevent the connection of boundary pins at the deselected location: Top Side, Bottom Side, Left Side,
and Right Side.
 (Optional) Deselect One Among Overlapped Pins.
If multiple pins exist in the same physical location, but on different layers, all of the pins are to be
connected when this option is deselected. If this option remains selected, only a single pin is
connected.
 (Optional) Select Layer selection, then select layer numbers in the From and To drop-down menus.
This limits the layers on which block pins can be routed. If you do not select this option, the software
routes block pins on all layers.
 (Optional) Select Width Selection and specify a minimum pin width in the From text entry field and a
maximum pin width in the To text entry field.
 (Optional) Select Connect Using Pin Width Only.
This ensures that connections to pins are the same width as the pin.
 (Optional) Select Connect to Aligned Pad Pins.
Connect Corners of Ring Pins
Support to connect the rings pins to the nearby targets by extension at the
corners. Total of eight possible connections per net.
Mostly used in those memories whose internal power connection from the
ring pin are modeled as obstructions.
VDD pin
VSS pin Block ring

Block
Ring pins
Connect Using Pin Width Only
The width of the blockwire can be the same as the width of the pin.
M5 VSS Pin M5 VSS Pin
Block Block
M5 VDD Pin M5 VDD Pin
Connect Using pin Connect Using pin

width only = OFF width only = ON
LEF Properties for SRoute
 In addition to SRoute settings and options, there are several properties in the LEF file
which impact how SRoute connects the power and ground nets and pins.
 For example, to create followpin routing in the design before the cells are placed, the
SRoute tool looks in the LEF file to find a representative cell and uses its attributes for
routing.
 The SHAPE parameter on the standard cell pins determines how the router connects
cells. A SHAPE ABUTMENT parameter allows the router to create a piece of metal that
completely overlays the pin geometries. The following diagram showsfollowpin routing
for pins with the SHAPE ABUTMENT parameter:
For details on other LEF parameters, go tohttp://support.cadence.comand download the

“Understanding How SRoute Interprets Design Data” application note.
Lab Exercises
Lab 2-8 Floorplanning a Design
Running Detail Placement
Module 8
February 3, 2011
Module Objectives
In this module, you
 Articulate the purpose of placement
 Specify and place spare cells in clusters
 Specify and place JTAG cells around the periphery of the core area
 Specify cell padding for clock tree synthesis
 Place cells and blocks using the detail placer
 Create and use placement blockages to alleviate congestion

 Place physical cells such as tie, end caps, filler and antenna.
 Evaluate the quality of the placement
 Set the design mode to achieve the best results for placement, timing,
and optimization
1 2 3 4 5
Design Import Scan Routing Add Metal Fill
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff
Create and Load JTAG and Cell Clock Tree Postroute Physical


Met? Met? Met? Met?
Signoff
Cell placement is used to place the cells that have been added to the design as a result of:
• Timing Optimization
• Clock Tree Synthesis
What Is Placement?
Placement is the process of placing the standard cells and blocks in a
floorplanned design.
Standard cell
Design before Placement Design after Placement
Placement Menu
Design ... View.. Floorplan Power Place Optimize Clock Route …
You can specify a list of spare cells for the Encounter Digital Implementation system before
running placement, and the tool will include them in the placement run.
You will probably place the JTAG cells after floorplanning.
The JTAG cells are added to test the I/Os of the design and need to be instantiated in the
netlist.
You can save and load the placements in DEF and in the Encounter Digital Implementation
place formats.
Specifying Spare Cells
Spare cells are added in the design to make post-mask
ECO changes. Choose Place – Specify – Spare Cell
Syntax
If spare cells are in the netlist run the following
commands:
specifySpareGate {-cell|-inst|-hinst}
setPlaceMode –moduleAwareSpare {true| false}
 When this parameter is true, spare cells in a

logical hierarchy are placed within the bounds of
the hierarchy.
 When this parameter is false, spare cells are
spread out within the placement area, and are not
bound to a hierarchical module.
Syntax
If spare cells are not in the netlist, run the following
commands:
createSpareModule -moduleName {modulename} -cell
{cellname} -tie {tiename} -clock {clockname}
placeSpareModule -moduleName {modulename}
deleteSpareModule
It is recommended that you have several ―clusters‖ of spare cells placed at different locations
of the core area. This technique allows easy access to spare cells from several parts of the
core area.
Adding Spare Instances
Run the addSpareInstance command for flat spare cell insertion.
Syntax
addSpareInstance -file <fname> [-tie <0 | 1>]
[-prefix <prefix>] [-clock netname]
The command can be used pre- or postplacement.
Preplacement
 Spare cells are added to the netlist.
 Run placeDesign to do the distribution and placement.
Postplacement
 Spare cells are added, distributed uniformly, and placed.
 No spare modules are created.
Placing Spare Cells
Choose Place – Place Spare Cells to place the spare cells in your design.
Specifying Cell Padding for CTS
Cell padding (spaces) is reserved for adding buffers during clock tree synthesis.
The CTS tools places cells with the default placement clearance of a metal2 pitch
dimension.
For synchronous designs, placement resources (utilization) of 5% to 7% of the
targeted final utilization needs to be reserved.
Syntax
specifyCellPad leafCellNames factor
Example
specifyCellPad *DF* 3
Choose Place – Specify – Cell Padding.
This value shows

that there is one
reserved space.
You can reserve space to the right of the flops for buffers. The extra space will always be
reserved on the right side of the flops.
Specifying JTAGs
JTAG Logic or Boundary Scan
Logic Place – Specify – Jtag Cell
Specify the JTAG cells, instances,

or hierarchical instances.
specifyJtag [-cell <cellName>]
[-inst instName|hInstName>]
or
traceJtag
The software traces JTAG logic

from leaf instances and generates
the JTAG Tcl input file. Each JTAG
area is assigned a placement area,
which is calculated in terms of the
heights of the standard cells.
You can use this command to not only place JTAG cells, but any cells that you want to place
close to the I/Os.
The recommended methodology is to place the JTAG cells before running placement on the
entire design. When placing JTAG cells, the tool temporarily creates a blockage over the
area that will not be occupied by the JTAG cells. This blockage will be removed
immediately after JTAG placement.
Placing JTAGs
 Place JTAGs cells at the chip boundary.
 The top, bottom, left and right JTAG placement areas are determined by the
defined number of rows
 Ensure that the instance placement is close to the I/O pads.
 You can customize the placement blockage layer.
 View the JTAG placement results and save the floorplan.
 Run placement for the remaining design.
Place- Place Jtag
Placement
Blockage Layer
Core Design Area
Specifying the Control of Placement Blockages
 Specify placement blockages for Power/Ground stripes and routing
blockages.
 You can disallow standard cell placement under power stripes and
routing blockage.
 By default, the Encounter Digital Implementation engine will not place
standard cells under the following layers:
 For a 3-metal-layer process: Metal 2 will be blocked
 For a 4-metal-layer or greater process: Metal 2 and Metal 3 will be blocked.
 Cells will be placed outside of the power stripes by one metal pitch.
However, the cells will abut routing blockages.
Placement Blockages for Preroutes
Preroutes are special nets, such as power, ground, and clock nets, where
you do not want any standard cells placed under them.
Example
setPreRouteAsObs {1 2}
Note: Unlike standard cells, filler cells are added under preroute wires.
Place-Specify-Placement Blockage
Setting the Placement Mode
Choose Options – Set Mode – Mode Setup to set up placement options
before running placement. Select Low placement effort to arrive at a quick
placement.
Select High to run a placement on highly congested
designs.
The Auto option is selected by default. The tool
automatically determines if the design is
congested and performs extra congestion
driven effort if needed
Select this option if you have a timing constraints file

loaded into the Encounter® software. Unselecting this
option will run placer in congestion mode.
Ignoring spare cell connections lets the placer

distribute the spare cells evenly.
Specify this option if fewer than the maximum routing

layers are to be used for the design.
Run Timing-Driven Placement

This option builds a timing graph before placing the design. Before using this option, make sure that the timing
constraints file is complete for the entire design. The placement program performs limited optimization by
upsizing and downsizing instances.
Note: By default, if you specify timing-driven mode, the software resizes concurrently with optimization.
Enable Module Plan
This option improves wire length, timing, relative module location, and congestion results during the early
phase of global placement for most designs. It is compatible with full and incremental placement, prototyping
mode, and the in-place optimization flow.
Note: Cadence recommends deselecting this option for designs with nested constraints, more than 1,000
floorplan constraints, or other types of complex floorplan constraints.
Post Place Congestion Optimization
This option runs congestion optimization after placement is complete in the detailed placement stage. Before
running postplacement congestion optimization, the design must be legally placed. If the placement is not legal,
the software does not run the refinement step during congestion optimization and instead exits.
Enable Clock Gating Awareness
This option specifies that placement is aware of clock gate cells in the design. Load the clock tree specification
file before running the placement command with this option.
Enable Power Driven
This option identifies and constrains power-critical nets to reduce switching power. In most cases, timing is not
degraded. However, in some cases, a trade-off between power and timing is required. An activity file (TCF or
VCD) is required to supply the net switching information.
Setting the Placement Mode (continued)
 Use the setPlaceMode command to set options before running the placeDesign command.
 If you set the –modulePlan option to true, the worst negative slack (WNS) is improved by an average of 100 to 300 ps.
Wire length is reduced by over 10%. The option is set to true by default.
 If you select the auto setting for the –congEffort option, the placeDesign command will detect and perform congestion-
driven placement
 You need to read in a clock tree constraints file before specifying the -clkGateAware option. Placement can cluster
clock-gating circuitry closer to the leaf FF and thereby improve post-CTS timing results.
 The -scanReorder command re-orders the scan chain based on the options specified in the specifyScanChain
command.
Syntax
setPlaceMode
[-checkPinLayerForAccess {list_of_layer_numbers}] [-checkRoute {false | true}]
[-clkGateAware {false | true}] [-congEffort {low | medium | high | auto} ]
[-dividedShifterCols {false | true}] [-dividedShifterRows {false | true}]
[-honorImplantSpacing {false | true}] [-honorSoftBlockage {false | true}]
[-ignoreScan {false | true}] [-ignoreSpare {false | true}] [-maxRouteLayer
layerNumber] [-maxDensity value] [-modulePadding moduleName factor]
[-modulePlan {false | true}] [-powerDriven { false | true}]
[-preserveRouting {false | true}]
[-reorderScan {false | true}]
[-reset]
[-swapEEQ {false | true}]
[-timingDriven {false | true}]
Running Placement
 The placement engine incorporates a spatial placement algorithm to provide better final
placement and faster timing closure.
 You can run a placement on multiple CPUs at the same time.
Place – Place Standard Cell

Run Placement
Select Run Placement in Floorplan
Mode to run a quick placement to
gauge the feasibility of your netlist.
Include Pre-Place Optimization

Runs optimization on the netlist before placing
the cells.
Include In-Place Optimization
Runs optimization on the netlist to better meet
timing constraints.
Running Placement with placeDesign
The placeDesign command is timing-driven by default, except in the
prototyping mode. If there is no timing constraint in the design, placeDesign
runs in congestion mode.
The modes that affect the placeDesign command in addition to the
setPlaceMode command are setClockDomains, setTrialRouteMode,
setOptMode, and setScanReorderMode.
The placeDesign command
 Presets recommended options by default
 Simplifies the placement process by tracing and reordering the scan

chains
 Provides a simple way to support optimization during the placement
process
Syntax
placeDesign [-noPrePlaceOpt] [-inPlaceOpt] [-incremental]
Macro and Blockage-Aware Placement
 You can set an option for the placer to recognize limited routing
resources over hard macros and inside narrow channels between
macros.
 By setting the option the placement tool will avoid placing cells that
require routing across the macro or through the narrow channels.
 The threshold for the options to take effect are:
 If there is <20% routing resources available
 The channel width is < 50 um
Syntax:
setPlaceMode -macroBlockageAware true
-autoBlockageInChannel true
Creating and Using Placement Blockages
 Placement blockages can have one of threeattributes: Hard, Partial or Soft
 The blockages are used to improve timing androutability
 A blockage of type "Hard" prevents placeDesign from placing any cells in this
area.
 Use this blockage type to totally restrict standard cells from being placed
here
 A blockage of type "Soft" prevents placeDesign from placing any cells in this
region; however placement legalization, timing optimization and clock tree
synthesis (CTS) can place buffers/inverters in this area
 Used to block channels between macros
 Prevents the placer from placing standard cells in this area, thus avoiding
congestion problems.
 Optimization is allowed to insert buffers/inverters in these channels and is
useful to buffer long nets to improve timing androutability.
Creating and Using Placement Blockages (continued)
 A placement blockage of “Partial" (also referred to as density screens)
will ensure that a certain percentage of the specified area is
unavailable for global placement.
 This percentage is specified when defining the partial blockage
 Example: A partial blockage of 30% means that 70% of the specified area
can be used for global placement. The 30% blockage is of type "soft"; that is
timing optimization and CTS can use this area.
Demo: Running Placement and Evaluating Route Congestion
Learning Activity: Placement
In order to run placement in timing-driven mode you need to have done one
of the following:
1. Set the view to Physical View.
2. Read in a constraints file.
3. Set the mode to Enable Module Plan.
In order to run placement in timing-driven mode you need to have done one
of the following:
1. Set the view to Physical View
Incorrect: The Physical View is for display only and does not have
anything to do with the functionality of placement.
2. Read in a constraints file
Correct: You need to read in a timing constraints file in order to run
placement in timing-driven mode. If you don’t have a constraints file,
you can run the placement tool in congestion mode.
3. Set the mode to Enable Module Plan
Incorrect: The Enable Module Plan option can reduce slack once a
constraints file has been read.
FAQ: Place Spare Cells in a Particular Area
You are trying to instantiate and place some spare cells into a certain area,
defined by {x0, y0 ; x1, y1}. The spare cells are in the netlist.
To place your spare gates into a particularx,y area, instantiate them into
their own “spares” module, then create a guide for that module in the
desired area. You should also use the specifySpareGate command to
identify the module that contains your spare cells.
Run the following commands:
specifySpareGate -inst mySparesModule
createGuide mySparesModule 834.2000 1012.0000
2498.4000 3087.0000
placeDesign
The placeDesign command will observe floorplan constraints such as
guides, regions and fences.
Placement: Hints and Tips
To begin with, always start with placeDesign.
If the design is congested
 Try this command:
setPlaceMode -congEffort high
 This option enables more aggressive cell padding by default.
The netlist size is growing:
 If it grows 5-10% during optimization, consider running
placeDesign -inPlaceOpt
The design has local congestion hotspots and it gets worse after routing:
 Spread cells out a bit more for that module, using
setPlaceMode -modulePadding <moduleName> <factor>
 Use partial placement blockages.
The design contains clock gating:
 Use the -clkGateAware option. (Requires CTS spec files.)
The placement engine clusters clock-gating circuitry closer to the leaf flip-flop
improving post-CTS timing results.
Generating a Placement Density Map
You can generate a map that uses colors
to represent placement density and
generate a placement congestion map.
Syntax
reportDensityMap [-gridInMicron i |
-gridInRow num] [-threshold value]
Value Definition
i Grid bin value in the X or Y direction, in
microns. Default is 50 microns.
num Grid bin value in row height. Width of bin
assumed to be that of row height.
Default is 10 rows. If less than 1 row
height specified, it will default to 1 row.
value Any number greater than 0. Default is
0.75. Any grid bin under the threshold
will not be reported.
To view the Density map, make sure that it

is selected in the All Colors pane.
Generating a Placement Density Map (continued)
Place – Display – Display Density Map reportDensityMap -gridInRow 10
1 row ~ 4.0 microns
Running ECO Placement
 Use ECO placement for minor design changes.
 Make sure that the ECO logic changes do not exceed the previous
imported design by more than 5 percent.
Place – ECO Placement
Start by restoring placement from file

This option restores an existing placement file before placing ECOs.
Keep existing placed instances fixed

This option specifies that instances with the PLACED status are not moved.
Restore Placement File

This option specifies the placement file that was saved from a placement run. This placement
file is saved from the previous netlist that was imported and placed in the Encounter®
software. Running ECO Placement changes this design to the newly imported netlist. The
placement file format must be from the Encounter software.
Save Placement to file

Specifies the filename for saving the placement results.
Placing Physical Cells
Physical cells are required for  Antenna diode cells
physical implementation and are not
setNanoRouteMode
instantiated in the original logical
–drouteFixAntenna true
Verilog® netlist.
–routeAntennaCellName
To add the various “physical-only” <cellName>
cells run the following commands:
 Decap cells
 Tie-Hi low cells addDeCap
addTieHiLo
 Well tap cells
 End cap cells addWellTap
addEndCap
 Filler cells
addFiller
Evaluating Placement Quality
 Evaluate the net length:
The placeDesign command reports the total net length when it completes.
You can compare the net lengths of multiple placements and select the one
with the smallest net length go forward with. The wire length directly influences
other parameters, such as timing, power, and routability.
 Amoeba view:
You can visually evaluate the placement using the Amoeba View. Click the
Amoeba View icon in the upper right. The Amoeba View shows the placement
of modules and blocks. Using the Amoeba View you can see how well the
placement of modules are clustered together.
 Create and view the density map:
The density map divides the design into square areas and colors each square
relative to the placement density of that area. The density map can highlight
how uniform the density is and identify localized areas of congestion.
Evaluating Placement Quality (continued)
 Analyze Congestion:
Once placed, the design must also be routable. Highly congested routing can
lead to longer routes which negatively impact timing, increased routing
runtime, and shorts. Run trialRoute and analyze the congestion of the design.
The chapter “Using Trial Route for Congestion and Timing Analysis” in the EDI
System User Guide provides details on this. Specifically, see the sections on
Analyzing Route Data and Improving Route Congestion.
Fixing Localized Congestion
If the congestion is
localized, one technique to
alleviate it is to use partial
placement blockages.
1. Click the placement
blockage icon.
2. Select the blockage
and change its type
from Hard to Partial.
3. Select a multiplier use
along with the initial
target utilization to
spread out the cells in
the congested area.
Checking Placement
Place – Check Placement
Place – Refine Placement
Checks for DRCs and Pin Access

for routing
Check For DRs Against Fixed Signal Routes

This option considers prerouted FIXED signal wires and avoids creating DRC violations between
FIXED signal wires and instance pins. When this option is not selected, the software ignores FIXED
signal wires. Running placement with this option might result in longer run time.
Honor Soft Blockages
This option specifies that soft blockages will be considered when running the command. Soft
blockages are different from density screens (partial blockages). Partial blockages are never
considered during refinePlace. By default, soft placement blockages are considered only during
global placement and are ignored during refinePlace and optimization stages.
Preserve Routing
Preserves all routed wires. Default: The Refine Placement command removes all wires.
Remove Affected Routing Only
Removes wires connected to moved cells.
Default: The Refine Placement command removes all wires, whether connected cells were moved or
not.
Swap EEQs
Specifies whether master cells can be replaced by EEQ cells during detailed placement to improve
routability. After detailed placement, the software reports the number of replacements. EEQ cells are
defined in the LEF file.
Access Checks For Pin Layers
Specifies the layers to check for pin access.
The Violation Browser for checkPlace Violations
Run the checkPlace command and then choose
Tools – Violation Browser to display the violations in the design.
Select and Zoom
The checkPlace violation markers
Setting the Design Mode
 You can set one global variable setDesignMode which will set the
effort level of all high-level commands such placeDesign, optDesign ,
and timeDesign.
 Individual set*Mode commands options have higher priority than the
setDesignMode –flowEffort option.
Syntax:
setDesignMode -flowEffort none|high
 none: This will use default settings. In this mode, the target is to achieve
good QoR with minimum runtime.
 high : This will set the commands to use their high effort setting. In this
mode, the target is to achieve best possible timing and yield at the expense
of some more CPU runtime.
Example:
setDesignMode –flowEffort high
placeDesign
Scan Optimization and Reordering
Module 9
February 3, 2011
Module Objectives
 Articulate the purpose of scan chains
 Specify and reorder scan chains
 Trace through the scan chains
 Display and save scan chains
 Delete scan chains
Scan Chain Menu
File View Partition Floorplan Place Clock Route …
What Are Scan Chains?
 The purpose of adding scan chains is to make the flip flops in the design
controllable and observable.
 When the SEN signal in the example below is asserted (set to 1) every flip-flop
in the design becomes part of a long shift register and the expected value that
is shifted out is compared to the actual value.
What Is Scan Reordering?
Reordered scan chain requires much less routing resources in the example design.
Before Scan Reorder After Scan Reorder

C C
dff1 dff3 dff1 dff3
RAM A1
RAM A0
RAM A1
RAM A0
dff2 dff2
Loading Scan Chain Information
Running placement while ignoring scan chain connections will reduce
routing congestion and wire lengths.
 Scan cells are identified in the timing library (.lib). If scan cells are not
in the timing library, use this command to load information:
specifyScanCell <cellName> [-in pinName] [-out pinName]
[-scanClock pinName] [-scanEnable pinName]
 Scan chains are specified in the DEF file. You can alternatively load
the scan chain with a Tcl file:
specifyScanChain <scanChainName> -start <startPinName>
-stop <stopPinName>
Creating a scanDEF File
A Design Exchange Format (DEF) file contains the design-specific
information of a circuit and is a representation of the design at any point
during the layout process.
A scanDEF file is a subsection of a DEF file. It is a pin-based format that
describes the set of reorderable scan chains present in the scan-mapped
and configured netlist.
To generate a scanDEF file for your design, use the write_scandef
command in Encounter RTL Compiler.
Syntax
write_scandef [version 5.5 [-partition partition
-chains chain...]...] > scandef_file
For detailed information about the scanDEF format, refer to the Cadence LEF/DEF
Language Reference, version 5.5.
Example: scanDEF File
VERSION 5.5 ;
NAMESCASESENSITIVE ON ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN test ;
SCANCHAINS 2 ;
- AutoChain_1_seg1_clk1_rising
+ START PIN DFT_sdi_1
+ FLOATING Two scan chains
out1_reg_0 ( IN SI ) ( OUT Q ) with START and
... STOP keywords that
out1_reg_74 ( IN SI ) ( OUT Q )
+ STOP PIN DFT_sdo_1 ; denote the starting
and ending points of
- AutoChain_2_seg1_clk1_falling
+ START PIN DFT_sdi_2 the chain
+ FLOATING
out2_reg[0] ( IN SI ) ( OUT QN )
...
out2_reg[99] ( IN SI ) ( OUT QN )
+ STOP PIN DFT_sdo_2 ;
Reordering and Optimizing Scan Chains
Reordering Scan Chains
 Scan tracing traces through buffers and inverters but not through
multiple input gates before reordering the scan chain.
 The main options are:
 Skip Buffer
Will skip buffers in the scan chain and Place – Scan Chain – Reorder
might delete them if scan reordering
fixes hold time violations.
 Skip Two Pin Cell
Will skip buffers and inverters in the
scan chain and might delete them.
No Skip buffers and inverters remain after the scan chain reorder.
Skip Buffer skips the buffers in the scan chain.
Skip Two Pin Cell skips buffers and inverters in the scan chain. The buffers and inverters are removed if not
used.
Scan reordering is clock-tree aware. The flip-flops connecting to the same clock buffer have higher priority and
are placed next to each other. This makes sure that two flip-flops on the same scan chain have less clock skew,
leading to less chance of a hold time violation.
Allow Swapping lets the software swap scan elements between scan chains. Default: Off
Keep Hierarchical Ports (MSMV Flow Only) maintains or corrects the hierarchical ports without deleting or
inserting shifters, and reorders the remaining scan chain. Default: Off
Clock Tree Aware Specifies whether scan reordering is clock tree aware. If this parameter is not specified, or
if 0 is specified for this parameter, scan reordering is not clock tree aware and is completely wirelength driven.
If a value is specified, the value must be a floating point number between 0 and 1, where 0 means scan
reordering is completely wirelength driven and 1 means it is completely clock tree driven. The closer the value
is to 1, the more importance is given to clock trees over wirelength. Value: Specify a floating number between 0
and 1. Specifying a value is optional. Default: Off (The software is not clock tree aware.) If this option is
selected, the default value is 1.
Syntax
scanReorder [-allowSwapping]
[-lowEffort | -mediumEffort | -highEffort]
[-skipNone | -skipBuffer | -skipTwoPinCell]
[-defInForce] [-clkAware [value]] [-keepHierPorts]
Displaying and Writing Out Scan Chains
Place – Display – Display Scan Chain
Displaying the Scan Groups

Display scan chains before and after
reordering the scan.
Syntax
displayScanChain scanChainName
File – Save – Netlist
Saving the Netlist and Placement

Save the scan reordering results.
Save the netlist and the placement
results to a file.
The hierarchical push-down feature allows scan chain information that is specified at the top
level to be pushed into the partitions. The scan chain information is saved in scan DEF files.
Deleting Scan Chains
Deleting a Scan Chain
After loading a scan file, you can remove a scan chain by
choosing Place – Scan Chain – Delete.
Syntax
deleteScanChain scanChainName
Analyzing Route Feasibility with Trial Route
Module 10
February 3, 2011
Module Objectives
 Articulate the purpose of routing
 Articulate the use-models for the various routing engines in EDI
 Run Trial Route and analyze the log file for congestion
 Interpret the congestion map display
 Restrict metal layers from being used for trial route to support your
detail route methodology
What Is Routing?
Routing is the step where the placed cells are connected with metal so that
they reflect the connectivity in the Verilog netlist.
DFF BUF NAND
CKBUF CKBUF CKBUF DFF
DFF
CKBUF NOR CKBUF INV
Placed Design
DFF BUF NAND
CKBUF CKBUF CKBUF DFF
DFF
CKBUF NOR CKBUF INV
Placed and Routed Design

The first picture is just a collection of gates. The second picture is a collection of gates that
are connected to each other using wires and nets.
Routers and Their Uses
 Sroute (power router)
 Connects the cells, block and pad power, and ground pins to global power and
ground
 Trial Route
 Fast signal router needed for extraction and timing analysis
 Useful for congestion analysis
 Will not be DRC or LVS clean
 NanoRoute router
 Accurate timing and SI-aware router for tapeout
 Run before running SI analysis, signoff timing analysis
 Mixed Signal router

 Shape-based router
 Use for small, custom blocks
 Wroute (previous generation router)

 Available for technologies that have two or three layers for routing
Route Menu
… Floorplan Place ... Clock Route …
You can load a fully routed DEF, generate a route guide, and then run trial route.
If you just load a routed DEF without generating a routing guide, the trial route will not
honor the routes that were initially loaded.
Trial Route
 TrialRoute quickly routes the design without fixing DRC or LVS violations.
 This router is a good predictor of congestion and enables physical synthesis to

use more accurate parasitic extraction information during timing optimization.
 Use a Route Guide file to specify preroute nets.
 The Ignore Routing Obstruct button allows routing over all partitions and
blocks.
Route – Trial Route
By default, run medium effort.

Run high effort for highly congested designs.
Use Routing Guide

Specifies a routing guide file for assigning preroutes.
Save Routing to
Specifies a filename in which to save the routing data after the Trial Route program
finishes.
Ignore Routing Obstruct
Allows routing over all partitions and blocks.
Handle Partition
If this option is selected, the tool routes around fences rather than through them. The tool
assumes that all fences in the design will be converted to partitions at a later stage.
Max. Route Layer
Specifies that all metal layers above the specified metal number are not routed. The
default is the top-most layer.
Trial Route (continued)
 Running Trial Route lets you extract RCs, which you can use to
determine if your are meeting your timing goals.
 You can view the congestion map after running Trial Route to see the
“hotspots” in your design.
Trial Route Effort Level

 Prototyping runs quickly to gauge the feasibility of your netlist, but
components in your design might not be routed at legal locations.
 Medium Effort is the normal selection.
 High Effort is for additional iteration to lower congestion.

 Low Effort is for quick routing and it completes without congestion
detouring.
 At this effort level, you throw away the route information.
 This mode is typically used only when you partition the design.
Trial Route Analysis
Visual Check
 A red diamond symbol represents overflow of horizontal or vertical routes.
Zoom in to view demand/resource numbers.
 Turn-on a display of Vertical and Horizontal color coded congestion:
 Blue Overflow = 1
 Green Overflow = 2
 Yellow Overflow = 3
 Red Overflow = 4
 Magenta Overflow = 5
 Grey to White Overflow > 6
Analyzing congestions and actions to consider
 You might want to adjust block placements and/or orientations to make sure
that connecting pins also face each other.
 Use a partial placement blockage to lower the congestion in a specific area.
 Read the log file for horizontal and vertical overflow numbers (%), where 1.0%
is the limit for 5+ metal layers and 0.5 % is the limit for 3 layers. These are
optimal limits for proceeding to detail routing.
Restrict Metal Layers from Trial Route
If there are layers in your design that are reserved and are not for routing,
then you can pass this restriction to Trial Route. This restriction will result in
a more realistic gauge of your routing resources.
Syntax
 Technology file contains several metal layers.
 Starts at minRouteLayer and uses up to maxRouteLayer to run Trial Route.
 If there are additional layers beyond the maxRouteLayer, they are reserved.
Example
trialRoute -minRouteLayer 3 –maxRouteLayer 6
 You have an 8-layer technology file.
 You can run Trial Route using metal layers 3 to 6 while reserving layers 7
and 8.
You cannot pass the minRouteLayer and maxRouteLayer information to the placer.
You can also add this option to trialRoute:
-skipTrack {layerName | all} numberOfTracksToSkip:outOfTracks
You can let Trial Route skip the specified number of tracks out of the specified total number
of tracks during routing. You can skip tracks on a specified layer, or on all layers. For
example, if you specify this command with these options,
trialRoute -skipTrack M5 1:3 -skipTrack M6 1:4
then Trial Route skips one out of every three tracks for routing on layer metal5. In other
words, it uses two adjacent tracks, then skips the third. It also skips one out of every four
tracks for routing on layer metal6. In other words, it uses three adjacent tracks, and then
skips the fourth.
Learning Activity: Routers and Their Capabilities
Which router would you use if you had to create power routing for your
design?
Which router would you use if you had to quickly gauge the feasibility of
your floorplan and placement?
Which router would use to detail route your design?
Take a few minutes to think of answers.
Which router would you use if you had to create power routing for your
design?
Answer: SRoute
Which router would you use if you had to quickly gauge thefesability of
your floorplan and placement?
Answer: Trial Route
Which router would use to detail route your design?

Answer: The NanoRoute tool
Lab Exercises
Lab 3-1 Running Placement
Lab 3-2 Running a Trial Route
Route (Flat)
iSection2: Extraction, Timing Analysis, CTS, and
Optimization
Version 10.1
February 3, 2011
Extracting Parasitics and Running Timing
Analysis
Module 11
February 3, 2011
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff

Setup Setup Fixing Setup/Hold Fixing Setup/Hold Fixing Timing Analysis

Met? Met? Met? Met?
Signoff
Module Objectives
 Explore the Encounter® timing closure flow
 Correlate fast extraction with sign-off extraction for accurate timing

analysis results
 Extract the RCs using the Encounter Digital Implementation extractor
 Specify operating conditions and delay calculator before running timing

analysis
 Run setup and hold analysis
 Account for on-chip variation in timing analysis
 Generate and analyze timing reports
 Use the Global Timing Debug to determine the causes of violations
Timing Menu
… Floorplan Place Route Timing …
Encounter Timing Closure Flow
Netlist
placeDesign
Placement
Common Timing Engine

optDesign Optimization
clockDesign CTS
Optimization
timeDesign
Routing
Easy to use,
convergent
and simplified Postroute Opt.
flow
Verification
Run QRC extraction after a detailed routing for sign-off quality results.
What Is a Capacitance Table?
 The capacitance table contains routing metal dimensions and
properties. It is technology and process-corner dependent.
 You can get a capacitance table from your foundry or from Cadence.
 You can also generate a capacitance table by running the

generateCapTbl command.
Example of a Capacitance Table
Generating and Using a Capacitance Table
 A capacitance table is used for more accurate, very fast RC extraction.
 Characterization is required once per technology.

 To use a capacitance table, read it into the Encounter ® system before running
extraction.
Generating a Capacitance Table from an ICT file

 Take the process layer information from the ICT file, converting it to a
capacitance table.
generateCapTbl –ict ict.pcs –output ict.capTbl
 You can use the capacitance table by doing one of the following:
 Add the following command to the configuration file:
set rda_Input(ui_captbl_file) “ict.capTbl”

 Add the capacitance table to the view file:
create_rc_corner –name dtmf_rc_corner –cap_table
{ict.capTbl}…
You can use the -coyote option to run the Cadence® 3-D field solver (Coyote), to generate an
extended capacitance table.
Generating a Three-Corner Cap Table
Best ict* Typical ict Worst ict
generateCapTable generateCapTable generateCapTable
Worst
Typical
Resistance
Capacitance and
Table Capacitance
Table
*Interconnect Technology
file for QRC
In addition to three corner capacitance tables, resistivity, and temperature variations are
included.
Resistivity and temperature variations (thermal coefficients) for each layer are defined in the
ICT file and copied into the CapTable.
 Reading resistivity information from the capacitance table has a higher precedent over
the values defined in LEF file during R calculations.
 To force the use of LEF resistance, use this command:
setExtractRCMode -useLEFResistance
Reading a CapTable for Three PVT Corners
 readCapTable Command
readCapTable {-typical <fileName1> -best <fileName2>
-worst <fileName3> | <fileName> }
 Graphical Interface
 Choose File – Import Design – Advanced tab and select RC Extraction in
the left pane.
 Fill in the parameters for the capacitance file names.
Correlating Extraction: Generating Scale Factors
Use the Ostrich utility to correlate the native extraction and sign-off
extraction engines. Ostrich is a standalone utility in the Encounter® system.
Ostrich generates the scaling factors after correlating the SPEF files. You
can then set the scaling factors for the next extraction cycle.
To bring up this utility, enter ostrich at the Encounter prompt and follow the
instructions in the Encounter User Guide.
Alternatively, you can use the following command:
generateRCFactor [-outputFile file_name]
[-preroute { true | false}] [-postroute { low | medium }]
[-reference {low | medium | high | signoff | externalSpef}]
[-spefIn spefInFile]
[-spefMapFile file_name]
The benefit of using Ostrich is that you can generate a histogram which
shows how well the two SPEF files correlate.
An alternative to the generateRCFactor command is to include the scale factors in the header section of the
Capacitance table in the following way.
#--- Created using "Encounter 10.10-b083_1" on Tue Oct 19 03:24:41 2010 ---#
#Process: CDN65LP_7M_typical
VersionNumber 1.1
NominalTemperature 25
#preRoute_res 1.0
#preRoute_cap 1.0
#preRoute_clkcap 0.0
#preRoute_clkres 0.0
PROCESS_VARIATION ...
LAYER M1
……
To apply scale factor values, uncomment the above values and provide generated scale factor values.
For existing capacitance table files, add the scale factor information in the header section.
In the case of MMMC, update the rcCorner capTable to add corner specific scale factors.
What is 2-D Versus 2.5-D Versus 3-D Extraction?
B
C
P&R
extraction
substrate 2-D or 2.5-D A B D
Self only E
Some near-body
effects are extracted. substrate
F C
3-D A B D
All near-body E G
effects are
extracted.
substrate
In older tools, only the area component for capacitance could be extracted as shown in the
upper left. As tools became more advanced, fringe and sidewall capacitance were also
extracted (upper right). With 3-D extraction all near-body effects are extracted.
Specifying Extraction Modes
Use the RC extraction mode to specify
 The threshold value (in picoseconds) for RC reduction
 Whether to consider noise during extraction
 The database output filename
Options – Set Mode – Specify RC Extraction Mode
Preroute : Preroute mode should only be used during an early prototyping stage where the more detailed extraction is not
needed. In this mode, the coupling capacitances are grounded.
Postroute: Postroute mode is used for RC parasitic extraction after detailed routing.
Effort Level : Specifies the postroute engine variant that you want to use for performing RC extraction.
Note: When you hover the cursor over an effort level (low, medium, high, signoff), a tooltip appears with information about
the postroute extraction engine that is being started. The effort levels and corresponding extraction engines are as follows:
 low = Native (detail) engine
 medium = Turbo QRC (TQRC)
 high = Integrated QRC (IQRC)
 signoff = Standalone Signoff QRC
Low starts the native detailed extraction engine.
Medium uses the TQRC extraction mode. TQRC performance and accuracy falls between native detailed extraction and
IQRC engine.
This engine supports distributed processing. TQRC engine is recommended for process nodes < 65nm. This option requires a
QRC techfile but does not require an extra license.
High uses the IQRC extraction engine.
IQRC provides superior accuracy compared to TQRC. IQRC is recommended for extraction after ECO. In addition, IQRC
also supports distributed processing. This option requires a QRC techfile and a QRC license.
Signoff uses the standalone signoff QRC extraction engine. This engine choice provides the highest accuracy.
The following options are only available in the postroute mode:
Coupled RC : Coupling capacitance to neighboring wires is reported separately. You must enter threshold data for the
capacitance values (Coupled RC panel). Use coupled RC for SI analysis.
Decoupled RC coupling capacitances to neighboring wires is grounded. Use decoupled RC for STA.
Specifying Extraction Modes (continued)
setExtractRCMode –engine {preRoute | postRoute}
–effortLevel {low | medium | high | signoff}
where:
 low enables the detailed extraction engine
 medium enables the integrated Turbo QRC extraction engine
 high enables the integrated QRC extraction engine
 signoff enables standalone QRC extraction
Syntax
setExtractRCMode –engine {preRoute | postRoute}
–effortLevel {low | medium | high | signoff}
optDesign –postRoute {-setup | -hold }
Extracting RC Data
Extraction of Interconnect Data
 Setload format (lumped capacitance on nets for Synopsys)
 Set Resistance format (resistance on nets for Synopsys)
 SPF saves the DSPF (detailed standard parasitic format) file.
 SPEF (standard parasitic exchange format)

Timing – Extract RC
The Importance of RC Correlation for Extraction
RC Correlation is one of the most important setup steps for successful design
implementation.
Preroute RC estimation uses the default 2.5 extraction engine.

 It is fast at the expense of accuracy.
Running extraction with pessimistic scale factors causes excessive run times and lead the
software to work on non-critical paths.
 This happens with especially deep paths with many levels of logic, because there is an
accumulation of pessimism.
Running extraction with optimistic scale factors can result in significant postroute optimization
requirement which is limited in scope.
 Postroute optimization is limited to buffer resizing and buffer insertion.
 Postroute optimization might be unable to resolve violations that could have been fixed
before routing.
The following methodology assumes a signoff extractor is used for correlation.
 If detailed extraction is the most accurate information that is available, then treat the
detailed extraction as signoff and skip the steps for setting detailed scale factors.
Best Case/Worst Case (BC/WC) Operating Conditions
Options – Set Mode – Specify Operating Condition/PVT
Best Case/Worst Case Operating Conditions (continued)
The setOpCond command sets the operating temperature, process, or
voltage conditions for the design. Use this command for designs that do not
require multi-mode multi-corner analysis.
You can read both -min and -max operating conditions from the same
library.
Syntax
setOpCond -min bccond -max wccond -minLibrary stdcell
-maxLibrary stdcell
Example
setOpCond -min bestopcond -max worstopcond -minLibrary
fastlib -maxLibrary slowlib
If NO operating conditions are specified, then

 The default operating condition of each library in the Max and Min Library groups is
used.
 Common group: Default operating condition of the first library found in the Max library
group is used during setup.
If no Max/Min library groups are specified, then the software uses the default
operating condition of each of the libraries in the common group.
You can fix hold violations while the software knows about the impact on setup
times.
Because the software knows about setup time in the design, it saves iterations.
In designs for which you will be running multi-mode multi-corner analysis, run the
create_delay_corner command.
BC/WC Setup Analysis Using Scaled OCV
Setup Analysis Using Scaled OCV
setOpCond -min fast -max slow -minLibrary fast -maxLibrary slow
set_timing_derate -max -early 0.8 -late 1.0
/* scaled OCV of 20% for setup near WC corner */
u0 x2 x3 x4 x5 x6 u7
ty u8
x x1 x7 x8
x9
clock period + clock arrival at target flop - data arrival >= library setup (to meet setup time)
or
clock period + (x +x9) *0.8 - (x + x1 + u0 + x2 + x3 + x4 + x5 + x6 + u7) *1.0 >= library setup
Note: Both Late and Early path delays are computed under worst case conditions. Late data path delay computed
under worst case conditions.
Early clock path delay computed

under worst case conditions.
BC/WC Hold Analysis Using Scaled OCV
Hold Analysis Using OCV
setOpCond -min fast -max slow -minLibrary fast -maxLibrary slow
set_timing_derate -min -early 1.0 -late 1.2 /* scaled OCV of 20% for
hold near BC corner */
u0 x3 x4 x5 x6 u7
x2
ty
u8
x x1
x7 x8
x9
data path delay - clock path delay to target flop >= library hold (to meet hold time)
or
(tx + tx1 + ty + tx7 + tx8 +tu7) *1.0 - (tx +tx9) *1.2 >= library hold
To take clock reconvergence pessimism removal (CRPR) Early data path delay computed
under best case conditions.
into account specify:
setAnalysisMode –crpr true Late clock path delay computed
under best case conditions.
BC/WC Analysis Mode and Derating Values
Options – Set Mode – Specify Analysis Mode
Options – Set Mode – Set Timing Derate
Best and Worst Case sets the timing analysis mode to best-case worst-case. In the best-case
worst-case analysis mode, the software checks the libraries for two extreme operating
conditions.
Specify Analysis Mode: Advanced Tab
Analysis Options include:
 Enable Latch Time Borrowing specifies whether to consider time borrowing during timing analysis. Time
borrowing is the amount of time borrowed by a previous logic.
 Include Output Pin Capacitance includes the output pin capacitance when calculating delay values. If you
do not select this option, the Encounter® software excludes only the pin capacitance of the driver that you
are calculating the delay for.
 Propagate Constants through Sequential Element sets the constants to be propagated while building the
timing graph. The software reads the constants from the timing constraints file or the netlist. Default:
Disables the propagation of the constants and does not use the constants from the SDC file.
 Consider Useful Skew File considers clock skew while performing timing analysis.
 Enable Timing Self Loop Skew considers clock skew due to clock uncertainty for a path starting and ending
at the same register. If the clock skew is considered, the timing for such paths is pessimistic.
 Enable Multiple Driver enables the multiple-driver support for reporting.
Reporting Options include:
 Path From Clock Source To Data Pin specifies whether to report the path from the clock source to the
D-input pin of a register path.
 Display Warning Messages as Timing Constraint is Read displays warning messages as the timing
constraints file is read.
Specifying the Delay Calculation Mode
Options – Set Mode – Specify Delay Calculation Mode
Use the Encounter delay calculator for

fast delay calculation results.
If you choose default, the Encounter Digital Implementation delay calculator is used.
Generating an SDF File
Select Ideal Clock if you Timing – Write SDF

have not run CTS on the
design.
Select the Ideal Clock option when running a design that has not run clock tree synthesis. This
forces the clock nets on each flip-flop clock input pin to use 120 ps rise and fall times.
Running Timing Analysis: Basic
Timing – Report Timing (Basic tab)
Run timing with the Pre-Place

option to find problems in your
constraints or other timing
data.
The Pre-Place option generates timing reports before the design is placed. In this mode, the
software ignores the net load while building the timing graph and runs Encounter Digital
Implementation timing analysis for generating timing reports. The DRV report files are not
generated in this mode.
The Pre-CTS option generates timing reports for a design whose clock tree has not been
created. By default, in this mode, the software runs Trial Route, native default extraction, and
Encounter Digital Implementation timing analysis for generating timing reports.
The Post-CTS option generates timing reports for a design whose clock tree has been created.
By default, in this mode, the software runs Trial Route, native default extraction, and
Encounter Digital Implementation timing analysis for generating timing reports.
The Post-Route option generates timing reports for a design whose routing is complete. By
default, in this mode, the software runs native detailed extraction, and Encounter Digital
Implementation timing analysis for generating timing reports. The Sign-Off option generates
timing reports for sign-off timing analysis.
The Include SI option runs the CeltIC® Nanometer Delay Calculator and generates a glitch
violation report and incremental SDF for timing analysis. You can use this parameter with the
Post-Route and Sign-Off options only.
Running Timing Analysis: Advanced
Timing – Report Timing (Advanced tab)
Report selected path groups.
The All Path Groups option reports all path groups.

The Specified Path Groups option reports selected path groups. To specify the path groups,
click on the Specify button. This opens the Specify Path Groups form.
Use Ideal Clock to run ideal clock analysis irrespective of the design stage.
The software performs propagated clock analysis with the Post-CTS and Post-Route options.
The software performs ideal clock analysis with the Pre-Place and Pre-CTS options.
The Expand Register to Register Paths option specifies that the register-to-register path
groups are divided into the following detailed path groups for generating reports:
 Flop to flop
 Macro to flop
 Flop to macro
 Macro to macro
Command for Running Timing Analysis
Instead of running timing analysis through the GUI, you can run the
timeDesign command.
To set non-default timing options, run setAnalysisMode before running
timeDesign.
Example
setAnalysisMode -analysisType onChipVariation -usefulSkew true
timeDesign -postCTS
If not explicitly specified, the check will be run for setup violations. For hold
checks, specify the -hold option for timeDesign.
Generating a Timing Report
 The report_timing command generates a timing report containing the various
paths in the design.
 You can use the -format parameter to customize the report fields
Command
report_timing
Valid format columns are: adjustment, annotation, arc, arrival, cell, delay, direction, edge,
fanin, fanout, incr_delay, instance, instance_location, load, locv_derate, net, phase, pin, hpin,
pin_location, required, retime_delay, retime_slew, slew, stolen, and user_derate.
Creating a Blackbox/Blob Model
You can run blackblob timing
analysis in Encounter Digital
Implementation by choosing
Timing – Create Black
Box/Blob Model.
 Use this form to view
blackbox details and to run
a what-if analysis of
blackboxes.
 You can navigate through
the blackbox or pin
specification easily.
Use the form to create timing arcs, set the output delay, and set the clock latency for the
blackboxes in your design.
Global Timing Debug Utility
After running timing analysis, choose Timing — Debug Timing to help
debug the causes of timing violations in your design.
Fix the negative slack in Path Histogram

the design by running (pass/fail)
optimization.
Timing Path Analyzer
From the timing analysis tab, double-click any path to open the timing path
analyzer.
Slack calculation
• Clock skew issues
• Latency balancing issues
• Huge clock uncertainties
SDC cross-probing
• See which SDC constraints
affect this path
Detailed path tabs

• View data, launch and
capture clock segments of
path, timing interpretation...
Path delay bar
• Large instance/net delays
• Repeater chains
• Paths with lots of buffers
• Large macro delays
Time-based hierarchical view

• Interpartition path problems
The idea is to make obvious problems “leap” out.
Path delay bar notation for status of the object:

Flag Description
a Assign net
b Blackbox instance
c Clock net
f Preplaced instance
i Ignore net
s Skip route net
t “don’t touch" instance
t “don’t touch" net
x External net
Examples of Debugging with Timing Path Analyzer
Launch and capture latency components are not aligned. Therefore, there can be
large clock latency mismatch in this path.
The cycle adjustment bar in the required time indicates the presence of multicycle
path.
Large input delay in an I/O path is represented by the light-blue bar in the arrival
time.
Path Delay bar in the required time indicates a set_max_delay constraint.
Timing Path Analyzer: Path SDC
The Path SDC tab shows all the SDC constraints that match the topology of
the current path. Use this software to debug typical constraint issues.
Filename
Line number
Constraint
On first invocation (click the Path SDC tab), the analyzer parses SDC constraint files and
processes them for cross-probing.
Subsequent clicks on Path SDC tab will use previously processed SDCs to perform cross-
probing.
The intent of SDC cross-probing is to display a complete set of constraints that apply to this
path.
Router and Extraction Matrix
Stage Route Engine and Effort Level
Pre-CTS Trial Route Pre-Route Engine
Post-CTS Detailed Route Pre-Route Engine, Medium Effort
Postroute Detailed Route Post-Route Engine, High Effort
Postroute Signoff Post-Route Engine, Signoff Effort
Learning Activity: Encounter Timing Closure Flow
Netlist
What commands belong

?
Placement in the empty green boxes?
? Optimization
? CTS
Optimization
?
Routing
Postroute Opt.
Verification
Netlist
placeDesign
Placement
optDesign Optimization
clockDesign CTS
Optimization
timeDesign
Routing
Postroute Opt.
Verification
Run QRC extraction after a detailed routing for sign-off quality results.
Multi-Mode Multi-Corner Analysis
Module 12
February 3, 2011
Module Objectives
 Explore Multi-Mode Multi-Corner (MMMC) Analysis usage
 Create and use MMMC views that are required for MSMV, DVFS, and
other types of designs
What Is MMMC Analysis?
Mode Core Drowsy Dull
DROWSY DULL Baseline 1.08V 1.08V 1.08V

125MHz 125 MHz 125 MHz
Slow 1.08V 1.08V 0.9V
CORE 125MHz 125MHz 66MHz
Standby 0.0V 1.08V 0.0V

125MHz
Multiple constraints (.sdc) Libraries Multiple modes need to be

analyzed/optimized for multiple corners
Example: baseline.sdc, ios.sdc, stdcell_1.08sl.lib,
stdcell_0.9sl.lib, Setup analysis for (WC, 1,125C) corner
dull.sdc, drowsy.sdc
stdcell_1.08fs.lib,
stdcell_0.9fs.lib
How MMMC Technology Works
View 1 View 2 View 3 View 4

Functional mode Functional Mode Functional Mode Test Mode
FF corner SS corner TT corner SS Corner
Analysis View Process
Corner Definition Constraint Mode

Library set (.lib, Temp
CDB, ECSM) Multi
PVT
Operating Constraints Corners
Condition (PVT) (SDC)
Voltage
Corner (SPEF,
Captable)
Concurrent analysis/optimization after views are set up

Dynamic Voltage Frequency Scaling (DVFS) is a low-power technique where certain power
domains can dynamically switch from high voltage, high frequency (a high performance
mode) to low voltage, low frequency (a power saving mode).
DVFS in Encounter technology is fully supported through our MMMC (multi-mode, multi-
corner) engine. Using MMMC, you create several “views”, where each view is indicative of a
certain mode for the power domain. Creation of these views is aided by power domain
information in the CPF. After views are created, placement, optimization, CTS, and timing are
all done with respect to the views. For example, during optimization, all views are optimized
concurrently, so you do not need to worry about optimization of one view breaking other
views.
All this provides a highly automated and integrated environment for DVFS design
implementation.
Multi-Mode Analysis Starts with Synthesis
Implementation
Synthesis Delay Calculation Analysis Views
Corners
view: user1_max
mode: user1
dcCorner: corner: default_corner_max
default_corner_max
-library_set
library_set: default_libs_max view: user2_max
Timing Libraries default_libs_max mode: user2
-opcond yyy corner: default_corner_max
Operating Conditions -opcond_lib xxx
view: lbist_max
mode: lbist
MSMV Power Domain corner: default_corner_max
Setup
FE Cmd/Config
Constraint
Modes view: mbist_max
mode: user1 mode: mbist
read_sdc –mode user1 … corner: default_corner_max
read_sdc –mode user2 … mode: user2
read_sdc –mode lbist …
read_sdc –mode mbist … mode: lbist
mode: mbist
Implementation with MMMC Flow
The library set can be a single library

Create library set or a collection of libraries.
Specify PVT condition for each corner.
Define various RC Specify capTbl for each corner.
corners Specify techfile for QRC extraction for each
corner
Specify SDC file for each mode.
Define constraint modes Same SDC file may be used or
specify 1 SDC file per domain
Create analysis views Associate a corner with a mode.
optDesign/ Run optimization and timing checks

timeDesign for concurrent handling of views.
Multi-Mode Multi-Corner Reporting and Interface
Aggregated Multi-Corner Setup Analysis Results
+--------------------------+----------+-------------------------+
.slk | Endpoint | Slack | Corner |
Setup Analysis at all corners .tarpt +--------------------------+----------+-------------------------+
| blockA/sub/dff1/D | -0.100 | mode1_setup |
| blockA/sub/dff2/D | -0.050 | mode3_setup |
.slk ...
Hold analysis at all corners .tarpt
Total Negative Slack: xyz
Worst-Negative Slack: mmm
Aggregated Timing Report Worst reg2reg
Worst reg2out
Worst in2reg
timeDesign Worst in2out
Aggregated Multi-Corner Hold Analysis Results

+--------------------------+----------+-----------------------+
The timeDesign command detects | Endpoint | Slack | Corner |
+--------------------------+----------+-----------------------+
analysis views. | blockA/sub/dff1/D | -0.100 | hold1 |
| blockA/sub/dff2/D | -0.050 | hold2 |
Generate aggregated setup/hold Total Negative Slack: xyz
results. Worst-Negative Slack: mmm
Worst reg2reg
Worst reg2out
GUI interface to view slack across Worst in2reg
Worst in2out
corners and manually choose
dominant corner for fixing.
Setting Up the Analysis View
Creating a Library Set
Complex designs can require the specification of multiple library files to
define all of the standard cells, memory devices, pads, and so forth, that
are included in the design.
 There can be sets of libraries to define different process corners,
operating voltages for MSMV power domains, and .lib and ECSM
library groups used in SignalStorm® interpolation flows.
 Library sets allow a group of library files to be treated as a single entity
so that higher-level descriptions (delay calculation corners) can simply
refer to the library configuration by name.
 A library set can consist of just timing libraries, or it also can include
cdB libraries to keep timing and signal integrity libraries in sync
throughout a multicorner flow.
 The same library set can be referenced multiple times by different
delay calculation corners.
To create a library set, use the following command:
create_library_set
Creating a Library Set (continued)
create_library_set
 Library sets are created
-name lsCOM-1V
-timing [list x.lib y.lib z.lib] so that library references
[list x.cdb y.cdb z.cdb] .cdB for
Timing .libs for
1 volt domains
-si
PVT1 can be created once and
create_library_set
conveniently referred to
-name lsCOM-2V through the specification
-timing { … } process.
Timing .libs for -si { … } .cdB for
PVT2
2 volt domains
 The same library set can
create_library_set
be referenced multiple
-name lsCOM-3V
-timing { … } times by different delay
-si { … } .cdB for calculation corners.
Timing .libs for
PVT3
3 volt domains
 Creates linkage between

timing libraries and signal-
integrity libraries (.cdb).
Creating an RC Corner
 An RC corner object provides the software with all of the information
necessary to properly extract, annotate, and use the RCs for delay
calculation.
 RC corner objects also control the attributes for running gate-level
extraction sequentially on each RC corner.
 For each active RC corner in the design, the software extracts and
stores a unique set of parasitics. You must use the RC corner scaling
attributes when running the software in multi-mode multi-corner
analysis mode.
To create an RC corner run:
create_rc_corner
For example, the following command creates an RC corner called rc-typ

that uses the capacitance table myTech_nc.CapTbl, and derates the
resistance values based on the temperature of 50 Celsius:
create_rc_corner -name rc-typ -cap_table myTech_nc.CapTbl -T 50
Creating an RC Corner (continued)
create_rc_corner
-name spef_2x_2x
-cap_table typRtypC.xyz
-T 50
-qx_lib_file
-qx_conf_file
-qx_tech_file
Creating a Delay Calculation Corner
 A delay calculation corner provides all of the information necessary to
control delay calculation for a specific analysis view.
 Each corner contains information on the libraries to use, the operating
conditions with which the libraries should be accessed, and the RC
extraction parameters to use for calculating parasitic data.
 Delay corner objects can be shared by multiple top-level analysis
views.
To create a delay calculation corner, use the following command:
create_delay_corner
Delay Calculation Corners
<library_set>
-name lsCOM-1.0 create_delay_corner
-timing { … } -name dcWCCOM
-si { … }
-library_set lsCOM-1.0
-opcond_library stdcell_1V
-opcond WCCOM_1.5
<rc_corner> -rc_corner rcMax
-name rcMax OR (for OCV in MMMC mode)
-cap_table rcmax.capTbl -early_library_set
-T 125 -early_opcond_library
-qx_lib_file -early_opcond
-qx_conf_file -early_rc_corner
-qx_tech_file
-late_library_set
-late_opcond_library
-late_opcond
-late_rc_corner
Adding MSMV Domains
<library_set>
-name lsCOM-1.0 create_delay_corner
-timing { … }
-name dcWCCOM
-si { … }
<rc_corner>
-opcond WCCOM_1.5
-name rcMax -rc_corner rcMax BlockA Block B
-cap_table rcmax.capTbl (1.0V) (1.0V)
update_delay_corner
-name dcWCCOM
-power_domain domain-2V BlockC
<library_set> (2.0V)
-name lsCOM-2.0
-timing { … } -opcond_library stdcell_2V
-si { … } -opcond WCCOM
VDD1 VDD2
Constraint Modes
 The create_constraint_mode command
create_constraint_mode
is used to associate a Tcl list of .sdc files
-name missionSetup
with a named mode.
[list io.sdc mission1-clks.sdc
.sdc files mission1-except.sdc]  SDC files can be shared by many
different modes.
 A mode defines one of possibly many
-name missionHold
{io.sdc mission1-clks.sdc different functional, test behaviors, or
.sdc files mission1-except.sdc DVFS modes of a design.
dont_use.sdc}
 SDC files contain the clock
specifications, conditionalizing constants,
-name testHold
{test-io.sdc test-clks.sdc I/O timings, and path exceptions that
.sdc files test-except.sdc} make each mode unique.
Analysis Views
<delay_corner>
-name dcWCCOM
-opcond_library stdcell_1V.lib
-opcond WCCOM_1.5
create_analysis_view
-name missionSlow
-delay_corner dcWCCOM
-constraint_mode missionSetup
<constraint_mode>  The create_analysis_view
-name missionSetup command builds a top-level
{io.sdc mission1-clks.sdc association of a delay calculation
mission1-except.sdc}
corner with a constraint mode.
 The set of active views defined to
<delay_corner> the system represent the different
design variations to be timed and
-name dcBCCOM
optimized.
-opcond_library stdcell_1V.lib
-opcond BCCOM_1.5
create_analysis_view
-name missionFast
-delay_corner dcBCCOM
-constraint_mode missionHold
<constraint_mode>
-name missionHold
{io.sdc mission1-clks.sdc
Analysis View Hierarchy
<analysis_view>
-name missionSlow
-delay_corner dcWCCOM
Corner -constraint_mode missionSetup Mode
Information Information
<delay_corner> <constraint_mode>
-name dcWCCOM -name missionSetup
{io.sdc mission1-clks.sdc
-opcond WCCOM_1.5
<rc_corner> -rc_corner rcMin
-name rcMin
-cap_table typRtypC.xyz <library_set>
-T 125 -name lsCOM-1.0
-timing { … }
-si { … }
.sdc files
3V
2V
1V MEM
PAD
PLL
.lib files
Setting the Active Analysis Views
After creating analysis views, you must set which views the software should
use for setup and hold analysis and optimization.
 These "active" views represent the different design variations that will
be analyzed. Active views can be changed throughout the flow to use
different subsets of views.
 Encounter applications can handle the views concurrently or
sequentially, depending on their individual capabilities.
 Libraries and data are loaded into the system, as required to support
the selected set of active views.
To set active analysis views, use the following command:
set_analysis_view
The following command sets missionSlow and mission2Slow as the active
views for setup analysis, and missionFast and testFast as the active views
for hold analysis:
set_analysis_view -setup {missionSlow mission2Slow} \
-hold {missionFast testFast}
Checking the Multi-Mode Multi-Corner Configuration
Run the following command to generate a hierarchical report of your current
multi-mode multi-corner configuration:
report_analysis_views
You can customize the report to show only the active setup or hold analysis
views, all of the active views, or all of the defined views in the design,
including those that are currently inactive.
Saving Multi-Mode Multi-Corner Configurations
 The Encounter® platform stores the multi-mode multi-corner
configuration as Tcl commands in a view definition file.
 The view definition file contains all the library sets, RC corner, delay
calculation corner, constraint mode, and analysis view definitions that
you created.
 When you specify the saveDesign command, the software saves the
file to the save directory, and updates the configuration file with a
pointer to the file.
 This multi-mode multi-corner configuration will be reloaded
automatically by the subsequent use of the restoreDesign command.
Example MMMC Script: Setting Up Views
create_rc_corner -name dtmf_rc_corner -cap_table {../captable/t18s.capTbl} -
preRoute_res {1.1} -preRoute_cap {0.8} -preRoute_clkres {0.9} -
preRoute_clkcap {0.9} -postRoute_res {1.1} -postRoute_cap {0.9} -
postRoute_xcap {1.1} -postRoute_clkres {0 0 0} -postRoute_clkcap {0 0 0}
create_library_set -name dtmf_libs_0.8 -timing {../lib/pllclk_0.8.lib
../lib/ram_128x16A_0.8_syn.lib ../lib/rom_512x16A_0.8_syn.lib
../lib/slow.lib ../lib/io-lite_0.8.lib} -si { ../CDB/slow.cdb}
create_library_set -name dtmf_libs_1.1 -timing {../lib/pllclk_1.1.lib
../lib/ram_128x16A_1.1_syn.lib ../lib/rom_512x16A_1.1_syn.lib
../lib/fast.lib ../lib/io-lite_1.1.lib } -si { ../CDB/fast.cdb }
create_constraint_mode -name common -sdc_files {dtmf.sdc}
create_delay_corner -name dtmf_corner_0.9 -rc_corner {dtmf_rc_corner}
-library_set {dtmf_libs_0.9}
create_delay_corner -name dtmf_corner_1.1 -rc_corner {dtmf_rc_corner}
-library_set {dtmf_libs_1.1}
Example MMMC Script: Setting Up Views (continued)
create_analysis_view -name dtmf_view_0.9 -constraint_mode {common} -
delay_corner {dtmf_corner_0.9}
create_analysis_view -name dtmf_view_1.1 -constraint_mode {common} -
delay_corner {dtmf_corner_1.1}
set_analysis_view -setup {dtmf_view_0.9} -hold {dtmf_view_1.1}
Performing Timing Analysis
The timeDesign command reports the results from each active analysis
view, as well as an aggregated summary.
Syntax:
timeDesign -expandedViews
For multi-mode multi-corner analysis, the software creates a separate
directory for each view. For example, if your design has two analysis views,
view1 and view2, the output reports are generated in the
./timingReports/view1 and ./timingReports/view2 directories.
By default, timeDesign will just create an aggregated summary.
The MMMC Wizard
 Select Timing – Configure MMMC to interactively set up Library Sets,
RC Corners, Delay Corners and Constraint Modes
 Additionally, use the MMMC Wizard to set up the Analysis Views
Best Practices for MMMC Analysis
In general, limiting the number of analysis views can have a big impact on run time.
For example, you might have a single functional mode but want verify it with a
couple of different corners; this can be either:
 Same libraries and captable but different temperatures
 Same libraries but different capacitance table and/or different temperature
 Different libraries and/or different capacitance tables and/or different
temperature
 These scenarios are different in the impact on run time and memory. Since the
constraints are the same the timing graph is not impacted but extraction and
delay calculation are affected. If the constraints are different, then, that affects
the timing graph as well.
Generally, multi-mode analysis is more expensive than multi-corner in terms of run
time.
 Even if you are planning analysis on using several corners, it is often sufficient
to run analysis with just the worst-case corner until after the CTS stage.
 After CTS, other corners should be activated to ensure cross-corner validation.
Lab Exercises
Lab 4-1 Extracting RC Data
Lab 4-2 Running Timing Analysis and Generating a Slack Report
Optimizing and Closing Timing
Module 13
February 3, 2011
Module Objectives
In this module, you
 Articulate the purpose of optimization
 Use the optimization guidelines to converge towards your constraints
 Run setup, hold, leakage and dynamic power, and DRV optimizations
 Meet timing at different stages of the design process, using the

optDesign command
 Use path groups to focus analysis and optimize failing paths
 Close timing with useful skew
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff

Setup Opt. Setup/Hold Opt. Setup/Hold Opt.

Met? Met? Met? Met?
Signoff
Optimize Menu
… Floorplan Place Optimize…
What Is Optimization?
 Optimization is the process of iterating through a design such that it
meets timing, area, and power specifications.
 In general, optimization can be broken down into the following areas:
 Timing
 Signal integrity
 Power
 Area
 The design has to satisfy multiple design objectives from above.
Optimization Operations
Depending on the stage of the design, optimization can include the
following operations:
 Adding buffers
 Resizing gates
 Restructuring the netlist
 Remapping logic
 Swapping pins
 Deleting buffers
 Moving instances
 Applying useful skew
Setting the Optimization Mode
Set the Optimization Mode by choosing Options – Set Mode – Mode
Setup. Select Optimization in the List of Modes pane.
High specifies high effort level. Use this level to
reach timing closure for challenging designs.
This level activates all the physical synthesis
optimization transforms.
Low Specifies low-effort level. Use this level for
design prototyping. This level triggers global
resizing and buffering in order to obtain a
good timing result in the fastest run time.
Simplify Netlist
Determines whether to simplify the netlist
during timing optimization. The software
recovers area, decreases congestion, and
improves run time by simplifying the netlist in
the following ways:
- Removing dangling output instances
- Propagating constants
- Remapping useless logic
Leakage Power Effort

 Low Reduces leakage power only in the postroute stage. The software does not insert
high-leakage cells during hold fixing.
 High Reduces leakage in pre-route and postroute stages. This mode is more aggressive
than low-effort mode, and might affect run time and timing closure.
Setting the Optimization Mode for Clock Gating
Syntax
setOptMode -clkGateAware {true | false}
Description: Specifies that timing optimization is aware of clock gating
instances in the design. The software automatically applies assertions on
those cells clock pins. Those assertions will be removed at the end of
optDesign.
This option is only active with optDesign -preCts.
Command Usage
Note: It is recommended to also enable setPlaceMode -clkGateAware true during
placement when enabling setOptMode -clkGateAware true to get the best handling of
clock gates throughout the flow.
Concurrent Timing and Leakage Optimization
Concurrently reduce leakage and optimize timing.
Set leakagePowerEffort.
setOptMode –leakagePowerEffort [none | low | high]
 none: This will be the regular flow.
 low: Reduces power in the post-route stage
 high: Reduces power in pre-route and post-route stage
 Setting -leakagePowerEffort will make the optDesign command power-

aware.
optDesign –preCTS | postCTS | postRoute
IPO stands for in-place optimization.
Concurrent Timing and Dynamic Power Optimization
The Encounter Digital Implementation system optimizes dynamic power by
implementing cell sizing on the netlist, without modifying the clock tree.
It is recommended to provide an activity file. If not provided, the Encounter ® Digital
Implementation software automatically generates a default activity file based on a
propagated toggle rate of 0.2 on each input port.
The only requirement to perform dynamic power optimization is to have internal
power tables for each of the cell modules in the .lib libraries.
Syntax
setOptMode -dynamicPowerEffort {none | low | high}
 low: Use the low-effort mode when dynamic power is not the highest priority.
Power optimization is done only in the postroute stage. Timing closure remains
the first priority and the worst negative slack achieved is same as in the none
effort mode. The CPU run-time impact is less than eight percent.
 high: Use the high-effort mode when dynamic power reduction is very critical.
Power optimization is done in the entire optDesign stage. Timing closure
remains the first priority. The CPU run-time impact is less than 20 percent.
 none: Specifies no power optimization.
Fixing Signal Integrity with Third-Party Full SDF
 If you use a third-party sign-off tool in your flow, you might see a few
violations remaining due to correlation issues.
 A reliable and converging SI closure flow based on reading third-party
SDFs has been provided.
 The optDesign command has been enhanced to read in a full SDF
(base delay + incr. delay) and will fix violations based on timing
analysis using the SDF delays.
 Only one iteration of fixing will be run and it is recommended that you
run final timing analysis in your signoff environment.
Commands (in MMMC mode)
read_sdf -view viewName1
read_sdf -view viewName2
……
read_sdf -view viewNameX
optDesign -postRoute -si -useSDF
Fixing Signal Integrity with Third-Party SPEF and Incremental SDF
 You can read a third-party SPEF and incremental SDF files into
Encounter DI for SI fixing.
 Only one iteration of fixing is done, and you have to run final timing
analysis in your signoff environment.
Commands
spefIn <fileName> -rc_corner
timeDesign -reportOnly
setSIMode -acceptableWNS <from above timeDesign>
read_sdf –view viewX <f1>
optDesign -postRoute –si [-hold] –useSDF
-acceptableWNS is very tricky here. SI optD will work towards third party’s SPEF WNS. If SI
delta+base > third party’s SPEF WNS, optD –si will keep pressing on.
Optimization Form
 Pre-CTS mode uses ideal clocks for timing and optimization.
 Before optimization in post-CTS mode, run timing analysis using

propagated constraints. This takes into account the real clock insertion
latencies and skews of the inserted trees. Adjust the clock uncertainty
to model only jitter. Before CTS, clock uncertainty includes both skew
and jitter.
Optimize – Optimize Design
If Post-Route is selected, then you can include

SI Options during optimization.
You can run optimization to fix setup, hold, signal integrity, or DRVs.
Mode
 Pre-CTS performs timing optimization on the placed design, before the clock tree is built.
 Post-CTS performs timing optimization after the clock tree is built. By default the
Encounter software repairs DRVs and setup violations for all path groups.
 Post-Route performs timing optimization on designs whose routing is complete. By
default, this option repairs DRVs and setup violations for all path groups.
Effort Level
 Low uses estimated delay values for faster run time.
 High optimizes paths across clock domains and does critical path analysis and fixes.
Specify the path groups for the optimizer to work on by selecting the Specified Path
Groups option. This brings up the form where you can specify the types of paths to
optimize.
Setting Path Groups for Optimization and Timing
You can create path groups to optimize specific failing paths.
 The path group feature is natively supported by the timing engine
(CTE).
 The report_timing command supports the -path_group option.
 Path groups can be added to an SDC file or from the command shell
by using the group_path command.
 You can apply different optimization effort levels, target slacks and
critical ranges for each path group.
To create the most commonly used path_groups, run:
createBasicPathGroups
 The command creates the reg2reg, in2reg, reg2out, in2out and clkgate
path_groups.
 It automatically sets High effort level on reg2reg.
 Once created, you can remove some of them and/or apply any options to
those path_groups.
When at least one path group is created:

 If no path groups have a high effort setting: optDesign optimizes all path groups at the
same time and will end as soon as the WNS cannot be improved.
 If one path group has a high effort setting: optDesign optimizes all path groups (Low
and High) at the same time and then will re-optimize independently the High effort path
group.
 If several path groups have High effort setting: optDesign optimizes all path groups
(Low and High) at the same time and then reoptimizes concurrently each high effort path
group to their best possible slack.
You can choose the level of timing optimization effort that should be spent on each path group
by setting the effort level.
setPathGroupOptions <group_name> -effort {low|high}
 Low: Those path groups will be optimized together until the best overall slack is
achieved. Low is the default for any user-created path group.
 High: Those path groups will be re-optimized concurrently to achieve the best possible
WNS for each of them.
When no path groups are defined, optDesign runs on temporarily created reg2reg, in2reg,
reg2out, in2out and clkgate path groups.
Creating and Reporting Path Groups
 You can create path groups by entering group_path commands in an
SDC file or in the Encounter command window.
encounter> group_path -name IO -from [all_inputs -no_clocks] -to
[all_outputs]
encounter> group_path -name FF -from [all_registers] -to [all_registers]
encounter> group_path -name 200MHZ –to slow_clk1
encounter> group_path -name 800MHZ –to fast_clk1
encounter> group_path -name 800MHZ –to fast_clk2
 You can report all start points and end points that are part of one or all
the path groups.
encounter> report_path_groups
To delete all path groups, enter:

reset_path_group -all
To delete one path group, enter:
reset_path_group –name <group_name>
Timing Reports with Path Groups
 When no path groups are defined, timeDesign will report a summary
table based on temporarily created reg2reg, in2reg, reg2out, in2out
and clkgate path groups. This is the same default behavior as without
clockDomains.
 When at least one path group is created, timeDesign will report a
summary table based on the path group.
Example
encounter> group_path -name IO -from [all_inputs -no_clocks] -to [all_outputs]
encounter> group_path -name FF -from [all_registers] -to [all_registers]
----------------------------------------------------
timeDesign Summary%%
----------------------------------------------------
+--------------------+---------+---------+---------+
| Setup mode | all | FF | IO |
+--------------------+---------+---------+---------+
| WNS (ns):| -2.536 | -2.536 | -0.170 |
| TNS (ns):|-686.438 |-672.698 | -0.170 |
| Violating Paths:| 868 | 729 | 1 |
| All Paths:| 2792 | 2344 | 41 |
+--------------------+---------+---------+---------+
Best Practices for Using Path Groups
Any path group that you create can cause extra run time, especially when adding
-slackAdjustment or -targetSlack options.
 If you created path groups just for timing analysis, then you can choose to
remove them for optimization.
 Do not create any path group unless you really need it. One approach to
prevent the creation of too many path groups is to first optimize without any
path groups and then create some high effort path groups for an incremental
optimization, if needed.
 Create minimal overlaps between path groups.
Examples
 To add .2ns of slack adjustment to all paths belonging to the
PATH_GROUP_A path group, specify the following command:
setPathGroupOptions PATH_GROUP_A -slackAdjustment .2
 By additionally specifying –slackAdjustmentPriority, you can provide priority
to a path group for slack adjustment.
 To specify that the optDesign command achieves a maximum of .2ns on path
group PATH_GROUP_A, specify the following command:
setPathGroupOptions PATH_GROUP_A -targetSlack .2
Running optDesign Pre- and Post-Route
 You can use the setOptMode and optDesign commands instead of the
timing optimization forms.
 The right default settings for timing and extraction are applied based
on the design stage.
 For pre-Route optimization, run the following syntax:
optDesign [–preCTS|-postCTS] [-hold]
 For post-route SI and timing analysis, use the Advanced Analysis

Engine (AAE) to combine base timing delays and delays due to SI in
one step:
setDelayCalMode –engine default –siAware true # AAE Engine
optDesign –postRoute
optDesign –postRoute –hold
Press Control–C to exit optDesign without exiting the Encounter session. Use this option to
debug an intermediate database but do not use it as a starting point for other flow steps. When
you are finished with debugging the design, delete the database.
Critical Range Optimization
The optDesign command optimizes a critical range of worst paths rather
than just the most critical path:
setOptMode –criticalRange <value>
<value> is between 0 and 1. Default is 0.2.
In this mode, optDesign works on all paths with slack between current slack
and range.
range = WorstSlack X (1.0 - <value>)
 Increasing the fix range causes the tool to spend more CPU time in
optimization.
 Use critical range optimization only in incremental optimization when
the current slack is close to the target slack.
For example, if the worst slack is -1.0 and the value is 0.3, paths with slack
ranging from -1.0 to -0.7 are in the critical range, so they are optimized. The
range is calculated dynamically. When the worst slack changes, the critical
range changes as well. In the example above, if the worst slack changes to
-0.5, the range is recalculated as -0.5 to -0.35.
Useful Skew
 Useful skew is a technique that takes advantage of the difference of
arrival time at flip-flops to correct datapath timing violations.
 Increased latency but decreased clock period provides a net timing
advantage.
 The conventional approach to clock tree generation is also called the
Zero Skew approach:
 The clock is treated as ideal.
 All combinational blocks must fit into same clock period.
 All registers are clocked at the same time.
 You don’t need knowledge of signal timing.
Clock skew is the maximum difference of clock arrival time between all pairs of registers
It is inherent to the inability to build a clock tree with fully balanced branches due to:
 C, RC
 Different types of buffers/inverters
 Gating Components
 Off-chip or on-chip variations (PVT)
You want to make clock skew as small as possible
 To take advantage of the full clock period.
 To allow direct register to register connection.
Closing Timing with Useful Skew
 A good classical skew minimization strategy does not necessarily
correlate with good performance.
 Some combinational paths require more time than the allowed clock
period.
 Adjusting clock delays to registers allows to allocate more time to
some paths and less on others.
 Time is borrowed from neighboring paths that have positive slack.
 Useful skew can be done pre- and post-CTS.
Two Complementary Approaches to Useful Skew
Violated Paths
Scheduling Pre-CTS: Padding Post-CTS:

Source clocks are sped up. Target clocks are slowed down.
Pre-CTS Useful Skew
Pre-CTS useful skew works on flip-flops and generates two files:
 Latency file
 Contains all the latencies generated by the following commands:
setOptMode –usefulSkew
optDesign -preCTS
 Is loaded automatically each time you report timing.
 Is saved in the .conf file:
set rda_Input(ui_latency_file) “latency_file.cts”
 Scheduling file
 Contains the information to be passed to CTS.
 Is used by CTS to build a clock tree.
 Is saved in the .conf file:
set rda_Input(ui_scheduling_file) “scheduling_file.cts”
Pre-CTS Useful Skew (continued)
 Running useful skew pre-CTS
 Use the setOptMode –usefulSkew and optDesign commands at the end of
the optimization to generate the scheduling file.
 Automatically report the new timing by using the latency file.
 Loading an Encounter Digital Implementation database with useful

skew
 Syntax
setAnalysisMode -usefulSkew true
 Report the timing with the timeDesign –preCTS command.
 Building the clock tree with a scheduling file

 The clockDesign command will automatically read the generated scheduling
file if the setOptMode -usefulSkew option remains set.
 Build the clock tree and report post-CTS timing by using the timeDesign
-postCTS command and option.
Post-CTS Useful Skew
Post-CTS useful skew performs time-borrowing by inserting buffers/inverter
pairs or resizing cells on clock nets.
Running Useful Skew After CTS

 Use the following commands at the end of the post-CTS optimization.
setOptMode –usefulSkew
optDesign -postCTS
 Report the new timing.
 You can specify the cells that optDesign uses during post-CTS buffer
insertion.
Syntax
setUsefulSkewMode [-useCells {cellName ...} -maxSkew]
 The getUsefulSkewMode command displays the mode that was set by
setUsefulSkewMode.
Interactive ECO
Optimize – Interactive ECO Use Interactive ECO to:
 Add a buffer
 Change a cell for a particular

instance
 Delete a buffer
 Display a buffer tree
Evaluates the effect of adding a cell. You can use this feature to
experiment with different cell types.
Implementing Maximum Wire Length Rules
Run the following command to specify a maximum wire length for inserting
repeaters:
setOptMode –maxLength <value_um>
When specifying the -maxLength option, the optDesign command will honor
the maxLength rule in the same way that it honors all any other DRV rules:
max_capacitance, max_transition, and max_fanout.
The value to be provided in is uM units. The optDesign command will fix all
the nets that violate this rule and will not create any long nets that would
violate it.
Default: off
Optimization Guidelines
 Check the timing constraints.
 Run timeDesign -prePlace to verify the timing constraints before
running timing optimization.
 If timing is not met after synthesis, it will most likely not be met during
implementation.
 Use the same constraints for implementation and signoff, such as
exceptions.
 Review Trial Route congestion report during optDesign and in the

graphical interface:
 High congestion causes detours and leads to worse results.
 For area critical designs use the following option to remove useless
logic or dangling output instances:
 setOptMode -simplifyNetlist true
Optimization Guidelines (continued)
 Make sure to leave 5-7% of your targeted final utilization for running
optimization.
 Running optimization will remove all or a majority of violating paths by:
 Downsizing instances to recover area, without degrading timing.
 Upsizing instances on violating path to meet timing by improving the
drive strength.
 Use advanced optimization techniques to enable physical
optimization routines to close timing for challenging designs or
blocks.
 Optimizing fanout on violating fanout net by either upsizing instance,
splitting the load by adding a similar instance or inserting a buffer to
meet timing.
 Fixing DRC for both transition time and capacitance load violations
 Run setOptMode –drcMargin <margin> (Use a positive number to
tighten the margin and a negative number to relax the margin)
Optimization Guidelines (continued)
After running optimization, you must examine the remaining violating paths
for the following possibilities:
 Make sure that the worst path can meet your target slack.
 Use path groups to further optimize the design.
 Check routability numbers from Trial Route.
 Check the congestion map to see if the worst paths are going through
local congestion hot spots.
 If there are congestion issues, try optimization on a high effort congestion-
driven placement.
 If there are timing issues, run placeDesign -inPlaceOpt
Implementing the Clock Tree
Module 14
February 3, 2011
Module Objectives
In this module, you
 Create a clock constraints file
 Run clock tree synthesis and route the clock tree for post-route timing
correlation
 Improve local skew using ckECO
 Analyze the clock display for delays in the clock tree
 Interactively insert buffers and inverters into the clock tree
 Analyze the Clock Tree by using the interactive Global Clock Debug
(GCD) tool
 Run diagnostics on your clock tree in pre- and post-CTS design stages
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
What Is Clock Tree Synthesis?
Before CTS, the clocks in the design are treated as ideal (no clock skew, no clock
latency, ideal transition time, etc.). During CTS, buffers are added to the clock nets
in order to minimize:
 Clock skew in the design
 Clock latency in the design

C
from_a dout
RAM A1
RAM A0
clk
u10 u11 c2 u12
u13 c3
c0 u14 u15
u16 u17 c1
c0,c1,c2,c3 clock buffers are added
from_b
What Is Clock Tree Synthesis? (continued)
Buffers are added to the clock tree in our example design.

Netlist before CTS
DFF1 DFF2
u11 u13
u10 u11
Netlist after CTS
DFF1 DFF2
u11 u13
u10 u11
c2 c3
c0 c1
Placement after CTS

dff1 dff2
u11 c2
u10 u11
u13 c3
c0 u14 u15
u16 u17 c1
Clock Tree Synthesis Menu
… Floorplan Place Clock Route ECO Timing SI
Clock Tree Synthesis (CTS) Guidelines
 Make sure the module utilization containing the clock nets is 5% to 7%
less than that of the targeted final placement utilization. You can use
cell padding to achieve this objective.
 There are two CTS modes for specifying the clock tree:
 Manual mode
 Automatic clock mode
 Both manual and automatic modes are driven by a clock tree

specification file.
 For manual mode, you specify the clock tree structure.
 The preferred way is to use the automatic mode.
Clock Tree Synthesis (CTS) Guidelines (continued)
 For the automatic mode, CTS traces the clock net through buffers, inverters,
and gated elements.
Tracing stops at a clock pin, D-input pin, instances without timing arcs, and
pins or ports specified in the file.
 CTS priorities are:
1. Clock skew.
2. Input transition time for power consumption
3. Clock insertion delay
 Recommended run procedure

1. Optimization to fix setup time violations
2. CTS
3. Optimization to fix setup time violations post-CTS
 To remove a previously synthesized clock tree, run the deleteClockTree

command.
Manual Clock Tree Specification Example
ClockNetName <netName> where netName is the clock net name.
LevelNumber <number> where number is the number of clock buffer levels.
LevelSpec <levelNumber> <#_of_buffers> <bufferType>
where levelNumber is the level number, total number of buffers, and name of buffer type.
To F/Fs
Example Specification File
ClockNetName MCK_GE CTS
,,,,,,,,
LevelNumber 2
MCK_GE
LevelSpec 1 2 CLKBUF40 MCK_GE
,,
LevelSpec 2 20 CLKBUF20
To F/Fs
End
,,,,,,,,,,,,
ClockNetName
….
End
,
Added by CTS
Automatic Clock Tree Specification
Phase Delay 1
SH1/I23/Z
Flip-Flops
 CTS buffer2
Sink Input Max Skew
CTS buffer1 Transition Time
Phase Delay 2
8 FPU/CORE
Buffer Input Designated Leaf or can be a
CTS buffer3 Pin FPU/CORE/A std cell
CTS buffer4 Transition Time
XPU/CAM
8
No skew balancing done for
Example of CTS spec file
Excluded Pin XPU/CAM/C
AutoCTSRootPin SH1/I23/Z Added by CTS
ExcludePin + XPU/CAM/C Example of CTS spec file (continued)
RouteClkNet YES
MaxDelay 5ns
RouteTypeName CK1
MinDelay 0ns
NonDefaultRule
Buffer buf1 buf2 inv1 inv2 del1 DBLCUT_RULE Additional details
MaxSkew 500ps PreferredExtraSpace 1 on CTS spec file
MaxDepth 20 TopPreferredLayer 5
LeafPin + FPU/CORE/A rising BottomPreferredLayer 4
syntax in EDI User
END Shielding VSS Guide
 Set NoGating NO for clock gating.

 Set RouteClkNet Yes for the NanoRoute® router to route the clock nets during CTS
(Recommended).
 The max skew/trans values need to be “realistic” with respect to the actual clock period.
Overconstraining the clock specification increases CTS buffer usage.
 Refer to “Creating a Clock Tree Specification File” in the Encounter User Guide.
Setting the CTS Mode
Options – Set Mode – Mode Setup
Refer to the Encounter Implementation System: Clock Tree Synthesis

QuickStart Guide on support.cadence.com for more details on CTS
(Trace) Data Pins of Flip-Flop/Latches

This option treats data pins of flip-flops and latches as synchronous pins, instead of as
excluded pins. Data pins include:
 Data pins
 Enable pins
 Scan-in pins
 Scan-enable pins
 Synchronous set and reset pins
(Route/EM) Route With NanoRoute Guidance
Tells the NanoRoute® software to use the CTS-generated route guide file when routing clock
nets.
Fix Violation Due To LEF AC Limit
Attempts to minimize EM violations during synthesis by resizing or inserting buffers to
enhance the electrical current flow through the wires. If any wire exceeds the library value,
CTS reports the violation in the standard CTS report.
Generating a Clock Tree Spec File
Generates a clock spec file by using the clock
Clock – Synthesize Clock Tree constraint and spec values in the timing constraints
file.
Command: createClockTreeSpec –file
<outputFileName>
SDC command Clock Spec File Command
create_clock AutoCTSRootPin
set_clock_transition SinkLeafTran and BufMaxTran

(Default 400 ps)
set_clock_latency MaxDelay (Default period,
MinDelay is set to 0)
set_clock_uncertainty MaxSkew (Default 300 ps)
create_generate_clock Add ThroughPins when

necessary
AutoCTSRootPin
Specify the clock buffers to use for clock tree

synthesis. Buffer selection can have a
significant impact on CTS quality. ThroughPin
Mapping SDC Parameters to CTS Spec Parameters
CTS Spec Parameters set_clock_transition BufMaxTran and
SDC and Design condition
(highest priority), SinkMaxTran (ps)
create_clock, MaxSkew = Lowest value of (4 % of clock setDesignMode –
set_clock_uncertainty period and set_clock_uncertainty value) process <num>
AutoCTSRootPin, LeafPinGroup Default 200
111 to 250 250
create_generated_clock GlobalThroughPin, DynamicMacroModel
78 to 110 200
set_case_analysis, 65-78 150
set_logic_zero,
Below 65 80
set_logic_one, GlobalExcludedPin
set_clock_sense, Other CTS Default Value
set_disable_timing, Parameters
1’b0 and 1’b1 in netlist MaxDelay 0.01ns
set_clock_latency -source SrcLatency MinDelay 0ns
RouteClkNet Yes
set_clock_latency (specified PostOpt Yes
MacroModel
at clock sink) OptAddBuffer Yes
create_clock AutoCTSRootPin clka create_clock AutoCTSRootPin clk_mux/Y

DynamicMacroModel ref reg1/CK pin reg2/CK
Reg
clka
D Q D Q Regs
reg 2 reg 1
clk_mux
LeafPinGroup GlobalThroughPin
+ clk_mux/A create_generated_clock + reg1/CK
Running Clock Tree Synthesis: Advanced Tab
Clock – Synthesize Clock Tree
Loads the specified

incremental SDC file. Use this
option to load an incremental
SDC file after clock tree
synthesis to make minor
changes, such as changing
the clock_uncertainty value,
or to add the
set_clock_latency statement.
Loads the specified post-CTS SDC file after clock tree synthesis, before running timeDesign.
If you specify this option, CTS clears the original
SDC file from memory and loads the new SDC file before running timeDesign -postCTS.
Delete Existing Clock Tree

Removes existing clock trees before performing clock tree synthesis.
Unfix Instances Before Building Clock Tree
Changes the placement status of all buffers, inverters, flip-flops, and gating cells of the clock
tree to PLACED, before building the clock tree. If you do not specify this option, the software
sets the placement status for the buffers, inverters, flip-flops, and gating cells of the clock tree
to FIXED.
Running Clock Tree Synthesis
The clockDesign command integrates the most-used CTS commands to simplify the CTS flow.
Set the clock mode with the following command:
Example
setCTSMode –moveGate false
Run clock tree synthesis with the following command:
Syntax
clockDesign [-specFile “filename1 filename2 … ” ]
[-outDir dirname] [-clk clockname] [-macromodel filename]
[-check] [-noDeleteClockTree]
The clockDesign command:

 Loads the clock specification file
 Removes existing buffers in the clock tree (ones that are not marked as dont_touch)
 If a clock tree has been previously inserted, it unfixes the tree so that the tree can be
removed
 Generates clock skew and timing reports
Creating and Using the CTS Spec File
There are three main ways for creating and using the clock tree synthesis
spec file:
 Clock spec file automatically created by the tool and used by the
following command:
clockDesign
 Clock spec file created and used by the following command:

clockDesign –specFile user.ctstch
 Automatically created spec file modified by the flow:

setDesignMode -process 65
createClockTreeSpec
#createClockTreeSpec –file auto.spec
specifyClockTree -update {AutoCTSRootPin * SinkMaxTran 100ps}
clockDesign
CTS Features
The clockDesign command automatically balances self-reconvergent
clocks.
clk Max Skew
First, the software analyzes the clk and determines the delay to
the MUX inputs.
Next, it balances the clock paths to the MUX.
CTS Features (continued)
The clockDesign command automatically

handles crossover clocks.
SH1/I23/Z1 Max Skew1
1 Max Skew12
Max Skew2
SH22/I6/Z2 2
First, do CTS on clk12 and determine delay to MUX inputs.

Second, do CTS on clk1 and balance delay to MUX pin 1.
Third, do CTS on clk2 and balance delay to MUX pin 2.
CTS Features (continued)
Timing-driven Cloning
CTS considers clk-to-gate setup timing slack during cloning.
Command: ckCloneGate -timingDriven
You can run the ckCloneGate command after loading a clock tree
specification file, and before running ckSynthesis.
En1 Timing En1

CL critical! CL
CG1
Clk CG1 Clk
CG1_Cloned1
En2 Timing En2
CL OK CL
CG2 CG2
Debugging the CTS Spec
Run the analyzeClockTreeSpec command
to detect a problem with the CTS spec file Edit clock spec file
before running CTS.
clockDesign –specFile my.ctstch Typical
Commands: Loop
timeDesign -preCTS Timing and Clock Analysis
specifyClockTree -clkfile
clk.ctstch
analyzeClockTreeSpec
Examine the timing report to see if
there is any big jump in TNS and WNS.
To debug further, use this command:
analyzeClockTreeSpec
-genSDCOnly
Results
The analyzeClockTreeSpec command provides warnings (in the form of a large increase in
slack) in the early state of the design. This increase in the slack can be indicative of a
potential timing issue that could arise after CTS.
What You Need to Keep in Mind

 The analyzeClockTreeSpec report will not match exactly the timing reports after actual
CTS.
The assumption is based on the clock latency value assigned to each input pin whether it
is leafPin, excludedPin, throughPin, etc.
 This feature does not provide recommendations on how to make correction on the clock
spec file.
You have to examine the timing report to make judgments on how to readjust the clock
spec file.
Displaying CTS Results
Choose Clock – Display – Display Clock Tree to view a color-coded display of
CTS Results. The CTS display includes:
 Clock tree and clock insertion delay
 Clock min and max insertion delay paths
 Color coded clock instances in a spectrum: Red (most delayed), orange, yellow, green,
gray, blue, purple (least).
CTS suffix naming for inserted buffer instances and created clock nets
Buffer
rootClockName__L#_I# (Example: MCK__L0_I0 )
Net Name
rootClockName__L#_N# (Example: MCK__L0_N0)
Global Clock Debug
The Global Clock Debug tool helps you debug the clock tree by providing:
 A consolidated view of the physical structure and timing of the clock
tree
 Structure of the tree
 Logical ( pre- and post-CTS )
 Physical
 Data to analyze the quality of the timing results

 Skew
 Latency
 Balancing between clocks
 Influence on STA (Example: gated clocks)
 Debugging of the CTS spec file
Bring up the clock tree analyst by choosing Clock – Debug Clock Tree.
The Global Clock Debug Window
Clock – Debug Clock Tree
Timescale
Leaf
Flops
Clock Root
Clock Grouping CTS Features
Clock Grouping inserts delays to balance the clocks and then meet clock
skew.
Example
ClkGroup
SH1/I23/Z1 clk1
Max Skew
+ SH1/I23/Z1
+ SH22/I6/Z2
clk2
SH22/I6/Z2
The Group Leaf Pin CTS Feature
CTS can balance the group of LeafPins separately with the main clock tree.
Benefits include:
 Smaller clock tree
D D
Q
D D
Q Q
Q gate_reg1, gate_reg1,
 Shorter latency gate_reg2 gate_reg2
 Less clock tree power

D D
Q
D D
Q Q
Q
D D
Q
Q
clk No valid clk
Default: false data timing D D
Q
Q
D D
Q
Q path
D D
Q
Q
Syntax:
LeafPinGroup Grp1
+ gate_reg1
+ gate_reg2
AutoCTSRootPin clk
Buffer CLKBUFX12
MaxSkew 100ps
…
End
Interactive Update of CTS Spec File
Use the -update option to interactively update clock tree specifications
specifyClockTree –update {<update_args>}
Command: The arguments to -update are the following:

{AutoCTSRootPin <rootpin> rootpinsectionkeyword <value>} |
{AutoCTSRootPin <rootpin> <TracingDirectives> +|- <pinName>} |
{RouteType <routetype> <routetypesectionkeyword> <value>} |
{GlobalLeafPin +|- pinName} |
{GlobalExcludedPin +|- pinName} |
{GlobalPreservedPin +|- pinName} |
{NameDelimiter <value>} |
{UseSingleDelim <YesorNo>}
Example
specifyClockTree –file clk.ctstch
specifyClockTree –update –AutoCTSRootPin * {MaxSkew 100ps}
specifyClockTree –update –AutoCTSRootPin clkA {MaxSkew 125ps}
Using the Clock Tree Browser
Choose Clock – Browse Clock Tree to open the Clock Tree Browser
window.
Model for Cell Insertion and Deletions
The following are some reasons for using the manual insertion and deletion
feature:
 Manual timing adjustment
 Skew
 Latency
 Useful Skew
 Max transition correction
Cell is inserted near selected instance.

Use the Move icon to move it to a different location.
Clock Tree Editing
Buffer/Inverter Insertion
 Select the target instance in the browser.
 Multiple instances are allowed. (One buffer will be inserted for each instance.)
 Specify the actual insertion point from the menu.
 Edit – Insert at input …
 Edit – Insert at output …
 After the Buffer/inverter is inserted, run refinePlace and write out the
placement.
 The physical location of the inserted components will be near the selected
target instance.
Buffer/Inverter Deletion
 Choose Edit – Delete.
Automatic Update
 Cells, levels, and timing are automatically updated.
Currently, there is no check for polarity changes.

Add instances for clock trees before the tree is routed.
Cell Insertion and Deletion
Cell Insertion
Cell Deletion
Reconnecting Clock Tree Components
The Encounter Digital Implementation system has the capability to attach
leaves to different buffers.
Reasons for disconnecting and reconnecting buffers:
 Timing or capacitance balancing
 Useful skew
The placements are not changed when the connections are changed.
Reconnecting Clock Tree Components (continued)
1b
2a 2b
3
1a. and 1b. Select leaf cells
1a to move.
2a. and 2b. Select driver to
attach leaf cells to.
3. Click OK or Apply.
#########################################
# Complete Clock Tree Timing Report
Clock Tree Report # CLOCK: DTMF_INST/TEST_CONTROL_INST/i_150/Y
# Mode: clkRouteOnly
#
# Delay Corner information
# Analysis View : dtmf_view_setup
# Delay Corner Name : dtmf_corner_max
# RC Corner Name : dtmf_rc_corner
# Analysis View : dtmf_view_hold
# Delay Corner Name : dtmf_corner_min
# RC Corner Name : dtmf_rc_corner
Nr. of Subtrees :3
Nr. of Sinks : 394
Nr. of Buffer : 28
Nr. of Level (including gates) : 4
Root Rise Input Tran : 120(ps)
Root Fall Input Tran : 120(ps)
Max trig. edge delay at sink(R):
DTMF_INST/TDSP_CORE_INST/EXECUTE_INST/pc_acc_reg/CK
770.6(ps)
Min trig. edge delay at sink(F):
DTMF_INST/TDSP_DS_CS_INST/t_bit_7_reg/CKN 647(ps)
(Actual) (Required)
Rise Phase Delay : 657.1~883.3(ps) 0~2500(ps)
Fall Phase Delay : 647~767.9(ps) 0~2500(ps)
Trig. Edge Skew : 123.6(ps) 250(ps)
Rise Skew : 226.2(ps)
Fall Skew : 120.9(ps)
Max. Rise Buffer Tran : 234.1(ps) 250(ps)
Max. Fall Buffer Tran : 233(ps) 250(ps)
Max. Rise Sink Tran : 286.2(ps) 250(ps)
Max. Fall Sink Tran : 128(ps) 250(ps)
Min. Rise Buffer Tran : 51.2(ps) 0(ps)
Min. Fall Buffer Tran : 49.1(ps) 0(ps)
Postroute Correlation
Achieving correlation between CTS results and post-route results is
essential.
Clock tree synthesis (CTS) will route the tree with theNanoRoute detail
router after placing CTS buffers.
 In the clock tree specification file, includeRouteClkNet YES.
 In the Encounter console, enter clockDesign. This command will create

a clock tree and route it using the NanoRoute detail router.
Post-CTS Optimization
Use the ckECO command for post-CTS optimization of clock tree(s) to
improve the skew of each clock and clock group, and to resolve minimum
phase delay violations.
The ckECO command can be run in three modes:
ckECO -preRoute
ckECO -clkRouteOnly
ckECO -postRoute
Clock Tree Synthesis Diagnostics
Run Clock Tree Synthesis diagnostics to:
 Detect library or design characteristics that can lead to poor QoR or
performance
 Detect unexpected behavior during CTS that may indicate a problem
 Checks can be run before CTS to prevent problems in building the

clock tree
 A different set of checks can be run after CTS to detect a different set
of problems
Pre-Synthesis Checks
Cell drive strength Post Synthesis Checks
Input pin capacitance Large refine placement moves
Root input transition NanoRoute follows CTS guidance
Reconvergent paths through MUXes Auto-save design snapshot during long run time
Deep gating levels Gating Location
Reports of FIXED, DontTouch and DontUse attributes Subtree delay and level checks
Clock pins without available placement locations nearby
Clock pins blocked by routing obstructions
Gate Location
MacroModel Definition
Pre-Synthesis Checks
 What is a drive strength check?
 Detects weak buffer choices in spec files and clock gating instance
that might not have sufficient driving strength to meet maximum
transition constraints
 What is an input pin Measured value
47.7ps
Smallest buffer
capacitance check? = 91ps
 Detects an instance that 0ps slew

X8 AND2X2
has huge input pin

capacitance the CTS Use biggest buffer Drive strength check
might not be able to meet
Use biggest buffer Measured value
the MaxCap constraint 47.7ps
= 91ps
and maximum transition

0ps slew X8 X8
constraints.
Test all buffer choices
Input pin cap check
Pre-Synthesis Checks (continued)
 What is a root input transition check?
 Detects root input transition value that does not seem to be reasonable to
meet maximum transition constraint
 What is a reconvergent mux check?
 Detects a multiplexer (mux) that has the same clock going through more
than one input pin.
 What is a gating-level check?
 Reports the maximum gating level and a sample path if the gating level of
the clock exceeds a certain threshold
RootInputTran > BufMaxTran?

clk
clk
Root input transition check Reconvergent mux check
Pre-Synthesis Checks (continued)
 What is an attribute check?
 Detects cells that are marked as Don’t touch, Don’t use, and the Fixed
placement attribute which prevents CTS from resizing them.
 What is a placeable distance check?
 Checks if there is an available location near the leaf pin where a buffer can
be placed legally to drive the pin with acceptable input transition.
 What is a route obstruction over clock pin check?
 Detects possible reasons that may cause routing correlation issue (e.g., the
clock pin have been covered by routing blockages that are equal level of
preferred routing layer).
Buffer far away from M3-M4

LeafPin due to placement
M1-M4
blockage
Placeable distance check Route Obstruction over clock pin check
Gate Location and Macromodel Checks
 What is a gating location check?
 Checks the following
 Clone receiver placement check at pre-synthesis stage
 Gate location at pre-synthesis stage
 Gate location during-synthesis
 What is a macromodel definition check?

 Check for macromodel definitions that may lead to poor CTS results, such as:
 Invalid delay values
 Max delay is too large that it may be impossible to meetMaxDelay
 skew is too large that it may be impossible to meetMaxSkew
 Large variance among different macromodel delays
Bounding Box
Margin
Overlapping area
Clone receiver placement check

Poor Gate location
Post Clock Tree Synthesis Checks
 What is a refineplace check?
 Detects if there is any large refineplace movement and reports those cells
that moved with distance that exceed the threshold
 What is routing correlation check?
 Reports nets that have wire length deviation between CTS estimation and
actual routing
 Reports nets that have low preferred routing layer utilization
Running CTS Diagnosis
 All checks are done with clockDesign or ckSynthesis before, during or
after synthesis.
 To do a pre-synthesis check without running synthesis, run
clockDesign –check or ckSynthesis –check.
 To do a post-synthesis check when the clock tree is built, run
ckSynthesis –postCheck.
 All checks are turned on by default. Use setCTSMode to disable the
check
 All checks have certain criteria and thresholds:
 WARN or ERROR messages are issued if the threshold is exceeded or the
criteriamet
 Use setCTSMode to override the default threshold or criterion
Encounter Digital Implementation CTS Flow
setCTSMode GUI
setCTSMode
Edit CTS
createClockTreeSpec File
CTS
Clock Tree Disgnostics Spec
File
clockDesign
Clock Tree Disgnostics
Result OK? NO Clock tree analyst
Clock tree browser

ckECO Manual ECO
Display clock tree
Lab Exercises
Lab 4-3 Running Timing Optimization
Lab 4-4 Running Clock Tree Synthesis
Lab 5-1 Extracting and Generating Scale Factors
Analyzing Power
Module 15
February 3, 2011
Module Objectives
 Explore the sources of dynamic and leakage power
 Run Early Rail Analysis and examine the IR drop
 Run Power analysis and view the average power dissipation
 Analyze the effect of Rail Analysis results on the power plan
Dynamic Power
Dynamic Power = Active Power = Switching Power
Dynamic/Active/Switching Internal Power Net Power

= +
Power (Internal switching power) (Net switching power)
Internal capacitance power

Internal short circuit
(caused by charging and
power (caused by
discharging of internal
crowbar current*)
capacitances)
*Crowbar current is defined as when both the P and N

channel transistors are partially on.
Leakage Power
Leakage power is the static power dissipation by the CMOS transistor when the circuit
is in the standby mode or when the device is inactive.
Gate Oxide
I4
I3
Vdd
Gate I2
I1
Subthreshold
Drain Vin Vout
Source I2
Gate I4 CL
p-substrate
GND
Components of Leakage Power

I1 - Diode reverse bias current
I2 - Subthreshold current
I3 - Gate induced drain leakage
I4 - Gate oxide leakage
Of all the above leakage components,

subthreshold leakage is critical and very important.
Due to today’s technology and Moore’s law, the two leakage components which are important
are:
 Subthreshold leakage (I2) transistor is the leakage current flowing through the transistor
when it is supposed to be turned off.
 Gate oxide tunneling (I4) currents are more important with smaller process technology
because the gate oxide that is supposed to insulate the transistor becomes thinner and
thinner. As a result, current that is going through the transistors leaks away.
Power and Rail Analysis Menus
… Power Place Help
Setting Up Power Analysis
 You can run either static or dynamic power analysis.
Power – Power Analysis – Setup
Analysis Method Specifies either static or dynamic power analysis

Dynamic Power Method If dynamic power analysis is set this specifies if the method of
analysis is vectorless or vector based.
Disable Static Analysis When selected in the dynamic vector-based or dynamic
vectorless flows, the command performs only dynamic
analysis and turns-off static power calculation.
Running Power Analysis
Run Power Analysis by choosing Power – Power Analysis – Run.
Specify input activity as the average number of times specified that a primary
input switches in a clock cycle. It can be any number between 0 and 1.
The generated report

contains global as well as
specific instance power,
clock network power, clock
domain power, and net
switching power.
Dominant Frequency specifies the dominant frequency of the design.

Flop Activity specifies the activity of outputs of sequential logic.
Clock Gate Activity specifies the average number of times that a clock-gating cell switches in
a clock cycle. Enter any positive number.
VCD File, if selected, activates the fields for entering VCD Information.
Scope specifies the scope of the VCD file.
Start specifies the start time in nanoseconds (ns) of the VCD file that will be used for power
analysis.
Stop specifies the stop time in nanoseconds (ns) of the VCD file that will be used for power
analysis.
Block specifies the block name.
Results Directory specifies the directory where the power analysis output will be placed.
Running Rail Analysis
Running rail analysis will provide you with a map of where your IR drops
are the worst so that you can fix them by modifying the power grid.
Choose Power – Rail Analysis – Early Rail Analysis.
Specify the net name for analysis and

its voltages
Specify the power pad location file which

contains the pad location coordinates for VDD
Running Rail Analysis (continued)
Use the default filter range or update it for the IR display.
Early Rail Analysis and Power Planning
PD2
HM3
HM2
PD1
HM1
Iterate and
Initial floorplan Build power grid
converge
IR/EM analysis
IRD/EM analysis Refine floorplan

and power rail
Lab Exercises
Lab 6-1 Running Power Analysis
Route (Flat)
iSection 3: Detail Routing, ECOs, and Foundation
Flows
Version 10.1
February 3, 2011
Detail Routing for Signal Integrity, Timing,
Module 16
February 3, 2011
Module Objectives
 Define LEF parameters for optimal routing
 Define varieties of vias for better routing results
 Set up optimal routing tracks
 Improve pin access and routing utilization with the use of additional
vias
 Set routing attributes to route specific nets
 Fix antenna violations using the various options and strategies
 Explore clock routing and critical net routing strategies
 Concurrently optimize routing for yield, timing, and signal integrity
 Route the design to prevent and fix lithography violations
 Shield critical nets for signal integrity
Scan
Design Import Add Metal Fill
Post-CTS Flow
Postroute Flow
Routing
Pre-CTS Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
The LEF File: Defining Pitch for Routing
Create a table that shows the line-to-via pitch for each routing layer, based
on information in the LEF file.
LAYER METAL1
TYPE ROUTING ;
WIDTH 0.160 ;
Line-to-via of metal1
SPACING 0.180 ;
# Pitch and OFFSET dictated by the 0.16/2 +0.21/2 + 0.18 = 0.365
STDCELL library image.
PITCH 0.365 ;
VIA via1_h DEFAULT
Y-coordinates
RESISTANCE 6.4000e+00 ; 0.16
LAYER METAL1 ; 0.365
0.18
RECT -0.145 -0.105 0.145 0.105 ;
0.21
LAYER VIA12 ;
RECT –0.095 -0.095 0.095 0.095 ;
LAYER METAL2 ;
RECT -0.100 -0.150 0.100 0.150 ;
END via1_h
The line-to-via distance is a guide to establish optimal pitch. The value of the pitch size must
be equal to or larger than the line-to via-distance in the preferred routing direction.
To find out the line-to-via distance, create a table outlining the layer information. When
measuring the via, you pick the smaller dimension of the metal enclosure.
M1 and M2 are typically governed by the standard cell pins and the cell boundary, which are
designed when the cells are being laid out.
Guidelines: Optimal Routing Tracks and Cell Size
Design the minimum pitch for each metal to be at least line-to-via distance.
Standard cell size recommendations:
 The standard cells height and width should be a multiple of the
horizontal routing grid and the vertical routing grid respectively
 In this example, width of cell = 4 x 0.46, height = 3 x 0.41
minimum pitch
minimum spacing
0.41
Cell boundary is located one half track

0.46 offset so that pins are on track.
When laying out the metal1 pins, ensure they are positioned on a certain pitch and offset
from the cell boundary. Preferably, the metal1 pitch equals the metal3 pitch.
To determine the Vertical pitch criteria

 Find the smallest value that is the multiple of the cell width.
 The value must be equal to or larger than the line-to-via distance.
 The tracks must cross as many pins as possible.
In the illustration, 0.46 is meeting all the vertical pitch criteria.
To determine the Horizontal pitch criteria

 Find the smallest value that is the multiple of the cell height.
 The value must be equal to or larger than the line-to-via distance.
 The tracks must cross as many pins as possible.
In the illustration, 0.41 is meeting all the horizontal pitch criteria.
When you calculate the pitch and offset, you can create or update the PITCH and OFFSET
statements in the LEF file.
Accounting for Vias on Upper Routing Layers
Via enclosures of upper routing layers typically have larger dimensions that
result in larger pitches.
0.20
LAYER METAL5
TYPE ROUTING ;
0.21 0.5
WIDTH 0.200 ; 0. 38
SPACING 0.210 ;
PITCH 0.5 ;
Line to via metal5 = 0.20/2 +0. 38/2 + 0.21 =0.5
DIRECTION HORIZONTAL ;
…
END METAL5 space width via line2via dir
VIA
METAL1 0.18 0.16 0.21 0.365 H
via5 DEFAULT
METAL2 0.21 0.20 0.20 0.41 V
LAYER METAL5 ;
RECT -0.23 -0.190 0.23 0.190 ;
METAL3 0.21 0.20 0.20 0.41 H
LAYER VIA56 ; METAL4 0.21 0.20 0.20 0.41 V
RECT -0.180 -0.180 0.180 0.180 ; METAL5 0.21 0.20 0.38 0.50 H
LAYER METAL6 ; METAL6 0.46 0.44 0.54 0.95 V
RECT -0.270 -0.270 0.270 0.270 ;
END via5
Setting the pitch sizes of the upper layers to the METAL1 and METAL2 pitch might create
some routability problems, because they might not be at least line-to-via distance. Again, the
first thing you want to do is to measure the line-to-via distance for these metal layers.
From the table, the preferred direction of METAL5 must be at least 0.50 µm and METAL6
must be at least 0.95 µm.
Aligning Routing Tracks
Align lower metal layers in their preferred routing direction. Align the non-
preferred direction to the next lower layer.
For upper layers, try to align the tracks at 1.5x, 2x, or 2.5x of the lower track
in the same direction.
line2via dir
METAL1 0.365 H
In this example the following needs to be
corrected, METAL2 0.41 V
 Align METAL1 and METAL3 to 0.41 pitch METAL3 0.41 H
in the preferred (horizontal) direction.
METAL4 0.41 V
 Align METAL5 and METAL6 at 1.5x of
METAL4 by changing the pitches to 0.615
in the horizontal tracks. METAL5 0.50 H
METAL6 0.95 V
For the preferred routing direction, you need to make sure pitches are at least line-to-via
distance. In the nonpreferred direction, they can follow pitches of the lower layer.
Specifying DEF Routing Tracks
Modify the DEF TRACKS file for optimal routing.
METAL5 pitch = 1.5 x METAL3 = 410 x 1.5 = 615
Example
TRACKS Y -468720 DO 21137 STEP 410 LAYER METAL1 METAL2 METAL3 METAL4 ;
TRACKS Y -469260 DO 17935 STEP 615 LAYER METAL5 METAL6 ;
TRACKS X -469260 DO 17935 STEP 460 LAYER METAL1 METAL2 METAL3 METAL4 METAL5 ;
TRACKS X -469260 DO 11957 STEP 950 LAYER METAL6 ;
Bold indicates preferred routing direction
You want to try to make the upper layers aligned to the lower layers as much as possible. This
alignment will help the router in utilizing stacked vias. Too many misaligned tracks will
require more time for the router to decide where to drop vias.
If layer alignment is not possible, you can use some multipliers (1.5X, 2X, 2.5X) of the lower
layer pitch size. However, after multiplying the pitch, if the value is much larger than the line
to via pitch size, then you do not want to use the multiplier.
Generating Routing Tracks
Use the generateTracks command to correct faulty track definitions and
tune tracks for routing.
 Generates new routing tracks based on the first horizontal and vertical
routing pitch, layer width/spacing, and minimum via widths.
 Minimum pitch for horizontal and vertical layers matches the pitch
defined in the LEF for those layers. If the core site width/height does
not match this pitch, a warning message is generated.
 Subsequent layers are created to meet routing half-width + spacing +
min via half-width pitch, which is aligned at 1x, 2x, 2.5x, 3x, ... multiples
of the lower common layer. Nonpreferred layers are aligned to the
preferred routing track of the lower layer.
Example
{...load/restore the design...}
generateTracks
routeDesign
Output of the generateTracks Command
encounter 2> generateTracks
Horizontal Layer M1 offset = 560 (derived)
Vertical Layer M2 offset = 660 (derived)
TRACKS Y 560 DO 2352 STEP 1120 LAYER M6 ;
TRACKS X 2640 DO 1336 STEP 1980 LAYER M6 ;
M1 pitch=1120 (min=970) [970 1120]
M2 pitch=1320 (min=1220) [1220 1320]
M3 pitch=1120 (min=1120) [1120 1120]
M4 pitch=1320 (min=1220) [1220 1320]
M5 pitch=1120 (min=1120) [1120 2240] - - 560 -
M6 pitch=1980 (min=1900) [1900 2640] - - - 660
Rotated Via for Fewer DRC Violations
A rotated via helps reduce Normal Via
violations when connecting
to the pin of a standard
cell.
You can add vias to the
LEF to help the router deal Min space
violation with
with this scenario. normal via
The LEF needs to contain
a variety of via definitions, No min spacing
but, too many vias will METAL1 violation
adversely affect the run
time.
Rotated Via
Many technologies require wire extension of the cut metal enclosures. In a LEF file, you will
typically see that either the horizontal or the vertical segment of the metal enclosure
dimension is longer. Unfortunately, there might be some pins that cannot be accessed with this
via definition, because the NanoRoute® router will not rotate the via automatically. This can
cause numerous METAL1 violations.
To solve this, you need to specify a rotated via with the wire extension in the opposite
segment. This will help reduce the number of violations, because the router will have more
via choices for avoiding violations.
Hammerhead Via
Most technologies use a
via resembling a cross
shape. You can add a A hammerhead via allows line-
hammerhead via if the to-via and via-to-via routing.
pitch allows enough
space.
0.41
The NanoRoute router
can place hammerhead
vias on adjacent tracks. 0.21 0.15
0.46
In this case, due to the 0.46 µm pitch, you can take advantage of having a hammerhead via
(both metal layers in the same direction). This via type allows line-to-via in the vertical
direction, and via-to-via in the horizontal direction. This hammer head via is preferred to the
cross via. The cross via allows line-to-via routing in the vertical direction, but won’t allow
via-to-via routing.
Including Multicut Vias for Yield Improvement
Usually this set of 8 double-cut vias in different orientations is good for getting a reasonable
percentage of double-cuts in the design. Typically defining many more vias may improve the
double-cut percentages marginally but will have a huge impact on run time.
We see a high percentage of double-cut vias for layers VIA2 and above (~90%). For the VIA1
though it is about 60% due to the complex nature of the rules at 90 nm and below. Good
library design can help achieve a higher percentage of double-cut via usage for VIA1.
Log File Up-Via Summary
#Total number of vias = 129276 #Total number of vias = 192165
#Up-Via Summary (total 129276): #Total number of multi-cut vias = 192165 (100.0%)
# #Up-Via Summary (total 192185):
#----------------------- # multi-cut Total
# Metal 1 76171 Library with no
#-----------------------------------------
# Metal 2 52273 multicut via # Metal 1 77939 (100.0%) 77939
# Metal 3 687 # Metal 2 86744 (100.0%) 86744
# Metal 4 145 # Metal 3 26115 (100.0%) 26115
#----------------------- # Metal 4 1367 (100.0%) 1367
# 129276 #-----------------------------------------
# 192165 (100.0%) 192165
#Total number of vias = 4232169

#Total number of multi-cut vias = 2799560 ( 66.1%) Library with
#Total number of non-fat single cut vias = 1432609 ( 33.9%) multicut via only
#Up-Via Summary (total 4232169):
# single-cut multi-cut Total
#-----------------------------------------------------------
# Metal 1 823940 ( 55.0%) 673502 ( 45.0%) 1497442
Library with both
# Metal 2 366424 ( 20.7%) 1405834 ( 79.3%) 1772258
single-cut and
# Metal 3 159853 ( 24.9%) 480969 ( 75.1%) 640822
multicut vias
# Metal 4 54559 ( 22.8%) 184979 ( 77.2%) 239538
#-----------------------------------------------------------
# 1432609 ( 33.9%) 2799560 ( 66.1%) 4232169
Optimizing Routing
The NanoRoute® software can route to off-grid pins and effectively route
designs with routing tracks that are not optimal.
You can speed up the routing process by ensuring the following:
 Libraries are designed with pins on the routing grid
 Lower level routing layers align with standard cell pins
 Upper level routing layers align
 With lower layers as much as possible
 As a multiple (1.5x, 2x, 2.5x) of adjacent layers
 Libraries contain rotated vias for better pin access
Setting NanoRoute Modes: Route
Choose Options – Set Mode – Mode Setup to set NanoRoute modes.
During ECO mode, the NanoRoute® router

completes partial routes with added logic,
while maintaining the existing wire segments
as much as possible.
Select Route Selected Nets Only to specify whether the NanoRoute® software routes all nets
at once or only routes selected nets. Select the critical nets and select this option in order to
route critical nets as short as possible.
Select the Automatically Optimize GCell Grids to help resolve congestion and over-the-
macro violations if you see routability issues due to hot spots.
Select Search And Repair Only to run a search-and-repair step. During search and repair, the
router locates shorts and spacing violations and reroutes the affected areas to eliminate as
many of the violations as possible. You must have already run detailed routing before running
search-and-repair.
Setting NanoRoute Modes: Timing and Signal Integrity (SI)
A higher value increases effort

for timing and decreases effort
for congestion.
Select Timing Driven to minimize timing violations by analyzing the timing slack for each
path, the drive strengths of each cell in the library, and the maximum capacitance and
maximum transition limits. During timing-driven routing, the NanoRoute® software routes
multipin nets to the most critical sink first, performs wire optimization by reducing resistance
and coupling, and continually adjusts detouring.
Select the routing effort to specify how aggressively the router works to meet timing
constraints. A higher value increases the effort to meet timing constraints and decreases the
effort to relieve congestion.
Select CTE to specify the Encounter® common timing engine for timing analysis.
Select SI Driven to prevent or to reduce crosstalk.
Select Post Route SI Fix after you run routing and signal integrity analysis.
This option uses information from a file that contains a list of victim nets to change the
routing topology, including layer assignments, spacing, and location, to prevent coupling to
other nets. Specify the file that contains the list of nets with crosstalk problems and therefore
needs to be rerouted in the Use SI Victim File field. Postroute signal integrity repair requires
both global and detailed routing.
Setting NanoRoute Modes: DFM
Multicut vias can be
inserted concurrently or can
be optimized as a postroute
function.
Select Swap Via to swap single-cut vias for multiple-cut vias, or vice versa.
Turns on postroute wire spreading by selecting the Spread Wire option. In the Minimum
Length field, enter the minimum length for wires to move.
Select Widen Wire to turn on postroute wire widening. Selecting this option might increase
the overall routing run time, but helps avoid yield loss caused by opens.
Select Widen Wire Rule to specify the nondefault rule for widening wires. The rule is
specified in the LEF file.
Setting NanoRoute Modes: Antenna
The router repairs process antenna violations if it can do so without creating
DRC violations. The router might need to make several passes before
repairing all antenna violations.
Select the Insert Diodes option to insert and place antenna diode cells during postroute
optimization if there are available placement locations for the cells. By default, the
NanoRoute router repairs antenna violations by changing layers (also called antenna stapling
or layer hopping), but it can also repair antenna violations by inserting diodes as closely as
possible to input gates to discharge current.
Setting Attributes
Select Route – NanoRoute – Specify Attribute to open the
attributes window.
When you set attributes for nets, the NanoRoute software routes the
design according to the attributes you set and saves the attributes with the
database. To repair SI violations on a specific net, run the following
commands: setAttribute -net net1 -si_post_route_fix true
setNanoRouteMode -routeWithSiPostRouteFix true
routeDesign
The menu choices correspond to the setAttribute command in the Encounter window.
To retrieve the attributes of a net, use the getAttribute command.
Route certain nets first (typically critical) by choosing the
Route – NanoRoute menu command. Then select the nets and turn on Selected Nets in the Job
Control section of the menu.
Use selectNet <netName> in the csh Encounter window to select a net in the design.
Enter one net name or specify more than one net using the * and ? wildcards. When ASIS is selected,
the router retains the current setting of the attribute. You can use up to 254 nondefault rules with the
NanoRoute software.
 External Nets
Selects all nets with external pins.
 Critical Nets
Selects all timing-critical nets.
 Weight
The default value is 2.
 Spacing
Number of tracks 0 to 3
 Pattern specifies the routing pattern.
Steiner Minimizes net length.
Trunk Minimizes delay for global nets.
Clock Net and Critical Net Routing Strategy
Clock Nets
The following attributes are set automatically if clock nets are marked USE CLOCK
in the DEF file or if you have defined a clock net in the Encounter database and
SI Prevention is turned on:
 Net weight for clock nets is 10 to give clock nets priority during global routing.
(The default net weight for other nets is 2.)
 Avoid Detour is set to True for clock nets, so they are routed as straight as
possible.
 Spacing to 1 extra, which adds one track of spacing around the clock nets to
improve coupling capacitance.
Critical Nets
For timing critical nets and nets connecting to external pins, set the following
attributes:
 Avoid Detour to True, Net weight to 5, Spacing to 1
 Spacing does not guarantee extra spacing. If the design has highly congested
areas, the router might not be able to provide extra spacing
For clock nets, you can add shielding for additional signal integrity (SI).
Postroute optimization will not touch clock nets.
You can choose to route clock nets by themselves first before routing the other nets.
Router Options
Choose Route – NanoRoute – Route to

display this form.
Litho Driven routing avoids lithography problems during

routing by avoiding certain routing patterns that might lead to
the creation of lithography hotspots.
Post Litho Repair corrects bridging, necking, and line-end
shortening problems caused by lithography. Prior to running the
router with this parameter, import a hotspot interface format
(HIF file) with the loadViolationReport command or by using the
Load Violation Report form.
Options that are selected are not saved with the database, so you must reset them for
subsequent runs.
The router can swap filler cells with antenna diode cells and fill the gap automatically if the
antenna diode cell is not the same size as the filler cell it replaced. To specify a list of filler
cells that can be deleted, run routeReplaceFillerCellList. To specify a list of filler cells to re-
insert if the antenna diode cell is smaller than the filler cell it replaced, use
routeReInsertFillerCellList.
 Global Route runs on the entire design area.
 Detail Route can route the design, an area, or selected nets.
Select the SI Driven option to prevent or reduce crosstalk. Works in conjunction with
timing-driven routing.
When Timing Driven is selected, the router uses SMART routing to identify victim nets and
minimize crosstalk by wire spacing, layer hopping, net ordering, and minimizing the use of
long parallel wires.
Select Post Route SI after routing and signal integrity analysis. NanoRoute SI fixing uses
information from a file that contains a list of victim nets. The router changes the routing
topology, layer assignments, spacing, and location to prevent coupling. Postroute signal
integrity repair requires both global and detailed routing. Specify the file name in the SI
Victim File field.
Antenna Fixing
Approach Rationale Impact M3
M2
Layer Top metal Longer routes M1
Hopping completes More RCs Poly
connection More congestion N+ N+ FOXN+ N+
p-substrate
Net diode Discharge Added capacitance Cell A M2
Cell B
insertion path through Area penalty M1
diode LVS (new cell) Poly
longer routes(Place N+ N+ N+ N+ N+
and route to diode) Diode Cell p-substrate
M2
Cell A Cell B
M1
Diode in Cell Added capacitance, Poly
cell protected by Area penalty N+ N+ N+ N+ N+
construction Diode p-substrate
Layer Hopping
The idea is to distribute the charge in the different metal layers versus one long route in a
single layer. It works because the last metal layer will always make the connection between
the diffusion and the gate. Therefore, the charge will be discharged through the diffusion. The
problem is that layer hopping will result in longer routes and more vias, causing more
congestion and an increase in RCs.
Net Diode Insertion
The idea is to provide a path other than the transistor gate for the charge accumulated to get
discharged. This is done by adding a diode cell. The addition of the diode cell occurs after
placement and during routing. Therefore placement of the diode close to the input pin
(transistor gate) many times is not possible. This will result in more placement density,
congestion, increase in net parasitics, increase in parasitics due to input capacitance of the
diode and LVS considerations handling the new cell in the netlist.
Diode in Cell
The idea is to provide a path other than the transistor gate for the charge accumulated to get
discharged. This is done by adding a diode inside the cell close to the input pin. It has to be
done during library development. It increases the area of the cell and increases the input pin
capacitance of the cell.
Antenna Repair
The routing engine can perform several operations concurrently, including antenna repair,
timing-driven routing, signal-integrity-driven routing, and timing optimization.
 Antenna repair uses layer hopping by default.
 Diode insertion is enabled when Fix Antenna is selected.
 Select Insert Diodes to define the Diode Cell Name of the cells to insert.
 By default, the NanoRoute engine searches the LEF file and inserts the first MACRO
with CLASS CORE ANTENNACELL it finds with the appropriate SITE definition.
setNanoRouteMode -drouteFixAntenna true

setNanoRouteMode -routeAntennaCellName “antenna"
setNanoRouteMode -routeInsertAntennaDiode true
The NanoRoute engine can insert antenna diode cells, even if filler cells are already placed.
The routeDesign Command
To run timing- and SI-driven global and detailed routing, run the routeDesign
command without any options:
routeDesign
To run timing- and SI-driven global routing only, enter the following command:
routeDesign -global
To run nontiming-driven global routing, enter the following commands:
setNanoRouteMode -routeWithTimingDriven false
routeDesign -global
To run timing- and SI-driven detailed routing, enter the following command:
routeDesign -detail
To run timing- and SI-driven global and detailed routing, enter the following
commands:
routeDesign –globalDetail
To interrupt the routeDesign command run, press Control–C. This is useful if you
want to stop the run to analyze the data at various stages of routing and not having
to wait until the route completes.
Signal-Integrity-Driven Routing
The SI Driven option creates routes with reduced coupling capacitance by
spreading adjacent wires.
Use the Post Route SI option after running routing and SI analysis. You specify a
victim file created by the CeltIC® nanometer delay calculator (NDC) or another
crosstalk tool.
The router reduces coupling by:
 Spreading wires apart
 Re-ordering nets
 Changing metal layers
Note: The Post Route SI option applies to nets with the attribute SI Post Route
Fix set to true.
Text Command
setNanoRouteMode
[routeWithSiDriven {true | false}]
[routeWithSiPostRouteFix {true | false}]
Yield Optimization: Postroute Wire Spreading
Postroute Wire Spreading
Syntax
setNanoRouteMode –droutePostRouteSpreadWire true
Default: 2 µm
When doing wire spreading, you can use the following option to control the effect on timing:
setNanoRouteMode -drouteMinSlackForWireOptimization <slack>
Default: 0.0 ns
By default, if a pin slack or neighboring pin slack is less than a certain value, then the
associated net is not spread.
To implement wire-spreading in nontiming-driven mode set, use this command:
setNanoRouteMode –routeWithTimingDriven false
Example
setNanoRouteMode -drouteMinSlackForWireOptimization 0.2
setNanoRouteMode -droutePostRouteSpreadWireRule true
routeDesign -wireOpt
The routeSelectedNetOnly and setAttribute -net <net_name> -skip_routing true will be

honored.
Preventing Shorts: Wire Spreading
Postroute Yield Optimization: Wire Widening
The NanoRoute software can widen wires where resources are available,
without adding DRC and antenna violations or affecting timing. Wire
widening uses NONDEFAULT rules. When widening a wire, you can use
the following commands to control the effect on timing:
setNanoRouteMode -drouteMinSlackForWireOptimization
<slack>
Default : 0.0 ns
If a pin slack or neighboring pin slack is less than a certain value, then
the associated net will not be spread.
setNanoRouteMode -droutePostRouteWidenWireRule ruleName
setNanoRouteMode -droutePostRouteWidenWire widen
After setting the mode, then run:

routeDesign –wireOpt
Preventing Opens and Shorts: Wire Widen and Spread
Wire Widening
Wire Widening and Spreading
Shrink Widened Wires Back to Min Width
Timing Aware
Timing is based on the following global variable setting:
setNanoRouteMode -drouteMinSlackForWireOptimization <value_in_ns>
If nondefault wires are used and they cause a timing violation, then the
–dRoutePostRouteWidenWire shrink variable will shrink back to minimum
width to meet timing.
Commands
setNanoRouteMode -drouteMinSlackForWireOptimization slack
setNanoRouteMode -droutePostRouteWidenWireRule ruleName
setNanoRouteMode -droutePostRouteWidenWire shrink
routeDesign -wireOpt
NanoRoute: Multi-Cut and Single-Cut Via Swap
NanoRoute supports double-cut via swap and single-cut via swap.
The routeDesign –viaOpt command runs via optimization by automatically setting
droutePostRouteSwapViato multiCut and drouteMinimizeViaCountto true.
Timing Driven
You can implement multi-cut via swapping in as follows:
1. Concurrent swap
setNanoRouteMode -drouteUseMultiCutViaEffort low | medium | high
routeDesign -viaOpt
2. Postroute Via Reduction

setNanoRouteMode -drouteMinimizeViaCount true
routeDesign -viaOpt
3. Postroute single-cut via to multiple-cut via swap.

setNanoRouteMode -droutePostRouteSwapVia multiCut
routeDesign -viaOpt
NanoRoute: Via Minimization
Vias have an impact on routing resources and you can choose the level of via
minimization that you want to implement by choosing the amount of time that the
tool will spend on this task.
Syntax
setNanoRouteMode -routeConcurrentMinimizeViaCountEffort
low | medium | high
 The current default setting is low.
 The medium effort will result in about ~15% via reduction with minimal run
-time
overhead
 High effort will result in about ~20-25% via reduction with some run-time
overhead.
Lithography Challenges
Exposing 193 nm wavelength
of light for 65 nm geometry
size results in a mismatch Layout 0.25 µm 0.18 µm
between the layout and
printed geometry.
The following are some of the
lithography problems:
 Bridging 0.13 µm 90 nm 65 nm
 Necking
 Line-end
Layout Silicon Image
Decreasing feature size

When the feature size is greater than the wavelength, correct polygon shapes can be drawn
easily. As the feature size becomes subwavelength, there are other effects. Light penetration
through a mask can result in interference. This interference can be constructive (RET:OPC,
phase shifting) or destructive, creating uneven polygons depending on the surrounding
geometries.
Lithography Effects for a Router
 A conservative design rule methodology impacts die size.
 The complex relationships of multiple objects compound the
complexity.
 A concurrent solution, such as double cut optimization, is a
requirement.
Double
cut
Original layout Retarget Model-based OPC Simulated
Why is it difficult to use design rules to address lithography effects completely?

The relationships between multiple objects compound the complexity of design rules in
representing lithography effects.
 Traditional routers understand the relationship between two objects. However, the router
needs to take into account the complex effects of lithography on multiple objects.
 Conservative methodologies to address complex configurations lead to hard or preferred
rules, but these rules impact die size by forcing the router to add extra spacing globally,
resulting in greater congestion.
For example, one problem with postroute via optimization is that it can be too
conservative and too late.
Therefore, local context-based spacing is necessary.
NanoRoute Lithography Fixing Flow
restoreDesign FE_DB/prerouted.enc.dat TOP
setNanoRouteMode -envNumberProcessor 2
Prerouted DB
### SMART routing and litho prevention options ###
############################################
setNanoRouteMode -drouteUseMultiCutViaEffort high
NanoRoute setNanoRouteMode -routeWithTimingDriven true

setNanoRouteMode -routeWithSIDriven true
Litho Prevention setNanoRouteMode -routeWithLithoDriven true
## Set Super Threading ###

setNanoRouteMode envSuperthreading "RSH { \
{ host1 2 path/nanoroute } \
Litho Process Check { host2 2 path/nanoroute } \
{ host1 2 path/nanoroute } \
Hotspot file { host2 2 path/nanoroute } \
}"
routeDesign
Hot spot?
saveDesign FE_DB/routed_lithoAware.enc
exit
NanoRoute
Litho Fixing
Incremental LPC
Hotspot file
With NanoRoute software, lithographic variation can be addressed along with other design
constraints, such as DRC, timing, SI, power, yield.
NanoRoute Lithography Fixing
Select Tools – Violation Browser
In the postroute flow, you can load the litho violation like the other DRC violations, such as
spacing and connectivity violations.
NanoRoute Lithography Fixing
Lithography violations appear in the browser, just like any other violation. You can fix these
litho violations with the NanoRoute software.
Syntax
setNanoRouteMode -droutePostRouteLithoRepair true
Example Command Sequence
setNanoRouteMode -droutePostRouteLithoRepair true
loadViolationReport -type CDNLitho -filename <f.hif>
detailRoute
Litho Hot Spot Fixing
Hot Spot Fixing is accomplished with minimal:
 Routing disturbance
 Impact on timing
CASE 1
CASE 2
Original Fixed Overlay

Notice that there is a necking problem due to double cut vias that surround a piece of metal.
The router fixes the violations by flipping the double cut vias or by changing them to single
cut vias. After overlaying the two layouts together, you can see that the change is very
minimal.
Shielding Features
Shielding supports shared shielding and power rail shield.
 The NanoRoute software reserves the adjacent track to the shielded
net to add shield wires without actually adding any shield wires if you
set the preferred extra space to 1.
 When a shielded net is routed next to a P/G stripe, the router uses that
P/G stripe as the shield wire on one side.
 The router allows overlapping of the reserved adjacent track for
shielded nets; that is, it shares the shield wires between different
shielded nets.
 At the end of the entire routing, the shield wires are created. Shield
wires might be dropped for segments of net(s) passing through
congested areas.
 For any incremental routing, the router removes all the shield wires
and recreates them at the end of the routing.
Demo: Creating Shielding
Shielding Example
Define commands and options
createShield
deleteShield
setNanoRouteMode –routeDeferredShield [true|false] default false
setNanoRouteMode –drouteAutoCreateShield [true|false]default true
Default Use model

setAttribute –net CLK –shield VDD
setNanoRouteModerouteDeferredShield true (default) Creates shield wires automatically
routeDesign when you run the routeDesign command..
Optional Use model

setAttribute –net CLK –shield VDD
setNanoRouteMode routeDeferredShield true
setNanoRouteMode drouteAutoCreateShield false
routeDesign
createShield Will only route shield after you run the
createShield command.
Autotuning Routing Options
You can tune the detail router options automatically for advanced notes by
running the following command:
setNanoRouteMode –routeAutoTuneOptionsForAdvancedDesign true
This option results in improved:

 Performance
 Multi-cut via addition
Lab Exercises
Lab 7-1 Routing Critical Nets with Shielding and Spacing
 Setting Shielded and Spacing Net Attributes
 Routing the Nets
Evaluating Routing Problems
Module 17
February 3, 2011
Module Objectives
 Run the LEF rule checker to check if there are problems
 Report DRC violations in cells
 Explore the iteration steps of the detail router flow
 Run the Trial Route and Global Route congestion displays
 Analyze log files and congestion maps that highlight routing violations
 Fix violations with search and repair
Checking the LEF File
As the technology rules become more complex, it is necessary to have the
Encounter® software check the rules for issues and output the results.
Syntax
setNanoRouteMode -dbCheckRule true {true | false}
Example of command output:
Debugging Cell Issues
 You can quickly isolate a specific cell or routing issue to debug
potential problems
 Run the following command to print a table of results listing each cell
master and the number of violation of each cell
Command:
pdi report_design –violation
Output:
Cell M1 M2 M3 M4 M5 #inst avg/inst
nand4 3 0 0 0 360 0.02
inv6x 2 0 0 0 30 0.06
flop 120 26 3 0 0 400 0.31
Testing LEF Rules
There are complex rules that are defined in the LEF file. Examples of the
rules have been provided in the Appendix titledNanometer Design Rule
Support.
If you want to debug a problem in the LEF or if you want to filter out a
selection of rules without modifying the LEF file, you can run the following
command:
setNanoRouteMode -dbFilterRules "[ none | enclosure |
minimumcut | minstep | minarea | eol | adjacentcut |
spanrule ]”
 None - Don't filter out any rules
 Enclosure - Filter out enclosure rules.
 Minstep - Filter out and minstep rules.
 Minimumcut - Filter out minimumcut rules.
 Adjacentcut - Filter out adjacent cut rules
 Eol - Filter out EOL rules.
 Spanrule - Filter out span length rules.
Basic Routing Strategy: Iteration Steps
 Run global route.

globalRoute
 Save the design for congestion analysis
saveDesign groute
graphically.
drouteStartIteration 0
 Initial detail route
drouteEndIteration 0
 Iteration 0 does not search and repair.
detailRoute
 To route a net, set the iteration to 0
saveDesign droute0
 1st search and repair iteration drouteEndIteration 1
 Save the design for analysis. detailRoute
SaveDesign droute1
 2nd – 19th search and repair iterations drouteStartIteration 2

 The switch box grows as the iteration drouteEndIteration 19
number grows. detailRoute
 Save the design for analysis. saveDesign droute19
drouteEndIteration default
 20th search and repair iteration
detailRoute
saveDesign droute
The basic routing strategy in the NanoRoute engine is to save and analyze at certain stages for
any possibility of problems.
 Global routing
Check the congestion map. If you have hot spots with lots of red, magenta, and white, the
design might be unroutable.
 Initial detailed routing
See if you have unbalanced number of routing violations. Lots of m1 and m2 violations
are an indication that there might be something wrong with the standard cell pin access,
such as off-grid pins, incorrect m1 and m2 tracks settings, overlapping cells, etc.
 1st iteration of search and repair
Check whether the violations are decreasing compared to the initial detail routing. If they
are not decreasing, then there might be problem with the data.
 19th iteration of search and repair
See if there are still a large number of violations (1000s) or an unbalanced distribution of
violations. This might be an indication of a congested design or a data problem.
 20th to postoptimization
This is the most costly in terms of time, but is a powerful step. You only want to do this
when you know the data and library are clean. Otherwise, the router will spend too much
time trying to search and repair unresolvable violations.
Congestion Map GUI and Display
The congestion maps from the TrialRoute and NanoRoute routers are
displayed differently in the Encounter Digital Implementation system.
Trial Route displays overflow in diamond or line style, while the
NanoRoute interface displays in vertical/horizontal overflow at gcell
edges.
Trial Route view
NanoRoute
GlobalRoute view
Interpreting the Congestion Analysis Table
NanoRoute congestion analysis table from the encounter.log file.
# Congestion Analysis:
#
# OverCon OverCon OverCon OverCon
# #Gcell #Gcell #Gcell #Gcell %Gcell
# Layer (1-2) (3-4) (5-6) (7-17) OverCon
# -------------------------------------------------------------------------------------------------------- Worst case
# Metal 1 1625(2.35%) 34(0.05%) 0(0.00%) 0(0.00%) (2.40%) on Metal2
# Metal 2 11546(16.7%) 6353(9.19%) 4728(6.84%) 3787(5.48%) (38.2%)
# Metal 3 8500(12.3%) 904(1.31%) 37(0.05%) 1(0.00%) (13.7%)
# Metal 4 14951(21.6%) 764(1.11%) 20(0.03%) 0(0.00%) (22.8%)
# Metal 5 8473(12.3%) 37(0.05%) 0(0.00%) 0(0.00%) (12.3%)
# Metal 6 854(1.24%) 0(0.00%) 0(0.00%) 0(0.00%) (1.24%)
# --------------------------------------------------------------------------------------------------------
# Total 45949(11.1%) 8092(1.95%) 4785(1.15%) 3788(0.91%) (15.1%)
#
# The worst congested Gcell OverCon (routing demand over resource in number of tracks) = 17
Note: Overflow or OverCon = (Demand – Supply) per Gcell
Interpreting the Congestion Analysis Table (continued)
 Read the table horizontally to see the distribution and percentage of
gcells on each layer that have a greater demand for tracks than they
have supply of tracks.
 Read the table vertically to see which layers have the most
overcongested gcells and how severe the congestion is.
 The table does not show how closely the overcongested gcells are
clustered. Look at the congestion map in the GUI to see clusters of
congestion and their exact location.
 There is no "magic number" that determines whether the design is
routable. In general, the more columns, and the more the percentages
increase toward the right side of the table, the worse the congestion.
 Rule of thumbs (excluding the pin access layer) :
 Total % of overCong < 2%  is easy to route
 Total % of overCong between 2% and 6%  will be difficult to route
 Total % of overCong > 6%  will have high number of DRC violations
Violation Trends
#start 19th optimization iteration ...
# completing 10% with 98611 violations
# completing 20% with 98648 violations Steps
…
 Run the search and repair
# completing 100% with 98663 violations
up to the 19th iteration.
# number of violations = 98663
#Complete Detail Routing.  Check the log file on which
#Total wire length = 559006793 um. layers the violations occur.
#Total half perimeter of net bounding box =
471147199 um.  Check the violations
#Total wire length on LAYER MT1 = 18600362 um. graphically if there are lots
… of violations (>1000).
#Total number of vias = 31662170
#Total number of vias on LAYER MT1 to MT2 =
11200471
…
#Total number of DRC violations = 98663
#Total number of violations on LAYER MT1 = 61945
…
Run the design and observe the number and type of violations after several search and repair
iterations. In the above example, the search and repair is stopped and saved at the 19th
iteration. If the number of violations are large (thousands), and the violations do not quickly
decrease, stop the run and check the violations graphically.
Often violations are not congestion problems, but rather design or library problems like the
following:
 Cells are overlapping, making the pins short each other.
 Pins are buried underneath power routing, which make them inaccessible.
 The tracks are not properly defined.
 The LEF does not have via rotation choices to access certain pins.
Violations: Incorrect Track Offset
These views show the results of
incorrect offset for routing layers.
The example below is the correct
H: 6.4 offset for this design. VerifyTracks
will show you pins that are off-grid.
0.8 LAYER m1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
W: 1.8 PITCH 0.8 ;
0.9 Incorrect offset OFFSET 0.4 ;
WIDTH 0.32 ;
SPACING 0.32 ;
END m1
LAYER m2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.9 ;
OFFSET 0.45 ;
WIDTH 0.4 ;
SPACING 0.4 ;
END m2
Off-grid pins
The most important thing in achieving optimal routing results is the correct setup of m1 and
m2 routing tracks. Make sure those tracks are set based on the pitch of the pins. In the
example above, the pitches for m1 and m2 are set correctly, 0.8 and 0.9 respectively. They are
also multiples of cell height (6.4) and width (1.8) respectively. The offset is set to ½ of the
pitch for these layers.
Violations: Imbalanced Layer Distribution
After the 19th iteration of search and repair:
#Total number of DRC violations = 1426
#Total number of violations on LAYER Metal1 = 876
Assessment
 Too many m1 violations
 Some m2 and m6 violations
Potential issues
 Cell overlapping
 Off-grid tracks
 Cell underneath power routing
 Not enough via rotation
 m6 pitch < line-to-via distance
Route the design through several search and repair iterations. You want to save the design at
that point, and check the violations distribution. When you see a distribution as in this
example, something is wrong. There are many m1 violations. Also there are a large number of
m2 and m6 violations.
Zoom in to those violations and determine if they are due to congestion or data problems.
Violations: Upper Metal Layers
LEF:
…
LAYER Metal6
TYPE ROUTING ;
PITCH 0.46 ;
WIDTH 0.2 ; m6 line to via
SPACING 0.21 ; = ½ W + S + ½ Via
…
END Metal6 = 0.1 + 0.21 + 0.19 = 0.5
…
VIA via6 DEFAULT
LAYER Metal6 ;
RECT -0.19 -0.23 0.19 0.23 ;
LAYER Via6 ;
RECT -0.18 -0.18 0.18 0.18 ;
LAYER Metal7 ;
RECT -0.29 -0.2 0.29 0.2 ;
RESISTANCE 0.68 ;
END via6
DEF:
TRACKS X –4749270 DO 6324 STEP 460
LAYER Metal6
Should be 500 to
match 0.5 line to
via spacing
Via-to-wire violation
Potential issue
m6 crisscrossing
violation  m6 pitch < line-to-via
You also need to check violations on the upper layers. These layers are typically used to route
on top of macros where there are only a few routing layers allowed. Furthermore, these upper
layers typically have larger vias.
When the routing pitch is not set to the line-to-via distance, there are two possible problems:
 Numerous via-to-wire violations
 Numerous crisscrossing violations
If these problems happen, you can change the TRACKS statement to have at least a line-to-
via STEP.
Highly Congested Design and Pin Access
There are hot spots (reds, magentas, and whites), around the corner of a block and in the
middle of the chip, which the router cannot resolve. Problems in this design include:
 Limited pin access to the macro block
 Congestion around the corner of a macro and in the middle of standard cells
Violations: Nontiming-Driven Versus Timing-Driven
Nontiming-driven Timing-driven
Timing-driven routing can force critical nets to go through narrow channels,

causing numerous violations and significantly increasing run time.
Violations: Nontiming-Driven Versus Timing-Driven (continued)
Nontiming-driven Routing channel

Timing-driven
These critical paths/nets are The same critical paths/nets
detoured around the block to are forced into the channel
avoid DRVs. causing congestion, which
increases DRVs and run time.
This type of violation might require a different placement of blocks

to resolve congestion and still meet timing.
In these examples, the nontiming-driven run detours those critical nets to avoid DRVs. When
the timing-driven option is on, the timing analysis declares those nets as critical. The router
forces those nets to be routed as short as possible, thereby creating congestion through the
channels in between the two large macros or blocks.
If there are too many critical nets routing through the channel, the channel will be overly
congested. Eventually, fixing the DRV takes precedence, and some of those nets have to
detour. However, this process will take more time, so the run time might increase
significantly.
Routing: Area Search and Repair
setNanoRouteMode
To test the violations, use small
iteration numbers. -drouteStartIteration 1
-drouteEndIteration 3
When the violations are caused by a data problem, you don’t have a chance to fix them. Using
the default settings, -droutestartiteration in default mode and -drouteenditeration in default
mode will cause the router to go through its normal search and repair iterations, 1-20 and
postoptimization. To avoid this, set the search and repair to some reasonable numbers, so you
don’t have to wait for a long time.
Other Methodologies to Fix Routing Violations
Following the violations guidelines in this section will help get you closer to
a successfully routed design. If violations still exist, other options include:
 Use the editDeleteViolations command to remove violating nets.

You can then use routeDesign -globalDetail to reroute the design.
 Use additional antenna repair options or the Wire Editor to fix antenna
violations.
 Redo placement in cases where corners near blocks or channels

between blocks are constrained for routing. Ensuring that blocks are
placed in corners and near boundaries helps to ease core congestion.
 Evaluating global congestion throughout the design. If congestion is

not localized, you might need to go back to floorplanning and expand
the design.
Wire Editing
Module 18
February 3, 2011
Module Objectives
 Route regular, shielded, and nondefault wires using the wire editor
 Create and replace vias on a route
Wire Editing
Customize the power and signal wires in your design interactively using
bindkeys, icons, and the Edit Route form. To edit signal wires, you can use
these options:
 Add wires
 Cut wires
 Move wires
 Change the wire to another layer
 Delete wires
 Merge wires
 Add vias
 Force wires to use specified widths
 Supports LEF/DEF 5.6 for 45-degree RDL routing

 Connects polygon or 45-degree special routes on same layer
 Adds 45-degree wires one at a time
 Supports the following operations:
Moving wires (non-connectivity based)
Deleting wires
Copying wires only special wires (no signal wires!)
Changing layers
Power Wire Editing
For power wires, you can use all of the options for signal wires, as well as
these additional actions:
 Trim selected wires
 Split selected wires
 Merge selected wires
 Duplicate selected wires
 Change wire width
 Fix wires wider than the maximum width
 Change vias
Selecting Nets to Edit
Select Edit – Wire – Edit.

Use the Nets tab to list nets
or read in a net file for editing
routes.
The e bindkey also opens this
form.
The order of the net names determines the drawing arrangement of the wires
(left to right for vertical and top to bottom for horizontal).
When reading in a net file, make sure the file contains one net name per line.
Net names for a bus must be listed as individual net names.
The Force Regular button allows the creation of signal nets even if power/ground nets are
being edited.
Demo: Editing Wires
Drawing Bus Routes
Use the Route tab to enter
the horizontal and vertical
metal layers to draw on, and
the uniform metal width and
spacing (in microns).
The Drawing wire field

defines which net from the
Nets list is the reference net
for drawing an array.
In the Drawing wire field, for horizontal wires, a value of 1 indicates the bottommost net. For
vertical wires, a value of 1 indicates the leftmost net.
This net is also used as the reference net when changing direction. All other nets around this
net are lengthened or shortened accordingly.
The Arrow increment field is a measure of microns used when drawing a wire.
Editing Route Icons
Clear
Change Duplicate Merge DRC
Layer Wires Wires Markers
Change Split Trim Fix Wires

Width Wire Wire Wider Than
Max Width
Shielding and Snap
The Shielding tab lets you add The Snap tab lets you specify
shields to specific sides of nets how new or changed wires
and between adjacent wires. snap to pins or to existing wires
and whether they snap to a
routing track.
Bindkeys Used in Add Wire Mode

d — Changes the added wire to the layer below the current layer.
u — Changes the added wire to the layer above the current layer.
Control w — Deletes the last segment created in the design area. This lets you remove one
segment of the route at a time.
Esc — Removes the entire route you have drawn.
Single mouse click — Ends the wire segment.
Double mouse click — Ends the wire segment.
Via Tab and Special Route Options
Use the Via tab to control the location

and stacking depth of vias.
The Options button on the Edit Route

form opens the Special Route
Options form to check DRCs and to
control the stacking depth of vias or
the layers used in special route mode.
Miscellaneous and Special Route Options
Use the Misc tab to control

the order of busses at turns
and to define special route
endpoints. The Move wires
with block option keeps
connection intact when a
block is moved.
Select one of the following Shape attributes for each wire created in draw mode:
 None
 RING
 STRIPE
 FOLLOWPIN
 IOWIRE
 COREWIRE
 BLOCKWIRE
 FILLWIRE
 PADRING
 BLOCKRING
 DRCFILL
Selecting and Deleting Routes
Use the delete icon or the d
bindkey to bring up the
Select/Delete form.
Via Creation
 Create a via array with the
Geometry option.
 Add a default via with the
Viacell option.
 To bring up the Edit Via form
select the Add Via icon and
press F3.
setViaEdit
[-create_by {Geometry | Viacell}]
[-auto_snap {0 | 1}] [-cut_layer cut_layer] [-x_space width] [-y_space
length] [-cols integer] [-rows integer] [-x_size width] [-y_size length]
[-x_topenc width] [-y_topenc length] [-x_botenc width]
[-y_botenc length] [-viacell cellname]
The editAddVia [x y] command:
 Creates new via at the specified coordinates.
 Parameters are specified with setViaEdit.
Selecting Vias and Editing Properties
 You can select, edit,
and delete vias.
 You can modify via
properties with the
Attribute Editor.
 Easy to select and
delete a via.
Changing Vias
To replace a selected via with another via in the design that has the same
LEF rule, follow these steps:
1. Turn on Auto Query mode and make sure that the main window is
active.
2. Place the cursor above the via to change. Then press the n or p
bindkey to select the correct via if multiple vias exist in the same
location on different layers.
3. Without moving the mouse, use the N (next) or P (previous) bindkey
to display a via that has the same LEF rule as the selected via.
 If a via is available, the display is updated with the new via when you press the
bindkey.
 If another via is not available, you will hear a warning beep when you press the
bindkey. This can occur if only one via is defined in the LEF file, when the
currently queried object is not a via, or when no object is currently queried.
The Edit Route form does not provide access to this feature. You can only change one via at a
time by using the bindkeys. To change multiple vias at the same time, use the editChangeVia
text command. You can also edit vias for power wires by choosing the Power –
Power Planning – Edit Power Via command.
Lab Exercises
Lab 8-1 Using the Interactive Wire Editor
 Manually Routing a Net
 Replacing a Via in a Design
 Reshaping a Wire
 Forcing the Width of a Signal Wire
 Manually Shielding a Net
Preventing and Fixing Signal Integrity
Problems
Module 19
February 3, 2011
Module Objectives
 Identify signal integrity issues
 Run prevention, analysis, and signal integrity fixing
 Detect and fix SI issues using the timeDesign and optDesign
commands
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
Impact of Glitch Noise on Functionality
A glitch noise that exceeds a threshold can

cause functional failures.
q
1 d
Attacker 0
clk
1 reset
Victim
In this example, coupling from attacker causes a significant glitch on the reset signal so that it
resets the flip-flop and destroys the stored logic state. This problem will not show up in logic
simulation, formal verification, or timing analysis.
Crosstalk Noise Induces Timing Variations
Crosstalk noise can create timing problems involving setup (switching
opposite direction) and hold (switching same direction).
Victim with no noise Opposite

direction
switching
Aggressor
(delayed)
Vdd/2
t
Victim
Same direction
switching (faster).
The CeltIC® nanometer delay calculator (NDC) analyzes and generates an incremental SDF
file for speed-up and slow-down of interconnect delays.
You can set the number of iterations to improve the accuracy of the switching windows.
Crosstalk Fixing: Routing
Twindow1
Aggressor 1 Va1
Twindow2
Victim Ca1
R R R Va2
Cother 2R Ca2 Vn1
Vn2
Aggressor 2
Vntot Vnthr
es
Tn
Syntax
optDesign -postRoute -si
Fast, on-the-fly extraction, timing, and crosstalk analysis
 Combines glitch peaks from all aggressors if there are overlapping
timing windows.
 Nets whose combined glitch exceeds the noise threshold (peak, width)
are rerouted.
Because signal integrity (SI) is an interconnect-centric issue, it is most effective to address it

at the routing stage when the wires meet the gates.
The NanoRoute engine combines high speed, large capacity routing with on-the-fly electrical
analysis that simultaneously estimates timing and crosstalk effects as it routes. It uses a fast-
glitch peak analysis to identify potential trouble spots and to determine where to take
corrective action such as rerouting.
Crosstalk Avoidance: Routing
Wire spacing
Balances SI/Timing/Routability
Net ordering
Wire topology control
Layer selection to reduce coupling
Layer selection to reduce resistance
Minimizing parallel long wires
Shielding
Buffer insertion
The NanoRoute® router uses a number of techniques to prevent signal integrity problems,
such as spacing or net re-ordering.
Crosstalk Avoidance: Routing (continued)
Wire spacing
Balances SI/Timing/Routability
Net ordering
Wire topology control
Layer selection to reduce coupling
Layer selection to reduce resistance
Minimizing parallel long wires
Shielding
Buffer insertion
Other techniques include using free space to minimize long parallel wires, layer switching,
shielding, and buffer insertion. While preserving signal integrity, the NanoRoute engine will
also balance timing with routability constraints.
Crosstalk Prevention
By default, the NanoRoute router takes into account timing and signal
integrity. To turn off these options, enter the following commands:
setNanoRouteMode -routeWithTimingDriven false
setNanoRouteMode -routeWithSiDriven false
Optionally, you can also set the following parameters:

setNanoRouteMode –routeTdrEffort <integer>
setNanoRouteMode –routeSiEffort <high|medium|low|min|normal | max >
These parameters fine tune the priorities that the router assigns to timing,
signal integrity (SI), and congestion. Use these parameters together to
minimize crosstalk. After meeting the timing requirements of your design,
adjust the values of these options and rerun routing while following these
guidelines:
 If your design is congested, use a low timing-driven effort.
 If your design is not congested, use a high timing-driven effort.
setNanoRouteMode -routeTdrEffort integer

 Specifies how aggressively the router works to meet timing constraints.
 A higher value increases the effort toward meeting timing constraints and decreases the
effort toward relieving congestion.
setNanoRouteMode -routeSiEffort <high | medium | low | min | normal | max>
 Specifies how aggressively the router works to minimize crosstalk.
 When timing-driven routing is specified, the default value is high. You can also specify
medium or low. If you specify min, normal, or max, the software converts it to high and
issues a warning message.
 A high signal integrity effort maximizes the priority for preventing and reducing
crosstalk. It requires more time during detailed routing and consumes more routing
resources than a medium or low effort. When the max setting is selected, the router adds
spaces between nets to prevent signal integrity issues.
 When timing-driven routing is not specified, the default value is min. You can also
specify normal or max. If you specify low, medium, or high, the software converts it to
the appropriate value. (Low is converted to min; normal is converted to medium; high is
converted to max.)
 The min, normal, and max parameters are included for backward compatibility with
previous versions of the software.
Displaying Noise Nets
Optimize-Display Noise Net

opens the form to view problem
nets interactively. After the options
are set, click OK or Apply to open
the Result Browser.
The noise result browser displays

a list of victim nets sorted by the
largest amount of coupling noise.
Noise Browser
To view a net in the design display area, double-click on one of the rows in the list.
To select additional pins in the design display area, click while pressing the Shift key.
To highlight aggressors and victim pins at the same time, click the Browse Aggressors
button.
Fixing Crosstalk Post-Route
Select Optimize – Optimize

Design. Select Post-Route,
Include SI and click SI Options.
Native TWF (Default) generates a TWF file based on the Encounter® delay calculations.
Infinite SW states that all aggressors can switch at the same time. The resulting analysis is
more pessimistic. You can use infinite switching windows when the timing constraints
information is not well defined.
External TWF lets you read in third-party TWF files.
Important: It is strongly recommended that you recalibrate the noise library with each new
release of the CeltIC crosstalk analyzer. Often the new features will not function properly
when used with an old .cdB file.
Crosstalk Repair
The Encounter platform supports signal integrity (SI) operations that include
crosstalk prevention, analysis, and repair. The software uses an advanced
crosstalk repair algorithm that features:
 Victim-driver upsizing
 Buffer insertion
 Aggressor downsizing
 Aggressor rip up
 Victim spacing and protection
Specifying the Delay Calculation Mode for Signoff
Options – Set Mode – Specify Delay Calculation Mode
Use the SignalStorm® delay calculator for

sign-off delay calculation results.
If you choose default, the Encounter Digital Implementation delay calculator is used.
Using timeDesign for Crosstalk Analysis
The timeDesign command runs trial route, extraction, and timing analysis. This
command also generates detailed timing reports.
Generates a glitch violation report and incremental SDF for timinganalysis.The
timeDesign command generates and backannotates an incr.sdf into Encounter
Digital Implementation XL to calculate worst negative slack due to cross-coupling.
The -signOff option calls QRC for extraction.
Syntax
timeDesign
{-prePlace | -preCTS | -postCTS | -postRoute[-si] |
-signoff[-si]}
[-idealClock] [-drvReports] [-slackReports] [-pathreports]
[-reportOnly] [-timingDebugReport] -]…
Example
timeDesign –postRoute –si
Running Optimization and Timing Analysis with SI
Here is the script fragment for running optimization using the Advanced
Analysis Engine (AAE) delay calculator
setDelayCalMode –engine default –siAware true
Optimization
optDesign –postRoute
For running timing analysis including the effects of SI, run the following
commands:
setDelayCalMode -engine signalStorm -SIAware false
Timing
timeDesign –postRoute –si Analysis
timeDesign –postRoute –si –hold
Other timing-driven applications like ECO and metal fill are also SI-aware
when AAE is enabled.
Example Timing Closure Script with SI and AAE
timeDesign –prePlace
# Load floorplan , Specify scan chains and Spare cells
# Placement with the placeDesign command
optDesign –preCTS
# Run CTS with the clockDesign command
optDesign –postCTS
# Run Detail Routing with the routeDesign command
# Set the analysis type to on-chip variations and enable CPPR
setAnalysisMode –analysisType onChipVariation –cppr both
#Set the SI analysis type to default
setSIMode –analysisType default
#Set the engines for STA: signoff delay calculation (SignalStorm)
# and signoff SI analysis (CeltIC) and report initial timing
Example Timing Closure Script (continued)
timeDesign –postRoute –si –outDir init_setup
timeDesign –postRoute –si –hold –outDir init_hold
#Set the engine for optimization to AAE
setDelayCalMode –engine default –siAware true
# Run SI-aware setup optimization
optDesign -postRoute
# Run SI-aware hold optimization
#Set engines back to the original settings:
#SignalStorm and CeltIC and report final timing
timeDesign –postRoute –si –outDir final_setup
timeDesign –postRoute –si –hold –outDir final_hold
Metal Fill
Module 20
February 3, 2011
Module Objectives
 Explore the impact of adding metal fill into the design
 Set up metal density parameters before adding metal fill to the design
 Add and remove metal fill in a design
What Is Metal Fill?
Description
Metal fill is the process of adding metal
wire shapes to the design that are
required to satisfy the foundry metal
density rules.
GND
Flow Impact
 Parasitic Extraction
Timing and SI issues

 Power Distribution
SI (EM and IR Drop)
 Power Connection to blocks
There are four ways to add fills.

1. Big piece of floating metal – normally avoided or monitored closely, because it can
cause a violation to the maximum metal density rule.
2. Big piece of metal connected to power or ground – same as above. Normally connected
to ground provides better noise immunity.
3. Smaller floating wires – Same as 1, but fills are small wires. Better control of metal
density.
4. Smaller wires connected to power or ground - same as small floating wires. Normally
connected to ground provides better noise immunity.
Flow Impact
The addition of metal shapes in a design affects the capacitance of the surrounding wires.
Therefore, the addition will impact flow steps that depend on parasitic extraction accuracy
(timing analysis, signal integrity). It also will add more connections to the power grid. If
the fills are connected on two sides, then they will form a current path and might change
the power distribution, creating possible electromigration (EM) and IR-drop problems. In
block modeling, you can model the fills as power pins, because they are part of the power
net. This can cause ECO and electromigration and IR-Drop issues, because this is not the
intended location for a power connection, and during an ECO the fill might be removed.
Note: Floating pieces of metal can cause coupling capacitance and work as a transmitter of
noise from an aggressor to a victim net.
Post-CTS FLOW
Scan
Pre-CTS FLOW
Design Import Routing
Postroute Flow
Definition Add Metal Fill
Signoff


Met? Met? Met? Met?
Signoff
Adding and Removing Metal Fill in the Design
 You insert metal fill areas into a placed-and-routed design to achieve a
metal density within the range required by a specific manufacturing
process.
 To remove metal fill that has been previously inserted, use the
editDelete command or the Select/Delete form.
Adding Metal Fill

setMetalFill -layer 1 -windowSize 200 200 -windowStep 100 100
addMetalFill -layer {1 2 3} -area 100 200 300 400 -net {VDD GND}
The following commands trim metal fill after ECO routing:

setNanoRouteMode -routeWithEco true
routeDesign
trimMetalFill (Used with ECO flow to minimize timing problems.)
Added metal fill has the SHAPE FILLWIRE attribute. You can use this
attribute to locate and delete the fill.
It is recommended that you add metal fill before extracting parasitic capacitance values. This
sequence lets you include extraction results and correct the metal fill accordingly.
Metal Fill Setup
Select Route – Metal Fill – Setup

to open the Setup window.
The fields are filled in with

information from the LEF file.
Command line syntax

addMetalFill
-area x1 x2 y1 y2
-layer {all | layerList}
-nets netNameList
[-removeFloatingFill]
Metal Density Approaches
Simple Definition
Maximum and Minimum Metal density
rules need to be satisfied to reduce the
effect of Chemical and Mechanical
Polishing (CMP).
GND
Approaches
Metal Fill – Min. metal density check. Pieces of metal added in 2 ways:
 Floating metal (polygons or small wires)
 Grounded metal (polygon or small wires)
Metal Splitting – Max. metal density check. Wires split in thinner wires
Metal Slotting – Max. metal density check. Small segments of metal are
removed from the wires.
Metal Fill Window and Density
Use the Window &

Density tab to
define the metal
density for each
layer along with
window and
stepping size.
Adding Metal Fill
After the setup is completed,

you add the fill by selecting
layers, shape, area and
connection by choosing
Route–Metal Fill–Add.
After you have added metal

fill, use the trimMetalFill
command or Route–Metal
Fill–Trim from the GUI to
remove fill that causes DRCs.
Tree/Mesh – Floating or connected to VDD/VSS
Adding Via Fill
The addViaFill command inserts vias into a design to achieve cut density
within the range required by a specific manufacturing process.
 Adds floating vias or vias connected to power or ground wiring.
 Uses metal width and spacing values from setMetalFill.
 Considers the metal layers above and below the cut layer.
 Add via fill in the following areas after adding metal fill:
 Where metal fill shapes will intersect with power or ground nets on
consecutive layers if no via fill is added
 Where metal fill shapes on consecutive layers will intersect if no via fill is
added.
Some Fab metal fill specifications require a special staggered pattern that is diagonal.
A new option to the addMetalFill command is
addMetalFill [–stagger (off | on | diag)]
The default is on.
Verification
Module 21
February 3, 2011
Module Objectives
 Verify a design for geometry, connectivity, mental density, and antenna
 Interpret the errors displayed in the violation browser
 Generate a block antenna LEF file that is used for antenna violation
analysis
What Are DRC and LVS?
 Design-rule checks (DRCs) that are flagged as violations need to be
fixed or waived before tapeout.
Examples:
Minimum width, minimum spacing, antenna violations
 Layout-vs.-schematic (LVS) violations occur when there is a mismatch

in connectivity between what is in the placed and routed design and
the Verilog netlist or shorted nets.
Example:
An ECO performed on the physical design no longer matches the
netlist that was read in resulting in a mismatch
Post-CTS FLOW
Scan
Pre- CTS Flow
Postroute Flow
Definition
Signoff


Met? Met? Met? Met?
Signoff
DRC Checks Using Place and Route Data
Description
All cells are modeled with abstract. No layout available.
Subblocks
modeled with I/O Pad
abstracts modeled with
abstracts
Hard Macro
modeled with
abstracts
Advantages Disadvantages
 Fast  The checks will be as accurate
as the abstracts.
 Small database  No checks at different hierarchy
levels.
 Problems can be debugged
and fixed fast.  Connection to pins could have
violations.
Design rule check in the place and route environment. The place and route environment is a
flat environment and it does not use layout. It is mostly used to identify problems in the
current level of hierarchy.
Accuracy
 It relies on the accuracy of the abstracts. Therefore, it is very inaccurate to identify
problems between adjacent cells or routes and cell internal wires. For example, a process
rule could impose a same net cut to cut minimum spacing. If the cuts are not modeled as
being part of the pin or obstructions, then the router can connect to the pin by dropping a
via and a real violation will be created. It can only be identified with the real layout as
the information is not available in the place and route environment.
 Normally layers under poly and sometimes metal1 are not part of the abstracts. Therefore
cell abutment problems can be generated on these layers and will not be detected in the
place and route environment.
Rule Availability
All process rules are not available in the place and route environment. Only a subset of
them. Therefore a design can pass the DRC check in the place and route environment and
fail in the layout environment. For example: Minimum area that can be surrounded by
metal (area of the hole in a donut).
Verification Tasks
You can verify the following items:
 Connectivity
 Metal density
 Geometry
 Process antenna
Verifying Connectivity
Choose Verify – Verify

Connectivity to detect and report
various conditions, such as open
nets, antennas, loops, and partial
routing, for all nets or specified nets
in your design.
Open – Partially routed

Unrouted Net – Not routed
Antenna – Dangling Wires
Connectivity Loop – Loops in regular wires
Geometry Loop – If an external router does not use centerline loop and you want to check for
that
Geometry Connectivity – If any part of a wire touches another wire, they are considered
connected
Verifying Connectivity (continued)
Syntax
verifyConnectivity -nets [{netNames} | -selected]
[-type {all | special | regular}] [-noOpen] [-noAntenna]
[-noUnConnPin] [-noUnroutedNet] [-noWeakConnect]
[-connLoop | -geomLoop | geomConnect] [-report filename]
[-warning value] [-error integer]
-dividePowerNet
Divides power nets into four subareas for

connectivity verification.
Use this parameter to decrease memory
usage in 32-bit machines with limited memory.
Select the -geomConnect option to check for connectivity violations of regular wires. This
option uses a geometrical model instead of the center-line model. In other words, if the wires
overlap at any point, they are considered to be connected. They do not have to connect at the
center line. Use this parameter if you manually change the routing or use a third-party router
that does not route using the center-line connection routing technique.
Select the -geomLoop option to check for loop violations of regular nets using a geometrical
model. The nets do not have to overlap on the center line. When you specify this parameter,
the Encounter® software does not run any other connectivity checks. Use this parameter if you
use a third-party router that does not route using the center-line connection routing technique.
In this case, the -connLoop parameter might not detect connectivity loop violations.
Verifying Metal Density
Choose Verify – Verify Metal Density

to check whether the metal density for
each routing layer is within the
minimum and maximum density values
specified in the technology file.
Verifying Geometry: Basic
Choose Verify – Verify Geometry

to check the physical layout of your
design, such as widths, spacing,
and internal geometry of objects.
Verifying Geometry: Advanced
Use this form to check for

violations related to newer
processes, such as wire
extension and via stacking.
Verifying Process Antenna
Choose Verify – Verify Process

Antenna to identify process antenna
violations in your design and output
an antenna.lef for I/O pins in a block.
Floating Metal Area Outputs
 Maximum floating area violations detected by the
verifyProcessAntenna command appear in the antenna report file:
SM (2)
...
M4: Floating Area: 378.00 ( 4500, -4200 ) ( 5500. -420 )
M1: Floating Area: 2475.00 ( -25000, -30920 ) ( 0. -29920 )
M1: Floating Area: 1158.00 ( -25500, -42000 ) ( -24500. -30420 )
\DO[0] (2)
...
M3: Floating Area: 462.00 ( 2000, -420 ) ( 3000. 4200 )
M2: Floating Area: 687.00 ( -3000, -4200 ) ( 0. 920 )
 Markers will be contributed to the database. You can view the markers
from the Violation Browser and the graphical interface.
Verifying Well Taps
Run verifyWellTap to check the
design after running the addWellTap
command to highlight row areas that
contain potential violations if cells
are placed in those areas.
Syntax
verifyWellTap [-cells
list_of_well_tap_cells]
-rule distance Center of
Well Tap
Rule Distance
The -cells option allows specification
of Well Tap cells by name.
Well Tap
If a list of cells is not specified, the
CLASS CORE WELLTAP will be
used from the LEF file to determine
the cell masters.
Causes of Electromigration
 Electromigration (EM) is
mechanical failure in the wire
caused by frequently varying EM Failures as seen though a Scanning
thermal conditions. Electron Microscope (SEM)
 As pulses go through the wire

the power dissipated by the wire
causes it to heat above oxide
temperature.
 The difference in the thermal
constants between the oxide and
the wire causes mechanical
stress, and the wire can
eventually fail resulting in chip
failure in the field.
Verifying AC Limit
Calculates the root mean square current (Irms) at the driver output and compares it
to the ACCURRENTDENSITY tables in the LEF file that contain the Irms limits for
routing layers.
Verify – Verify AC Limit
Use this form to check for AC current

violations on signal nets.
Generates an error and attaches a violation
marker to a net if the calculated Irms for a net
exceeds the ACCURRENTDENSITY Irms limit
for a routing layer or width used by the net.
The software calculates the root mean square current (Irms) at the driver output. The software
then compares the value of Irms with the ACCURRENTDENSITY tables in the LEF file,
which contains the root mean square limit values for routing layers. If the calculated Irms for
a net exceeds the ACCURRENTDENSITY limit for any of the routing layers or widths used
by the net, then the software generates an error.
Violation Browser
After you use one or more

verification commands,
open the Violation Browser
to see the violations.
Choose Tools – Violation
Browser.
Mark Violations as False marks the selected violation as a false violation. These violations
are stored in the database as false violations.
Marks Violations as True marks the selected violation as a true violation.
You can also load Calibre and Assura DRC files and view the violations in the Violation
Browser.
Lab Exercises
Lab 9-1 Using the Verify Commands in a Design
 Verifying Connectivity
 Verifying Geometry
Engineering Change Order (ECO)
Module 22
February 3, 2011
Module Objectives
In this module, you
 Explore interactive ECO menu options
 Explore several ECO commands and options
 Run ECO on a design
What Is an ECO?
 An Engineering Change Order (ECO) is written when a change has to
be made to an implemented design.
 If the required change is a late-stage ECO, and the base layers have
been taped out, then the ECO is called a post-mask ECO.
 Otherwise the change is a pre-mask ECO.
 Example of a post-mask ECO:
 The base layers have been taped out and during simulation, a logical error
has been found in the design: an output has to be inverted.
 If there is an spare-cell available that’s an inverter, then the routing layers
can be changed to route to it and to leave the base layers undisturbed.
Traditional Functional ECO Process
Traditional ECO implementation can be manual, time consuming, and risk-prone.
No ECO Semi-automated ECO Flow
RTL
RTL RTL
w/ECO
Synthesis
Synthesis
 Potential risks
Gate  Inaccurate timing
Gate  Design rule violations
Place and  Time consuming
Route Manual editing
GDS II Place and

Gate Route
GDS II
ECO Methods
New
RTL Synthesis
New New Old

Method 3 Verilog
DEF Method 5 Verilog
Make changes to DEF.
Make changes to RTL.
ecoCompareNetlist Conformal ECO
-def Method 4
Make changes
Method 1 Eco Directive to Verilog.
File (.eco) New
Use ECO directives. Verilog
old
loadECO loadConfig Old design
DEF DB
Method 2
Use Encounter Interactive ECO
interactive commands. ecoDefIn ecoDesign
(super-command)
ecoPlace/ecoRemap
Optionally, if the design
is fully ECO routed, you
can perform interactive
ECO.
ecoSwapSpareCell
ecoRoute Signoff
Setting the ECO Mode
The setEcoMode command controls the behavior of the ECO commands.
Syntax
setEcoMode [-help] [-reset] [-honorDontTouch {true|false}]
[-honorDontUse {true|false}] [-honorFixedStatus {true|false}]
[-inheritNetAttr {true | false}] [-LEQCheck {true|false}]
[-prefixName prefix] [-refinePlace {true}false}]
[-spreadInverter {true|false}] [-updateTiming {true|false}]
 The -LEQCheck option enables functionality checking when swapping cells.

During ECO, the software can swap cells that are logically equivalent.
 The -spreadInverter option distributes an inverter pair evenly between the
driver and the first bifurcation point. The design must be routed before you use
this parameter.
 The -updateTiming option controls whether the eco* commands recompute
timing. If false, the commands do not recompute timing, and later you can run
report_timing to recompute timing.
Running an ECO with the ecoDesign Command
The ecoDesign command takes an Encounter database and a modified netlist as input and
performs ECO operations (including placement and routing).
It restores the design, examines the changes in the new netlist, and automatically implements
the required changes.
Syntax
ecoDesign [-postmask] [-tiecell "cellname1 cellname2"] [-addhierportsfortieoff] [-
modifyonlylayers mlb:mlt] {-sparecells sparecellname} [-suffix suffix] [-usegacells gacoresite] [-
noecoplace] [-noEcoRoute] [-ecosdc newsdcfile] [-def filename] [-fillerprefix prefix]
design.enc.dat top_cell new_netlist
Options
 -modifyOnlyLayers MLb:MLt specifies the layers to be modified during the ECO process.
 {-spareCell spare} specifies the name of the spare cell to use during the ECO process.
 -newSpareCellName suffix specifies the suffix to be appended to the spare cells.
 -noEcoRoute prevents routing during the ECO process.
 -postMask specifies that the changes are being made on a postmask design.
 {-useGACell GA_site} specifies the sites of the gate array cells.
Following are some examples:

ecoDesign -fillerPrefix FILL \
-spareCells ECO1 \
original.enc.dat myDesign myDesign.new.v
ecoDesign –spareCell *spare* -postMask \

-modifyOnlyLayers 1:3 \
original.enc.dat myDesign myDesign.new.v
Mapping Cells with the ecoRemap Command
The ecoRemap maps the unplaced, newly added cells to spare cells. The
remapping algorithm will continue to remap for better timing and DRV.
ecoRemap [-remapSuffix string] [-rpt filename]
[-spareSuffix suffixName] –allowConstantTie
-remapSuffix string
 When an unplaced cell is remapped to multiple cells, remapped cells will have their
instance name appended with specified suffix. For example, if a NANDX3 cell with
instance name I1 is mapped to ANDX4 and INVX8, the ANDX4 will have an instance
name I1_remap1 and INVX8 an instance name I1_remap2.
-rpt filename
 Default output filename is ecoRemap.rpt. This file contains all the mapping information.
-allowConstantTie
 Maps a cell to a spare cell containing more inputs than the cell in order to improve
timing. The extra input are tied to a constant.
VDD
Desired function Desired function
 The ecoRemap command is a postmask operation or a way to preserve diffusion layers.

In any case, no new cell is added or deleted physically.
 By default, all newly added ECO cells will be unplaced.
 The ecoRemap command bases the remap on the functionality of the unplaced cells and
maps it to equivalent logic gates that might be constructed from spare cells that yield the
best cost function (DRV, timing, congestion).
Requirements for the ecoRemap Command
The ecoRemap command depends on the availability of spare cells. More
spare cells mean:
 More possible solutions
 It will be easier to meet timing
 Possible increase in leakage power
The current implementation selects simple gates rather then complex
gates.
Recommendation
 Use the following commands to add/delete spare cells:
 createSpareModule
 deleteSpareModule
 placeSpareModule
Performing an ECO with ecoDefIn
Restores physical information from an old design and compares the
information with the design in memory.
Syntax
ecoDefIn [-postMask [-suffix suffixName]]
[-cleanFEData] [-ecoDef {new_def_filename}] {old routed
def file}
 -cleanFEData: Specifies that the old DEF file is Encounter data with
Nanoroute routing. The ECO routing function will skip routing analysis
because you have declared the routing is from the NanoRoute
software. Do not use this option with TrialRoute or with a third-party
routed database.
 -ecoDef {new def filename}: This option lets you specify the partial
DEF file mentioned above.
Performing an ECO with ecoDefIn (continued)
Example
ecoDefIn –postMask –suffix _SPARE –reportFile ecoDefIn.rpt myOld.def
 In this example a DEF file, myOld.def, is read in for postmask ECO.

 Instances that are converted to a spare cell contain the _SPARE suffix.
 The generated report file contains ECO directives.
Comparing Netlists with ecoCompareNetlist
The ecoCompareNetlist command compares a specified DEF file with an old design DB for
structural and logical equivalence, and creates a file containing the differences.
Syntax
ecoCompareNetlist {-def referenceFileName | [-inMemory | -external] }
[-logical] -outFile fileName
Parameters
 -def referenceFileName specifies the name of the DEF file that Encounter uses to compare with the
design.
 -external compares the post-ECO netlist to an external netlist.
 -inMemory compares the post-ECO netlist to the netlist in memory. This is the default behavior.
 -logical compares the netlists for logical equivalence.
 -outFile fileName specifies the file that contains the differences between the specified DEF file and
the design in the database.
Example Commands
restoreDesign oldChip.enc
ecoCompareNetlist –def myFile.def –outFile oldChip.eco
loadECO oldChip.eco
….
Loading ECO Directives
The loadECO command reads a file containing ECO directives and applies
changes to the current netlist. A summary report is generated.
ECO Directives:
loadECO myDirectivesFile.txt
ADDHIERINST
ADDINST
ADDNET
Example file myDirectivesFile.txt:
ATTACHTERM FORMATVERSION 2.0
CHANGECELL ADDINST TOP/eco_inst1 BUFX1 2
CHANGEINST DELETE INST TOP/mycell_1010
CHANGECELL TOP/mycell_2020 BUFX8
DELETEBUFFER ADDNET eco_net1
DELETEINST DELETENET mynet_3030
DELETENET
DETACHTERM
INSERTBUFFER
SWITCHTERM
Running Interactive ECO
Timing – Interactive ECO Use Interactive ECO to:
 Add a buffer
 Change a cell for a particular

instance
 Delete a buffer
 Display a buffer tree
Adding a Repeater at a Specific Location
Output New buffer
If specified, a downstream sink point will

be buffered at a particular location.
Interactive ECO: ecoAddRepeater
Adds single buffer or two inverters on a net.
Examples
 To add a buffer near the receiver run:
ecoAddRepeater -net net1 -relativeDistToSink 0.1
-cell BUFX16
 To add a buffer near the driver run:
ecoAddRepeater -net net2 -relativeDistToSink 0.9
-cell BUFX8
 To add an inverter pair in a specified location run:
ecoAddRepeater -net net3 -loc 40.5 85.2 46.5 85.2
-cell INVX8
Note: To prevent ecoAddRepeater from running refinePlace, run setEcoMode-refinePlace
false. This helps speed up run time when you have thousands of buffers to add.
Interactive ECO: ecoChangeCell
Upsize or downsize specified instance.
Examples
 To upsize specified instance, run:
ecoChangeCell -inst Top_Inst1 -upsize
 To downsize specified instance, run:

ecoChangeCell -inst Top_Inst2 -downsize
 To modify specified instance to specific cell, run:

ecoChangeCell -inst Top_Inst3 -cell BUFX20
Note: To prevent ecoChangeCell from running refinePlace, use setEcoMode -refinePlace

false. This helps speed up run time when you have thousands of buffers to add.
Interactive ECO: ecoDeleteRepeater
Deletes a buffer or inverter pair.
Examples
 To delete specified buffer, where one buffer is A/inst1, run:

ecoDeleteRepeater -inst A/inst1
 To delete back-to-back inverter pair, where one inverter is A/inst2 and

another is A/inst3, run:
ecoDeleteRepeater -inst A/inst3
What-if ECO Features
This feature lets you perform what-if ECO analysis without committing the
changes.
The -evaluateOnly option evaluates with the user-specified cell, whereas the
-evaluateAll will evaluate all the cells with similar functionality.
The –evaluate* options allow you to evaluate the effect of the ECO on timing.
Syntax
ecoAddRepeater [-evaluateOnly | -evaluateAll]
ecoChangeCell [-evaluateOnly | -evaluateAll]
ecoDeleteRepeater [-evaluateOnly]
Examples
ecoChangeCell -inst DTMF_INST/TDSP_CORE_INST/i_10177–evaluateAll
ecoChangeCell -inst DTMF_INST/TDSP_CORE_INST/i_10177–cell BUFX4 -evaluateOnly
ecoChangeCell -inst DTMF_INST/TDSP_CORE_INST/i_10177-evaluateOnly -upsize
ecoChangeCell -inst DTMF_INST/TDSP_CORE_INST/i_10177-evaluateOnly -downsize
ecoDeleteRepeater -inst DTMF_INST/TDSP_CORE_INST/i_10177–evaluateOnly
ecoAddRepeater -net ibiasI -cell BUFX2 -evaluateOnly
ecoAddRepeater -net ibiasI -cell BUFX2 –evaluateAll
ECO Placement and Routing
ecoPlace
 Incrementally places unplaced standard cells.
 Premask flow: Moves unplaced standard cells in the core area.
 Postmask flow: Maps unplaced cells to available spare cells.
 Use -useSpareCells option. First checks if all unplaced cells match spare
cells. Then chooses a spare cell and changes the connections from
unplaced cell to the selected spare cell. Finally, it deletes the unplaced cell.
 -fixPlacedInsts: Specifies instances with PLACED status are not
moved.
ecoRoute
 Performs incremental ECO routing on the newly placed ECO cells.
ECO Routing Actions
During ECO routing, the router does the following:
 Reroutes partial routes and nets without routing.
 Retains fully prerouted nets and pin-to-pin paths.
 Might use dangling paths to complete routes, but removes dangling
wires left over from global routing.
 Keeps connectivity within the bounding box, but does not constrain
layers or positions.
 The router might change the routing path of another net and route it on a
different layer or in a different position during ECO routing. To fully constrain
a net, specify the -skip_routing attribute for the net.
 The router does not support ECO routing of wires with the FIXED keyword.
Change FIXED to ROUTED to route the wires in ECO mode.
 Run ecoRoute when you run ECO routing.
Freeze Metal ECO
 Use the freeze metal ECO flow to restrict layer usage above and below
the ECO routing layers.
 Run ecoRoute -modifyOnlyLayers bottomLayer:topLayerto allow only
a subset of layers to be modified. This option works in conjunction with
other Encounter® ECO operations.
 Alternatively you can set the following modes to restrict routing to
certain layers.
Syntax
setNanoRouteMode -routeEcoOnlyInLayer “low:high”
Example
{... load ECO design, prep ECO routes...}
setNanoRouteMode -routeEcoOnlyInLayer “2:4”
setNanoRouteMode -routeWithEco true
routeDesign
NanoRoute ECO
During engineering change order (ECO) routing, the NanoRoute® router
completes partially finished routes with changed logic, while maintaining the
existing wire segments as much as possible.
This feature minimizes routing changes during ECO routing, and is less
likely to cause signal integrity or timing closure problems.
Use NanoRoute ECO (after routing) under the following conditions:
 You receive a new netlist with minor changes.
 Buffers were added to repair setup or hold violations or DRVs during
physical optimization.
 Buffers were added or gates were resized during manual editing of a
routed design.
 Antenna diodes were added interactively to repair process antenna
violations.
Writing Out a Design
Module 23
February 3, 2011
Module Objectives
 Save and export a design in several formats
Writing Out a Design
 You can export GDSII or OpenAccess databases in the Encounter®
flow.
 The OpenAccess database can be passed back to Encounter for final

verification, extraction, and timing analysis after the chip finishing steps
have been completed.
Map File for Writing Out a GDS file
 In order to write out a GDSII file, you need a GDSII map file that
contains the layer name and equivalent layer number.
 The layer number is used by the custom tool (such as Virtuoso Layout
Editor) to interpret the layers in the same way as EDI.
Example Layer Map File Format

EDI Layer Name Layer Type Layer Number Data Type
METAL1 NET 1 0
METAL1 PIN 1 1
METAL2 NET 2 0
METAL2 PIN 2 1
Writing Out a GDSII/OASIS File
 In addition to writing out the design in GDSII file, you can also include
the GDSII library containing the cells and the macros in the design.
 This feature is useful if you are not planning on using a custom tool for
the chip-finishing step
Select File – Save – GDS/OASIS to
display the GDS Export form.
Use the Stripes option to break
large designs into multiple GDS
files.
Use the Output Stream File text field to specify the name of the GDSII output file. Click the
file folder icon to find the directory and file you want.
Add the .gz extension to the filename to enable compression, such as GDS_file.gds.gz.
The Map File field specifies the file for layer mapping between the system and GDSII. Use
the file folder icon to find the file you want. If a file is not specified, a default map file is
created with the name streamOut.map.
If a map file is not specified, a default map file is created with the name streamOut.map.
The Library Name field specifies the library that you want to convert to GDSII format. The
default name is DesignLib.
Saving a Design
Select File – Save

Design to select the
either Encounter or OA
formats.
In order to keep snapshots of your work, save the design in Encounter format periodically.
If you are planning on exporting the design to Virtuoso, then, write out the design in OA
format or GDSII.
Writing out the design in OA format will retain the properties of the data when you transfer
the design between EDI and Virtuoso.
Writing Out a Verilog Netlist with Physical Cells
 In order to include the all physical cells that were added during
implementation such as filler cells and well tap cells in yourVerilog
netlist, run the following command.
Syntax:
saveNetlist <filename> -phys
Use the generated netlist to run LVS

 In order to select physical cells to write out, run the following command
Syntax:
saveNetlist <filename> -includePhysicalInst <cellname>
Lab Exercises
Lab 10-1 Loading a Design for ECO Routing
Encounter Database Access Commands
Module 24
February 3, 2011
Module Objectives
In this module, you
 Explore Encounter® database access commands to get and set object
attributes.
 Run some of the most commonly used database commands to output
design properties.
 Explore the most commonly used commands:
 dbGet
 dbSchema
 dbSet
 dbTransform
The dbGet Command
The Encounter database is both readable and writable with TCL commands
 The dbGet command returns object and attribute information for the specified
database object in the design.
 The dbGet command takes an object or object list as a starting point, then
uses a period to traverse to other related objects, or to access attributes.
 Additional periods can be used to continue traversing the database schema.
 For example, the following command returns the master cell names for all of
the instances in the design:
dbGet top.insts.cell.name
top is a pointer to the top cell.
insts is a list of pointers to the instances in the
top cell.
cell is a list of pointers to the master cells for
each instance.
name is the master cell name.
Example: Printing Out All the Clock Nets
What is the easiest way to print out all the clock nets in the design?
Answer: Run the following command:
dbGet [dbGet -p top.nets.isClock 1].name
Clock nets are identified in the following ways:
 A net is considered to be clock from when there arecreate_clock
statements in the constraints file. When timing analysis is performed,
the create_clock statements propagate from net to net and then some
objects along that tracing are considered “clock” or not.
 A marking in the .lib file declares a lib_cell pin to be a clock or not.
 A net in the design is found to be part of a clock tree that’s been
physically built and has a DEF marking on the nets declaring them to
be CLOCK.
The dbSchema Command
The dbSchema command returns all of the available objects and attributes
for the specified database object, and also includes the following
information:
 A short description for each object and attribute.
 The type for each object.
 The legal enum values for each attribute.
 Whether the attribute value can be set (whether it is editable).
Example
The following command returns the available objects and attributes for an
instance:
dbSchema inst
box: rect, Bounding box of the instance

cell: obj(libCell ptnCell), Pointer to child cell master or ptnCell
instTerms: objList(instTerm), List of pointers to instance terminals
isDontTouch: bool, Indicates that the instance is marked Don’t Touch
isHaloBlock: bool, Indicates that the instance is a halo block
isJtagElem: bool, Indicates that the instance is a JTAG element
isPhysOnly: bool, Indicates that the instance is physical only
isSpareGate: bool, Indicates that the instance is a spare gate
name: string, Fully qualified (path) name of the instance
objType: enum(bndry densityShape fPlan group hInst hInstTerm hNet hTerm head
inst instTerm layer libCell net netGroup pBlkg pd prop ptnCell rBlkg row sWire
shape term topCell vCell via wire), Object type: Instance
orient(settable): enum(MX MX90 MY MY90 R0 R180 R270 R90 Unknown), Instance
placement orientation
pStatus(settable): enum(cover fixed placed unplaced), Instance placement
status
pgCellTerms: objList(term), List of pointers to the instance’s power terminals
pgTermNets: objList(net), List of pointers to nets attached to P/G terminals
pt(settable): pt, Location of the instance
The dbSet Command
 The dbSet command changes the specified attribute value for a
database object.
 The dbSet command takes an object or object list as a starting point,
then uses a period to traverse to other related objects, or access
attributes. Additional periods can be used to continue traversing the
database schema.
 The dbSet command does not create or delete objects.
Example
The following command changes the placement status of the top cell
instances to fixed:
dbSet top.insts.pStatus fixed
The dbTransform Command
 The dbTransform command takes the local coordinates of a cell and
returns them in context with the global design space.
 You can specify a specific instance of a cell in the design, or you can
specify a library cell, its location in the design, perform a “what-if”
translation of coordinates within that cell.
Example
Assume that a shape exists on M1 within a NAND2 cell, from (1 1) to (2 2).
If an instance of the NAND2 cell is placed at (10 10), with an R0 (N)
orientation, the following command converts the local points (1 1 2 2 ) of the
NAND2 cell into their global coordinates:
dbTransform -cell [dbGet -p head.allCells.name NAND2] \
-pt {10 10} -orient R0 -localPt {1 1 2 2}
The software returns the following information:
{11 11 12 12}
Implementing Logical Operations with dbShape
The dbShape command enables logical operations on lists of shapes
(AND, OR, etc.)
Syntax:
dbShape [-help] [-d] [-step <step>] [-output <polygon|rect>]
<shapeList> [AND <shapeList> | ANDNOT <shapeList> | OR
<shapeList> | XOR <shapeList> | SIZE <value>| BBOX | MOVE
{<dx> <dy>}] ...
Example:
dbShape $shapeList1 AND $shapeList2
Returns a list of intersecting shapes between $shapeList1 and $shapeList2.
Using dbShape for Logical AND
dbShape $shapeList1 AND $shapeList2
One polygon is returned
ShapeList1 Result
ShapeList2
Sample Scripts in the gift Directory
There are several sample scripts that you can use as-is or modify to better
fit your requirements
Location: <your installation>/ <OS>/share/fe/gift/scripts/tcl
Example:
Lab Exercises
Lab 11-1 Using the dbGet and dbSet Commands
Foundation Flow Scripts
Module 25
February 3, 2011
Design Implementation Flow
Scan
Post-CTS Flow
Postroute Flow
Pre-CTS Flow Definition
Signoff
Load JTAG/Cell Clock Tree Postroute Physical

Timing Analysis
Setup Setup Fixing Setup/Hold Fixing Setup/Hold Fixing

Met? Met? Met? Met?
Signoff
Module Objectives
In this module, you
 Articulate the purpose and usage or the EDI Foundation Flows
 Create a design-specific setup file which is required to run the
Foundation Flow
 Automate the Flat Encounter implementation flow by using the
Foundation Flow Wizard to generate and run the Foundation Flow
scripts
What Is the EDI Foundation Flow?
 The Foundation Flow is a set of Tcl scripts generated by EDI to further
automate the design implementation flow.
 The scripts are generated for each stage of the implementation
process: the commands and options are tuned to work well for most
designs out of the box.
 If further customization is needed you can writeTcl plugins that can
address specific requirements.
Foundation Flow Demos and Documentation
Choose Flows – Foundation Flow Demo to view the demos at
support.cadence.com.
Choose Flows – Foundation Flow Documentation to view the related

docs.
Design Data
List of the Design Data Required for This Flow
Netlist Design Netlist – Verilog Timing Timing Constraint File(s) – SDCs for all modes
Constraints
Floorplan Floorplan File – Encounter Digital

File
Implementation .fp file, DEF file
Timing Timing Libraries – .libs for all sets, all Vts
Libraries
Clock Tree
Spec Clock Tree Specification File LEF LEF Libraries
Libraries
Scan
Information Scan chain information – TCL or DEF
Technology Technology Files – Cap Tables and QRC (optional)
Files
GDS
Layer Map GDS Layer Map File SI *SI Libraries – CDB and/or UDN format
Libraries
*SI Libraries are not an absolute requirement but are strongly recommended.
Foundation Flow Wizard
Use the Foundation Flow Wizard to
create a template for your
implementation flow
The flow wizard lets you specify
technology and design file locations
Additionally you can specify:
 Power optimization settings
 MMMC
 Tools to use
 Plug-ins
Additional Details are in the EDI

Foundation Flows Guide
Running the Flow Wizard
Run the Flow Wizard to create a design-specific setup.tcl file which is:
 Used to drive the foundation flow Note: The Flow Wizard
 Reloaded and updated for flow management does not execute the flow
Foundation Flow Code Generation
The Foundation Flow code generation methodology includes the following
files and features:
 Design-specific and run-specific scripts that are generated on-the-fly
 Procedural core script modules that include only one level of
procedural calls within each module
 Makefile
 Generated on-the-fly
 Calls the code generator before each step to make sure changes to plug
-
ins, etc. are incorporated
 File and variable checking during code generation so that errors can
be resolved ahead of time
Example: Code Generation
Plug-ins
$ tclsh SCRIPTS/gen_edi_flow.tcl all Plug-ins Defined

------------------
------------------------------------------------- > post_init_tcl
<FF> TCL VERSION -> 8.4 > pre_place_tcl
------------------------------------------------- > post_place_tcl
<FF> LOADING CONFIGURATION FILES: > pre_route_tcl
<FF> setup_tcl -> ./setup.tcl Tags
<FF> edi_config_tcl -> ./edi_config.tcl Tagged Commands
<FF> INFO: Variable vars(version) not defined- setting to '10.1.0' ------------------
------------------------------------------------- > place,time_design,skip
<FF> Generating scripts for dtmf_recvr_core > prects,opt_design,pre_tcl
------------------------------------------------- > route,check_place,skip
<FF> Generating step init > route,time_design,skip
<FF> Generating step place > postroute_si,set_design_mode,pre_tcl
<FF> Generating step prects
<FF> Generating step cts Warnings/ Warning Summary
<FF> Generating step postcts ------------------
<FF> Generating step postcts_hold
Errors (1) Recommended variable cts_spec not defined
<FF> Generating step route (2) CDB libraries not defined for slow_libs library set
<FF> Generating step postroute (3) CDB libraries not defined for fast_libs library set
<FF> Generating step postroute_hold
<FF> Generating step postroute_si_hold
<FF> Generating step postroute_si Steps -------------------------------------------------
<FF> Generating step signoff <FF> CODE GENERATION COMPLETE
------------------------------------------------- Generated <FF> ... VERSION -> 10.1.0
Output
<FF> Generating flat Makefile for 12 steps <FF> ... SCRIPTS -> FF
------------------------------------------------- <FF> ... REPORTS -> FF/check.rpt Files
<FF> Generating step debug <FF> ... -> FF/check_vars.rpt
------------------------------------------------- <FF> ... MAKEFILE -> Makefile
<FF> Generating step lec -------------------------------------------------
-------------------------------------------------
Output Files
Makefile Makefile
FF/vars.tcl
FF/run.conf
FF/procs.tcl
Supporting Scripts
FF/check_qor.tcl • Variable Settings
FF/mmmc.tcl • Design Configuration File
• FF utility procedures
FF/check.rpt • MMMC timing setup
FF/check_vars.rpt
FF/EDI/run_init.tcl
FF/EDI/run_place.tcl
FF/EDI/run_prects.tcl
FF/EDI/run_cts.tcl
FF/EDI/run_postcts.tcl
FF/EDI/run_postcts_hold.tcl Individual Step Scripts
FF/EDI/run_route.tcl • Can be run individually
FF/EDI/run_postroute.tcl
• Used for multi-step runs
FF/EDI/run_postroute_hold.tcl
FF/EDI/run_postroute_si_hold.tcl
FF/EDI/run_postroute_si.tcl
FF/EDI/run_signoff.tcl
FF/EDI/run_all.tcl
FF/EDI/run_simple.tcl
FF/EDI/gen_html.tcl
FF/EDI/run_debug.tcl Miscellaneous Scripts
FF/EDI/run_lec.tcl
Lab Exercises
Lab 12-1 Generating and Running the Foundation Flow Scripts
Completing the Post-Class Assessment
1. In a web browser enter: http://exam.cadence.com.
2. Log in to the exam server:
a. Name: your complete email address (example:joe@cadence.com)
b. Group: your company’s email suffix (example:cadence.com)
3. Select the assessment with the title of:
ES Floorplanning, Phys. Synth. Place and Route (Flat) POST
4. Complete the assessment.
5. Click Submit at the bottom of the exam.
Note: You will be given a score and the correct answers. We will
discuss these following the exam.
Thank You!
Live
2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat)
550
Setting Constraints Using SDC
Appendix A
February 3, 2011
Module Objectives
 Identify constraints on each type of design object
 Set design-level constraints
 Set environmental constraints
 Set the wire-load models for net delay calculation
Note: If you need more comprehensive training on Static Timing Analysis,

you may want to sign up for our Basic Static Timing Analysis online
course.
What Are Constraints?
Constraints provide specifications that the design must meet through
optimization.
Typical examples of constraints are:
 Clock constraints
 External constraints
 Power constraints
 Net Delay constraints
 Environmental constraints
 Design rules for manufacturing
Constraint Formats
The Synopsys Design Constraints (SDC) format is the standard for writing
constraints in the industry.
STA tools also have their own style of writing constraints, which conform to Tcl
syntax.
SDC Format Equivalence
As you look at examples of constraints, you might notice slight differences in format.
The following list shows the three equivalent ways to create SDC constraints:
 Manually written constraint
create_clock -period 100 -waveform {0 50} clk
 Generated constraint from Design Compiler

create_clock -period 100 -waveform {0 50} [get_ports {clk}]
 Generated constraint from PrimeTime

create_clock -period 100.000000 -waveform {0.000000\ 50.000000}[get_ports {clk}]
All three of the above formats are functionally equivalent. Some tools might prefer
one way to another.
Common SDC Constraints
Operating conditions Timing
 set_operating_conditions  create_clock
Wire-load models  create_generated_clock
 set_wire_load_mode  set_clock_latency
 set_wire_load_model  set_clock_transition
 set_wire_load_selection_group  set_disable_timing
Environmental  set_propagated_clock
 set_drive  set_clock_uncertainty
 set_driving_cell  set_input_delay
 set_load  set_output_delay
 set_fanout_load Exceptions
 set_input_transition  set_false_path
 set_max_delay
 set_port_fanout_number
 set_multicycle_path
Design rules
Power
 set_max_capacitance
 set_max_dynamic_power
 set_max_fanout
 set_max_leakage_power
 set_max_transition
This list of commands includes some of the most commonly used. They are categorized by
function.
Design Objects
You apply certain constraints to design
objects to affect different parts of the Object Command Description
design.
Design is a container for
Design current_design
The table shows several design objects cells or is the entire circuit.
and the commands to get a list of these
Cell is an instance of a
objects. Cell or
get_cells design or is a library
Block
component.
get_ports
A port is a signal entry point
Port all_inputs
or exit point to a design.
all_outputs
A pin is a hierarchical port of

a design, port of an
Pin get_pins
instance, or a port of a
library cell.
get_clocks A clock is a port or a pin that

Clock
all_clocks drives sequential cells.
A net is an interconnect
Net get_nets between cell pins and
design ports.
Design Object: Chip or Design
Operating conditions affect the chip
or a block. Object Command Description

cells or is the entire circuit.
Cell or
Block
component.
get_ports
Port all_inputs
all_outputs

Pin get_pins
library cell.

Clock
design ports.
In multisupply voltage (MSV) designs, operating conditions can be set on a block.
Design Object: Cell or Block
Apply power constraints and wire-
load models to the cell or block Object Command Description
object.
Cell or
Block
component.
get_ports
Port all_inputs
all_outputs

Pin get_pins
library cell.

Clock
design ports.
Design Object: Port
Apply timing constraints and
environmental constraints to a port Object Command Description
object.
Cell or
Block
component.
get_ports
DataOut A port is a signal entry point
Port all_inputs
all_outputs

Pin get_pins
DataIn library cell.

Clock
design ports.
Design Object: Pin
Apply timing constraints and
environmental constraints to a port Object Command Description
object.
Pins are like ports of subdesigns. cells or is the entire circuit.
Cell or
Block
component.
get_ports
Port all_inputs
all_outputs

Pin get_pins
library cell.

Clock
design ports.
Design Object: Clock
Apply clock related timing
constraints to the clock object. Object Command Description
Design is a container for cells or

is the entire circuit.
Cell or Cell is an instance of a design or

get_cells
Block is a library component.
get_ports
A port is a signal entry point or
Port all_inputs
exit point to a design.
all_outputs

Clock
A pin is a hierarchical port of a

Pin get_pins design, port of an instance, or a
port of a library cell.
Clk2
A net is an interconnect between
Net get_nets
cell pins and design ports.
Clk1
Design Object: Net
Apply timing constraints to the net
objects. Object Command Description
Wire-load models affect the delays of Design is a container for
these net objects. cells or is the entire circuit.
Cell or
Block
component.
get_ports
Port all_inputs
all_outputs

Pin get_pins
library cell.

Clock
design ports.
Setting Operating Conditions
Operating conditions are applied at the design level. Nowadays, the
technology library is created for a specific set of operating conditions. Thus,
specifying the library is probably sufficient.
To switch between the operating conditions use:
set_operating_conditions –name “WCCOM” –library “slowtech”
The timing analysis tool resets itself when you switch between operating
conditions, and creates different timing data based on the new library
information.
set_operating_conditions
Process, temperature, and voltage define the operating conditions of a chip or design. After a
chip or design is manufactured, the operating conditions under which it will likely work is
important for calibrating the chip characteristics. Each design is tested for the set of operating
conditions it will work under, and beyond which it might fail. The operating conditions are
usually specified for the entire design. You might have multisupply and multivoltage in
different areas of a design. For this course, assume that the design is tested for one operating
condition at a time.
Design Rule Constraints
Design rule constraints are applied at the design level.
You must meet design rule constraints to make sure that you can
manufacture the design. The technology and the fabrication process
determine the constraints.
The following commands set these design rule constraints:
 set_max_capacitance
 set_max_fanout
 set_max_transition
Setting Environmental Constraints
Environmental constraints are applied at the port level.
The environment of the chip has an influence on chip performance. You
need to model the environment in terms of constraints that take into
account the following aspects:
 The driving cell that drives the input of the chip
 The load that must be driven by the output pins
set_drive set_load
set_driving_cell The set_wire_load

command sets the wire-
load model for the current
design.
set_fanout_load*
set_port_fanout_number*
Think of environmental constraints as attributes that are applied to ports.
Setting the Driving Cell
The input drive of a pin is the strength of incoming signal, or its capacity to
drive the input and its fanout.
set_driving_cell -lib_cell BUFX8_TAX0 -library xlite_core [get_ports {ipmitxbfr_rdata[3]}]
Use the set_driving_cell command to define the cell that drives the input
port.
set_drive
set_driving_cell
You can also use set_drive command to set the driving capability of the input port.
The set_driving_cell command is also used as a design rule constraint for the ports.
Setting Output Load
The load of the output port is the amount of capacitance that the port has to
drive. It is the total capacitance as seen by the output port. If multiple pins
are driven by the output port, then it is a summation of all the capacitances
of individual end points.
set_load -pin_load 0.2 [get_ports {decalf_hdrmem_ld}]
The set_load command lets you define the net capacitance load that the
output pin “sees.”
set_load
set_fanout_load*
set_port_fanout_number*
You can specify the same information as shown above using the following commands
together:
The set_port_fanout_number command lets you specify the fanout of the output port. This
command is used in conjunction with the set_fanout_load command.
set_port_fanout_number 5 [all_outputs]
The set_fanout_load command lets you specify the value of the input capacitance of a cell
driven by the output port.
set_fanout_load 100x100 -library slow [get_ports CELLX1/A*]
The set_port_fanout_number and set_fanout_load are also used as design rule constraints for
the ports.
Pipeline Register Placement
Appendix B
February 3, 2011
Pipeline Register Placement
Description/Benefit
On big designs with long net connection between blocks timing cannot be met even
with buffer insertion. This can be addressed by inserting divide registers to several
pipeline stages to meet target frequency.
Use Model
 Analysis flow
 Done after floorplanning step
 Main purpose is to evaluate how many PFF is needed for long nets in the design
 Once this is known, the designer will insert PFF in the RTL and re
-synthesize
 Note: Long net connectionsmay be between placed standard cells, blocks, IO’s or
partitions. The command(s) expect the end-points to be preplaced.
 Implementation flow
 Places the newly added PFF at equidistance spacing, as per the given requirement.
 Note: It is assumed that PFF have clock connected in the RTL and scan chains
inserted during synthesis.
 Provides a means of reporting the achieved spacing per net group.
Pipeline Register Placement (continued)
Flow
Create or Modify
Create Pipeline Net Groups
Pipeline Net Groups
Analysis
Create Bus Guides
Report Pipeline Registers
Implementation
(Optional)
 Report Pipeline Stages

 Generate Bus Guide Place Pipeline Registers
(optional)
Trial Route
(Optional)
Netlist Resynthesis
Report Pipeline Registers
Syntax
createPipelineNetGroup netGroupName
{-inst instNames|-startTerm termList -endTerm
termList|-net netNames}
[-startReserve distInMicrons] [-endReserve distInMicrons]
-inst instNames
Create net group of all nets connected to the given instances. The instances must all be flip
-flops or latches.
All the nets attached to the D and Q pins will be put into the PFF net group. Wildcards accepted.
-startTerm termList -endTerm termList
Create net group of all data nets between the given end points. The PFF
-chain will be traced from the
startTerm, through D and Q terminals of PFF(s) until anendTerm is matched. Wildcards accepted.
-net netNames
Create net group of all given nets. Wildcards accepted.
-startReserve distanceInMicrons
Specify a distance budget from internal connections inside block to the start point of the PFF net. This value
is added to the first stage distance when calculating equidistant spacing for each stage.
-endReserve distanceInMicrons
Specify a distance value from the end points on block boundary to the internal connection inside the block
that needs to be accounted for in each stage distance value.
Syntax
modifyPipelineNetGroup netGroupName
{-inst instNames|-startTerm termList -endTerm termList|-net
netNames} [-startReserve distInMicrons]
[-endReserve distInMicrons]
-inst instNames
Modify net group of all nets connected to the given instances. The instances must all be flip
-flops or latches.
All the nets attached to the D and Q pins will be put into the PFF net group. Wildcards accepted.
-startTerm termList -endTerm termList
Modify net group of all data nets between the given end points. The PFF
-chain will be traced from the
startTerm, through D and Q terminals of PFF(s) until anendTerm is matched. Wildcards accepted.
-net netNames
Modify net group of all given nets. Wildcards accepted.
-startReserve distanceInMicrons
Specify a distance budget from internal connections inside block to the start point of the PFF net. This value
is added to the first stage distance when calculating equidistant spacing for each stage.
-endReserve distanceInMicrons
Specify a distance value from the end points on block boundary to the internal connection inside the block
that needs to be accounted for in each stage distance value.
Syntax
placePipeline [-netGroup {netGroupName}] [-region {true|false}]
-netGroup {netGroupName}
Specify the PFF net group, or a list of net groups, to place. By default, all PFF net
groups in design would be considered.
-region {true | false}
Create region constraints for flops in each stage of pipeline, to allow adjustments at a
later stage. Default is false. When no regions are used, the PFFs are placed with fixed
placement status; and placed status for when regions are used.
Syntax
reportPipeline [-netGroup {netGroupName} ]
[-spacing maxSpace [-busWidth bits –busLayers id1:id2]]
[-outFile fileName]
-netGroup {netGroupName}
Specify the PFF net group, or a list of net groups, to report. By default, all PFF net groups in
design would be reported.
-spacing maxSpace
-busWidth bits
-busLayers id1:id2
-outFile fileName
Notes
 A single PFF-chain is zero or more PFF that form the pipeline stages for
a single bus-bit.
 PFF must all be flip-flops (or latches) with a D input and Q output, and
scan pins (if used) that can be identified from the .lib definition.
 A PFF net-group consists of all the nets for one or more pipeline-chain.
 Each PFF-chain in a pipeline must have the same number of stages as
the other chains in that pipeline.
 The nets of one PFF-chain must follow the following rules:
 Each net is only connected to two terminals, except scan (in/enable)
connections which are ignored.
 The terminals of each net are only from a PFF Q output to a PFF D input,
except for the start / end terminals.
 The start / end terminals must be on preplaced cells.
Encounter Parallel Processing
Appendix C
February 3, 2011
Why Parallel Processing?
 Single CPU performance even at ~3-4 GHz is not adequate for the
implementation of today’s designs.
 Multiple CPU machines are becoming more common.
 In addition to multi-CPUs, you can use distributed processing, or
farms of machines on the network using load-sharing software.
The Encounter® platform continues to add multi-CPU and distributed

processing capabilities to most of the processing-intensive applications.
Memory Guidelines for Distributed Processing
Multithreaded Applications
 Runs on one host on multiple-CPUs and with
shared memory.
 Each extra CPU requires extra ~1-20% of full
design memory.
Distributed Applications
 Can run on one host or multiple remote hosts.
 Each extra CPU has to accommodate thefull

design, so the host needs enough memory for the
full design.
Superthreaded (distributed with memory usage like MT)
 Can run on one host or multiple remote hosts.
 Each extra CPU requires extra ~1-20% of full

design memory.
 Only a small fraction of the designis
processed by each CPU.
The setMultiCpuUsage Command
Syntax
setMultiCpuUsage
[-acquireLicense integer] [-keepLicense {true | false}] [-licenseList {string}]
[-localCpu {integer | max}] [-remoteHost integer] [-cpuPerRemoteHost integer]
[-releaseLicense]
[-threadInfo {0 | 1 | 2}]
[-verbose]
Examples
To run placement with 4 threads run the following commands:
setMultiCpuUsage -localCpu 4
placeDesign
To run optDesign SI in distributed mode on two machines with four threads,

run the following commands:
setDistributeHost -lsf -queue antonio # Antonio is the name of the
# queue in this example
setMultiCpuUsage -remoteHost 2 –cpuPerRemoteHost 4 optDesign –si
The setDistributedHost Command
The setDistributedHost command is required for distributed and
superthreading capabilities.
The following is an example to set up placeDesign in superthreading mode
with a maximum of 3 machines and 4 threads, using an LSF queue with
machines of 32 Gb memory.
Example
setDistributeHost -lsf -queue mem32G
setMultiCpuUsage -remoteHost 3 –cpuPerRemoteHost 4
placeDesign
Nanometer Design Rule Support
Appendix D
February 3, 2011
Module Objectives
 Understand the nanometer rules supported by the NanoRoute® router
 Explore LEF syntax as it relates to the rules
 Review the generateLef command
Support for 65 Nanometer Rules
 65 nm rules
 PARALLELOVERLAP Cut Spacing Rule
 ENDOFLINE Spacing Rule
 MINSTEP MAXEDGES Rule
 MAXFLOATINGAREA Rule
 Property definitions
Property Definitions
For new 65 nm design rules, the new properties are used in LEF 5.6 and
must be defined at the beginning of the LEF in the
PROPERTYDEFINITIONS section.
LEF Syntax
PROPERTYDEFINITIONS
[LAYER propName STRING ;] …
END PROPERTYDEFINITIONS
LEF Example
PROPERTYDEFINITIONS
LAYER LEF57_SPACING STRING ;
LAYER LEF57_MINSTEP STRING ;
LAYER LEF57_MAXFLOATINGAREA STRING ;
Parallel Overlap Cut Spacing Rule
LEF Syntax
PROPERTY LEF57_SPACING
“SPACING minSpacing PARALLELOVERLAP ;” ;
Cuts that have a parallel edge overlap greater than or equal to 0 require
minSpacing distance between them. Only one PARALLELOVERLAP
statement is allowed per cut layer. PARALLELOVERLAP does not apply to
cuts that share the same metal shapes above or below.
LEF Example
LAYER VIA1
TYPE CUT ;
PROPERTY LEF57_SPACING "SPACING 1.5 PARALLELOVERLAP ;" ;

…
END VIA1
Parallel Overlap Examples
SPACING 1.0 ; # Default Spacing
SPACING 1.5 PARALLELOVERLAP ;
1.5 1.5 1.0 1.0
1.5 1.5 1.0 1.0
Cuts have parallel Cuts have parallel Cuts have no parallel Cuts overlap, but they
overlap > 0, so overlap = 0, so overlap, so share the same metal.
SPACING value of SPACING value of PARALLELOVERLAP PARALLELOVERLAP
1.5 applies. 1.5 still applies. does not apply. Only rule does not apply.
needs 1.0 spacing. Only need 1.0
spacing.
End-of-Line Spacing Rule
"SPACING eolSpace ENDOFLINE eolWidth WITHIN eolWithin
[PARALLELEDGE parSpace WITHIN parWithin [TWOEDGES]] ;" ;
eolWithin
Overlap in this
eolSpace
area is a violation.
end of line eolWidth
eolWithin < minSpace < [parSpace=parWithin=eolWidth] < eolSpace
Because of the additional ENDOFLINE and WITHIN spacing constraints, metals extending
into the area of the orange box will result in a violation.
End-of-Line Parallel Edge Spacing Rule
PARALLELEDGE parSpace WITHIN parWithinspacing indicates the
end-of-line rule applies only if there is a parallel edge that is less than
parSpacing away, and is also less than parWithin from the end-of-line and
eolWithin beyond the end-of-line.
eolSpace
eolWithin
parWithin
eolSpace applies
here
parSpace
End-of-Line Spacing Rule Examples
SPACING 1.2 ENDOFLINE 1.3 WITHIN 0.6 PARALLELEDGE 1.1 WITHIN 0.5;
1.0 1.0 1.0

0.4
1.0 1.0 1.0

No violation, no Violation, has parallel Violation, has parallel
parallel edge edge. Needs 1.2 EOL edge. Needs 1.2 EOL
spacing. spacing,
1.2 1.0 1.0
1.0 0.5
1.1 1.1
No violation. EOL No violation. Parallel edge No violation, no
spacing is 1.2. is >= 1.1 away. parallel edge
End-of-Line Spacing Rule Quiz Answer
SPACING 1.4 ENDOFLINE 1.3 WITHIN 0.6 PARALLELEDGE 1.1 WITHIN 0.5;
1.2 1.2
0.4
1.2 1.2
Violation, has parallel Violation, has parallel

edge. Needs 1.4 EOL edge. Needs 1.4 EOL
spacing. spacing,
Minimum Step Rule Support
To provide the complete solution for detecting and fixing of the 65 nm
MINSTEP rule, the NanoRoute software now supports MAXEDGES in
LEF.
Example of MINSTEP Violation:

Both edges are less than the MINSTEP 0.05
0.02
PROPERTY LEF57_MINSTEP
"MINSTEP 0.1 MAXEDGES 1 " ;
The router only supports

MAXEDGES as 1 for now.
NanoRoute allows 1 edge
to be less than the
MINSTEP value.
In the illustration, both edges are less than 0.1 µm, resulting in a MINSTEP violation.
Example of MINSTEP Rule
PROPERTYDEFINITIONS
LAYER LEF57_MINSTEP STRING ;
…
LAYER Metal1
TYPE ROUTING ;
SPACING 1.00 ;
WIDTH 1.00 ;
PROPERTY LEF57_MINSTEP “MINSTEP 0.01 MAXEDGES 1 ;” ;
#MINSTEP 0.01 ;
### older version of MINSTEP property ###
#PROPERTY LEF57_MINSTEP “MINSTEP 0.01 INSIDECORNER ;” ;
#PROPERTY LEF57_MINSTEP “MINSTEP 0.01 STEP INSIDECORNER ;” ;
…
END Metal1
It is a violation to have two or more minEdges of less than 1.00 µm adjacent to each other.
Via-to-Pin Routing
Use the following commands to avoid MINSTEP violations when routing to pins in
standard cells.
LEF Syntax
routeWithViaInPin {true | false}

 Encloses the via geometry completely inside standard cell pin when
the router uses a VIA for a connection.
 Default: false
routeWithViaOnlyForStandardCellPin {true | false}

 Allows via access only to standard cell pins. No planar access.
 Default: false
Spacing Table Parallel Run Length Rule
The spacing between a wire and its neighboring wire depends on the width
and parallel (adjacent) run length of both wires.
Example
SPACINGTABLE
PARALLELRUNLENGTH 0.00 0.50 3.00 5.00 #lengths must be increasing
WIDTH 0.00 0.15 0.15 0.15 0.15 #max width>0.00
WIDTH 0.25 0.15 0.20 0.20 0.20 #max width>0.25
WIDTH 1.50 0.15 0.50 0.50 0.50 #max width>1.50
W2
PARALLELLRUNLENGTH
SPACING
W1
Use the following steps to find the rule from the SPACINGTABLE
PARALLELRUNLENGTH that applies:
 Find the maximum width of the two objects.
 Find the table row that matches the maximum width.
 Find the table column that matches the parallel run length. The value listed where the
row and column intersect is the required spacing for that maximum width and parallel
run length.
 Special nets are tied to nondefault rules.
Spacing Table Influence Rule (Halo Rule)
Processes often require a second spacing table to enforce the wide wire
spacing rules between nearby wires, even if the wires are narrow.
SPACINGTABLE INFLUENCE
WIDTH 1.50 WITHIN 0.50 SPACING 0.50 #w > 1.50, dist < 0.50, needs sp >= 0.50
WIDTH 3.00 WITHIN 1.00 SPACING 1.00 #widths must be increasing
WIDTH 5.00 WITHIN 2.00 SPACING 2.00 ;
The halo rule is applied

to A, C, and E. A C
B
It is not applied
between W
Wide metal W
and other
wires in its
halo range F
E
Halo range D
(B and F)
The SPACING in this SPACINGTABLE INFLUENCE depends on the WIDTH of the metal
object within a distance around the metal object. In this example, if WIDTH of the wide metal
is >1.5; within <0.50 distance around the object SPACING between two regular wires has to
be 0.50.
This SPACINGTABLE INFLUENCE rule has nothing to do with the SPACING between the
wide metal and neighboring wire. This rule is strictly related to how the SPACING between
neighboring wires is influenced by the presence of a wide metal nearby.
Adjacent Cuts Rule
 SPACING among via cuts is dependent on the number of adjacent
cuts.
 Newer technologies use tighter SPACING between via arrays of 1x1,
2x1, 1x3, and 2x2, but larger SPACING is needed for bigger arrays.
All vias have 2 adjacent vias 3 adjacent vias
LAYER CUT12
SPACING 0.20 ; #default SPACING
#A cut adjacent to 3 other cuts (2nd picture) < 0.25 away requires a
larger SPACING of >=0.22
SPACING 0.22 ADJACENTCUTS 3 WITHIN 0.25 ;
Note: Spacing includes diagonal/euclidean directions.
With this syntax, you do not need to have SAMENET SPACING for cut layers for the latest
technologies. Both SAMENET SPACING and ADJACENTCUTS syntax with this definition
can create confusion. Therefore, SAMENET SPACING is not needed.
Notes: ADJACENTCUTS statement will override cut-to-cut SPACING used in a VIARULE
GENERATE statement for large vias if the ADJACENTCUTS spacing value is larger that the
VIARULE spacing value.
Also, only ONE ADJACENTCUTS statement per cut layer is allowed.
Minimum Cut Rule
Certain processes have multiple rules: two cuts for .5 μm wide wire, and
four cuts for 1.0 μm wide wire. Some processes have different rules,
depending on whether the cut is below the metal or above the metal.
Example
LAYER m4
# 2 via cuts required for m4 > 0.50 µm when connecting from m3 or m5
MININUMCUT 2 WIDTH 0.50 ;
# 4 via cuts required for m4 > 0.70 µm when connecting from m3
MININUMCUT 4 WIDTH 0.70 FROMBELOW ;
# 4 via cuts are required for m4 > 1.0 µm when connecting from m5
MININUMCUT 4 WIDTH 1.0 FROMABOVE;
In this example, the minimum number of cuts needed to connect to metal layer m4 from the
next consecutive lower or upper layer is 2 (older syntax). In the next scenario, the WIDTH
requirement of the lower layer (m3) is 0.70 and the upper layer (m5) is 1.0 to connect to an
m4 wire with a minimum of 4 cuts.
Minimum Cut Rule (continued)
Some processes require more than one cut when a wire is connected to
another geometry within a certain distance.
Example
# 2 via cuts are if m4 > 1.1 µm wide and m4 > 20.0 µm long, and the
# via cut is < 5.0 µm away from the wide wire
MININUMCUT 2 WIDTH 1.1 LENGTH 20.0 WITHIN 5.0 ;
Within < 5.0 µm
Length > 20 µm
Width > 1.1µm
Minimum cut statement can have multiple definitions.

Example
LAYER METAL1
...
MINIMUMCUT 2 WIDTH 3.0 LENGTH 20.0 WITHIN 5.0 ;
MINIMUMCUT 2 WIDTH 0.42 LENGTH 0.42 WITHIN 1.0 ;
END METAL1
Maximum Via Stacking Rule
The MAXVIASTACK rule defines a limit on the number of single cut
stacked vias that are allowed in one continuous stack.
Example
MAXVIASTACK 4 ; # Only allow 4 stacked-vias on top of each other
MAXVIASTACK 4 RANGE m1 m7 ; # Only allow 4 stacked-vias between m1 to m7
A via is considered to be in a stack with another via if the cut of the first via
overlaps any part of the cut of the second via.
The MAXVIASTACK statement needs to follow the LAYER statements in the LEF file.
However, it is not attached to any particular layer. You can specify only one
MAXVIASTACK statement in a LEF file.
Minimum Enclosed Area Rule
This rule defines the minimum permissible area of a donut that has been
created during routing (same-layer).
Examples
LAYER M1
MINENCLOSEDAREA 0.40 ; #donut hole must be >= 0.40 square microns
MINENCLOSEDAREA 0.40 WIDTH 0.15 ;
# hole area >= 0.40 square microns when w <= 0.15
Metal 1 pin
Metal 1
This rule constrains the router to strictly avoid small holes or donuts.
In the first example, the donut area has to be 0.40 µm2.
In the second example, the minimum threshold area for the AREA is 0.40 µm2, if the
enclosed area has been surrounded by a wire of WIDTH <0.15.
A design rule violation can occur near a semi-enclosed M1 pin when the router tries to
connect to multiple points of the pin.
Protrusion Width Rule
The PROTRUSIONWIDTH rule requires a minimum WIDTH (W1) of a
narrower metal connected to a wider metal (W2), less than a specified
LENGTH (L).
Example
PROTRUSIONWIDTH 0.30 LENGTH 0.60 WIDTH 1.20 ;
This means W1 must be greater than or equal to 0.30µm if the protrusion L
is less than 0.60 µm, and W2 has a width greater than 1.20 µm.
0.6 L W1
0.30
W2
1.2
Range Range Rule
Several fabs have asked for “range-range” rules. These rules define
spacing that depends on the widths of both nearby objects rather than just
the maximum width of either object.
LEF Example
SPACING 0.3 RANGE 0.2 0.5
SPACING 0.2 RANGE 0.2 0.5 RANGE 0.0 0.19
Range Range Rule (continued)
Example of Range Range Rule
SPACING 1.00 RANGE 7.00 999.00 RANGE 0.00 1.99 ;
1.00
<2
1.20
Wire <4
1.70
<7
Width >= 7.00

Range Range Rule (continued)
LEF Example
SPACING 0.20 ;
SPACING 0.60 RANGE 3.00 4.00 RANGE 1.01 2.99 ; Range Range spacing
SPACING 0.80 RANGE 3.00 4.00 ; needs to be smaller
than Range spacing.
SPACING 1.40 RANGE 4.00 7.00 ;
SPACING 1.00 RANGE 7.00 999.00 RANGE 0.00 1.99 ; Width range has to be
SPACING 1.20 RANGE 7.00 999.00 RANGE 2.00 3.99 ; increased
SPACING 1.70 RANGE 7.00 999.00 RANGE 4.00 6.99 ; monotonically.
SPACING 2.00 RANGE 7.00 999.00 ;
Note: Range Range Spacing overrides Range Spacing and must specify smaller
spacing and can’t be mixed with the SPACINGTABLE syntax, that is, no
parallelRunLength.
Floating Metal Area Definitions
MAXFLOATINGAREA maxArea
Means a single floating metal shape must have a total area less than
or equal to maxArea.
Floating metal is defined as metal that cannot trace a path to diffusion.
The rule depends on the existing LEF MACRO PIN
ANTENNADIFFAREA and ANTENNAGATEAREA statements to
indicate which pins are connected to diffusion or polysilicon-gates.
CONNECTED
If the CONNECTED keyword is given, the areas of the floating metal
shapes connected by lower layers are added and the sum is compared
to maxArea, rather than having each area checked separately.
Max Floating Area
 Floating Metal Area (FMA) is used for a metal shape not connected to
a diffusion or poly-silicon gate.
 Avoids shorts between floating and non-floating wires caused by arcing due
to charge build-up during layer processing.
 Similar to process antenna, it applies to the current layer and any lower
layers.
Floating Metal Area (FMA) Inputs
New LEF 5.7 LAYER ROUTING syntax:
[MAXFLOATINGAREA maxArea [CONNECTED] ; ]
Property Version
“MAXFLOATINGAREA maxArea
{SINGLELAYER | CONNECTED | ALLCONNECTED}
minRoutingLayer maxRoutingLayer
[[LAYERS minRoutingLayer maxRoutingLayer]
SPACING minSpacing [PARSPACING minParSpacing
minParallelLength ...]] ...
;" ;
FMA Example
M3_1 metal3
metal2
M2_1 M2_2 M2_3
grounded
metal1 M1_1 M1_2 M1_3 metal
floating metal floating Gate
Diffusion
Charge can bleed off

through diffusion.
CONNECTED floating area = M2_1 + M2_2
M2_1 M2_2 M2_3
45 nm Design Rule Support
End of line
SPACING eolSpace ENDOFLINE
eolWidth WITHIN eolWithin
[PARALLELEDGE parSpace
WITHIN parWithin [TWOEDGES] ];
45 nm Design Rule Support (continued)
Example of End-of-line Spacing Rule
PROPERTYDEFINITIONS
LAYER LEF57_SPACING STRING ;
…
LAYER Metal1
TYPE ROUTING ; 0.7
SPACING 1.00 ; 1.5
WIDTH 1.00 ;
1.4
PROPERTY LEF57_SPACING "SPACING 1.5 ENDOFLINE 1.0
1.3 WITHIN 0.7 PARALLELEDGE 1.4 WITHIN1.0 ;" ;
END Metal1
<1.3
MINSTEP … ADJACENTLENGTH
1.0 1.0
This is a same-corners edge.
0.5 0.5 1.0
0.5 0.5 0.5
0.8 0.8
1.1 1.0 1.0
a) Violation: an edge < b) OK: all edges < c) Violation. The edges
0.6um long has < 0.6um long have >= < 0.5um have an
1.0um adjacent edges. 1.0um adjacent edges.. adjacent edge < 1.0um.
Example 2: PROPERTY LEF57_MINSTEP

“MINSTEP 0.6 MAXEDGES 1 MINADJACENTLENGTH 1.0 ;” ;
Parallel overlap Cut layer spacing
SPACING 0.095 ; #diff-net cut-spacing
SPACING 0.07 SAMENET ; #same-net cut-spacing
SPACING 0.11 PARALLELOVERLAP ; #cut-spacing for paralleloverlap, unless same metal
Parallel overlap spacing

0.11
Same-net
spacing 0.07
Cuts connected in
Cuts NOT connected in
same wire
same wire
Cut Spacing and Stacked Vias
LAYER via1 LAYER via2

SPACING 0.12 ;
SPACING 0.12 ;
SPACING 0.12 LAYER via1 ;
SPACING 0.1 SAMENET ;
SPACING 0.1 SAMENET LAYER via2 STACK;
END via1
END via2
32 nm Rule Support for addViaFill
Description
 Support CUTCLASS in 32 nm LEF rule
Notes
VIA selecting procedure for addViaFill to fill in one white space
 Check the vias and VIARULEs defined by –includeVia.
 Check the vias defined in LEF.
 Try to generate via by VIARULEs defined in LEF.
 Sort available via list and found the VIA has maximum cut number.
 Sort by cut ratio (cut area/via box area) for same cut number VIAs and
try to insert maximum cut ratio via.
32 nm Rule Support for addViaFill (continued)
1. Cut layer adds CUTCLASS:
[CUTCLASS className WIDTH viaWidth [LENGTH viaLength] [CUTS numCut] ;]
2. Cut layer SPACINGTABLE adds CUTCLASS:

[SPACINGTABLE
[ ORTHOGONAL {WITHIN cutWithin SPACING orthoSpacing} ... ;
| [DEFAULT defaultCutSpacing] [SAMENET|SAMEMETAL] [LAYER secondLayerName]
[CENTERTOCENTER { {className1|ALL} TO {className2|ALL} }…]
CUTCLASS { {className1|ALL} [SIDE|END]}…
{ {className2|ALL} [SIDE|END] {-|cutSpacing} {-|cutSpacing}…}… ; ]
;]
3. Cut layer ENCLOSURE adds CUTCLASS, EXTRACUT:

[ENCLOSURE [CUTCLASS className] [ABOVE | BELOW] overhang1 overhang2
…
;]
4. Routing layer SPACINGTABLE adds PARALLELSPANLENGTH:

[SPACINGTABLE PARALLELRUNLENGTH {length} ... {WIDTH width {spacing} ...} ... ;
[SPACINGTABLE
PARALLELSPANLENGTH PRL runLength {SPANLENGTH spanLength {spacing} ...}…;
|…
];
32 nm Rule Support for addViaFill (continued)
VXLRG
VXLRG
0.09
VXBAR
0.09 VXBAR
a) Violation, spacing < 0.10 between end b) OK, no parallel edge overlap > 0 with the end edge of
edge of a VXBAR via and a VXLRG via VXBAR
VXLRG
VXLRG
0.09
VXBAR 0.09
VXBAR
c) OK, no parallel edge overlap > 0 with the end d) OK, no parallel edge overlap > 0 with the end
edge of VXBAR. Violation if non parallel edge edge of VXBAR. Violation if non parallel edge
overlap value is 0.10 also overlap value is 0.10 also
Example of: SPACINGTABLEDEFAULT 0.08

CUTCLASS VXBAR SIDE VXBAR END VXLRG
VXBAR SIDE - - - 0.12 - -
VXBAR END - 0.12 - 0.12 - 0.10
VXLRG - - - 0.10 0.11 0.11 ;
Cross-Via Support in addViaFill
Description
 Support via with different size of top and bottom metal
 Fix via with different geometry of top and bottom metal
 Generated due to setMetalFill setting, where no overlap range
 Generated due to VIARULE defined
Example of fix VIA

VIA V45_dummy DEFAULT
LAYER M4 ;
RECT -0.20000 -0.20000 0.20000 0.20000 ;
LAYER W0 ;
RECT -0.0700000 -0.0700000 0.0700000 0.0700000 ;
LAYER B1 ;
RECT -0.40000 -0.40000 0.40000 0.40000 ;
RESISTANCE 1.500000 ;
END V45_dummy
Multi-Via Support in addViaFill
Description
 To meet the minimum density request, addViaFill adds multi-via in the
white spacing.
 The spacing of the dummy via is controlled by gapSpacing of
setMetalFill setting.
Example
gapSpacing
gapSpacing
32 nm Rule Support for addMetalFill (continued)
Description
 addMetalFill will insert VIA for connection with option–nets.
 CUTCLASS and related LEF rules will be checked for VIA adding.
Simplify Logging for addMetalFill
Description
 Clear information provided on timing-aware mode, P/G nets, signal
nets and clock nets.
 Generate <top>.metalfill.rpt to report metal fill results.
 Metal fill setting and density report (before/after metal fill) will be
included in the <top>.metalfill.rpt.
32 nm Rule Support
Description/Benefit: To support 32 nm rules in power planning and
routing.
 Support only for cut-to-cut and cut-to-metal spacing for the new
CUTCLASS statement
 CUTCLASS will be supported for following syntaxes in LEF
 ENCLOSURE
 ADJACENT CUTS
 ARRAY SPACING
 MINIMUMCUT
 SPACING TABLE
 AddRing, AddStripes, editPowerVia, and SRoute commands support

the new syntax.
 New syntax will be supported through PROPERTY definition
statements only in LEF5.8.
32 nm Rule Support (continued)
Syntax
 CUTCLASS Statement
 CUTCLASS syntax is used to define the cut classes that different type of cut vias belong to.
 Syntax
 [CUTCLASS className WIDTH viaWidth [LENGTH viaLength] [CUTS numCut] ;] …
 Cut layer SPACINGTABLE adds CUTCLASS

 Syntax
PROPERTY LEF58_SPACINGTABLE
“SPACINGTABLE
[ ORTHOGONAL
{WITHIN cutWithin SPACING orthoSpacing} ... ;
| [DEFAULT defaultCutSpacing]
[SAMENET|SAMEMETAL]
[LAYER secondLayerName]
[CENTERTOCENTER { {className1|ALL} TO {className2|ALL} }…]
CUTCLASS { {className1|ALL} [SIDE|END]}…
{ {className2|ALL} [SIDE|END] {-|cutSpacing} {-|cutSpacing}…}… ;
]
;“;
 Cut layer ARRAYSPACING adds CUTCLASS
 Syntax
[ARRAYSPACING [CUTCLASS className] [PARALLELOVERLAP]
[LONGARRAY] [WIDTH viaWidth] CUTSPACING cutSpacing
{ARRAYCUTS arrayCuts SPACING arraySpacing} …
;]
 Cut layer ENCLOSURE adds CUTCLASS
 Syntax
[ENCLOSURE [CUTCLASS className] [ABOVE | BELOW] overhang1
overhang2
[ WIDTH minWidth
[EXCEPTEXTRACUT cutWithin [NOSHAREDEDGE] ]
| LENGTH minLength
| EXTRACUT
| REDUNDANTCUT cutWithin ]
;] …
Cut layer ARRAYSPACING adds CUTCLASS in ADJACENTCUTS
Syntax
“SPACING cutSpacing
[ MAXXY
| [CENTERTOCENTER]
[ SAMENET | SAMEMETAL | SAMEVIA ]
[ LAYER secondLayerName [STACK]
| ADJACENTCUTS {2 | 3 | 4} WITHIN cutWithin
[EXCEPTSAMEPGNET] [CUTCLASS className]
| PARALLELOVERLAP [ EXCEPTSAMENET | EXCEPTSAMEMETAL |
EXCEPTSAMEVIA ]
]
;“ ;
MINIMUMCUT in CUTCLASS
Syntax
PROPERTY LEF58_CUTCLASS
“CUTCLASS className WIDTH viaWidth [LENGTH viaLength] [CUTS numCut]
Use Model
 Supported through PROPERTY syntax
LEF Generation
The generateLef command translates Synopsys technology files and older
LEF files to an optimal LEF. This command uses via generation and track
generation utilities. It can generate optimal vias for both DEFAULT and
NONDEFAULT rules.
This command provides a baseline LEF for the current version of the
Encounter software. Optimization can gain over 2x improvement in run time
and accuracy. Allows quick migration to future versions of LEF.
Syntax
generateLef {-lefFile lefFileName | -techFile
technologyFileName -clfFile clfFileName | -lefFileList
{technology.lef cell1.lef cell2.lef ...}} [-useVia {viaName |
viaRuleName}] [-2cutVia {yes | no}] [-altVia {yes | no}] [-
noWE] outputLefFileName
Use the 2cutVia {yes | no} option to specify double-cut vias. Default: Automatically generates
double-cut vias if a MINIMUMCUT statement is provided.
Use the -altVia {yes | no} option to specify alternative (hammerhead) vias. Default: yes
Use -clfFile clfFileName to specify a Milkyway CLF input file. You must also specify the
-techFile parameter when you specify this parameter.
Use the -lefFile lefFileName option to specify a LEF input file.
Use the -lefFileList {technology.lef cell1.lef cell2.lef ...} option to specify a list of LEF files
to read into the software to use for generating vias with different orientations, extensions, and
offsets. The first file in the list must be the technology LEF file.
Use the -noWE option to generate a new set of vias to replace current LEF vias that do not
contain built-in wire extensions.
Implementation Details
Appendix E
February 3, 2011
I/O File Syntax for Pins inside Core
To save and reload an IO file with syntax to support pins that are inside the
core boundary and not the periphery run the following commands:
saveIoFile –locations <FileName>
loadIoFile <FileName>
Inside
core pins
Example I/O File:

(iopin
(up
(pin name="io_1" x=2455.4700 y=4049.1000 layer=8
width=0.5400 depth=0.5400 )
(pin name=“io_2" x=2455.4700 y=4101.9000 layer=8
width=0.5400 depth=0.5400 )
(pin name=“io_3" x=2455.4700 y=4154.7000 layer=8
width=0.5400 depth=0.5400 )
I/O File Support for Multiple Corner Cells
The software supports multiple corner cells in each corner on one ring,
overlapping each other.
Example I/O File
(globals
version = 3
io_order = default
)
(row_margin
(top
(io_row ring_number=1 margin=137.0000)
)
(left
)
(bottom
)
(right
)
)
(iopad
(topright
(inst name="MON@0004" orientation=R0 cell="ZMGACS101NRW_40SPS" )
(inst name="CNR@0004" orientation=R0 cell="ZCGLSNEISAXX0" )
)

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Floorplanning, Physical Synthesis,

and Place and Route (Flat)

Allegro® Incisive® Silicon Express™

ii Cadence Design Systems, Inc. 2/2/2011

iSection 1: Floorplanning, Placement, and Trial Route

Module 1 About This Course .................................................................................... 3

Module 2 Encounter Digital Implementation (EDI) Overview .............................. 25

Module 3 Design Import and Customizing the EDI Environment ........................ 39

Module 4 Selecting and Highlighting Objects in the Design ............................... 59

Module 5 Floorplanning the Design ....................................................................... 69

Module 6 Planning Power ..................................................................................... 119

Module 7 Routing Power with Special Route ...................................................... 145

Module 8 Running Detail Placement .................................................................... 157

Module 9 Scan Optimization and Reordering ..................................................... 193

Module 10 Analyzing Route Feasibility with Trial Route ...................................... 205

2/2/2011 Cadence Design Systems, Inc. iii

Module 11 Extracting Parasitics and Analyzing Timing ...................................... 219

Module 12 Multi-Mode Multi-Corner Analysis ...................................................... 253

Module 13 Optimizing and Closing Timing ........................................................... 281

Module 14 Implementing the Clock Tree .............................................................. 311

Module 15 Analyzing Power ................................................................................... 355

iv Cadence Design Systems, Inc. 2/2/2011

Module 17 Evaluating Routing Problems .............................................................. 413

Module 18 Wire Editing ........................................................................................... 431

Module 19 Preventing and Fixing Signal Integrity Problems .............................. 447

Module 20 Metal Fill ................................................................................................. 465

Module 21 Verification ............................................................................................ 475

Module 22 Engineering Change Order (ECO) ....................................................... 493

Module 23 Writing Out a Design ............................................................................. 517

Module 24 Encounter Database Access Commands ........................................... 525

Module 25 Foundation Flow Scripts ...................................................................... 537

Appendix A Setting Constraints Using SDC ............................................................ 551

Appendix B Pipeline Register Placement ................................................................ 569

Appendix C Encounter Parallel Processing ............................................................ 577

Appendix D Nanometer Design Rule Support ......................................................... 583

Appendix E Implementation Details ......................................................................... 629

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iSection 1: Floorplanning, Placement, and Trial Route

 Place and route concepts

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ASIC: Application-specific integrated chip

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2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 7

 Analyzing and Optimizing for

 Verifying the Design

 Using Encounter Database Access

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 8

 Analyzing and Optimizing for Signal

 Using Encounter Database Access

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 10

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 11

For more information about Cadence® courses:

 Cadence Online Support: Accessing documents and support

 Cadence Community: Staying current with tips and tricks

 The Encounter commandGetIt standalone utility

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 12

 The command line: cdnshelp

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 13

 Software updates for Cadence

2/3/11 Floorplanning, Physical Synthesis, and Place and Route (Flat) 14

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