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Unit I:
INTRODUCTION TO 8086 MICROPROCESSOR
Introduction to 8086, Pin diagram, Architecture,
addressing mode and Instruction set
2
What is Microprocessor?
3
Microprocessor Functional blocks
5
Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
7
8086 Microprocessor
Pins and Signals Common signals
MN/ MX
MINIMUM / MAXIMUM
TEST
READY
RESET (Input)
CLK
Segment
Registers
14
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
15
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
16
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
17
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
18
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
19
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
20
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 21
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
22
8086 Microprocessor
Architecture Execution Unit (EU)
23
8086 Microprocessor
Architecture Execution Unit (EU)
Example:
24
8086 Microprocessor
Architecture Execution Unit (EU)
25
8086 Microprocessor
Architecture Execution Unit (EU)
26
8086 Microprocessor
Architecture Execution Unit (EU)
27
8086 Microprocessor
Architecture Execution Unit (EU)
28
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
8. String Addressing
37
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) 0A9FH
12. Implied Addressing
38
8086 Microprocessor
Addressing Modes : Memory Access
1. Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
42
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA +1)
43
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(AL) (MA)
44
(AH) (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA + 1)
45
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
46
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing
50
INSTRUCTION SET
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
3. Logical Instructions
52
8086 Microprocessor
Instruction Set
53
8086 Microprocessor
Instruction Set
54
8086 Microprocessor
Instruction Set
56
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD A, data
57
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADDC A, data
58
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SUB A, data
59
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SBB A, data
60
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
61
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
62
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
63
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
64
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
65
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
66
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP A, data
67
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
68
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
69
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
70
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
71
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
72
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
73
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
74
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
75
8086 Microprocessor
Instruction Set
76
8086 Microprocessor
Instruction Set
REP
77
8086 Microprocessor
Instruction Set
MOVS
(MAE) (MA)
78
8086 Microprocessor
Instruction Set
CMPS
79
8086 Microprocessor
Instruction Set
LODS
81
8086 Microprocessor
Instruction Set
STOS
82
8086 Microprocessor
Instruction Set
CLC Clear CF 0
NOP No operation
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
84
8086 Microprocessor
Instruction Set
Checks flags
85
8086 Microprocessor
Instruction Set
Mnemonics Explanation
JC disp8 Jump if CF = 1
JP disp8 Jump if PF = 1
JO disp8 Jump if OF = 1
JS disp8 Jump if SF = 1
87
Assembler directives
8086 Microprocessor
Assemble Directives
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
89
8086 Microprocessor
Assemble Directives
DB Define Byte
PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 90
8086 Microprocessor
Assemble Directives
DB Define Word
PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 91
8086 Microprocessor
Assemble Directives
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS
SHORT
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 93
8086 Microprocessor
Assemble Directives
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 94
8086 Microprocessor
Assemble Directives
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…
DB
Examples:
DW
RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP
SHORT
MACRO
ENDM 96
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 97
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 98