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Starting questions:
– do we need dynamically reconfigurable architectures for security?
– do we need it for performance reasons, i.e. better execution time, less power
or energy, smaller area?
– or do we need it to improve secure implementations? meaning to protect
implementations from attacks?
– does dynamically reconfigurable architectures hurt or help security?
The three main open research problems as conclusion of the panel:
1. IP protection, IP distribution, evaluation etc. in a trusted and secure way.
The more reconfigurable, remote reconfigurable, dynamically reconfigurable
an architecture becomes, the more urgent this problem becomes.
2. Secure remote update. This holds for FPGA reconfigurations as well as em-
bedded SW (both are "soft")
3. API’s and interfaces between HW & SW. HW becomes softer, SW intermixed
with HW.
However, using DPR means struggling with architectural details of the used
FPGAs and the according synthesis and implementation tools. A developer
would focus most of the time on DPR and only a small part of the time on
the implementation of the actual modules - of course that is the opposite of
what hardware engineers want to do.
The second trend concerns the way hardware is described. Many hardware
developing groups are looking forward to an HDL which operates on the algo-
rithmic level, since this would come with a significant increase in productivity.
The aim is to be able to translate common software algorithms to hardware in
an efficient way (which is called high-level synthesis or HLS).
Although both DPR and HLS are important future trends regarding hard-
ware design, they develop quite independently. Today’s software-to-hardware
compilers focus on conventional hardware and therefore have to remove dy-
namic aspects such as the instantiation of calculating modules at runtime. Even
object-oriented languages like SystemC do not support the dynamic instantia-
tion of objects (that means the usage of new or delete outside of the constructor)
for synthesis at all. On the other hand, DPR tools are working on the lowest pos-
sible layer regarding FPGAs: the bitfile level. Our research focuses on the design
and the implementation of a Framework combining the two technologies, since
this has the potential to kill two birds with one stone. Firstly, DPR can change
the programming paradigm in future HDLs regarding dynamic instantiations.
Dynamic parts would not have to be removed any longer but could be realized
on the target FPGA using DPR. Secondly, a high-level language support of DPR
technologies could help end its shadowy existence and turn it into a commonly
used method.
Keywords: FPGA, DPR, HLS, Object-Orientation
Full Paper: http://drops.dagstuhl.de/opus/volltexte/2010/2836
See also: Norbert Abel, Design and Implementation of an Object-Oriented
Framework for Dynamic Partial Reconfiguration, FPL 2010, Milano, Italy, Au-
gust 2010
this may depend on the input data for the application. Here, it would be de-
sirable that the information about the actual application/system requirements
that are only available during run time would be used to determine which re-
configurations should be performed.
In this talk, concepts and strategies are presented to increase the run-time
adaptivity of reconfigurable processors significantly. As foundation, a novel hi-
erarchical composition of Special Instructions is presented that allows switch-
ing between different performance/area trade-offs efficiently during run time.
To determine which trade-off shall be chosen (and thus, to provide adaptivity),
light-weight approaches for online monitoring, dynamic instruction-set selection,
reconfiguration-sequence scheduling, and accelerator replacement are discussed
and a comparison with state-of-the-art reconfigurable processors is provided.
Joint work of: Bauer, Lars; Shafique, Muhammad; Henkel, Jörg
Traditionally special functional units for each application are developed sepa-
rately. These are plugged to a general purpose processors to extend its instruction
set making it an application specific instruction set processor. As this strategy
reaches its boundaries in area and complexity reconfigurable architectures pro-
pose to be more flexible. Thus combining both approaches to a reconfigurable
application specific processor is going to be the upcoming solution for future
embedded systems.
Keywords: reconfiguration, ASIP, RASIP, low power, high performance, video
encoding, encryption, wireless sensor node, mobile device
Joint work of: Hanke, Matthias; Kranich, Tim; Berekovic, Mladen; Papaefs-
tathiou, Yannis
Full Paper: http://drops.dagstuhl.de/opus/volltexte/2010/2837
For example the utilized chip area and the location for a dynamic area on
the chip is traditionally fixed during design-time. Thereby the shape and the
size of the area is fixed by the largest module. If a smaller module is placed
on the region of a bigger one, chip area remains unutilized. These restrictions
are only some examples for the current status for the support of development
and run-time tools for reconfigurable hardware architectures. A new approach
is will be presented for exploiting the full capability of reconfigurable hardware
architectures more efficiently than traditional solutions. This is achieved by a
new concept of using micro blocks for the communication infrastructure as well
as for the functional elements on the FPGA. In addition, a Mesh-based Network
on Chip (NoC) which is specifically designed for the constraints given by the
FPGA completes this approach. This paper will present the current status of
this approach and provides some ideas about the possible tool chain to support
designers in creating such a PDR system.
We discuss the role of FPGAs in the near future and some challenges for them
to reach the general purpose arena.
Keywords: Software ccompatibility, reconfigurable general purpose processing
Our recent work on how to use reconfigurability to alleviate the problems caused
by process variation and degradation is presented. Techniques for efficient online
delay measurement that allow us to characterize the delay of any path on an
FPGA with pico-second resolution is described.
Dynamically Reconfigurable Architectures 7
The motivation for and preliminary results on the dilated placement of com-
munication task graphs into a regular network topology will be described. Fur-
ther work will be discussed.
Keywords: Placement, Dynamic reconfiguration, Run-time support
Joint work of: Diessel, Oliver; Hredzak, Branislav
The FPGA research community can improve the level of contributions, enable
meaningful comparisons, and promote reuse by creating incentives for imple-
menters to share their source code and datasets at the time of publication. In
order to do so, we should add a reproducibility scale and score to manuscripts’ re-
view process so that the effort for creating reproducible research is appropriately
rewarded – this score could, in some cases, compensate for low originality scores.
Further, a committee of academic and industry members should be formed to
guide implementers and reviewers of common pitfalls and how to report results
in a way that helps meaningful evaluations. This guide will be continuously up-
dated. Specifically in the FPGA security field, interesting topics to explore are
Dynamically Reconfigurable Architectures 9
scheduling of the tasks, the resource management and the configuration of the
system at runtime. This talk will present the RAMPSoC approach, the current
status of the design methodology and the CAP-OS.
Keywords: Reconfigurable Computing, Multiprocessor Systems, Design Method-
ology, Programming model
Computing has to be re-invented because of two main problem areas, both being
related to power efficiency. Technical limits of power dissipation per processor
chip caused the transition to multicore architectures. Financial limits will be
reached within about a decade or slightly more by rising energy prices and rapid
growth of the electricity consumption of the entirety of all kinds of computers
everywhere worldwide. If we do not find a timely effective solution we will run
into a severe economic crisis.
A key issue is the tremendous inefficiency of what we call "software", i. e.
running on instruction-stream-driven architectures. Improvements by orders of
magnitude can be obtained by migration to data streams in the context of mas-
sive software to configware migrations. Data-stream-driven reconfigurable archi-
tectures are useful by providing the basis to reinvent computing for avoiding the
future unaffordability of its electricity bill. The talk discusses how to implement
a rescue campaign.
Keywords: Power-efficiency, overhead, paradigm shift
With the increasing process variations in advanced technologies, delay defects are
gaining a larger impact on FPGA timing yield. If the delay defect areas can be
quickly and accurately located, FPGA timing yield can be improved by avoiding
them. Conventional delay testing methods do not take into account the spatial
information of variability-induced delay faults, thus cannot accurately locate the
delay defects to a well restricted areas. Based on the superb locality preserving
12 Peter M. Athanas, Jürgen Becker, Jürgen Teich and Ingrid Verbauwhede
Scaling technology enables even higher degree of integration for FPGAs, but
also brings new challenges that need to be addressed from both the architec-
ture and the design tools side. Optimization of FPGA interconnection network
is essential, given that interconnects dominate logic. Two approaches are pre-
sented, with one based on the time-multiplexing of wires and the other using
hierarchical interconnects of high-speed serial links and switches. Design tools
for both approaches are discussed. Preliminary experiments and prototypes are
presented, and show positive results.
Keywords: field-programmable gate array, architecture, computer-aided design
In this talk I will briefly introduce the concept of AMIDAR processors. AMIDAR
stands for adaptive microinstruction driven architecture. It forms a good basis
for processors that can be reconfigured on the fly at runtime. I will then show
recent results of our research (what speedup can we achieve, how many resources
are required for this).
The main part of my talk will be focused on the simulator that we use to
carry out our experiments. I will show its structure and I will give a short live
presentation, where I let different code fragments run with varying parameters.
Keywords: Online Adaptivity, Coarse Grain Reconfigurable Array, Reconfig-
urable Processor, AMIDAR
Dynamically Reconfigurable Architectures 13
With passing over the 1M LUT barrier, FPGA technology is heading into new
challenges and opportunities. While the present ASIC-like design methodology
and tools will struggle to scale with such huge devices, providing partial run-time
reconfiguration will be become obligatory for dealing with long configuration
times and the increasing vulnerability to single event upsets.
Within the COSRECOS project, we address these issues by developing meth-
ods and tools that allow to compose systems rapidly by plugging together fully
physically implemented components. Moreover, by allowing a hot-swapping of
Dynamically Reconfigurable Architectures 15
This paper presents a solution for secure remote reconfiguration of FPGAs. Com-
municating the bitstream has to be done in a secure manner to prevent an at-
tacker from reading or altering the bitstream. We propose a setup in which the
FPGA is the single device in the system’s zone-of-trust. The result is an FPGA
architecture that is divided into a static and a dynamic region. The static re-
gion holds the communication, security and reconfiguration facilities, while the
dynamic region contains the targeted application.
Joint work of: Mentens, Nele; Vliegen, Jo; Braeken, An; Touhafi, Abdellah;
Wouters, Karel; Verbauwhede, Ingrid
Full Paper: http://drops.dagstuhl.de/opus/volltexte/2010/2839
A PUF can be used to extract a non-volatile secret key from an FPGA fabric
by exploiting process manufacturing variations. In this talk, we present the re-
quirements for the implementation of Physical Unclonable Functions in FPGA.
They include security requirements, such as the nature and the amount of
challenge/response pairs in the PUF. The also include quality metrics such as
Uniqueness and Reliability. The focus of the talk is on three observations related
to the implementation of PUF in FPGA. First, we note that a PUF should be
analyzed in terms of the population of chips, not in terms of a single design.
Second, we note that most existing PUF architectures do not map well into
the FPGA fabric. Third, we point out that the use of PUF as a root-of-trust in
non-volatile FPGA is very tricky, and requires an access-protected bitstream.
Keywords: Hardware Security, Physical Unclonable Functions, Authentication
18 Peter M. Athanas, Jürgen Becker, Jürgen Teich and Ingrid Verbauwhede
Today the hardware for embedded systems is often specified in VHDL. However,
VHDL describes the system at a rather low level, which is cumbersome and may
lead to design faults in large real life applications. There is a need of higher level
abstraction mechanisms.
In the embedded systems group of the University of Twente we are working
on systematic and transformational methods to design hardware architectures,
both multi core and single core. The main line in this approach is to start with a
straightforward (often mathematical) specification of the problem. The next step
is to find some adequate transformations on this specification, in particular to
find specific optimizations, to be able to distribute the application over different
cores. The result of these transformations is then translated into the functional
programming language Haskell since Haskell is close to mathematics and such a
translation often is straightforward. Besides, the Haskell code is executable, so
one immediately has a simulation of the intended system.
Next, the resulting Haskell specification is given to a compiler, called CëaSH
(for CAES LAnguage for Synchronous Hardware) which translates the spec-
ification into VHDL. The resulting VHDL is synthesizable, so from there on
standard VHDL-tooling can be used for synthesis. In this work we primarily fo-
cus on streaming applications: i.e. applications that can be modeled as data-flow
graphs.
At the moment the CëaSH system is ready in prototype form and in the pre-
sentation we will give several examples of how it can be used. In these examples
it will be shown that the specification code is clear and concise. Furthermore,
it is possible to use powerful abstraction mechanisms, such as polymorphism,
higher order functions, pattern matching, lambda abstraction, partial applica-
tion. These features allow a designer to describe circuits in a more natural and
concise way than possible with the language elements found in the traditional
hardware description languages.
In addition we will give some examples of transformations that are possible
in a mathematical specification, and which do not suffer from the problems
encountered in, e.g., automatic parallelization of nested for-loops in C-programs.
Or, will we see architectures with Islands of individual FPGA modules being
interconnected by a high speed network on a chip (NoC)? Or, will fine grain
reconfigruable architectures such as FPGAs vanish in the era of 1000 processors
on a chip?
We try to give a prognosis based on other currently available technology such
as GPUs and discuss possible architectural evolutions based on the dominating
factors of a) efficiency, b) flexibility (programmability) and c) productivity.
The Mojette transform (MOT) is an exact discrete Radon transform defined for
a set of specific projections. This method was introduced by Jean-Pierre Gué-
don, although it is a simple transform using only additions, but it can be used
from image processing applications up to distributed databases due to its prop-
erties. These properties will be introduced not only for the Mojette but also for
the Inverse Mojette transform (IMOT). The paper presents the implementations
of the transform in .NET environment and based on different projections and
different realizations. Afterwards the HW implementation of the Mojette with
FPGA is introduced and compared in speed computation with other implemen-
tations. Also describes possible applications of the Mojette transform in mobile
communications on a simple example of a movie rental system with different ap-
proaches, to make it possible for the users to watch clips, trailers or even movies
while they are not at home.
Keywords: Mojette transform, Secutrity, distributed databases, image process-
ing
Joint work of: Vasarhelyi, Jozsef; Szoboszlai, Peter; Serfözö; Peter, Turan, Jan
Full Paper:
http://www.ieeexplore.org
Full Paper:
http://www.iccc.uni-miskolc.hu
See also: 53. Serfözö P., Vásárhelyi, J., Szoboszlai P., Turan, J.; Performance
requirements of the Mojette transform for internet distributed databases and
image processing, IEEE OPTIM 2008. 11th International Conference on Opti-
mization of Electrical and Electronic Equipment, 2008., Brasov, Romania, IEEE
Digital Object Identifier 10.1109/OPTIM.2008.4602504, 22-24 May 2008 pp.:87
- 92;
Dynamically Reconfigurable Architectures 23