8251A PROGRAMMABLE COMMUNICATION INTERFACE 1 Synchronous and Aeynehronous Asynchronous Baud Rate—DC to 192K Operation Baud 1 Synchronous 5-0 BI Characters 1 Ful-Dupiox, DovbleButtored iernl or External Character Sranemtier and Receiver Synchronization; Automate Syne 1 ror Detection—Paty, Overun and Framing ‘Compatible with an Extended Range of Intel Microprocessors = Asynchronous 5-8 Bit Characters; Clock Rate—t, 16 or 64 Times Baud Rate; Break Character Generation; 1, 1Yfy oF 2 Stop Bits; False Start Bit = 25-Pin DIP Package Detection; Automatic Break Detect and All Inputs and Outputs are TTL Handling Compatioie = Synchronous Baud Rate—DC to 64K Available in EXPRESS and Military Baud Versions ‘The Intel 8251A is the industy standard Universal Synchronaus/Asynchronous. Receiver/Transmiter (USAF, dosigned or data communications wih Intals microprocessor families such as MCS-#8, 80,85, anc IAPX.88, 88. The 8251A is used as a peripheral davice and is programmed by the CPU to operate using ‘idwally any serial data transmission technique presently in use (inciuding IBM “bi-sync’). The USART accepts dala charactors trom the CFU in parallel format and than conver thom into continuous serial data stream for transmission. Smuitaneously, can recelve serial data streams and convert them ino paral data cherac- {ars for tho CPU. Tho USART will signal the CPU whanaver It can accopl a now charactor for Vansmnissian ot whenever thas received a characte for the CPU. The CPU can read the complete status ofthe USART at any timo. Theso include data vansmission exfors and contol signals such as SYNDET, TxEMPTY. Th chip is fericaed using te’ igh performance HIMOS technol. al “= fel) fat any ss rnov Figure 2. Pin Configuration Figure 1. Block Diagram p!conamonaan empha styoan cdy tn ai pas Ne tet82518 FEATURES AND ENHANCEMENTS ‘The 8251A Is an advanced design of the industry standard USART, the Intel 8251. The 825A oper ales with an oxtondod tango of Into! microproces. Sore and mainiaine compatibily withthe 6257. Fa trllertzaion timo 's minal because of eompatilty {and involves oniy knowing the adctional features ‘and enhancements, and reviewing the AC and DC ‘poclications of the 8251. ‘Tho 825%A incorporates all the Koy foatures of the 8251 and has the folowing acalional features and ‘enhancements ‘8251 nas couote-pulereo data patns win sepa: rate I70 registers for conto, status, Data i, and Data Out. which considerably, simaliies. contol programming and mramizos CPU overhead ‘In asynchronous operations, the Racoiver do: tects and handles “break” automaticaly, roley. ing tho CPU of tis task {rom stating when in “break” state, preventing unwanted inlerupis from a disconnected USART. * ‘tho conclusion of a tansmission, Tx0 tne wil ‘anaye return to tho marking elala Uniees SEAK Is programmed, ‘Tx Enable lodc enancement prevents a Tx Dis- able command from halting transmission unl al data previously written has been transmitted, The tegiealee provonte tho tranemittor rom turing ‘off in the mide of @ wore ‘+ When External Syne Detect is programmed, In tomal Sync Detect is disabled, an an External Syne Detect siatus is provided via a fliptlop which cloars ites upon & status road Possbilly of falso syne dotoct is minimized by ‘ensuring that it-double character syne is. pro ‘grammes, the characters be contguously detect {and also by clearing tho Px regstor to all ones ‘whonever Enter Hunt Command i issued in Syme mode ‘As Jong as the 82514 isnot selected, the FD and WR so not allect the internal operation of the dovce, + The 92514 status can ge reas a any ume Butte talus update wil be inhibted during satus read Tho 82574 iste trom extrancous gltchos and has enhanced AC and DG characteristics, prov: Ing higher speed and better operating margins + Synchronous Baud rate from DC to 64K. FUNCTIONAL DESCRIPTION General ‘Tho 8251A is a Universal Synchronous/Asyncheo- nous Roosiver/Tranemitse Cosigned fora vide fango of Intel microcomputers such as 8048, 6080, 085, 8086 and 8088. Like othe: I/O dovoss in & mmiccocompuler system, its functional configurations programmed by the system's software for maximum flowbity. Tho 8251A can support most serial cata techniques in use, neuding IBM “brsync ‘must convat parla format systom cata into seal focmat for vansmission and convert incoming sexal format daca rte parait systorn vata Tor recopten, ‘The interlace devios must also delate or insert bts or characters that aro functionally unique tthe Communication technique. In essence, the interface Should appoar "transparent" to the CFU, a simple input or output of byte-arcnted system data Data Bus Buffer “This Gstat bidrectonal, 8-b buler is used to inter- fava the 8281A to the systom Date Bus, Data is transmites or recived by the bulle upon execution Of INput or OUTputinstrctions of the CPU. Control ‘words, Command words and Slatus information are aso transterod through the Data Bus Buttor. Tho fare separate, 6 registers communicaing withthe system bus through the Data Bus Butler, “This functional block accepts inputs from the system Control bus and generates contol signals for overall Govies operation. I contains the Control Word Flog ister and Command Word Register that store the ‘various contro ormats forthe device funcional del htion RESET (Reset) ‘A “high’ on this input forces the 8251A into an "idle" mode, The device will remain at “ile unt a program its tunetional dition. Minimum RESET pulse widths 6 toy (lock must be runing), ‘A command reset operation also puts the device inta the "ale" slate,82518 cpm =] oe fem t sama, Figure 3. 251A Block Diagram Showing Data Bus Butfer and Rlead/Write Logic Functions CLK (Clock) ‘The CLK input is used to generate internal device timing and is normally comectod to the Phase 2 (TTL) output of tha Clock Gonorater. No external in puts oF outputs are referenced to CLK but the fre ‘quency of CLK must be greater than 30 times the Fecawer oF Transmitter data of rates, WR (Write) (CPU's wetng data or control words to the 82514. RD (Read) ‘Slow’ on tis int infos the 625A thatthe (CPU's reading data or satus Information fom the 251A. [B25TADATA —> DATABUS| DATA BUS —> 825:ADATA /STATUS —> OATABUS DATA BUS —> CONTROL DATA RUS —> aSTATE DATA BUS —> aSTATE C/D (Contro!/Data) “Ths int in conuncin wth the WH ang FO in puls, informs the 82514 that the wors on the Data Basis ether # data character, cordrol word or satus CCONTROLSTATUS; 9 = DATA.82518 TS (Chip Select) ‘A “low on this input selects the 8251A. No reading ‘or writing wil occur unless the device is selected ‘Won CS is high, tho Data Bus isin tho float stato ‘and FD anc WA have no effect on the chip Modem Control ‘The 825%A has a set of contrat inputs and outputs {nal can bo used to simolty the interface to almost fany madem, The modem cont signals are general purpose in nature and can be used fr functions oth Erthan modem sono necessary DSR (Data Set Ready) ‘The DSR input signal is a general-purpose bitin vartiag input ports condition ean be tested by tho (CPU using a Status Foad operation. Tho DSF input |g novmally used to ast madam conditions such a8 Data Sot lady, ‘Tne OTR output signal is a generalpurpose, 7-bit Investing output pot it can be set “iow” by program ming the appropriate Bit inthe Command Instruction word. The BTR output signal is normally used for modem contol such as Data Terminal Ready RTS (Request to Send) ‘The ATS output signal is a goneralpurpose, 1-bit inverting output port itcan bo set "ow" by program ming the appropriate bitin the Command fnsruction ‘word. The RTS output signal is normally used for modem contol such as Request to Sond. CTS (Clear to Send) ‘A“low on this input enables the 6251 to vansmit ‘Serial cata the i enable bein the Command byte ig sat toa “ono”. eer a Tx Enable off or CTS oll Condition occurs while the Txis in operation. the Tx ‘wi warent all the data Ia tho USAR, wren lor {Tx Disable command before shutting down intel. “The Transmitter Butfer accepts peal data from the Data Bus Buller, converts it toa seca bi steam, inserts the appropriate charactors or Bs (o8s0a on the communication technique) and outputs @ com- posits sal siream of data'on tho TaD output pn on the tating e6go of TxC. Tho vansmitir wil begin transmission upon being enabled i CTS ~ 0. The ‘TxD line wil be held in the marking slate immediate Iy upon a master Reset or when Tx Enable or CTS Or the tansmiter is eat. Transmitter Buffer ‘Tranomitter Control ‘The Transmitter Control manages all activities asso- lated wan the tanamisson ot sera aa, Coops fan Issues signals both externally and internally 0 accomplish iis function. ‘TxRDY (Transmitter Ready) “This output signals the CPU that the transmitter is ‘oady to accopt a data character. Tho TsADY output pin canbe used as an intorupt to tho system, since IUis masked by TxEnable; oF, for Polled operation, tho CPU can chock THRIDY using @ Status Reed op” ration. THADY is automatically reset by the leading fedoa of WR when a data character is fnadod trom the CPU, “TaRDY stats Bis not masked by TxEnabio, but wil only indicate the Empty/Full Status ofthe Tx Data Input Hogitor. ‘TE (Transmitter Empty) When the 8251 has no characters to send, the THEMPTY output will go “high”. It resets upon ceiving a charactor from CPU it the transmitter Is hablow. THENPTY romans fugh when tha vans tor ig dablod. TXEMPTY can bo Used to indicate the end of @ transmission mode, so that the CPU nows" when 10 "tur the line aroun inthe hale uplex operational mode. In the Synchronous mode, a “high” on this output indicates that a character has nol been loaded ang the SYNC charactor or characters are about fo be or fre being Wansmitted automatically 9s “les”. Tx EMPTY does not go low whon the SYNC characters fre being shifted out82518 nese Figure 4. 8251A Block Diagram Showing Modem and Transmitter Buffer and Control Functions ‘THC (Transmitter Clock) ‘The Transmitter Clock controls the rate at which the characters to 62 transmited. In the Synchronous twansmission mode, the Bava Rate (1) Is oqual to the THC frequency. In Asynctroncus Wansmission mode, the baud rate is Traction of the afual Tx ffoqueney. A portion of the mede insttucton solocts this factor it can be 1, Yu oF You tho THC. For Example: U1 Baud Rate equals 110 Baus, THC equals 110 He in tho tx mode. ‘TG oquals 1.72 kHz in tho 16x modo. ‘TG equals 7.04 kHz in the 64x mode. ‘The faling edge of THC shits the serial data out of tno 82514, Receiver Buffer ‘The Roceivor accepts soral cata, converts this sox al nput to paral format, checks for bits or charac: {ors that are unique to ths communication technique fand sends an'"assomblec” cheractor to the CPU. ‘Serial daa fs input to FD pin, and is clocked in on the rising edge of FAC. Receiver Control “This functional block manages all recsiverselated actives which consists of the following features, ‘The PD iniiaization circuit prevents the 825°A from mistaking an unusod input line for an active iow data ina inthe "break conation”. Batore starting to focave saial characters on tho RxD lino, avald"1" must fist b@ datocted aller a chip master Reset, ‘Ones ths has been determined, a search fora vali tow (Start i) fs enabled. THs foatre is only active inthe asynchronous mode, and Is only done once foc each master Reset. ‘The False Start bit detection circuit prevents false starts due toa transient noise spike by lst detecting the falling edge and then strobing the normal cantor of tho Start bt (xD ~ fw), Parity error detection sets the corresponding status ot ‘Tho Framing Error status bit is sot ifthe Stop bit is absent at te end of the data byte (asynchrongus mode),82518 RxRDY (Receiver Ready) ‘This output indicates that the 8251A containg a Character that's ready t0 be input to the CPU, FuADY can be connected tothe interupt structure Of the CPU er, for poled operation, the CPU. can ‘hock the condition of AXADY using a Status Read ‘operation. Enable, whon af, holds PxADY in tho Resot Con lon. For Asynchronous mace, 1o sel FXRDY, the FRceiver mist be enablod fo sone a Stert Bit and & Complate character must be assembled and Wane: ferred to the Data Output Register. For Synchronous modo, to sot AXADY, the Recaver must be enabled {nd a character must nish assembly and be lane ferred to the Data Output Register. Fale to road the received charactor from the Fx Data Oulput Register prior to th assembly of the next Fix Data character wil sat ovemun conaton or and the provious charactor wil bo witon over ‘nd ost I tho Rx Daa is bolng road by tho CPU when tho intemal tanster Is occuring, overrun error wil be Sot and tho old charactor wil bo fst, Fx (Receiver Clock) Tho Rocolve Clock contols the rate at which the charactor is 10 be received, In Synecrondus Mode, the Baa Fata (13 is equal to tho actual frequency Of Fx. In Asynctvonous Modo, the Baud Ft is & fraction ofthe actual FXC Frequency. A portion ofthe ‘mode instruction salects ths actor, he OF Yee the Fic. For Example Baud Rate equals 300 Baus, it Fat equals 200 Hein the 1x mode; Rx oquals 4800 a in the 16x modo: aC equals 19.2 kee in the 64x moe Baud Rate equals 2400 Baud, i FxC oquals 2400 He in tho 1x mode: xt oquals $8.4 kez in the 16 moc aC equals 159.6 kez in tne 64 mode. oS) alle | wn «ef sn | Figure 6. €251A Block Diagram Showing Receiver Buffer and Control FunctionsData is sampled into the 8251 on the rsing edge of Fc. Note: In most communication systoms, the 8251A will be handling bath tho eansmission and reception ope. ations of a single ink Consequently, the Receve fand' Transmit Baud Rates wil be the same, Both ‘TRC and FC wil requie identical requencies for this operation and can be tad togetner and con: nected 10 a single frequency source Baud Rate Gonorate) to simpily tho interlace. ‘SYNDET (SYNC Detect/ BRKDET Break Detect) This pins usod in Synchronous Mode for SYNDET and may ba used as eter input or ouput, program ‘able trough the Control Word. Its reset to output mode low upon RESET. Whon used as an output {internal Syne mods), the SYNDET pin will go “high to indleste that the 8251A has located the SYNC 82518 character Inthe Receive mode It the 6251/ Is pro (grammed to use double Sync charactors (b-syne), thon SYNDET wil go “tigh* in the mide of tha last Bit of the second Sync character. SYNDET is auto- matically reset upon a Slalus Read operation, ‘When used as an input (external SYNC detect mode). a positive going signal wil cause tho 825; to start assemiing data. characters on the rising f2dge of the nxt Fa. Once In SYNG, the “high” iroUt sgnal can bo romovod. Whon Exiornal SYNC Detect s programmed, Inlernal SYNC Detect is s- abled BREAK (Async Mode Only) This output will go high whenever the receiver re- mains ow trough two consecutive stop Bit so- ‘quences (nciucng the start bits, dala bis, and party Bil), Break Dotoct may also be road as a Salus bi itis rosat only upon a master chip lest or Fx Data roturring to a one” state t ono j Figure 6, 8251A Interface to 8080 Standard System Bus82518 DETAILED OPERATION DESCRIPTION General ‘The complete functional definition of the 82574 is programmed by the systm’s software. A sot of con- {tol words must bo saat out by the CPU to iiaizo the B25%A to support the desired communications format. These contrel words wil program the: BAUD RANTE, CHARACTER LENGTH, NUMBER OF STOP ITS, SYNCHAONOUS or ASYNCHRONOUS OP. ERATION, EVEN/ODD/OFF PARITY, etc. In tho ‘Syncarondus Made, options are als provid to so lect eithr intemal or external charactor syncheon: zalon, ‘Once programmed, the 8251A is ready to perform is ‘communication functions, ‘The TxADY output Is raised “high to signal the CPU that the 82574 is rady torecove a data character rom the CPU. This fulput (TxADY) is reset automatically when the CPU Wwites @ cheracter Info the 251A. On the other hana, the 82574 recelves serial data from the MO: DEM or 1/0 device. Upon recoving an ante charac for, the FxROY output is raised "high" to signal tho (CFU that the 82514 has a compte character ready for the CPU to fetch. FxROY is rosel automatically ‘pon the CPU eal read operation. ‘The 8251A cannot begin transmission untl tho Tx Enable (Transmitter Enable) bits set in the Com mand Insttucton and it has received 2 Cicer TO ‘Song (CTS) input. The TxD output wil be held in the marking state upon Fes. “nm soon spe character spat ade rete hae Figure 7. Typical Data Block intel. Programming the 82518 Prior to staring data tansmission or reception, the 251A must be loaded with a sot of control words {gonerated by the CPU. Those contol signals deine tho complete functional datntion of the 8257 anc ‘must immeciataly folow a Reset operation internal or external), Tho control words aro spt into two formats 1 Mede Instruction 2, Command instruction Mode Instruction This instuction dofines the goneral_ operational characteristics of the 8251A. I must folow a Reset Operation {internal or external) Once the Moge In- Sltuction has Ben wttan info the 8257 by the CPU, SYNC charactors or Command Instructions may bo writen. Command Instruction ‘Thisinstuction defines a word thats used te control Bath tho Mode and Command Instructions, must conform to a specitied sequence for proper device ‘Operation (soe Figure 7). The Mode Insttucton must bo written immecitaly following a Reset operation, prior to using the 8257A for data communication. ‘All contol words writen inte the @251A aller the ‘Made Intruction wil load the Command instruction Command Instuctions can be wen into the 825° at any tie inthe data block during tho operation of the 825°A, To return fo tho Modo Instucton format, the master Reset bitin the Command Insivuction ‘word can be set to initiate an intemal Reset opera: tion which automaticaly places the 825A back into the Mode Instruction format. Command insiuctions ‘must folow te Mode Insitucton or Syne charactors Mode Instruction Definition ‘Tho 8251A can bo used fr ether Asynchronous or ‘Synchronous dala communication. To undersiana how the Mode Instruction defines the functional op- tration ofthe 825A, the Gesignar can best vow the device as two separate components, one Asyncheo: ous and tho other Synchronous, sharing tha same package, The format detntion can be changed only fitor a master chip Reset. For explanation purposas the two formats wil de Isolate,intel. \Whon partys enabled itis not considered as ono fof tho’ data bits for the purpose of programming word longth, The actual parity bt received on the Fix Data tne cannot be read on the Data Bus, In the case of a programmed character length of loss than 8 Bits, the least signitcant Data Bus bits wil hold the data; unused bits are “don't care” when writing data to the 8251A, and will be "zeros" when ‘eading the data from the 82518 Asynchronous Mode (Transmission) Whenever a data character is sent by the CPU the '825iA automatically adds a Start bit (ow level) 10 lowod by the data bts (east significant bit frst), and the programmed umber of Slop bits lo each char ‘eter. Also, an evan or odd Party bit fs nsartex prior to the Stop bits), a6 defined by the Mode instruc: tion. The characteris then iansmiled a8 a setal data stream on tho TxD output, Tho sorial data is ‘hited out on the faling edge of TXC at arato equal {0 1, the, oF he thal af the TC, 28 dofined by the Mode Instruction. BREAK characters can be contin ously sent to the TxD if commanded 10 do so. 82518 \when no data characters have been loaded into the 8251 tho TxD output romans “righ” (marking) Un less a Break (continously low) has boon pro- grammes. Asynchronous Mode (Receive) “The FD tine is normally high. A fang edge on tis line wiggers tho Boginring of a START it. The valc- tyof ts START itis checked by again tobing ths Bit atts nominal conter (16K oF 84X modo ony). Ita low is detoctod again, tis. a valid START bit, and tho Bit counter wil tart counting. Te bit counter thus Tocates the center of the data its, the pay Bit (tit fists) and the stop Dis. If pay err occurs, the patty oor fag is set. Data and parity bits aro sam pied on tho FxD pin withthe rising edge of the FC: Tra low levels detactod asthe STOP bit tha Fram ing Error flag wil be set. The STOP bit signals the fond ofa charactor. Note thal the receiver requies Only one stop bit, rogaraiess of the rumber of stop bits programmed. Ths charactor is then loaded into the paral 1/0 butfer of tha 82514, Ths RXADY pin is raised fo signal tne CPU that a charactor 's ready to be fotchod. Ita previous charactor has not boon fetched by the CPU, the present character replaces itin the 1/0 butter, and the OVERAUN Error fag Eaieaeaee Figure 8. Mode Instruction Format, Asynchronous Mode82518 Is raised (thus the previous characteris los) All of tho aor lags can be rosot by an E1ror oso In stuction, The occurence of any ofthese exors will not affect the operation of the 8251. ‘Synchronous Mode (Transmission) ‘The TxD output is continuously high unt the CPU ends ts first charactor tothe 82544 which usually isa SYNC character. When the CTS line goes ow, tho ts charactor is savialy transmitted aut Al char factors aro shilee out on the ‘aling e6ge.of TKC. Data is sited out at the same rato as the THC. (Once transmission has started, the data stream at the TaD output must continuo atthe THC rat. I tho (CPU does not provide tho 82574 witha data charac- ter bofore the 8251 Transmitter Butlers Bacome temply, the SYNC characters for charactor iin single SYNC character modo) wil bo automaticaly insortes in the TxD data sroam, In ths caso, tho TXEMPTY pin raised high 1o signal that tho 8251A is ompty fand SYNC characters are being sent oul. THEMPTY does not go low when the SYNC 's being sitec out (600 figure below). The TXEMPTY pin is internally resot by a dala character being wlten into the Basta. necenven nour ye “wore: arate length ie dotnod as 5,6 or 7b the unused is aro so to “rr Figure 9. Asynchronous Mode82518 nu 4 ‘Synchronous Mode (Receive) In this mode, charactor synctronization can inte naly oF externally achieved. the SYNC mode nas ‘boon programmed, ENTER HUNT command should be included in the first command insruction word vwtten. Data on the RxD pins then sampiee on the Fising edgo of FAC. The content ofthe Fix butler Is ‘Compare at evory bit boundary with the fst SYNC. haractor Unt’ a match occurs I the B251A has. Doon progammed for two SYNC characters, the ‘Subsequent recalved character is also. compared ‘when both SYNC cheracters nave been detected the USART ends the HUNT modo and is in charac- ter syncronization. The SYNDET pin is thon sot high, andis rest automaticaly by @ STATUS READ. I pays pcogrammes, SYNDET wil not be sot unt the mila of the pay Bt Instead of the middie of the Inst data bt In the external SYNC made, synchronization is achieved by applying a high evel on the SYNDET Din, thus forcing tho 8251A out of the HUNT mode, ‘Tho high level can be removed alter one FC eye's An ENTER HUNT command has no affect in the fsynchroncus mode of operation. Note: In estaral syne modo, programing dele cheractr syne wl tec ony the Tx. ond must be 0 Figure 10, Mode Instruction Format, Synchronous Mode ”82518 Patty ror nd overrun error are beth checked in tho same way as in tho Asynchronous Ax modo Panty i checked when not in Hurk, rogardlass of ‘whether the Recover is enabled or not ‘The CPU can command the receiver 10 ener the HUNT mode it synchvonization is lost. This wil also sel al the used charactor tite in tho Bull 10. "one." thus preventing a possible false SYNDET ‘causea by data that happens fo Be in the Rix Bulfor SIENTER HUNT timo, Noto tha the SYNDET F/F Is resol al each Status lead, regardless of whother internal or external SYNC has: been programmed ‘This doos not cause tha 82514 to return to tho HUNT modo, When in SYNC. modo, but not in HUNT, Syne Dotoction sil functional, bul only oc urs al the "known" word Boundaries. Thus, it one Status Road indeates “SYNOET and a second Status Read also indicates SYNDET, then the pro {grammed SYNDET charactors have beon received ‘Since tho provious Slatus Read, (I dauble character ‘3h has boon programmes, then both syne charac {ers have been contguousy received to gate a SYN- DET indication), When external SYNDET mode is. selocted,inlornal Syme Dotoct is dsablod, and tho 'SYNDET F/F may be sot al any bit boundary COMMAND INSTRUCTION DEFINITION ‘Once the functional detntion of the 6251 has been programmed by the Mode Insruction and the ‘Syne charactors are loaded (i in Syne Mode) then the dovice Is roady to be used for data communica: tion. Tae Command Inruetion controls the actual ‘operation ofthe solected format. Functions such as Enable Transmit/ReceWve, Error Reset are Modem Controls are provided by the Command instuction nee the Made instruction has boon written inte the 8251A and Sync characters inserted, of necessary, than all furtner “control writes" (C/D ~ 1) wil load & Command Instruction, A Reset Operation (internal or external) wil lum the 82514 to the Mode instruc- ton forma NoTE: Internal Reset on Power-un |Whan power is fst appted, the 8251 may come up in the Mode, Syne character or Commans formal. To guarantee thal the device isin the Command In- Siuction format belore the Reset command ie Ie fed tis sales! to execute the worst-case niiaiza- tion sequence (yne med with two syne charac: 159) Leading oe Os conseutvetyie vice with C/B = 1 configures syne operation anc ‘wiles wo dummy OOH syne charactors. An Internal FResat command (40H) may then be issued to return the device fo the "cls stat, cruavres (oasTscnan) Figure 11. Data Format, Synchronous Mode82518 4 Note: Err eset must be parormad whenever Rabi and Enter Hunt ve progranmed. Figure 12. Command instruction Format STATUS READ DEFINITION In data communication systems is oon nocossary {9 examine the "stale" of the active device to as Certain Ht errors have occured or other condtons. that require the processors attention. The 82514 has facies that allow tho programmer to “road” the status ofthe device at ary tie during the func tional operation (Status update is inhibited curing status read) A normal reed command is issued by the CPU with O70 “To accompish iN funoton Some of the bis in the Status Read Foxmat have igoncal moanings to extornal output pins so that the 82514 can be used in a. completly poled or interuptcriven enveonment. TxADY Is an excep- tion 1982518 intel. Note that status update can have a maximum dolay of 28 clock periods from the actual event affecting the status. Ome ety l= ITSTADY stats bit has iter! mecrings om the TXADY outta. The loemer is nol condtoned by CTS and THEN theater condoned by both CTS and THEN {a tanby statue bt = Oe Euter Emery ‘DAADY pin out ~ 08 Buiter Empty «(CTS ~ 0) (HEN ~ 3) Figure 13, Status Read Formatintel. aasin APPLICATIONS OF THE 8251A ORE | conn nis ? aaa — 2 Figure 14, Asynchronous Serial Interface to CAT Terminal, DC—9600 Baud sone ae 1 5 enrRot aoe 5 Figure 16, Synchronous Interface to Terminal or Peripheral Device82518 APPLICATIONS OF THE 8251A (Continued) er 3 Le —_ itt = , Ie Figure 17. Synchronous interface to Telephone Lines: Notes: 1 AC tnings measured Vou — 20 Vox = 0.8, and wih oad oro of ue 18. 2 ip See (C3) ard Comma (6/9) we concede dee. 4 Ths recovery ten for Mode incon any Wite Data i alowed only when TARDY ~ 1. Recovery Tene betwoon ‘ites for Asynchronous Mods 8 gy and or Synchronous Mods 18 Gy. '5'The TC and Aix Fequonies have te folowing lntatons wih resp fo CLK: For Baud Rat, feo the = 1180 te For tex end 6x Baud Rate 0 fy = 1/44 oy). Tie apps to Baud Paes es han or Cau W 64K Baud 6 Rose Pulse Wath = Bley meimuny Syston deck must be uraing ing Resse 7, Stas updo can havo a axa delay of 28 cock pads tom th eve aflecing tho stats. {In extra eye maga ta tas apos. ome the Yabo of ho aston cok (oct To raceve of waren atos to be (geste than 3 [a toa dtne asthe pint where the data bus fas Below alge #(20V © lox ni Fos sbove a Loge 0 (OV & toc,intel. ABSOLUTE MAXIMUM RATINGS* “Ambient Temperature Under Blas ......0°C10 70°C ‘Storage Temperature =85'C 10 +1500 Votage on Any Fin with Respect to Ground, -05Vi0+7V ower Dissipation Ww D.C. CHARACTERISTICS T. ~ 0101070, Vo 82518 NOTIGE: This is a production datasheet. The spect. aon are subject to change wihout notice, “WARNING: Siressngthe device beyond the “Asoka Maximum faings” may cause permanent damage These are sressratngs onl. Operation beyord the "Operating Conations” is not recommended and ek. ended exposure Beyond tne "Operating Conettons” ‘may afoot sevice rekably. 16 ~ SOV 110%, GND ~ ov" ‘Symbol Parameter Min | Max [Unit Test Conditions Viv Input Low Vatiage =05 | 08 v Vin Input Figh Votiege 20 | Veo | Vv Vou Output Low Votage 045 | _V_| l= 22ma Vor Output Figh Vonage 2a V | on = = 400 3A Tort ‘Output Float Loekags TiO | wA | Vour = Veo o4ev mn Input Leekoge 210 | wa | Vin = Voc 19 045v tee Power Supply Curent 100 [ma | _Aluiputs = High CAPACITANCE 14 ~ 25°C, Voc = GND = ov Symbol Parameter Min [Max | Unit ‘Test Conditions CH Input Capactance so [oF | tea tee Guo 170 Capastence 20 | BF | Unmessured pins returned teGnd Bus Parameters (Note *) A.C. CHARACTERISTICS 7, ~ 0°10 70°C, Voc ~ 5.0V 4 10%, GND = Ov" READ CYCLE ‘Symbol Parameter Min | Max | Unit | Test Conditions a ‘Adr0ss Siabio Botoro READ (CS,C/0) | 0 ns | (ote2) tha ‘Adress Hold Time for FEAD (CS, G/B) [0 ns | (Note 2) th EAD Pulse Wieth 250 1s tao. Data Delay rom FEAD. 200 | ns | 8.0, = 180pF ‘or. TREAD to Data Floating 70 | 100 [ns] (Notot.8) WRITE CYCLE Symbot Parameter ‘Win | Max | Unit | Tost Conditions: aw ‘Adress Stablo Botore WATE ° ne wa ‘Adsress Hold Time for WHITE | 0 1s ww WRITE Pulso Wioth 250 ns ‘ow ‘Data Sot Up Time for WATTE 750) ne wo ‘Data Hold Time fe WRITE 2 ne tay Recovery Time Between WRITES | 6 ter ‘Note a) wv82518 A.C. CHARACTERISTICS (coninues) intel. OTHER TIMINGS ‘Symbol Parameter ‘Min [Max | Unit | Test Conditions toy ‘GiockPatiod 320 [1950 | ns | (Notes, 6) & (Glock High Pulse Width 120 | toy—90 | ns o ‘Glock Low Pulse Width Ey ns tele (Glock ise and Fall Timo 20 | ne ‘ote TeD Delay irom Falling Edge of + [as tx Transmitter Input Cock Frequency 1x Baud Rate pe | ee | ite 36x Baud Rate pc | 310 | kee 64x Baud Rate oc | 6s _| we tw ‘Transmitter Input Cock Pulse Width 1x Baud Rate 2 tov Bc and 64x Baus Rate 1 lov ‘ipo ‘Transritir input Cock Pulse Delay x Baus Ralo 6 tov 6c and 64% Baud Rate a lov ‘ee ‘Receiver Input Cock Frequency “x Baus Rate oc | ot | ite 16 USART) a \ -eltrenny cLeaR jlo mw OATAM (OB) ____eowreane SaTAsTaMLe CONN CAE “e y———— READ DATA CYCLE (CPU — USART) waornas tana EF aset Sana82518 intel. WAVEFORMS (Continise) WRITE CONTROL OR OUTPUT PORT CYCLE (CPU —> USART) READ CONTROL OR INPUT PORT (CPU USART) Pisa as anaes at 282518 intel. WAVEFORMS (Continise) (BOON ONASV) ONIMIL OVI GNY TOHLNOD USLLINSNVEL82518 ome 2 2 hnea nM REINO HE — i ams WAVEFORMS (Continise) (GaoW ONAS) ONIMIL OV7 GNY TOHLNOD ULLINSNVEL 2482518 intel. 2 2 $ £ a z 5 yg 9 ous pu ug outs ual 'SR10N ‘owes i 3188 (Gaon ONAS) ONIML OVI GNY TOHLNOO W3AIZDUREVISION SUMMARY ‘The following lst represents the key lferences betwoon version 003 and version 002 of the 8251A 0: Sheet 1 Figure 10, Mode Instruction Format, Synchronous Mode. A note was added fo bits D0 and 0+ 26