Outline

Introduction to
‰ Introduction
CMOS VLSI ‰ Delay in a Logic Gate
Design ‰ Multistage Logic Networks
‰ Choosing the Best Number of Stages
Lecture 7B: ‰ Example

Logical Effort ‰ Summary

Lecture by Jay Brockman

University of Notre Dame Fall 2008
Modified by Peter Kogge Fall 2009
Based on lecture slides by David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html

6: Logical Effort Slide 1 5: Logical Effort CMOS VLSI Design Slide 2

Review Normalized Delay

‰ Assume gate G1 is driving some # of other gates G2 ‰ Normalized Delay: gate delay relative to:
– Fanout = number of such gates being driven – “fanout of 1” inverter (drives one inverter)
‰ Delay of a gate G1 = parasitic delay + effort delay – with no parasitic capacitance
‰ Parasitic Delay = delay if gate G1 is driving 0 load – of value 3RC
– Function of diffusion capacitance in gate • R = eqvt resistance of unit nmos transistor in
– Delay seen when G1 drives no other circuits saturation
‰ Effort Delay: delay due to capacitance of circuits • C = eqvt capacitance of gate of unit nmos
driven by G; function of transistor
– the number of gates of type G2 being driven
– the input capacitance presented by a G2 gate

CMOS VLSI Design CMOS VLSI Design

Normalized Parasitic Delay Normailzed Effort Delay
‰ h = fanout or electrical effort = property of circuit
‰ Inverter has 3 units of diffusion capacitance – = # equivalent G1 gates being driven by G1
– 2 from pmos – = Cout/Cin where
– 1 from nmos • Cout = total load capacitance presented by G2 inputs
‰ Parasitic delay of inverter is τ =3RC • Cin = input capacitance G1 presents on its sources
‰ Normalized Parasitic Delay of a gate is p/3RC – When gates G2 (those being driven) are type G1, then
– p is parasitic delay from Elmore model • h = # of copies
‰ To convert to psec, multiply by parasitic delay of an ‰ g = logical effort to drive a gate of type G2
inverter in chosen technology
– effort required to drive one gate vs perfect inverter
– how many eqvt invertors one G2 gate looks like
– = (Input cap of G2 gate)/(Input cap of inverter)
– = (Input cap of G2 gate)/3
‰ Inverter has logical effort = 1
CMOS VLSI Design CMOS VLSI Design

Summary Common Gates

Rise Time Input Cap per load
# of loads Gate type Number of inputs
1 2 3 4 n

R Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3 g=Logical Effort
Fall Time is similar NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2

Cdiff hCin # of G2s

XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8

Gate type Number of inputs

Logical effort of type G2
1 2 3 4 n
delay = RCdiff + hRCin Inverter 1
NAND 2 3 4 n
p=Normalized Parasitic
relative-delay = RCdiff + hRCin NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
-------------------------- = pG1 + h*gG2 XOR, XNOR 4 6 8
3RC
CMOS VLSI Design CMOS VLSI Design
 n-input NAND Gates Scaling Transistors
‰ What if all transistors in gate G got wider by k?
– Denote as gate “G(k)”
‰ Parasitic delay of G(k): delay of unloaded gate
– Diffusion capacitance increases by k
– Resistance decreases by k
– Result: No change
‰ Effort delay: ratio of load cap to input cap
– If drive same # of G(k) as before, no change
parasitic delay = (N2/2 + 5/2N)RC – If drive same # of G(1) as before, decrease by 1/k
‰ Result: fanout to type G(1) gates increases by k
SLOW!!!!!!

CMOS VLSI Design CMOS VLSI Design

MultiStage Logic Networks Overall Delay

Relative Input Capacitance
(based on gate design & transistor size)
gi = logical effort to drive a gate of type i = input cap/cap of inverter
hi = fanout of gates of type i = load cap/input cap
Question: if delay thru one gate is p + hg,
can we write delay thru multistage as some P+HG?
CMOS VLSI Design
‰ delay = ∑delay(i)
– where delay(i) = delay thru I’th “stage” of logic
‰ delay(i) = pi + hi * gi
– pi function only of gate type at stage i
– gi function only of gate type at stage i
• input cap/cap of inverter
– hi depends on gates at stage i+1
• total load on gate i/input cap of gate I
‰ delay = ∑(pi + hi * gi ) = ∑(pi ) + ∑(hi * gi )
‰ Can we write ∑(hi * gi ) as some H*G?
CMOS VLSI Design
 Paths that Branch
Definitions Branch point
‰ Path Logical Effort G =
∏g i
‰ No! Consider paths that branch:
‰ Individual terms
‰ Path Electrical Effort Cout-path g1 = g2 = 1 (inverters) 15
H= 90
Cin-path h1 = (15 +15) / 5 = 6 5
‰ Path Effort F =∏ f i = ∏ gi hi h2 = 90 / 15 = 6
15
‰ Path Terms 90
G = Πgi = 1x1 = 1
10 H = Cout/Cin = 90 / 5 = 18
x z
y GH = 18
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z F = g1h1g2h2 = 36 = 2GH != GH

Question: Can we write F = GH?

5: Logical Effort CMOS VLSI Design Slide 13 5: Logical Effort CMOS VLSI Design Slide 14

Branching Effort Multistage Delays

‰ Introduce Branching Effort ‰ Path Delay D = ∑ d i = DF + P
– Accounts for branching between stages in path
‰ Path Parasitic Delay
Con path + Coff path P = ∑ pi
b= ‰ Path Effort Delay
Con path DF = ∑ f i
B = ∏ bi
Note:

‰ Now we compute the Path Effort

∏h i = BH
– F = GBH

5: Logical Effort CMOS VLSI Design Slide 15 5: Logical Effort CMOS VLSI Design Slide 16
 Designing Fast Circuits Gate Sizes
‰ How wide should the gates be for least delay?
D = ∑ d i = DF + P
‰ Delay is smallest when each stage bears same effort fˆ = gh = g CCoutin
1
fˆ = gi hi = F N gi Couti
⇒ Cini =
‰ Thus minimum delay of N stage path is fˆ
1 ‰ Working backward, apply capacitance
D = NF N + P transformation to find input capacitance of each gate
‰ This is a key result of logical effort given load it drives.
– To find fastest possible delay ‰ Check work by verifying input cap spec is met.
– Doesn’t require calculating gate sizes

5: Logical Effort CMOS VLSI Design Slide 17 5: Logical Effort CMOS VLSI Design Slide 18

Example: 3-stage path Example: 3-stage path

x
‰ Select gate sizes x and y for least delay from A to B y
x
45
A 8
x
y B
45
x
Logical Effort G=
y Electrical Effort H=
x
45 Branching Effort B=
A 8 Path Effort F=
x
y B Best Stage Effort fˆ =
45 Parasitic Delay P=
Delay D=

5: Logical Effort CMOS VLSI Design Slide 19 5: Logical Effort CMOS VLSI Design Slide 20
 Example: 3-stage path Example: 3-stage path
x

y
‰ Work backward for sizes
x
45
A 8
y=
x
y B
45 x=
Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27
Electrical Effort H = 45/8 x
Branching Effort B=3*2=6
y
Path Effort F = GBH = 125 x
45
Best Stage Effort fˆ = 3 F = 5 A 8
x
Parasitic Delay P=2+3+2=7 y B
45
Delay D = 3*5 + 7 = 22 = 4.4 FO4

5: Logical Effort CMOS VLSI Design Slide 21 5: Logical Effort CMOS VLSI Design Slide 22

Example: 3-stage path Choosing Best # of Stages

‰ Work backward for sizes ‰ Goal: estimate delay & choose transistor sizes
y = 45 * (5/3) / 5 = 15 ‰ Many different topologies (combinations of gate types)
that implement same function
x = (15*2) * (5/3) / 5 = 10
‰ We know in general
– NANDs better than NORs
– Gates with fewer inputs better than more inputs
‰ Typical shortcut: estimate delay by # of stages
45 – Assuming constant “gate delay”
A P: 4 – and thus shorter paths are faster
P: 4
N: 4 P: 12 B ‰ THIS IS NOT ALWAYS TRUE!
N: 6 45
N: 3 – Adding inverters at end with increasing sizes
can speed up circuit, esp. when high load

5: Logical Effort CMOS VLSI Design Slide 23 CMOS VLSI Design

 Example (p. 178) Best Number of Stages
(p. 178)
‰ How many stages should a path use? ‰ How many stages should a path use?
– Minimizing number of stages is not always fastest – Minimizing number of stages is not always fastest
‰ Example: drive 64-bit datapath with unit inverter ‰ Example: drive 64-bit datapath with unit inverter

InitialDriver 1 1 1 1 InitialDriver 1 1 1 1

D = D = NF1/N + P 8 4 2.8

= N(64)1/N + N 16 8

23

DatapathLoad 64 64 64 64 DatapathLoad 64 64 64 64

N: 1 2 3 4 N: 1 2 3 4
f: f: 64 8 4 2.8
D: D: 65 18 15 15.3
Fastest

5: Logical Effort CMOS VLSI Design Slide 25 5: Logical Effort CMOS VLSI Design Slide 26

General Derivation Best Stage Effort

‰ Consider adding inverters to end of n1 stage path ‰ pinv + ρ (1 − ln ρ ) = 0 has no closed-form solution
– How many give least delay?
Logic Block:
N - n1 ExtraInverters
‰ Neglecting parasitics (pinv = 0), we find ρ = 2.718 (e)
n1 n1Stages

D = NF + ∑ pi + ( N − n1 ) pinv
1
N Path Effort F

i =1 ‰ For pinv = 1, solve numerically for ρ = 3.59

∂D 1 1 1
= − F N ln F N + F N + pinv = 0 N total stages with (N-n1)
∂N Inverters ‰ Again,
‰ Define best stage effort ρ = F N
1
• do not change logical effort
• do add parasitic delay – these ρ values are best logical effort per stage

^ = log
pinv + ρ (1 − ln ρ ) = 0 – when you have N ρ F stages

5: Logical Effort CMOS VLSI Design Slide 27 5: Logical Effort CMOS VLSI Design Slide 28
 Sensitivity Analysis 1st Example, Revisited
‰ How sensitive is delay to using exactly the best ‰ Ben Bitdiddle is the memory designer for the Motoroil 68W86,
number of stages? 1.6
1.51 an embedded automotive processor. Help Ben design the
decoder for a register file.

D(N) /D(N)
1.4 A[3:0] A[3:0]
1.26 32 bits
1.2 1.15

1.0

4:16 Decoder

16 words
(ρ=6) (ρ =2.4)
‰ Decoder specifications: 16
Register File

– 16 word register file

– Each word is 32 bits wide
0.0
0.5 0.7 1.0 1.4 2.0 – Each bit presents load of 3 unit-sized transistors
N/ N = actual N vs optimal N – True and complementary address inputs A[3:0]
‰ 2.4 < ρ < 6 gives delay within 15% of optimal – Each input may drive 10 unit-sized transistors
– We can be sloppy! ‰ Ben needs to decide:
– How many stages to use?
– I like ρ = 4
– How large should each gate be?
– How fast can decoder operate?

5: Logical Effort CMOS VLSI Design Slide 29 5: Logical Effort CMOS VLSI Design Slide 30

What Does This Mean? Number of Stages

‰ 16 word register file
– There are 16 separate row lines ‰ Decoder effort is mainly electrical and branching
– Branching factor of 16 at end Electrical Effort: H=
‰ Each word is 32 bits wide & each bit presents load Branching Effort: B=
of 3 unit-sized transistors
– The load on each row line is 32*3 ‰ If we neglect logical effort (assume G = 1)
‰ True and complementary address inputs A[3:0] Path Effort: F=
– Any address input needed for only 8 row lines
‰ Each input may drive 10 unit-sized transistors Number of Stages: N=
– Total input capacitance from 1st stage gates on
inputs = 10

5: Logical Effort CMOS VLSI Design Slide 31 5: Logical Effort CMOS VLSI Design Slide 32
 Number of Stages 3 Stage Gate Sizes & Delay
Logical Effort: G = 1 * 6/3 * 1 = 2
‰ Decoder effort is mainly electrical and branching Path Effort: F = GBH = 154
Electrical Effort: H = (32*3) / 10 = 9.6 Stage Effort: fˆ = F 1/ 3 = 5.36
Branching Effort: B=8 Path Delay: D = 3 fˆ + 1 + 4 + 1 = 22.1
Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
‰ If we neglect logical effort (assume G = 1)
Path Effort: F = GBH = 76.8 A[3] A[3]

10 10
A[2] A[2]

10 10
A[1] A[1]

10 10
A[0] A[0]

10 10

Number of Stages: N = log4F = 3.1 y z word[0]

96 units of wordline capacitance

‰ Try a 3-stage design y z word[15]

5: Logical Effort CMOS VLSI Design Slide 33 5: Logical Effort CMOS VLSI Design Slide 34

Comparison Review of Definitions

‰ Compare many alternatives with a spreadsheet
Term Stage Path
number of stages 1 N
Design N G P D
NAND4-INV 2 2 5 29.8 logical effort g G = ∏ gi

NAND2-NOR2 2 20/9 4 30.1 electrical effort h= Cout

Cin
H=
Cout-path
Cin-path
Con-path + Coff-path
INV-NAND4-INV 3 2 6 22.1 branching effort b= Con-path B = ∏ bi
NAND4-INV-INV-INV 4 2 7 21.1 effort f = gh F = GBH
NAND2-NOR2-INV-INV 4 20/9 6 20.5 DF = ∑ f i
effort delay f
NAND2-INV-NAND2-INV 4 16/9 6 19.7
parasitic delay p P = ∑ pi
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
delay d= f +p D = ∑ d i = DF + P
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6

5: Logical Effort CMOS VLSI Design Slide 35 5: Logical Effort CMOS VLSI Design Slide 36
 Method of Logical Effort Limits of Logical Effort
1) Compute path effort ‰ Chicken and egg problem
F = GBH
2) Estimate best number of stages – Need path to compute G
3) Sketch path with N stages N = log 4 F – But don’t know number of stages without G
4) Estimate least delay 1
‰ Simplistic delay model
5) Determine best stage effort D = NF N + P – Neglects input rise time effects
1
fˆ = F N ‰ Interconnect
6) Find gate sizes gi Couti – Iteration required in designs with wire
Cini = ‰ Maximum speed only
fˆ
– Not minimum area/power for constrained delay

5: Logical Effort CMOS VLSI Design Slide 37 5: Logical Effort CMOS VLSI Design Slide 38

Summary
‰ Logical effort is useful for thinking of delay in circuits
– Numeric logical effort characterizes gates
– NANDs are faster than NORs in CMOS
– Paths are fastest when effort delays are ~4
– Path delay is weakly sensitive to stages, sizes
– But using fewer stages doesn’t mean faster paths
– Delay of path is about log4F FO4 inverter delays
– Inverters and NAND2 best for driving large caps
‰ Provides language for discussing fast circuits
– But requires practice to master

5: Logical Effort CMOS VLSI Design Slide 39