Counters

Learning objectives
• Understanding the operation and characteristics of asynchronous and synchronous counters
• Analyze counter circuits and counter timing diagrams
• Determine the sequence of a counter
• Determine the modulus of a counter
• Analyze various types of counters
• Construct of up/down synchronous counters
• Design of sequential systems
• Design of sequential counters with specified sequences
• Counter decoding by use of logic gates
• Applications of synchronous counter design – stepper motor control

A counter is an electronic circuit that is able to count the number of pulses applied to its input
terminals.
Essentially, a counter consists of cascade connection of a number of flip-flops, usually of either the J-K
type or the D type which may be operated either synchronously or non-synchronously.
With synchronous operation all the flip-flops making up the counter operate at the same instant in time
under the control of a clock pulse. In the case of non-synchronous operation each flip-flop operates in
turn. The first flip-flop is clocked by the external clock pulse and then successive flip-flop is clocked
by the output of the preceding flip-flop. This means that each stage must change state before the
following stage can do so. As a result, synchronous operation is much faster and the use of a
non-synchronous counter is acceptable only when the speed of operation is not of particular
importance.
The possible applications for counters are many. They are often used for the direct counting of objects
in industrial processes and of voltage pulses in digital circuits such as digital voltmeters. Counters can
be used as frequency dividers and for the measurement of frequency and time.

Non-synchronous (asynchronous) counters

A 2-bit asynchronous binary counter
High
FF0 FF1
Q0 Q1
J0 J1
CLK
Q0
K0 K1

The clock (CLK) is applied only to the clock input of FF0, which is always the least significant bit
(LSB). FF1 is triggered by the Q0 output of FF0. FF0 change state at the positive-going edge of each
clock pulse, but FF1 changes only when triggered by a positive-going transition of the Q0 output of
FF0. Because of the propagation delay through a flip-flop, the counter operation is asynchronous.
The timing diagram

1 2 3 4
CLK

Q0

Outputs
{ Q0(LSB)

Q1(MSB)

For simplicity, the transitions of Q0, Q1, and the clock pulses are shown as simultaneous even though
this is an asynchronous counter.

Binary state sequence for the 2-bit asynchronous binary counter

Clock pulse Q1 Q0
Initially 0 0
1 0 1
2 1 0
3 1 1
4 (recycles) 0 0

The term recycle is commonly applied to counter operation; it refers to the transition of the counter
from its final state back to its original state.

A 3-bit asynchronous binary counter

High
FF0 FF1 FF2
Q0 Q1 Q2
J0 J1 J2
CLK
Q0 Q1
K0 K1 K2

The basic operation is the same as that of the 2-bit counter, except that the 3-bit counter has eight states,
due to its three flip-flops.
The 3-bit counter progress through a binary counter of zero through 7 and then recycles to the zero
state.

Asynchronous counters are also called ripple counters as an input clock pulse “ripples” through the
counter, experiencing propagation delays, to reach the last flip-flop.

Asynchronous decade counters

The modulus of a counter is the number of unique states that the counter will sequence through. The
maximum modulus of a counter is 2n, where n is the number of flip-flops in the counter.
Counters can be designed to have a number of states in their sequence that is less than 2n. The resulting
sequence is called a truncated sequence.
One common modulus for counters with truncated sequence is ten. Counters with ten states in their
sequence are called decade counters.
A decade counter with a count sequence of zero (0000) through nine (1001) is a BCD decade counter.
This type of counter is useful in display applications in which BCD is required for conversion to a
decimal readout.

CLR

High
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J0 J1 J2 J3
CLK
K0 K1 K2 K3
CLR CLR CLR CLR

One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a
NAND gate and connect the output of the NAND gate to the clear ( CLR ) inputs of the flip-flops.

Question:
How many states does a modulus-14 counter have? What is the minimum number of flip-flops
required?

Synchronous counters
The term synchronous refers to events that have a fixed time relationship with each other.

A 2-bit synchronous binary counter

High
FF0 FF1
Q0 Q1
J0 J1
Q0
K0 K1

CLK

Assume that the counter is initially in the binary 0 state; that both flip-flops are RESET. When the
positive edge of the first clock pulse is applied, FF0 will toggle and Q0 will therefore go HIGH. What
happens to FF1 at the positive-going edge of CLK1? At first, inputs J1 and K1 are both LOW because of
Q0. Remember, there is a propagation delay from the triggering edge of the clock pulse until the Q
output actually makes a transition. So, J1 = 0 and K1 = 0 when the leading edge of the first clock pulse
is applied. FF1 does not change state.
After CLK1, Q0 = 1, Q1 = 0. When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go
LOW. Since FF1 has a HIGH on J1 and K1 inputs at the triggering edge of this clock pulse, the flip-flop
toggles and Q1 goes HIGH.

Timing diagram

1 2 3 4
CLK

Q0

Q1

* For simplicity, the propagation delay is not demonstrated.

A 3-bit synchronous binary counter

HIGH
FF0 FF1 Q0Q1 FF2
Q0 Q1 Q2
J0 J1 J2

K0 K1 K2

CLK

Timing diagram

1 2 3 4 5 6 7 8
CLK

Q0

Q1

Q2

Questions
In an asynchronous counter, all filp-flops change states at the same time, true or false?
How does a synchronous counter differ from an asynchronous counter?

Comparison of synchronous and asynchronous counters

A synchronous counter can operate at a much higher input frequency.
However, the circuitry of the synchronous counter is more complex than that of the asynchronous
counter.
Up/Down synchronous counters
An up/down counter is one that is capable of progressing in either direction through a certain sequence.
An up/down counter is sometimes called a bidirectional counter, can have any specified sequence of
states.
In general, most up/down counters can be reversed at any point in their sequence.
Up Up

{
{
0, 1, 2, 3, 4, 5, 4, 3, 2, 3, 4, 5, 6, 7, 6, 5, etc.

{
Down Down

Up/Down sequence for a 3 bit binary counter

Clock Pulse Next State
Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

An examination of Q0 for both the up and down sequence shows that FF0 toggles on each clock pulse.
Thus,
J0 = K 0 = 1
For the up sequence, Q1 changes state on the next clock pulse when Q0 = 1. For the down sequence, Q1
changes state on the next clock pulse when Q0 = 0. Thus, the J1 and K1 inputs of FF1 must equal 1
under the conditions expressed by the following equation:

J1 = K1 = (Q0 iUP ) + (Q0 i DOWN )

For the up sequence, Q2 changes state on the next clock pulse when Q0 = Q1 = 1. For the down
sequence, Q2 changes state on the next clock pulse when Q0 = Q1 = 0. Thus, the J2 and K2 inputs of FF2
must equal 1 under the conditions expressed by the following equation:

J 2 = K 2 = (Q0 iQ1 iUP) + (Q0 iQ1 i DOWN )

Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the appropriate point
in the counter sequence.
 UP Q0UP
High
FF0 FF1 FF2
Q2
J0 Q0 J1 J2
UP/DOWN Q1
Q0 Q1 Q2
K0 K1 K2

DOWN
Q 0DOWN
CLK
UP/DOWN control input is HIGH for UP and LOW for DOWN

Question
What is the difference between the counting sequence of an up counter and a down counter?

Design of synchronous sequential systems

A general sequential system consists of a combinational logic section and a memory section
(flip-flops).
The design of sequential systems typically starts with a problem statement, a verbal description of the
intended behavior of the system.
The goal is to develop a block diagram of the system utilizing the available components and meeting
the design objectives and constrains.

Design example
State table
0
Qn Qn+1 z
x=0 x=1
A/0
A A B 0 1 0
0 0
B A C 0 1
B/0 C/0 D/1
C A D 0 1 1
A state diagram
D A D 1

A state table shows for each input and present state what the output is and what the next state is.
A state diagram is a graphical representation of the behavior of the system, showing for each input and
present state what the output is and what the next state is.

One possible state assignment

Q Q1 Q2
A 0 0
B 0 1
C 1 0
D 1 1
From either the state diagram or the state table, we can construct the design truth table for the next
state.
Q x Q1n Q2n Q1,n+1 Q2,n+1
A 0 0 0 0 0
B 0 0 1 0 0
C 0 1 0 0 0
D 0 1 1 0 0
A 1 0 0 0 1
B 1 0 1 1 0
C 1 1 0 1 1
D 1 1 1 1 1

We can now map Q1,n+1, Q2,n+1, and z

X X
Q1Q2 0 1 Q1Q2 0 1
00 00 1 Q1
Q2 0 1
01 1 01 0
11 1 11 1 1
1
10 1 10 1 z
Q1,n+ 1 Q2,n+ 1

We thus have the state equations

Q1,n +1 = xQ2 n + xQ1n
Q2,n +1 = xQ2 + xQ1
z = Q1nQ2 n

For the D flip-flop, the design table

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
The equations
D1 = xQ2 n + xQ1n
D2 = xQ2 + xQ1
Implementation using D flip-flop
 CLK
x

D Q1 z

Q1

D Q2

Q2

Question
How many sections does a sequential system consist of?
What is the state diagram?

Design of synchronous counters

Step 1: State diagram
A counter is first described by a state diagram, which shows the progression of states through which
the counter advances when it is clocked.

000
100 001

101 011

111 010

110

Step 2: Next-state table

Once the sequential circuit is defined by a state diagram, the next step is to derive a next-state table,
which lists each state of the counter (present state) along with the corresponding next state.
The next state is the state that the counter goes to from its present state upon application of a clock
pulse. The next state is derived from the state diagram.
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 0 1 0
0 1 0 1 1 0
1 1 0 1 1 1
1 1 1 1 0 1
1 0 1 1 0 0
1 0 0 0 0 0
Step 3: Flip-flop transition table
All possible output transitions are listed by showing the Q output of the flip-flop going from present
states to next states. Qn is the present state of the flip-flop (before a clock pulse) and Qn+1 is the next
state (after a clock pulse). For each output transition, the J and K inputs that will cause the transition to
occur are listed. The Xs indicate a “don’t care” (the input can be either 1 or 0).

Output Transition Flip-Flop Inputs

Qn Qn+1 J K
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0
To design the counter, the transition table is applied to each of the flip-flops in the counter, based on the
next-state table.

Step 4: Karnaugh maps

Karnaugh maps can be used to determine the logic required for the J and K inputs of each flip-flop in
the counter. There is a Karnaugh map for the J input and a Karnaugh map for the K input of each
flip-flop.

Example of Karnaugh map procedure:

J0 map K 0 map
Q0 Q0
Q2Q1 0 1 Q2Q1 0 1
00 1 00 X

01 01

11 11

10 X 10 1

The completed Karnaugh maps for all three flip-flops

 Q0 Q0 Q0
Q 2Q1 0 1 Q 2Q1 0 1 Q 2Q1 0 1
00 0 0 00 0 1 00 1 X Q 2Q1
01 1 0 01 X X 01 0 X
Q 1Q0
11 11 1 X
X X X X Q 2Q0 11 Q 2Q1
10 X X 10 0 0 10 0 X
J2 map J1 map J0 map
Q0 Q0 Q0
Q 2Q1 0 1 Q 2Q1 0 1 Q 2Q1 0 1
00 X X 00 X X 00 X 0

01 X X 01 0 0 01 X 1 Q 2Q1

11 0 0 11 0 1 11 X 0

10 1 0 10 X X 10 X 1 Q2Q1
Q 1Q0 K1 map Q 2Q0
K2 map K0 map

Step 5: Logic expression for flip-flop inputs

From the completed Karnaugh maps for all three flip-flops, the following expressions for the J and K
inputs of each flip-flop can be obtained:

J 0 = Q2Q1 + Q2 Q1 = Q2 ⊕ Q1
K 0 = Q2 Q1 + Q2Q1 = Q2 ⊕ Q1
J1 = Q2Q0 K1 = Q2Q0
J 2 = Q1 Q0 K 2 = Q1 Q0

Step 6: Counter implementation

The final step is to implement the combinational logic from the expressions for the J and K inputs and
connect the flip-flops to form the complete 3-bit counter.

FF0 FF1 FF2

Q0 Q1 Q2
J0 J1 J2

Q0 Q1 Q2
K0 K1 K2

CLK

A summary of steps (can be applied to any sequential circuit):

1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition. The transition
table is always the same for a given type of flip-flop.
4. Transfer the J and K states from transition table to Karnaugh maps. There is a Karnaugh map for
each input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each flip-flop input.
6. Implement the expressions with combinational logic, and combine with the flip-flop to create the
counter.

Example
Design a counter with the irregular binary count sequence shown in the state diagram as shown. Use
J-K flip-flops.
001
(1)

111 010
(7) (2)

101
(5)

Solution
Step 1: A 3-bit counter is required to implement this sequence. The invalid states (0, 3, 4, 6) can be
treated as “don’t cares” in the design. However, if the counter should erroneously get into an invalid
state, we must make sure that it goes back to a valid state.

Step 2: The next-state table is developed from the state diagram.

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1
Step 3: The transition table for the J-K flip-flop is shown.
Output Transition Flip-Flop Inputs
Qn Qn+1 J K
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0

Step 4: The J and K inputs are plotted on the present-state Karnaugh maps. Also “don’t cares” can be
placed in the cells corresponding to the invalid states of 000, 011, 100, and 110, as indicated by the red
Xs.
 Q0 Q0 Q0
Q2Q1 0 1 Q 2Q1 0 1 Q 2Q1 0 1
00 X 0 00 X 1 00 X X

01 1 X 01 X X 01 1 X
Q1
11 X X 11 X X 1 11 X X 1
10 X X 10 X 1 10 X X
J2 map J1 map J0 map
Q0 Q0 Q0
Q2Q1 0 1 Q 2Q1 0 1 Q 2Q1 0 1
00 X X 00 X X 00 X 1
Q2
1
01 X X 01 1 X 01 X X
Q1
11 X 1 11 X 1 11 X 0

10 X 0 10 X X 10 X 0
K 2 map K1 map K0 map

Step 5: Group the 1s, taking the advantage of as many of the “don’t care” states as possible for
maximum simplification. The expression for each J and K input taken from the maps is as follows:

J 0 = 1, K 0 = Q2
J1 = K1 = 1
J 2 = K 2 = Q1

Step 6: The implementation of the counter is as shown.

HIGH Q0 HIGH Q1 Q2
FF0 FF1 FF2
J0 J1 J2

Q2
K0 K1 K2

CLK

An analysis shows that if the counter, by accident, gets into one of the invalid states (0, 3, 4, 6), it will
always return to a valid state according to the following sequence: 0 → 3 → 4 → 7, and 6 → 1.

Counters with nonstandard sequences

One convention that makes the design process easier is to list the present states, including unused states,
even if the circuit does not count in binary order. Since the synchronous input functions are Boolean
functions of the present state variables, keeping them in truth table order allows us easily to use
familiar techniques of simplification, such as K-maps.

Example
Design a synchronous sequential circuit that will produce the biquinary sequence shown in the state
diagram. Test the unused states to ensure that they enter the main sequence in one or more clock pulses.
 0000
1100 0001

1011 0010

1010 0011

1001 0100

1000

Solution
State table for a Biquinary Sequence Counter
Present state Next state
QD QC QB QA QD QC QB QA JD KD JC KC JB KB JA KA
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 1 0 0 0 1 X X 1 0 X 0 X
0 1 0 1 X X X X X X X X X X X X
0 1 1 0 X X X X X X X X X X X X
0 1 1 1 X X X X X X X X X X X X
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 1 0 1 0 X 0 0 X 1 X X 1
1 0 1 0 1 0 1 1 X 0 0 X X 0 1 X
1 0 1 1 1 1 0 0 X 0 1 X X 1 X 1
1 1 0 0 0 0 0 0 X 1 X 1 0 X 0 X
1 1 0 1 X X X X X X X X X X X X
1 1 1 0 X X X X X X X X X X X X
1 1 1 1 X X X X X X X X X X X X

The J and K inputs indicated in the above table are loaded into Karnaugh maps as shown in the
following figure.
 QBQA QBQA
QDQC 00 01 11 10 QDQC 00 01 11 10
00 0 0 0 0 00 X X X X
QC QC
01 1 X X X 01 X X X X

11 X X X X 11 1 X X X

10 X X X X 10 0 0 0 0
JD KD

QBQA QBQA
QDQC 00 01 11 10 QDQC 00 01 11 10
00 0 0 1 0 00 X X X X
QBQA
01 X X X X 01 1 X X X 1

11 X X X X 11 1 X X X

10 0 0 1 0 10 X X X X
JC KC

QBQA QBQA
QDQC 00 01 11 10 QDQC 00 01 11 10
00 0 1 X X 00 X X 1 0
QA QA
01 0 X X X 01 X X X X

11 0 X X X 11 X X X X

10 0 1 X X 10 X X 1 0
JB KB

QBQA QBQA
QDQC 00 01 11 10 QDQC 00 01 11 10
00 1 X X 1 QC 00 X 1 1 X

01 0 X X X 01 X X X X 1

11 0 X X X 11 X X X X

10 1 X X 1 10 X 1 1 X
JA KA

This yields the following Boolean equations for the synchronous inputs:

J D = QC , K D = QC , J C = QB QA, KC = 1
J B = QA , K B = QA , J A = QC , KA =1

The counter derived from these Boolean equations.

QA QC QD
JA JB QB JC J2
QC
1 KA KB 1 KC K2

CLK
There are six unused states in the count sequence. Each of them is tested as shown in the following
table.
Present state Next state
QD QC QB QA JD KD JC KC JB KB JA KA QD QC QB QA
0 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0
0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 0
0 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0
1 1 0 1 1 1 0 1 1 1 0 1 0 0 1 0
1 1 1 0 1 1 0 1 0 0 0 1 0 0 1 0
1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0

The revised state diagram is shown in the following figure, including the six unused states.

1111
0000
1100 1101
0001

1011 0010 1110

0110
1010 0011

0101
1001 0100

1000

0111

Questions
What determine the counter sequence for a counter circuit?
The synchronous counter design procedure can be used for the following sequence: 0010, 0011, 0100,
0111, 1010, 1110, 1111, and repeat, true or false?

Counter Decoding
In many applications, it is necessary that some or all of the counter states be decoded. The decoding of
a counter involves using decoders or logic gates to determine when the counter is in a certain binary
state in its sequence.
To decode binary state 6 (110) of a 3-bit binary counter, when Q2 = 1, Q1 = 1, Q0 = 0, a HIGH appears
on the output of the decoding gate, indicating that the counter is at state 6. This is called active-HIGH
decoding.
 High
FF0 FF1 FF2
Q0 Q1 Q2
J0 J1 J2
CLK
Q0 Q1
K0 K1 K2
1
1 1
LSB MSB
Decoded 6
Q1Q2Q0

Example
Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous counter. Show the
entire counter timing diagram and the output waveforms of the decoding gates. Binary 2 = Q2Q1 Q0 , and
binary 7 = Q2Q1Q0.
Solution
High
FF0 FF1 FF2 MSB
Q0 LSB Q1 Q2
J0 J1 J2

Q0 Q2
K0 K1 K2
CLK

7
2

1 2 3 4 5 6 7 8
CLK

Q0

Q1

Q2

2
Decoded
outputs { 7

Applications of synchronous counter design -- stepper motor control

A stepper motor is a motor that rotates in steps, typically 15° per step, rather than in a continuous
motion. Magnetic coils or windings within the motor must be energized and deenergized in a specific
sequence in order to produce this stepping action. Digital signals are normally used to control the
current in each of the motor’s coils. Stepper motors are used extensively in situation s where precise
position control is needed, such as in positioning of read/write head on magnetic disks, in controlling
print heads in printers and in robots.

Coil 1 Coil 1
A
D Synch 2 Current CW
A
(Direction 3 4
Counter B amplifiers
input) 4
B
2 Stepper
CCW
3 motor
Step
(clock)

For the motor to rotate properly, coils 1 and 2 must always be in opposite states; that is, when coil 1 is
energized, coil 2 is not, and vice versa. Likewise, coil 3 and coil 4 must always be in opposite states.

The outputs of a two-bit synchronous counter are used to control the current in the four coils; A and A
control coils 1 and 2, and B and B control coils 3 and 4. The current amplifiers are needed because
the Flip-flop outputs cannot supply the amount of current that the coils require.
Because this stepper motor can rotate either clockwise (CW) or counter-clockwise (CCW), we have a
Direction input, D, which is used to control the direction of rotation.

The state diagram

For CW rotation to occur, we must have D = 0, and the state of the counter BA, must follow the
sequence 11, 10, 00, 01, 11, 10, … , and so on, as it is clocked by the Step input signal. For CCW
rotation, D = 1, and the counter must follow the sequence, 11, 01, 00, 10, 11, 01, … , and so on.
CW rotation CCW rotation
D=0 D=1
11 11

01 10 01 10

00 00

Next state and transition table

Present State Next state Control inputs
D B A B A JB KB JA KA
0 0 0 0 1 0 X 1 X
0 0 1 1 1 1 X X 0
0 1 0 0 0 X 1 0 X
0 1 1 1 0 X 0 X 1
1 0 0 1 0 1 X 0 X
1 0 1 0 0 0 X X 1
1 1 0 1 1 X 0 1 X
1 1 1 0 1 X 1 X 0
K maps
D D D
0 1 0 1 D
BA BA BA 0 1 0 1
BA
00 0 1 00 X X
00 1 00 X X
0
01 1 0 01 X X 0 1
01 X X 01
11 X X 11 0 1 1 0
11 X X 11
10 X X 10 1 0 X X
10 0 1 10
JB KB JA KA

J B = DA + D A = D ⊕ A, K B = D A + DA = D ⊕ A
J A = DB + DB = D ⊕ B, K A = DB + DB = D ⊕ B

Synchronous counter implementation from the J, K equations

B To current To current
A
B amplifiers amplifiers
A

JB B JA A

KB B KA A

Step
D (direction)

Review Questions
z What is a counter?
z How many states does a modulus-10 counter have?
z What is a state diagram?
z What is the next-state table?
z What is the procedure for designing a synchronous counter?
z A certain J-K flip-flop has propagation delay of 12 ns. What is the largest modulus of the counter
that can be constructed from these flip-flops and still operate up to 10 MHz?
z True or false: The synchronous counter design procedure can be used for the following sequence:
0010, 0011, 0100, 0111, 1010, 1110, 1111 and repeat.
 Exercises
1. By analyzing the J and K inputs to each flip-flop prior to each clock pulse, prove that the decade
counter in the following figure progresses through a BCD sequence. Explain how these conditions
in each case cause the counter to go to the next proper state.

High
Q0
J1 J3 Q3
J0 J1 Q2
Q1
Q3
K1 K3
K0 K1
FF2 FF3
CLK FF0 FF1

2. Determine the sequence of the counter in the following figure. Begin with the counter cleared.
High

J0 J1 J1 J3
Q0 Q2 Q3
Q1
K0 K1 K1 K3

CLK FF0 FF1 FF2 FF3

3. Analyze the sequential circuit as shown in the following figure. Write down the input equation,
next state equation and output equation and draw the output waveforms of Q1, Q2 and Y for the 4
consecutive clock pulses. Assume that Q1 and Q2 are initially Reset.

Y
D D Q1 D Q2

Q1 Q2

CLK

4. Design a counter to give the necessary states from 000 (state 0) through to 111 (state 7). Use
D-type flip-flops.

5. Write the logic expression of a mod-6 binary up-counter using J-K type flip-flops.