library IEEE;

use IEEE.std_logic_1164.all;

entity and2 is

port (a,b: in std_logic;

F: out std_logic);

end and2;
architecture primitive of and2 is
begin

F <= a and b;

end primitive;

library IEEE;

use IEEE.std_logic_1164.all;

entity and3 is

port (a,b,c: in std_logic;

F: out std_logic);

end and3;

architecture primitive of and3 is

begin

F <= a and b and c;

end primitive;

library IEEE;

use IEEE.std_logic_1164.all;

entity automat is
port(ck,a,b,rn:in std_logic;
Q2,Q1,Q0:out std_logic);
end automat;

architecture structural of automat is

component divizor is port (
clk: in std_logic;
clk_out: out std_logic);
end component;
component cls is
port(D2,D1,D0,ck,rn: in std_logic;
Q2,Q1,Q0: out std_logic);
end component;

component clc is
port(Q2,Q1,Q0,a,b:in std_logic;
JK2,JK1,JK0:out std_logic);
end component;

signal netQ2,netQ1,netQ0,netJK2,netJK1,netJK0,net_ck : std_logic;

begin
U1:cls port map
(D2=>netJK2,D1=>netJK1,D0=>netJK0,ck=>net_ck,Rn=>rn,Q2=>netQ2,Q1=>netQ1,Q0=>netQ0);
U2:clc port map
(JK2=>netJK2,JK1=>netJK1,JK0=>netJK0,a=>a,b=>b,Q2=>netQ2,Q1=>netQ1,Q0=>netQ0);
U3:divizor port map (clk=>ck, clk_out=>net_ck);

Q2 <= netQ2;
Q1 <= netQ1;
Q0 <= netQ0;

end;

library IEEE;
use IEEE.std_logic_1164.all;

entity clc is
port (Q2, Q1, Q0, a,b: in std_logic;
Y,JK2,JK1,JK0: out std_logic);
end clc;

architecture structural of clc is

component and2
port (a: in std_logic;
b: in std_logic;
F: out std_logic);
end component;
component and3
port (a: in std_logic;
b: in std_logic;
c: in std_logic;
F: out std_logic);
end component;
component or2
port (a: in std_logic;
b: in std_logic;
F: out std_logic;
Y: out std_logic);
end component;
component or3
port (a: in std_logic;
b: in std_logic;
c: in std_logic;
F: out std_logic;
Y: out std_logic);
end component;
signal net1 : std_logic;
signal net2 : std_logic;
signal net3 : std_logic;
signal net4 : std_logic;
signal net5 : std_logic;
signal net6 : std_logic;
signal net7 : std_logic;
signal net8 : std_logic;
signal an :std_logic;
signal Q2n :std_logic;
signal Q1n :std_logic;
signal Q0n :std_logic;

begin
an <= not a;
Q2n <= not Q2;
Q1n <= not Q1;
Q0n <= not Q0;

U1: and3 port map (a => an, b => Q2n, c => Q0n, F => net1);
U2: and3 port map (a => b, b => Q2n, c => Q0, F => net2);
U3: and3 port map (a => a, b => Q1, c => Q0, F => net3);
U4: or3 port map (a => net1, b => net2, c => net3, F => Y, Y => JK2);
U5: and3 port map (a => an, b => Q2n, c => Q0, F => net4);
U6: and3 port map (a => an, b => Q2, c => Q1n, F => net5);
U7: and3 port map (a => a, b => Q2, c => Q0, F => net6);
U8: or3 port map (a => net4, b => net5, c => net6, F => Y, Y => JK1);
U9: and2 port map (a => a, b => Q1n, F => net7);
U10: and2 port map (a => Q2, b => Q1, F => net8);
U11: or2 port map (a => net7, b => net8, F => Y, Y => JK0);

end structural;

library ieee;
use ieee.std_logic_1164.all;

entity cls is
port(D2,D1,D0,ck,rn: in std_logic;
Q2,Q1,Q0: out std_logic);
end entity;

architecture structural of cls is

component JK is
port ( J,K, ck, Rn : in std_logic;
Q, Qn: out std_logic);
end component;

signal D2n, D1n, D0n : std_logic;

begin

D2n <= not D2;

D1n <= not D1;
D0n <= not D0;
U2: JK port map (J => D2, K => D2n, ck => ck, Rn => Rn, Q => Q2);
U1: JK port map (J => D1, K => D1n, ck => ck, Rn => Rn, Q => Q1);
U0: JK port map (J => D0, K => D0n, ck => ck, Rn => Rn, Q => Q0);
end structural;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity divizor is port (

clk: in std_logic;
clk_out: out std_logic);
end entity;

architecture behavior of divizor is

signal net1,net2,net3 : std_logic;
component ic163 is port (
clk, clrn, loadn, enp, ent: in std_logic;
a, b, c, d: in std_logic;
rco, qa, qb, qc, qd: out std_logic);
end component;
begin
U1: ic163 port map (clk => clk ,clrn => '1', loadn=> net1 , enp => '1', ent =>'1',a
=> '1', b=>'1', c=>'0',d=>'0',
rco => net2);
U2:ic163 port map (clk => clk ,clrn => '1', loadn=> net1 , enp => '1', ent =>net2,a
=> '0', b=>'1', c=>'0',d=>'1',
rco => net3);

net1 <= net2 nand net3;

clk_out <= not net1;
end behavior;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity ic163 is port (

clk, clrn, loadn, enp, ent: in std_logic;
a, b, c, d: in std_logic;
rco, qa, qb, qc, qd: out std_logic);
end entity;

architecture behavior of ic163 is

signal counter: std_logic_vector(3 downto 0) := "0000";
begin
process (clk, clrn)
begin
if clrn= '0' then
counter <= "0000";
elsif rising_edge(clk) then
if (loadn = '0') then
counter <= d & c & b & a;
elsif(enp = '1' and ent = '1') then
 counter <= counter+1;
end if;
end if;
end process;

qd <= counter (3) ;

qc <= counter (2) ;
qb <= counter (1) ;
qa <= counter (0) ;
rco <= '1' when (ent = '1' and counter = "1111") else '0';
end architecture;

library IEEE;

use IEEE.std_logic_1164.all;

entity JK is

port (J,K,ck,Rn: in std_logic;

Q,Qn: out std_logic);

end JK;

architecture behavior of JK is

signal D, Qint : std_logic;

begin
D <= (J and (not Qint)) or ((not K) and Qint);

inregistrare: process (CK, Rn)

begin

if Rn = '0' then

Qint <= '0';

elsif CK = '1' and CK'event then

Qint <= D;

end if;

end process;

Q <= Qint;

Qn <= not Qint;

end behavior;
library IEEE;

use IEEE.std_logic_1164.all;

entity or2 is

port (a,b: in std_logic;

F,Y: out std_logic);

end or2;

architecture primitive of or2 is

begin
F <= a or b;
end primitive;

library IEEE;
use IEEE.std_logic_1164.all;
entity or3 is
port (a,b,c: in std_logic;
Y,F: out std_logic);
end or3;
architecture primitive of or3 is
begin
F <= a or b or c;
end primitive;

library IEEE;
use IEEE.std_logic_1164.all;

entity test_automat is
end test_automat;

architecture testbench of test_automat is

component automat is --entitate mux2

port(ck,a,b,rn:in std_logic;
Q2,Q1,Q0:out std_logic);
end component;

signal ck,a,b,rn,Q2,Q1,Q0 : std_logic;

begin

UUT:automat port map (ck => ck, a => a, b => b,rn => rn, Q2 => Q2, Q1 => Q1, Q0 =>
Q0);

gen_ck: process
begin
ck <= '0';
wait for 0.5 ns;
ck <= '1';
wait for 0.5 ns;
end process;

gen_a: process
begin
a <= '0' after 0 ns, '1' after 500 ns, '0' after 900 ns;
 wait;
end process;

gen_b: process
begin
b <= '0' after 0 ns, '1' after 600 ns, '0' after 1000 ns;
wait;
end process;

gen_rn: process
begin
rn <= '1';
wait for 5 ns;
rn <= '0';
wait for 5 ns;
rn <= '1';
wait;
end process;
end testbench;

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity test_divizor is
end test_divizor;

architecture testbench of test_divizor is

component divizor port (
clk: in std_logic;
clk_out: out std_logic);
end component;

signal clk,clk_out:std_logic;

constant period: time := 1 ns;

begin
UUT : divizor port map (clk => clk, clk_out => clk_out );
gen_clk: process
begin
clk <= '1';
wait for period/2;
clk <= '0';
wait for period/2;
end process;
end testbench;