A Scalable Physical Model for Nano-Electro-Mechanical

Relays

ABSTRACT More parallelism

11
11
Operating at a

Normalized Energy/op
Normalized Energy/op
does not help
Nano-Electro-Mechanical (NEM) relay is a promising device lower energy point
1×

10
10
overcoming the energy-efficiency limitations of CMOS tran- 1×
sistors operating at or near the sub-threshold voltage. Many

9
9
2× 8× 2×
exploratory research projects are currently under way inves-
tigating the mechanical, electrical and logical characteristics

8
8
Run in
of NEM relays. However, before this new and exciting tech- parallel to recoup performance

nology can become mainstream a lot needs to be done on the 0 1 2 3 4 5 6 0 1 2 3 4 5 6

EDA front. One particular issue that this paper addresses
is the need for a scalable and accurate physical model of the
NEM switch that can be plugged into the standard EDA
software.
The existing models are accurate and detailed but they
suffer from the convergence problem. Once a design be-
comes big enough to be practically interesting (tens of NEM
relays or more) the simulation often diverges. This problem
requires finding ad-hoc workarounds and significantly im-
pacts the designer’s productivity. In this paper we propose
a new simplified Verilog-A model. To test scalability of the
proposed model we cross-checked it against our analysis of a
range of benchmark circuits. Results show that, compared
to standard model, the proposed model is sufficiently accu-
rate with an average of 5.9% error and can handle larger
designs without divergence. This model presents a viable
solution of NEMS modelling for larger NEMS-based VLSI
designs.
1. INTRODUCTION
During the last 4 decades, the scaling of complementary
metal-oxide-semiconductor (CMOS) has provided significant
improvements in terms of performance and energy efficiency
of integrated circuits. This scaling has now arrived to a
point at which any further reduction in threshold voltage
of integrated circuits comes at the expense of power con-
sumption. As a consequence, designers have moved towards
parallel computing methodology [2]. In this method each
processor is designed to run at a lower throughput, energy
1/ Throughput 1/ Throughput
Figure 1: Plots of normalized energy per operation
vs. 1/throughput, illustrating the advantages of par-
allelism and its restricted effectiveness due to CMOS
minimum-energy constraint [6].
microprocessor can improve the overall system performance
by employing two parallel processing units as shown in Fig.
1. However, multi-core methodology will eventually become
impractical [18]. This is attributed to the fact that CMOS
approaches its minimum energy per operation constraint as
the number of processor cores increases. Consequently, this
would not result to any lower in energy consumption as
shown in Fig. 1.
To overcome the energy-performance constraint, another
MOSFET alternative devices have been emerged such as:
Tunnelling Field Effect transistor (TFET) [8], Tri-Gate tran-
sistor , Nano-electromechanical field effect transistor (NEM-
FET), ferroelectric FETs, impact ionization MOS. Unfortu-
nately, many of these CMOS like transistors achieve a steep
sub-threshold swing (S < 60mV /dec.) over only a specific
range of supply voltage. This leads to a significant short-
coming including: either a poor (Ion /Iof f ) current ratio or
a very low Ion current at a low supply voltage. A feasible
way to overcome the limitation of energy-efficiency in CMOS
circuits can be deduced from Fig. 2.
Drain Current [Log (Ids)]

per operation, and supply voltage. For example, a dual core

One decade CMOS


Ids
Ideal switch

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DAC ’14 SAN FRANCISCO, CA, USA Figure 2: Sub-threshold regime of MEM relay and
Copyright 20XX ACM X-XXXXX-XX-X/XX/XX ...$15.00. CMOS transistor.
 Spring-Mass-Damper
K b Model

 
  


    

   
Source Base Drain
Insulator : 

Substrate : Si

(a) (b)

Figure 3: (a) Schematic 3-D view of 4-terminal suspended gate MEM relay based on [18], (b) Schematic 2-D
cross section view in the off state.

If the slope of sub-threshold regime of CMOS can be made 2. BACKGROUND

steeper, CMOS circuits would experience immeasurable low Relays can be classified based on the method of actua-
leakage current at the same supply voltage, making it possi- tion into electrostatic, electrothermal, magnetostatic, and
ble for further improvements in energy-efficiency. This will piezoelectric. However, they could be also classified either
require, then, an alternative device that overcomes the es- according to the axis of deflection (lateral, vertical) or to the
sential CMOS energy-efficiency limit. contact interface (ohmic or capacitive).
To that end, a micro-electro-mechanical (MEM) relay (shown Based on the method of actuation, each relay has differ-
in Fig. 3) has recently emerged for ultra-low-power digital ent characteristics including: bias voltage, bias current, on
circuit applications [18] [7] [12]. This is because the relay resistance, delay time, current handling, and endurance as
exhibits perfect abrupt on-off switching behaviour, since it illustrated in Table I.
has nearly an ideal switch characteristic. Furthermore, the Among these relays, MEMS has recently received a re-
MEM relay has immeasurable off-state leakage current and markable attention in digital logic applications due to: low
steeper sub threshold slope. Therefore, its operating volt- active power consumption, being scalable, and easy to manu-
age can be scaled down to approach zero, in principle. Thus, facture using conventional planar processing techniques [12].
the MEM relay can potentially overcome the fundamental To minimize the parasitic capacitor effects and improve the
energy efficiency limit of the CMOS technology. reliability, drastic improvements in relay design have led to
Having a scalable model for NEM relay is crucial for de- design and fabricate three generations of MEMS as reported
sign systems consist of mixed NEMS and CMOS electronics. in [11]. As a consequence, numerous implementations of
To evaluate the mechanical, electrical and logical character- MEM and NEM relay have been proposed recently that in-
istics of a MEM relay at the 90 nm technology node for dicate an order of magnitude more power saving than CMOS
a range of VLSI circuits, efforts by Matt Spencer have led in low frequency applications ≤ 100 MHz [7] [4] [19] [9] [10].
to build a Verilog-A switch model based on experimental re- In general, MEM relays can be classified into two types:
sults in [18]. This model is accurate and detailed, however, it 1. Three-Terminal MEMS: a 3-Terminal (gate, drain, source)
suffers from the long simulation time and convergence prob- laterally actuated relay has been designed and fab-
lem. To overcome the limitations of the model in [18], this ricated in [1] to achieve 1ns pull-in delay and 0.1 fJ
paper proposes an approximate model which is more scal- switching energy at 1.5V. However, connecting many
able, fast, simple, and more stable (especially near contact 3-T switches in series causes the gate to source volt-
discontinuities). The major contributions of this paper are: age change undesirably, and hence this may affect the
1. Implementing and evaluating the standard NEMS model. state of switch [14].
The model is analysed and pros and cons are evaluated 2. Four-Terminal MEMS: a vertical actuated relay as shown
and discussed. The model is found to be accurate. in Fig. 3 and 4 has emerged to overcome the short-
However, it suffers from the convergence problem for comings of the 3-T relay. The state of switch can be
large designs due to the model’s complexity.
2. Building a more scalable NEM relay model which can
be applicable for VLSI circuits without any divergence Table 1: MEM Relay Characteristics
issue. Actuated Switching Current Bias
MEMS Voltage Time handling current
3. Verifying the proposed model against a range of bench- [V] [µs] [mA] [mA]
marks with an average error rate 5.9%. Moreover, for Electrostatic 1-100 0.1- 0.2 0.1-10 0
the same benchmarks our model didn’t suffer from di- Thermal 0.5-5 100-5000 10-2000 0.5-10
Magnetostatic 1-5 100-5000 10-2000 20-150
versity problems, while the standard one did diverge Piezoelectric 5-50 10-500 1-1000 0
as the model become big and complex in size.
 determined based on gate-body terminal voltage (Vgb ),
which is independent of the source-drain voltage. Fur-
thermore, adding the fourth terminal makes the re-
lay turn on either by applying positive Vgb (mimick-
ing NMOSFET operation) or by applying negative Vgb
(mimicking operation of PMOSFET). The 4-Terminal
relay can then be categorized into two types:
(A) Cantilever Beam Relay: This relay consists of gate elec-
trode that carry a metal channel separated by a gate oxide,
in addition to body, drain, and source electrode which is
located below the gate as shown in Fig. 4. When the gate-
body voltage increases above “pull-in voltage” (|Vgb | ≥ Vpi ),
a contact dimples touch the source and drain terminal, caus-
ing the current flow. While, the electrical contact is broken
when the gate-body voltage decreases below the “pull-out
voltage” (|Vgb | ≤ Vpo ), as shown in Fig.4 (b) and (c).
(B) Suspended Gate Relay: To alleviate the impacts of
any residual stress that may cause bending the beam out
of plane, a suspended gate relay, as shown in Fig. 3, has
emerged to address this problem. The position of gate elec-
trode depends on the balance between the electrostatic force
and the spring force. As a result, when the electrostatic force
is sufficient enough to overcome the spring force, the chan-
nel touches drain/source electrode, thereby allowing cur-
rent to flow. Otherwise, an air gap separates channel from
drain/source electrode when the electrostatic force is less
than the spring force. It was reported in [18] that the MEM
relay operates at 8-10V with a 90nm gap thickness (gd ) be-
tween drain/source electrode and dimple. Like CMOS, scal-
ing the MEM relay can improve the performance and min-
imize the energy of operation [7]. In this context, [18] has
implied that MEM relay in the 90nm technology node with
5nm gap thickness (gd ) can operate at less than 0.5V.
3. MODELLING OF SUSPENDED GATE NEM
RELAY
3.1 Terminology and definition of NEM relay
parameters
Operating in a pull-in mode (i.e, ggd0 ≥ 0.3) results in most
energy-efficient relay which is more preferable for digital
logic applications [7]. However, pull-in mode of operating
causes the electrical characteristics of MEM relay exhibit
some hysteresis behaviour [16]. Pull in voltage (Vpi ) refers
to the voltage which is able to overcome the resistance of the
Figure 4: Cantilever beam relay as reported in [3]
(a) plan view (b) cross-section view in the off-state
(c) cross-section view in the on-state.
spring-mass-damper system and causes the relay to turn on.
While, release voltage (Vrl ) refers to the voltage required to
pull-out the device. The mechanical turn-off delay time is
less than mechanical turn-on time (Tmon > Tmof f ). This
is attributed to the fact that the electrical contact is bro-
ken rapidly as the gate electrode moves 1 nm away from
the body electrode [18]. While, the gate electrode needs to
travel the entire gap between gate and body to turn the de-
vice on. Noticeably, the mechanical delay time is an order
of magnitude more than the electrical delay time. For ex-
ample, the mechanical delay time of the adopted NEM relay
in this work is about 15ns which is approximately 100 times
more than the electrical delay time.
3.2 Mechanical Modelling
The movement of gate electrode under the applied volt-
age is governed by a Nonlinear time-variant second order
differential equation [5]. The spring-mass-damper system as
shown in Fig. 3(b) has been used to model the mass of the
gate and flexures.
p
2
kmef f
mef f Z̈ + Ż + kZ = Fele (Z) + Fvdw (Z) (1)
Q
where, Z is the displacement of the gate, mef f is the effec-
tive mass, Q is the quality factor between [0-1] for digital
logic applications [7], K is the spring constant, and Fvdw is
the Van der Waals’ force.
The electrostatic force Fele (which is always attractive, i.e.,
ambipolar) is equal to the derivative of electrostatic energy
stored in the Cgb capacitor with respect to the gap thick-
ness. 2
ε0 Aov Vgb
Fele = (2)
2(g0 − Z)2
where, ε0 is the permittivity of free space, Vgb is the voltage
between gate-body electrode, g0 is the area gap thickness
when Z=0, Aov is the overlap area between gate and body
electrode.
In a nano scale relay, undesirable attraction forces such
as Van der Waals’ force and Casimir force can significantly
affect the pull-in stability of NEM relay. It was noted in [17]
that, Van der Waals force is dominant over the dispersion
force when the air gap thickness is several tens of nano-
meters. Whereas, Casimir attraction force is the effective
one as the air gap thickness increases above several nano-
meters. Therefore, in this work only Van der Waals force
will be considered in the simulation as the gap thickness of
the adopted NEM relay is 10nm. The Van der Waals force
(Fvdw ) of the suspended gate NEM relay can be expressed
in a more intuitive formula based on [17] as:
AwL
Fvdw = (3)
6π(g0 − Z)3
where, A is the Hamaker constant, L and w is the length
and width of the suspended gate respectively.
The voltage required to switch-on the device “Vpi ” can be
derived as follow [16]:
s
8kg03
Vpi = (4)
27ε0 Aov
The mechanical delay time “Tmech. ” of NEM relay is in-
versely proportional to the gate over drive ( VVdd
pi
), resonant
q
k
frequency m , and actuation-gap to contact-gap thickness
ratio. This is presented as:
r
m Vpi gd
Tmech. ∝ .( ).( ) (5)
k |Vgb | g0
3.3 Electrical Modeling Newton’s second law. According to the state-space defini-
Unlike CMOS, a NEM relay based digital circuit should tion [13], a first order differential equations can be used to
be designed in a large complex logic gate such that only one describe the input, state, and output variables. This can be
mechanical delay incurs at each stage. However, this signifi- presented as:
cantly increases the total on-state resistance, and hence this   " 0 1
#   
Ż √ Z1 0
in turn leads to an increase in electrical delay time. Calcu- = −k − 2 kmef f + 1 (Fele. + Fvdw ) (7)
Z̈ Z2
lating the amount of time required to charge or discharge m Qm m
the load capacitance demands precise modeling of both the The procedure of simulating the NEM relay in this work
on-state resistance and the device capacitances. can be summarized according to the algorithm shown below:
The on state resistance of NEM relay, as shown in Fig. 5,
consists of Rtrace (resistance of wire leading to/and from Algorithm 1 NEMS model.
the tungsten electrode), Rch (the resistance of channel), Define: Source:=s, Drain:=d, Gate:=g, Base:=b, Displace-
Rcon (the resistance of the channel-drain/source contact), ment:=Z.
and Rpox (the resistance of passive oxide which is used to Define: Discipline: Electrical ← (s, d, g, b).
improve the endurance). Discipline: Kinematic ← (Z, velocity).
The load capacitance of a NEM relay is represented by Input: (Vg , Vs , Vb ).
Output: (Vd ).
several parasitic capacitances such as gate-body (Cgb ), gate- Define: Constant (Cgc , Ccb , Rtrace , Rch/2 , Rpox ).
source (Cgs ), gate-drain (Cgd ), gate-channel (Cgc ), and channel- Define: Dimple gap (gd ), Spring constant (k), mass, Damping
body (Ccb ) capacitance. In the off-state, the gate to channel ratio.
Cgc capacitance will not be contributed in the overall ca- 1: Initially (Vg , Z) ← 0.
pacitance as the channel terminal is floating. The electrical 2: Calculate Fe , Fs , Fvdw at (Z = 0).
delay required to charge and discharge the NEM relay para- 3: Calculate Z1 by solving:
sitic capacitance can be written in an approximate formula Ż = velocity
√ = Z2
1 − 2 kmef f
as: Tele. = Ron (Cgb + Cgd + Cgs ) (6) Z̈ = m ( Qm
Z2 − kZ1 + Fele. + Fvdw ).
g 4: If Z1 < gd Then: (NEM relay is on)
 /
  / ε0 Aov ε0 A(d)
5: Calculate Cgb = (g0 −Z1 )
, Cgd = Cgs = (g0 −Z1 )
, Rcon =
f 4ρλξH


 3Fele (gd)
,
Fele , Fvdw .




 +  


 +  
6: Find: V (d, a) = V (j, s) = Rtrace ∗ I(d, a), I(g, a) = I(g, j) =
  dV(g,j)
d   Cgs ∗ dt
, V (a, f ) = V (f, j) = R(ch/2+pox+con) ∗ I(f, a),
a b s dV
j I(f, g) = Cgc ∗ (g,f dt
)
.
7: Find I(d, s), Tele , Tmech , Vpi .
2 .
8: Calculate Switching Energy: Es = (Cgb + Cgd + Cgs )Vdd
Figure 5: On-state electrical characterictics of NEM
relay [18]. 9: else: I(d, s) = 0. (NEM relay is off)

3.4 Simulation of Suspended Gate NEM relay 3.5 Proposed Model

A digital NEM relay can be modeled by incorporating all
the mechanical and the electrical effects shown in Fig. 3. An
accurate conservative Verilog-A model has been adopted in
this work to simulate the behavior of NEM relay based on
fabricated parameters published in [18], and shown in Table
II.
The Verilog-A has been utilized in this work as it has
a multiphysics framework, which deals with different dis-
ciplines such as kinematic, electrical, thermal, and fluidic.
This Verilog-A model is co-simulated with the Cadence solver
to simulate the mass-spring-damper system defined in Eq.1
and the electrical model shown in Fig. 5. Noteworthy, this
model can handle the self-actuation effects of the NEM re-
lay but does not cover the thermal impacts on the electrical
parameters. In order to avoid hidden states in Verilog-A,
the state-space form has been used to rewrite the inhomo-
geneous nonlinear differential equation (Eq. 1). This equa-
tion describes the motion of the gate electrode according to
The equivalent electrical circuit of the NEM relay can be
simplified to a lower complexity model. This is advanta-
geous to mitigate the non-linearity issue in the standard
model (which is one reason of the divergence problem) while
sacrificing some degree of accuracy. This assumption is in-
spired by the transmission line model approximation in [15].
The proposed simplified paradigm of the NEM relay can be
explained through the following stages:
1. The trace resistance is very small in comparison with
Rcon , Rpox , and Rch/2 therefore it can be ignored.
Rtrace  Rcon , Rtrace  Rpox , Rtrace  Rch/2 . Due
to a small overlap area between the body and channel
electrode, Ccb is insignificant and can be neglected. In
the same way, Ccg can be ignored, as shown below:
(Ccg +Ccb )  Cgb , (Ccg +Ccb )  Cgd , (Ccg +Ccb ) 
Cgs .
g
 /  /




 +   

 +  
Table 2: NEMS parameters based on [18]
g0 10 nm d s
gd 5 nm b
Aov 0.77 [µm2 ]
A 12 [µm2 ] 2. The non-linear parasitic capacitor Cgd , and Cgs can be
Cgd (Z = 0), and Cgs (Z = 0) 0.6 [f F ] linearised by taking the maximum value (Cgd = Cgs =
Cgb (Z = 0) 1.46 [f F ] 0.6f F at Z = 5 nm). Then, they have been added
R(ch/2+con+pox) 800 Ω together as shown below.
 g
7.0

Latency Error [%]

A40 Measure Error [%]

 +
A2 Linear Fit
A1 6.5
/ / A0 6.0
Vs

 A1 A10 A40 5.5

 +
  +
 5.0

A0
d b s 4.5
A1 A10 A40
VB 0 5 10 15 20 25 30 35 40
VG Number of stages
3. In the same way, Rcon can be linearised by taking the
Ω (a) (b)
average value (200 [ contact ]). Then, it has been added
to the Rpox and Rch/2 resistance, as shown below.
g Figure 6: (a) CMOS-NEM relay mapping of cascade
AND gates (b)Latency Error rate.

 +

f

 +
 average. However, as the size of the circuits increase, the

 +

 +
/ simulation time of the standard model is expected to be in-

 +
/
d b s creasing drastically, and hence this percentage can be con-
sidered only for the used benchmark circuits.
In terms of computational complexity, the original model In terms of latency, results indicate a small difference be-
needs to solve 8 non-linear equations to approach the solu- tween the output signal of the two models (less than 6% in
tion. While our proposed model can approach the solution average). This is attributed to the presence of approxima-
by only solving 5 non-linear equations as shown in Algorithm tion in the electrical circuit of the proposed model. It has
II. been noted from the results in Table III that the standard
Algorithm 2 Proposed NEMS model. model usually diverges when the design becomes complex
Define: Source:=s, Drain:=d, Gate:=g, Base:=b, Displace-
and big in size, such as in: 3-inputs C-Element and 5-bit
ment:=Z. carry ripple adder. This is attributed to the fact that the
Define: Discipline: Electrical ← (s, d, g, b) accumulating error due to contact discontinuities will rise
Discipline: Kinematic ← (Z, velocity). significantly as the number of stage increases. Furthermore,
Input: (Vg , Vs , Vb ). numerous number of non-linear parasitic capacitance in the
Output: (Vd ). big design is the second reason of causing the model to be
Define: Constant(Cgc , Ccb , Rtrace , Rch/2 ,Cgd ,Cgs ,Rpox , Rcon ).
diverging.
Define: Dimple gap (gd ), Spring constant, mass, Damping ratio.
1: Initially (Vg , Z) ← 0. The proposed model has checked against the standard one
2: Calculate Fe , Fs , Fvdw at (Z = 0). for different clock speed and stage levels. Results in Fig. 7
3: Calculate Z1 by solving Eq. 7. have shown a very slight impact in the simulation time of
4: If Z1 < gd Then: (NEM relay is on) the proposed model can happen as the clock period changes
5: Calculate Cgb , Fele , Fvdw . from 100ns to 500ns. For example, at stage four the simula-
6: Find: V (d, f ) = V (f, s) = R(pox+ch/2+con) ∗ I(d, f ), tion time increases only 10% as the clock period changes to
dV dV
I(f, g) = 2Cgd ∗ (g,f dt
)
, I(g, b) = Cgb ∗ (g,b)
dt
. 500ns. In contrast, the standard model shows a significant
7: Find I(d, s), Tele , Tmech , Vpi , and Es . 800
8: else: I(d, s) = 0 (NEM relay is off) Standard model [100ns]
Simulation time [sec.]

700 Proposed model [100ns]

Standard model [500ns]
4. MODEL EVALUATION 600 Proposed model [500ns]
500
4.1 Simulation of the Proposed Model 400
To verify the validity of this model, the error rate (la-
300
tency) between the output signal of the standard and pro-
200
posed model of cascade AND gates, as shown in Fig. 6(a),
100
has been measured. The results indicate that a 4.6 % error
rate can be noted between the output signal of the two mod- 0
1 2 3 4
Number of stages
els in the case of adopting one AND gate, while it increases
to less than 7% after cascading of 40 AND gate in series as
shown in Fig. 6(b). Noteworthy, the error rate is linearly Figure 7: Model execution time versus clock speed
proportional with the number of stages, which is advanta- and number of stages.
geous for adopting this model with this acceptable error rate increasing (which is about 26% at stage four) in the simula-
in the VLSI circuits. tion time as the clock period shifts from 100ns to 500ns. This
is attributed to the fact that the discontinuity period of the
4.2 Evaluation with Benchmark Circuits switch will be shorter as the switching frequency increases,
To evaluate the proposed model in terms of latency, scal- and this make the simulator approaches the solution very
ability, simulation time and stability, it has been checked fast. In contrast, the simulator needs long time to approach
against a range of benchmark circuits including: combina- the solution at low switching frequency (long discontinuity
tional (AND, OR, XOR), sequential (D-latch, C-Element), period).
and arithmetic (carry save adder, carry ripple adder) as
shown in Table III. Results have clearly shown that, the 5. CONCLUSION
proposed model is 28 % faster than the standard model on Scaling of CMOS has arrived to a point at which any
 Table 3: NEM Model Benchmark circuits
Circuit No. of relays Latency Simulation Time
Standard Proposed Error Standard Proposed Improvement (%)
AND Gate 2 15ns 15.7ns 4.6% 3m 4s 2m 23s 23%
Logic OR Gate 2 15ns 15.6ns 4.0% 4m 49s 3m 26s 29%
XOR Gate 2 15ns 15.5ns 3.3% 848 ms 783 ms 7%
D-latch 4 15ns 15.7ns 4.6% 1m 47s 1m 2s 41%
Sequential 2-input C-Element 10 15ns 16ns 6.0% 6m 28s 3m 55s 39%
3-input C-Element 14 Div. 17ns —- Div. 9m 19s —-
1-bit 3-input CSA 22 15ns 17ns 13% 13m 23s 9m 37s 28%
Arithmetic 1-bit CRA 12 15ns 16ns 6.0% 6m 52s 4m 37s 33%
2-bit CRA 24 Div. 18ns —- Div. 14m 34s —-
5-bit CRA 60 Div 22ns —- Div. 31m 35s —-
Average 5.9% 28%

further reduction in threshold voltage of integrated circuits
comes at the expense of high power consumption. Further-
more, supply voltage of the smaller node technology is not
expected to be scaled less than the limit set by kT q
. Thus,
an alternative device with a less energy-hungry and steeper
sub-threshold regime like a NEM relay is necessary to be im-
plemented in integrated circuits. NEM models are crucial
to EDA design. However, the standard NEM model suffers
from convergence problem and long execution time. This pa-
per proposes a new simplified NEM model that can be used
for large scale circuit simulation with insignificant error. The
proposed model is evaluated with a variety of benchmark cir-
cuits and results show it can be adopted for simulating VLSI
circuits with less than 6 % error rate. The proposed model
can be integrated in the existing EDAs and can be used for
simulating and designing of NEM-based VLSI circuits with
better scalability and less execution time than the standard
model.
6. REFERENCES
[1] Akarvardar, K., Elata, D., and et al. Design
considerations for complementary
nanoelectromechanical logic gates. In Electron Devices
Meeting, 2007. IEDM 2007. IEEE International
(2007), pp. 299–302.
[2] Asanovic, K., Bodik, R., and et al. The landscape
of parallel computing research: A view from berkeley.
Tech. Rep. UCB/EECS-2006-183, EECS Department,
University of California, Berkeley, Dec 2006.
[3] Chen, F., Kam, H., and et al. Integrated circuit
design with nem relays. In Computer-Aided Design,
2008. ICCAD 2008. IEEE/ACM International
Conference on (2008), pp. 750–757.
[4] Fariborzi, H., Chen, F., and et al. Design and
demonstration of micro-electro-mechanical relay
multipliers. In Solid State Circuits Conference
(A-SSCC), 2011 IEEE Asian (2011), pp. 117–120.
[5] Gupta, R., and Senturia, S. Pull-in time dynamics
as a measure of absolute pressure. In Micro Electro
Mechanical Systems, 1997. MEMS ’97, Proceedings,
IEEE., Tenth Annual International Workshop on
(1997), pp. 290–294.
[6] Jeon, J. Advanced Relay Design and Technology for
Energy-Efficient Electronics. PhD thesis, EECS
Department, University of California, Berkeley, Jul
2011.
[7] Kam, H., Liu, T.-J. K., and et al. Design,
optimization, and scaling of mem relays for
ultra-low-power digital logic. Electron Devices, IEEE
Transactions on 58, 1 (2011), 236–250.
[8] Kim, S. H., Kam, H., and et al. Germanium-source
tunnel field effect transistors with record high ion/ioff.
In VLSI Technology, 2009 Symposium on (2009),
pp. 178–179.
[9] Lee, D., Lee, W., and et al. Combinational logic
design using six-terminal nem relays. Computer-Aided
Design of Integrated Circuits and Systems, IEEE
Transactions on 32, 5 (2013), 653–666.
[10] Manohar, S., Venkatasubramanian, R., and
Balsara, P. Hybrid nems-cmos dc-dc converter for
improved area and power efficiency. In VLSI Design
(VLSID), 2012 25th International Conference on
(2012), pp. 221–226.
[11] Nathanael, R. Nano-Electro-Mechanical (NEM)
Relay Devices and Technology for Ultra-Low Energy
Digital Integrated Circuits. PhD thesis, EECS
Department, University of California, Berkeley, May
2013.
[12] Nathanael, R., Pott, V., and et al. 4-terminal
relay technology for complementary logic. In Electron
Devices Meeting (IEDM), 2009 IEEE International
(2009), pp. 1–4.
[13] Nise, N. S. CONTROL SYSTEMS ENGINEERING,
(With CD). John Wiley & Sons, 2007.
[14] Pott, V., Kam, H., and et al. Mechanical computing
redux: Relays for integrated circuit applications.
Proceedings of the IEEE 98, 12 (2010), 2076–2094.
[15] Rabaey, J. M., Chandrakasan, A., and Nikolic,
B. Digital integrated circuits- A design perspective,
2ed ed. Prentice Hall, 2004.
[16] Senturia, S. D. Microsystem Design. Springer
(India) Pvt. Limited, 2006.
[17] Shen, X., Chong, S., and et al. 2d analytical model
for the study of nem relay device scaling. In
Simulation of Semiconductor Processes and Devices
(SISPAD), 2011 International Conference on (2011),
pp. 243–246.
[18] Spencer, M., Chen, F., and et al. Demonstration of
integrated micro-electro-mechanical relay circuits for
vlsi applications. Solid-State Circuits, IEEE Journal
of 46, 1 (2011), 308–320.
[19] Venkatasubramanian, R., Manohar, S., and
Balsara, P. Nem relay-based sequential logic circuits
for low-power design. Nanotechnology, IEEE
Transactions on 12, 3 (2013), 386–398.