Prime time analysis Modes: Extracted Timing Model (from netlist)

1.Single operating condition mode: #primetime

(setup,holdsingle operating condition) .synopsys_pt.setup
»simple test set search_path {. ./designs ./STAMP\
2.Best case/worst case operating condition mode QuickTime™ and a ./QTM ./OC_BLOCK./EXTRACT]
(setupupworst case ____; TIFF (LZW) decompressor note: each directory is separated by space
holdbest case _____; are needed to see this picture. set link_path {* ./libs/mymodel_lib.db\
»pessimistic & reasonable, allows 2 operating ./QTM/STACK_lib.db ./STAMP/y_lib.db}
conditions.
3.on chip variation  most pessimistic read_db UPC.opt.db
Timing Parameters used for setup check: (by link_design UPC
default, it is single operating condition) source extract_constraint.pt –echo
Analysis Launch Data Capture set_multicycle_path –setup 2/6 –from\ update_timing
mode clock path a clock [get_cells FF4] –to [get_cells FF5] write_script –output
path path set_multicycle_path –hold 1/5 –from [_] to [ ] ./EXTRACT/const_UPC.opt.pt
Single max max min set extract_model_data_transition_limit 5.0
operating delay delay delay write_interface_timing ./EXTRACT/netlist.rpt –
condition verbose
best/worst max max min QuickTime™ and a extract_model –output ./EXTRACT/UPC.extr\
TIFF (LZW) decompressor
case delay delay delay are needed to see this picture. format {lib db} –library –cell
operating (worst) (worst (worst remove_design –all
condition case) case) remove_lib *
on-chip max max min
variation delay delay delay Bottleneck Analysis:
set_multicycle_path –setup 6 –to [get_pins report_bottleneck
»lot of (worst (worst (best
“c_reg[*]/D”] cell reference cost
calculation case) case) case)
set_multicycle_path –hold 5 –to [get_pins report_alternative_lib_cells –libraries core_slow
time
“c_reg[*]/D”] U43186 # this finds out a better cell than U$3186
Note: these constraints removes the delay caused
by launching & capturing clock. Swap_cell U43186 core_slow|BUFX20
Notr: Primetime cannot optimize, it only does #if BUFX20 is better than can be swapped
Timing_remove_clock_reconvergence_permission
timing analysis
report_design : to view PVT
*everyting insert_buffer
report_clock
? single character remove_buffer
report_cell –connection to view the connections
Block Optimization create_cell
report_cell-connections –verbose gives detailed
set_operating_conditions –library pt_lib WCCOM remove_cell
report
report_design connect_net
report_net
characterize_context {u2 u3} remove_net
report_path_group if capturing clock is same.
write_context u2 –output\ disconnect_net
Report_port
./SCRIPT_OP/UPC.char.dctcl –format dctcl
Report_disable_timing
write_context u3 –output ./SCRIPT_OP/ Standard Delay Files:
Group_path  to group different paths
UPS.char.dctcl –fromat dctcl
eg:group_path –name INPUTS –from [all_inputs]
Write_context REGENT.char.dctcl –output\
group_path –name OUTPUTS –to [all_outputs]
./SCRIPT_OP/UPC.chardctcl –format\dctcl
report_timing –group INPUTS QuickTime™ and a
write_script –format ptsh –output\ TIFF (LZW) decompressor
group_path COMBINATIONAL_PATHS(ALL) – are needed to see this picture.
./SCRIPT_OP/AMZ910.new.pt
from [all_inputs] –to [all_outputs]
#open design vision
using primetime:
source optimize.dctcl
.sysnopsys_pt.setup
exit # quit design vision <cell
set search_path {../designe ____}
#PRIME TIME (cell_type “and2”)
set linkpath {* . /libs/mylib.db}
read_db {REGCNT.opt.db upc.opt.db} (instance top/b/d)
read_verilog mydesign.v
current_design AM2910 (delay
(read_ddc ww.ddc
swap_cell u3{REGCNT.opt.db:REGCNT} (absolute
read_db
swap_cell u2 {UPC.opt.db:UPC} (IOpath a y (1.5:2.5:3.4) (2.5:3.6:4.))
read_sdf)
source ./SCRIPT_op/AM2910.new.pt (IOpath b y (1.5:2.5:3.4) (2.5:3.6:4.))
link_design
check_timing )
create_clock –p 6666 –name clk [get_ports clk1]
report_constraints –all_violators (cell
set_clock_latency 2.0 clk
report_timing (celltype “DFF”)
set_input_delay 2.0 –clockclk [get_ports in*]
NOTE: -prelayout timing analysis (delay
set_output_delay1.0 –clock clk [all_outputs]
Then focus on setup violations than hold (absolute
report_clock
-Buffers can be added to minimize (IOpath (posedgeclk) q(2:3:4) (5:6:7))
report_clock
to disable a path; no timing analysis on that path #prop delay of D flipflip: from clk ot q
report_clock_skew
-set_case_analysis o [get_ports (port clk (2:3:4) (5:6:7))
report_port –input_delay
CONDITION_code] )
report_port –output_delay
before getting clock report, we should check )
report_case_analysis
wheather all the scripts are good & complete
report_disable_timing Timing Check
check_timing
report_timing (TIMING CHECK
set_driving_cell –lib_cell IV [all_inputs]
report_mode #data, reg, stack, UPC (SETUPHOLD d (posedge clk) (3:4:5) (1:1:1))
set_load –pin_load 1 [all_outputs]
set_case_analysis o [get_pins U4/operation [*]] (WIDTH clk (4.4:7.5:11.3))
set_wire_load_model –name10kgates
set_mode data U4/core )
report_design
report_timing )
if we want to remove all of these netlist & apply
report_timing –to y_output*
a new netlist then  remove design –all
set_mode stack U4/core to read standard delay file use read_sdf
it the new netlist is from new vendor thern 
report_mode -read*
remove_lib –all
report_timing –to Y_output * TCL scripting: (same as perl)
Timing Exceptions:
remove_case_analysis [get_pins U4/OPERATION set DESIGN_BLOCKS {aclk bclk cclk dclk}
used to override the default single –cycle
[*]] for each CLK_FROM $DESIGN_BLOCKS{
constraints described by create_clock,
report_care_analysis set_false_path –from $clk_FROM –to\
set_input_delay and set_output_delay
reset_mode [remove_from_collection [all_clocks]\
set_false_path > set_max_delay or
report_mode $CLK_FROM]
set_min_delay>set_multicycle_path
exit }
-set reqcells [get_cells –hier * -filter{\
full_name=~xyz/* && is _seqential\ -data_file #Block Optimization
==true}] ./design/STAMP/STAMP_MODEL_Y.data --set_operating_conditions –library pt_lib
This finda all of the sequential cells in hierarchy --output ./STAMP/Y. WCCOM
-set_false_path –from $seqcells --report_design
set_false_path –to $seqcells QUICK TIMING MODEL (FOR) --characterize_context {U2 U3}
NOTE: read DFT online --Source create_qtm_model_stack.pt --write_context U2 –output
--save –qtm_model –output ./QTM/STACK – script_op/UPC.char.dctcl –format dctcl
format db (or ddc) --write_context U3…….
QUICK TIMING MODEL: --#./QTM/STACK _lib.db ……./REGENT.char.dctcl/…..
SET GLOBAL PARAMETER --#./QTM/STACK.db --conte_script
1.tech library 2.path library For
3.flip-flop setup, hold time, clk to output delay --.synopsys_pt.setup (in this file like) PRIME TIME
4.load type 5.drivetype --set search_path {. ./designs ./stamp Primetime:
SET MODEL INFORMATION ./QTM ./DV_BLOCK_OPT} Cannot do synthesis, can analyze bigger circuits.
1.model port 2.input port capacitance --set link_path {* ./libs/mytech.lib It is both pre and post layout timing analysis.
3.output port drive 4.timing arcs ./QTM/STACK_lib.db ./STAMP/Y_lib.db}
Delay Info:
STAMP MODEL #for reading Standard delay format(SDF)
1. model file 2. Model data file --read_db AM2910.db Parasitic data is reduced standard parasitic
link_design AM2910 format(RSPF)[less details, reduced net]
1) MODEL FILE Parasitic data is detailed standard parasitic
--MODEL #design hierarchy format(DSPF)[has more details,more capacitances]
--VERSION “1.0”; --report_reference Standard parasitic exchange format(SPEF)
--DESIGN “MY RAM”; Synopsis binary parasitic format(SBPF)
--INPUT DI | [15:0] #for best_case/worst_case analysis: SPEF is a IEEE standard other tools may follow.
--INPUT A| [6:0} --Set_operating_conditions –library pt_lib – SBPf is a synopsis format . Other tools dnt
--INPUT RWN1; min BCCOM –max WCCOM follow(exclusive)
--OUTPUT D0 | [15:0]; --set_wire_load_mode top
--MODE ram_modes = read 1 WHEN --set_wire_load_model –library pt_lib –name Prime time analysis flow:
(“RWN1”) SDF_COND(“RWN==1b1”) 05x05 –min
--MODE ram_modes=write 1 WHEN (“| -- set_wire_load_model –library pt_lib – 1. Read design data:
RWN|”) SDF_cond(RWN==1b0”) name 20x20 –max Set search_path
--TAA1 : DELAY A1 D01 MODE Set link_path
(ram_modes = read 1) #setting operating conditions Read_db,read_verilog
--TWOD1 : DELAY DI | D0 | MODE --create_clock –period 30[get_ports CLOCK] Link_design
(ram_modes=write1); --set clk [get_clocks CLOCK] Read_sdf
--set_clock_uncertainity 0.5 $clk Read_parasitics
--END MODEL --set_clock_latency –min 3.5 $clk
--set_clock_latency –max 5.5 $clk 2. Constrain the design
Model Data File --set_clock_transition –min 0.25 $clk Create_clock
--MODEL DATA --set_clock_transisiton –max 0.3 $clk Set_clock_uncertainity
--DESIGN “my ram”; --set_clock_gating_check –setup 0.5 –hold Set_clock_latency
--MODEL DATA_VERSION “1.0”; 0.1 $clk Set_clock_transition
--OPERATING_CONDITION “fast” --set_min_pulse_width 2.0 $clk Set_input_delay
--VOLTAGE 3.30; --Report_design #operating condition Set_output_delay
--TEMPERATURE 25; #wire load model etc
--TIMESCALE “1PS”; 3. Specify the environment and analysis
--PORT DATA Check timing condition:
--DI1 [15:0] : MAXTRANS (3.300), CAP Set_operating_condition---PVT
(23); --set nonclock [remove_from_collection Set_load
: [all_inputs][get_ports clock]] Set_driving_cell
: --set_input_delay 0.5 $nonclock –clock $clk Set_wire_load-model-- pre layout
--ENDPORT DATA; --set_output_delay 2.0 Read_sdfpost layout
--CELLDATA; [get_port_INTERRUPT] –clock $clk Read_parasiticspost layout
--AREA: 12345.00; --set_output_delay 1.25[get_port Set_case_analysis
--ENDCELL DATA. OVERFLOW] –clock $clk Set_mode
--Set_driving_cell –lib_cell IV –library pt_lib Set_multicycle_path
Model Data File [all_inputs] Set_false_path
--TIMING DATA --set_capacitance 0.5[all_outputs] Set_disable_timing
--GLOBAL --check_timing #for checking
--14_table_template (delay_table) --write_script –format ptsh –output 5.perform a full anlysis and examine results:
{ variable_1: total_output_net_capacitance} AM2910.pt Report_timing
: --write_script –format dctcl –output Report_constraint
: AM2910.dttcl Report_bottleneck
--END GLOBAL Report_analysis_coverage
#intitial timing analysis
--ARC DATA --report_constraint 4.Check design and analysis:
--TAA, TOD 1; -report_constraint –all_violators Setup:
--cell_full (delay_table) {index_1 (“16, 32, --report_timing Check_timing
64, 128, 256, 1024”); #setting timing exception Report_clock
value (“2462, 2475, 2497.......); --set_false_path –from Report_design
: U3/OUTPUT_reg[*]/cp –to Report_port
: U2/OUTPUT_reg[*]/D Report_cell
--END ARC DATA --set_multicycle_path –setup 2 –from Report_net
--END TIMING DATA INSTRUCTION[*] –to U2/OUTPUT_reg[*] Report_hierarchy
--END MODEL DATA --set_multicycle_path_hold 1 –from Report_reference
INSTRUCTION[*] –to U2/OUTPUT_reg[*]
HIERARCHIAL ANALYSIS: --report_exceptions
--Compile_stamp_model/ --report_exceptions –ignored
-model_file --report_constraint _all_violation
./design/STAMP/STAMP_MODEL_Y.mod --report_timing –delay_type