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Introduction to FETs
Field-effect transistors (FETs) are unipolar devices, because unlike BJTs that use
both electron and hole current, they operate only with one type of charge carrier.
The two main types of FETs are the junction field-effect transistor (JFET) and the
metal oxide semiconductor field-effect transistor (MOSFET). A BJT is a current-
controlled device; that is, the base current controls the amount of collector
currents. A FET is different. It is a voltage-controlled device, where the voltage
between two of the terminals (gate and source) controls the current through the
device.
JFET [5]
Basic Structure:
Figure 7.1 A representation of the basic structure of the two types of JFET. [5]
Basic Operation:
Figure 7.2 shows dc bias voltages applied to an n-channel JFET. VDD
provides a drain-to-source voltage and supplies current from drain to source. V GG
sets the reverse-bias voltage between the gate and the source. The JFET is always
operated with the gate-source pn junction reverse-biased. Reverse-biasing of the
gate-source junction with a negative gate voltage produces a depletion region along
the pn junction, which extends into the n channel and thus increases its resistance
by decreasing the channel width. The channel width and the channel resistance can
be controlled by varying the gate voltage, thereby controlling the amount of drain
current ID. Figure 7.3 illustrates this concept when VGG = VGS.
JFET symbols:
The schematic symbols for both n-channel and p-channel JFETs are
shown in figure 7.4. Notice that the arrow on the gate points “in” for n channel and
“out” for p channel.
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JFET CHARACTERISTICS AND PARAMETERS [5]
Drain Characteristic Curve:
Consider the case when the gate-to-source voltage is zero (VGS = 0 V).
This is produced by shorting the gate to the source, as in Figure 7.5 (a). As VDD is
increased from 0 A, ID will increase proportionally, as shown in Figure 7.5 (b)
between point A and B. In this area, the channel resistance is essentially constant
because the depletion region is not large enough to have significant effect. This is
called the ohmic area because VDS and ID are related by Ohm’s law. At point B in
Figure 7.5 (b), ID becomes essentially constant. As VDS increases from point B to
point C, the reverse-bias voltage from gate to drain (VGD) produces a depletion
region large enough to offset the increase in VDS, thus keeping ID relatively
constant.
Figure 7.5 The drain characteristic curve of a JFET for VGS = 0 V. [5]
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VGS controls ID:
Let’s connect a bias voltage, VGG, from gate to source as shown in Figure
7.6 (a). As VGS is set to increasingly more negative values by adjusting V GG, a
family of drain characteristics curves is shown in Figure 7.6 (b). Notice that ID
decreases as the magnitude of VGS is increased to the larger negative values
because of the narrowing of the channel. For each increase in negative values of
VGS, the JFET reaches pinch-off at values of VDS less than VP. So, the amount of
drain current is controlled by VGS.
Cutoff voltage:
The value of VGS that makes ID approximately zero is the cutoff voltage,
VGS(off). This cutoff effect is caused by the widening of the depletion region to a
point where it completely closes the channel, as shown in figure 7.7. The JFET
must be operated between VGS = 0 V and VGS(off). For this range of gate-to-source
voltages, ID will vary from a maximum of IDSS to a minimum of almost zero. The
relation between VP and VGS(off) is VP = –VGS(off).
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Figure 7.7 JFET at cutoff. [5]
Example 1:
(a) For the JFET, VGS(off) = – 4 V and IDSS = 12 mA. Determine the minimum value
of VDD required to put the device in the constant-current are of operation.
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(b) If VDD is increased to 15 V, what is ID and VDS?
Solution: ID remains at approximately 12 mA.
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Figure 7.11 JFET transfer characteristic curve (n-channel). [5]
The JFET transfer characteristic curve shows that the operating limits of a JFET
are ID = 0 when VGS = VGS(off)
and ID = IDSS when VGS = 0
The JFET transfer characteristic curve can be developed from the drain
characteristics curves, as illustrated in figure 7.12. For example, when V GS = – 2 V,
ID = 4.32 mA. Also, for this specific JFET, VGS(off) = – 5 V, and IDSS = 12 mA.
Figure 7.12 n-channel JFET transfer characteristic curve (blue) from the JFET
drain characteristic curves (green). [5]
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A JFET transfer characteristic curve is expressed approximately as
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Using the minimum values of VGS(off) = – 0.5 V and IDSS = 1 mA, we can solve for
the following points.
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JFET Biasing Circuits [5]
7.3.1 Gate Bias (or Fixed Bias)
The gate bias of biasing arrangements for the n-channel JFET appears in
Figure 7.14. The configuration of Figure 7.14 includes the ac levels Vi and Vo and
the coupling capacitors (C1 and C2). Recall that the coupling capacitors are “open
circuits” for the dc analysis and low impedances (essentially short circuits) for the
ac analysis. The resistor RG is present to ensure that Vi appears at the input to the
FET amplifier for the ac analysis.
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From Figure 7.15, using KVL:
Example 4: The JFET has values of VGS(off) = -8 V and IDSS = 16 mA. Determine
the values of VGS, ID and VDS for the circuit.
Example 5: Determine the Q-point values for the gate biasing circuit if V GG =
0.5V , VGS(off) = -7 V , IDSS = 9 mA , VDD = 5 V and RD = 500 .
Solution:
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Figure 7.17 For Example 5.
Example 6: From Figure 7.16, determine the range of Q-point values. Assume that
the JFET has ranges of VGS (off) = – 1 to – 7 V and IDSS = 2 to 9 mA.
Solution:
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Figure 7.18 For Example 6.
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Figure 7.19 Self-bias configuration.
Example 7: Determine the Q-point values for the self biasing circuit if V GS(off) =
‒ 8 V , IDSS = 16 mA , VDD = 10 V , RD = 500 , RG = 1 M and RS = 500 .
Solution:
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Figure 7.20 For Example 7.
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Example 8: Plot the range of Q-point values. Assume the JFET in the self biasing
circuit has parameters of VGS(off) = -5 to -10 V and IDSS = 5 to 10 mA. Assume RD =
500 , RG = 1 M and RS = 500 .
Solution:
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Figure 7.21 For Example 8.
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The method used to plot the dc bias line for the voltage-divider bias is as follows:
2. Calculate VG.
Example 9: Plot the dc bias line and the Q-point for the voltage-divider biasing
circuit. Let R1 = 1.5 M, R2 = 1.5 M, RD = 1.1 k, RS = 10 k,VGS(off) = -8 V ,
IDSS = 16 mA and VDD = 30 V.
Solution:
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For voltage – divider bias:
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Example 10: Plot the dc bias line and the range of Q-point for the circuit shown in
Figure 7.23. Here, assume VGS(off) = -2 to -8 V and IDSS = 4 to 16 mA.
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For voltage – divider bias:
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Homework 11
1. For the JFET in Figure 7.25, VGS(off) = 2 to 5 V and IDSS = 5 to 10 mA.
(a) Using these values, plot the maximum transconductance curve, minimum
transconductance curve, DC bias line and the range of Q-point values.
(b) Determine the values of VGS and ID at the minimum Q-point.
2. For this JFET, VGS(off) = 6 V and IDSS = 12 mA. (a) Using these values, plot the
transconductance curve (or transfer characteristics), DC bias line and Q-point.
(b) Determine the values of VGS and ID at Q-point.
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(a)
(b)
Figure 7.27 For problem 3.
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4. Consider the graph in Figure 7.28(a) and the circuit in Figure 7.28(b). (a) Find
RS in the circuit of Figure 7.28(b). (b) Calculate the values of VGS and ID at the Q-
points in the graph in Figure 7.28(a). (c) Find RD in the circuit of Figure 7.28(b).
ID (mA)
40
DC bias line 30
20
10
Q-point
VGS (V)
0 (a)
- 20 - 15 - 10 -5
+ VDD
+ 20 V
RD
1 k
+
5V
RRGG RS
12 M R
1 k
S
M
(b)
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MOSFET [5]
Recall that the reverse bias of the gate is varied to deplete the channel in
JFETs. This type of operation is called depletion-mode operation. A depletion-type
device is a device that uses an input voltage to reduce the size of the channel to
control the amount of current. An enhancement-type device is a device that uses an
input voltage to increase the size of the channel to control the amount of current.
JFETs can operate only in depletion mode. There are two types of MOSFETS:
depletion-type MOSFETs or D-MOSFETs, and enhancement-type MOSFETs, or
E-MOSFETs. There are two types of channel: n-channel and p-channel. We will
use the n-channel MOSFETs to describe the basic operation, as shown in Figure
7.29, and 7.30. The p-channel MOSFETs is the same, except the voltage polarities
are opposite those of the n-channel.
Here,
The channel already exists.
An input voltage to the gate will increase or decrease the channel size.
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Figure 7.30 N-Channel enhancement-type MOSFET(NMOS)
Here,
The device has no channel.
An input voltage to the gate will form a channel.
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Figure 7.31 Representation of the basic structure of D-MOSFETs. [5]
Depletion Mode:
Visualize the gate as one plate of a parallel-plate capacitor and the channel
as the other plate. The silicon dioxide insulating layer is the dielectric. With a
negative gate voltage, the negative charges on the gate repel conduction electrons
from the channel, leaving positive ions in their place. Thereby, the n channel is
depleted of some of its electrons, thus decreasing the channel conductivity. The
greater the negative voltage on the gate, the greater the depletion of n-channel
electrons. At a sufficiently negative gate-to-source voltage, VGS(off), the channel is
totally depleted and the drain current is zero. This depletion mode is illustrated in
Figure 7.32 (a). Like the n-channel JFET, the n-channel D-MOSFET conducts
drain current for gate-to-source voltages between VGS(off ) and zero. In addition, the
D-MOSFET conducts for values of VGS above zero.
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Enhancement Mode:
With a positive gate voltage, more conduction electrons are attracted into
the channel, thus increasing (enhancing) the channel conductivity, as illustrated in
Figure 7.32 (b).
D-MOSFET Symbols:
The schematic symbols for both the n-channel and the p channel depletion
MOSFETs are shown in Figure 7.33. The substrate, indicated by the arrow, is
normally (but not always) connected internally to the source.
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D-MOSFET Transfer Characteristic:
The D-MOSFET has the same transconductance curve and equation as the
JFET.
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Figure 7.35 For Example 11.
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D-MOSFET Biasing Circuits [2]
Recall that D-MOSFETs can be operated with either positive or negative
values of VGS. A simple bias method is to set VGS = 0 V. A MOSFET with zero
bias is shown is Figure 7.36.
Example 13: Determine the drain-to-source in the circuit of figure 19. Assume
VGS(off) = -8 V, IDSS = 12 mA, VDD = 18 V, RD = 620 and RG = 10 M .
Solution:
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Enhancement MOSFET (E-MOSFET) [5]
The E-MOSFET operates only in the enhancement mode and has no
depletion mode. It differs in construction from the D-MOSFET in that it has no
structural channel. Notice in Figure 7.37(a) that the substrate extends completely to
the SiO2 layer. For an n-channel device, a positive gate voltage above a threshold
value induces a channel by creating a thin layer of negative charges in the substrate
region adjacent to the SiO2 layer, as shown in Figure 7.37(b). The conductivity of
the channel is enhanced by increasing the gate-to-source voltage and thus pulling
more electrons into the channel area. For any gate voltage below the threshold
value, there is no channel.
Figure 7.37 The basic E-MOSFET construction and operation (n-channel). [5]
The schematic symbols for the n-channel and p-channel E-MOSFETs are
shown in Figure 7.38. The broken lines symbolize the absence of a physical
channel. An inward-pointing substrate arrow is for n channel, and an outward-
pointing arrow is for p channel.
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E-MOSFET Transfer Characteristic:
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Example 14: For a 2N7008 E-MOSFET with ID(on) = 500 mA at VGS(on) = 10 V
and VGS(th) = 1 V. Determine the drain current for VGS = 5 V.
Solution:
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Figure 7.41 Voltage-divider bias of n-channel E-MOSFET. [5]
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Example 15: Determine VGS and VDS for the E-MOSFET circuit. Assume this
MOSFET has ID(on) = 200 mA at VGS = 4 V and VGS(th) = 2 V.
Solution:
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Example 16: Determine the amount of drain current for the circuit shown in
Figure 7.44. The MOSFET has a VGS(th) = 3 V.
Solution:
Therefore
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