CXL4

Hardware Description

Compiled by Thunder-link.com

A leading professional Huawei network product supplier

HUAWEI TECHNOLOGIES CO., LTD.

Copyright © Huawei Technologies Co., Ltd. 2013. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means
without prior written consent of Huawei Technologies Co., Ltd.

Trademarks and Permissions

and other Huawei trademarks are trademarks of Huawei Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their
respective holders.

Notice
The purchased products, services and features are stipulated by the contract made between
Huawei and the customer. All or part of the products, services and features described in this
document may not be within the purchase scope or the usage scope. Unless otherwise
specified in the contract, all statements, information, and recommendations in this document
are provided "AS IS" without warranties, guarantees or representations of any kind, either
express or implied.
The information in this document is subject to change without notice. Every effort has been
made in the preparation of this document to ensure accuracy of the contents, but all
statements, information, and recommendations in this document do not constitute a warranty
of any kind, express or implied.

Huawei Technologies Co., Ltd.

Address: Huawei Industrial Base
Bantian, Longgang
Shenzhen 518129
People's Republic of China
Website: http://www.huawei.com

Email: support@huawei.com
1.1 CXL4
This topic describes the version, application, functions, working principle,
front panel, and technical specifications of the CXL4 (1xSTM-4 SCC unit,
cross-connect unit, timing unit, and line unit integrated board). This topic also
describes how to configure and commission the CXL4.
5.2.1 Version Description
The CXL4 is available in several functional versions. The functions provided
by the functional versions are different.
5.2.2 Application
The CXL4 provides service processing, service grooming, clock input/output,
and communication control functions in the OptiX OSN system.
5.2.3 Functions and Features
The CXL4 processes SDH signals, controls communication, grooms services,
and inputs/outputs clock signals.
5.2.4 Working Principle and Signal Flow
The CXL4 consists of the synchronous timing module, O/E converting
module, MUX/DEMUX module, SDH overhead processing module,
communication and control module, cross-connect module, power module,
and other modules.
5.2.5 Front Panel
The front panel of the Q2CXL4 has indicators, an optical interface, functional
button switches, a bar code, and a laser safety class label. The front panel of
the Q3CXL4 has indicators, an optical interface, a bar code, functional button
switches, and a laser safety class label.
5.2.6 Jumpers and DIP Switches
The CXL4 has a jumper, which is used to set the enable state of the battery,
and a DIP switch, which is used to set the running state of the equipment.
5.2.7 Valid Slots
The CXL4 must be installed in a valid slot in the subrack. Otherwise, the
CXL4 cannot work normally.
5.2.8 Feature Code
The number code that follows the board name in the bar code is the feature
code of the board. The feature code of the CXL4 indicates the type of optical
interface.
5.2.9 Configuring and Commissioning the Board
After you select a correct board, you need to configure and commission the
board. The following tasks need to be performed: checking the hardware of
the board, configuring the board, commissioning the board, and checking the
operation of the board.
5.2.10 Parameter Settings
The physical slot that houses the CXL4 is different from the logical slot
displayed on the U2000. You can set parameters for the CXL4 by using the
U2000.
 5.2.11 Maintaining the Board
This topic describes the alarms and faults that may occur when the board
operates. This topic also provides the methods and precautions to be taken for
rectifying the faults.
5.2.12 List of Alarms
This topic lists the alarms that may occur when the board operates. The alarms
are reported according to the logical board on the U2000.
5.2.13 List of Performance Events
This topic lists the performance events that may occur when the board
operates. The performance events are reported according to the logical board
on the U2000.
5.2.14 Technical Specifications
The technical specifications of the CXL4 include the parameters specified for
optical interfaces, cross-connect capacity, clock access capability, laser safety
class, mechanical specifications, and power consumption.

1.1.1 Version Description

The CXL4 is available in several functional versions. The functions provided
by the functional versions are different.
Table 5-14 describes the versions of the CXL4.

Table 1-1 Versions of the CXL4

Item Description

Functional versions The CXL4 is available in two functional versions, namely, Q2 and
Q3. The Q3CXL4 is discontinued.

Differences The differences between the Q3CXL4 and the Q2CXL4 are as
follows:
 The Q3CXL4 supports the transmission of the DCC information
over the two-channel external clock interface.
 The Q3CXL4 hardware supports the CF card.
 The Q3CXL4 supports the transparent transmission of DCC bytes
when the TPS protection group is configured.

Substitution The Q5CXLLN can substitute for the Q2CXL4 that operates at the
same line rate by using the board version replacement function.

1.1.2 Application
The CXL4 provides service processing, service grooming, clock input/output,
and communication control functions in the OptiX OSN system.
The CXL provides the other boards in the system with the timing information,
processes the SDH signals, grooms the services between line boards or
tributary boards, communicates with the other boards in the system, and
performs the configuration and management functions for the other boards in
the system.
 Figure 5-8 shows the position of the CXL in the system.

Figure 1-1 Position of the CXL in the system

CXL
Line O/E Line
SDH converting
processing unit unit

Auxiliary
Auxiliary interface
SCC unit unit

Cross-connect and -48 V/-60 V

PIU
timing unit

PDH and other

service signals

1.1.3 Functions and Features

The CXL4 processes SDH signals, controls communication, grooms services,
and inputs/outputs clock signals.

1.1.3.0.1 SDH Processing Unit

Table 5-15 provides the functions and features of the SDH processing unit of
the CXL4.

Table 1-2 Functions and features of the SDH processing unit of the CXL4
Function and Feature CXL4

Basic functions Transmits and receives 1xSTM-4 optical

signals.

Specifications of optical interfaces Supports different types of standard optical

interfaces, namely, the I-4, S-4.1, L-4.1, L-4.2,
and Ve-4.2.

Specifications of the optical module
 Supports the detection and query of the
information about the optical module.
 Provides the ALS function. The optical
interface supports the setting of the on/off
state of a laser.

Service processing Supports the VC-12 services, VC-3 services,

VC-4 services, and VC-4-4c concatenation
services.
 Function and Feature CXL4

Overhead processing  Processes the section overheads of the

STM-4 signals.
 Supports the transparent transmission and
termination of the path overheads.
 Supports the setting and query of the J0, J1,
J2, and C2 bytes.
 Supports one channel of ECC
communication.

Alarms and performance events Reports various alarms and performance

events, which facilitates the management and
maintenance of the equipment.

Protection schemes Supports the following protection schemes:

 Two-fiber ring MSP
 Four-fiber ring MSP
 Linear MSP
 SNCP
 SNCMP
 SNCTP

Maintenance features  Supports inloops and outloops at optical

interfaces.
 Supports warm resets and cold resets. The
warm reset does not affect services.
 Supports the query of the manufacturing
information of the board.
 Supports the in-service loading of the
FPGA.
 Supports the upgrade of the board software
without affecting services.

1.1.3.0.2 SCC Unit

Table 5-16 provides the functions and features of the SCC unit of the CXL4

Table 1-3 Functions and features of the SCC unit of the CXL4
Function and Feature CXL4

Basic functions Configures and monitors services, monitors

the service performance, and collects the
information about the performance events and
alarms.
 Function and Feature CXL4

Specifications of the interfaces  Provides one 10M/100M compatible

Ethernet NM interface, which is accessed
through the SAP.
 Provides one 10M/100M Ethernet port,
which is used for implementing the
inter-board communication.
 Provides one 10M Ethernet port, which is
accessed through the SAP and is used for
implementing the communication between
the active and standby SCC boards.
 Provides the RS232 OAM interface, which
is accessed through the SEI and is used for
connecting a PC or workstation. Supports
the remote maintenance by using the RS232
DCE modem.
 Provides one orderwire interface and two
NNI phone interfaces, which are accessed
through the SEI.
 Provides four broadcast data ports
(serial1–4), which are accessed through the
SEI.
 The Q3CXL4 supports the receiving of the
check result of the NE ID and provides the
interface for querying the check result.

Maintenance features The Q3CXL4 supports the CF card, simulation

package loading, and diffused loading. The CF
card is hot swappable. The capacity of a
standard CF card is 512 MB and can be
expanded to 1 GB.

DCC processing capability The Q2CXL4 can process 40 channels of DCC

signals. The Q3CXL4 can process 80 channels
of DCC signals.

Fan alarm management Manages fan alarms.

PIU management Supports the in-service check function for the

PIU and supports the failure check function
for the lightning protection module of the PIU.

Protection schemes Supports the 1+1 Hot Backup for the

Cross-Connect, Timing and SCC Units.

1.1.3.0.3 Cross-Connect Unit

Table 5-17 provides the functions and features of the cross-connect unit of the
CXL4.
 Table 1-4 Functions and features of the cross-connect unit of the CXL4
Function and Feature CXL4

Basic functions Realizes 20 Gbit/s higher order

cross-connection at the VC-4 level, and 20
Gbit/s lower order cross-connection at the
VC-12 or VC-3 level.

Fast emergency channel Provides two 4 Mbit/s HDLC fast emergency

channels, which are used for the MSP
switching, SNCP switching, TPS, or other
functions.

Service processing  Dynamically grooms services.

 Adds or deletes services without
interrupting other services.
 Supports the SNCP protection at the VC-4,
VC-3 and VC-12 levels.
 Supports VC-4-4c concatenation services.

Protection schemes Supports the 1+1 Hot Backup for the

Cross-Connect, Timing and SCC Units
(non-revertive, by default).

1.1.3.0.4 Clock Unit

Table 5-18 provides the functions and features of the clock unit of the CXL4.

Table 1-5 Functions and features of the clock unit of the CXL4
Function and Feature CXL4

Basic functions Provides the standard system synchronization

clock.

Other functions  Supports the extraction, insertion, and

management of the SSM and clock ID.
 The Q3CXL4 supports the transmission of
the DCC overhead information at two
external clock interfaces.

Input and output  Inputs two-channel 2048 kHz or 2048 kbit/s

timing signals and selects the external
timing source.
 Outputs two-channel 2048 Hz or 2048 kbit/s
timing signals.

1.1.4 Working Principle and Signal Flow

The CXL4 consists of the synchronous timing module, O/E converting
module, MUX/DEMUX module, SDH overhead processing module,
communication and control module, cross-connect module, power module,
and other modules.
Figure 5-9 shows the functional block diagram of the Q2CXL4.

Figure 1-2 Functional block diagram of the Q2CXL4

Synchronous
timing module T1 Line unit
38 MHz (SETS) T2
OSC Tributary unit
SETG T3 SEI
T4
(clock external output) SEI
T0 Frame header
155 MHz Service unit
PLL T0 (reference clock)
Service unit
155 MHz High-speed
4x155 SDH overhead bus
Another CXL
Mbit/s processing module Cross-connect Higher order cross-
O/E High-speed
STM-4 DEMUX data unit connect unit bus
4x155 RST MST MSA HPT Line unit
E/O Mbit/s High-speed bus
STM-4 data
MUX Lower order cross-
O/E
K1/K2 connect unit
converting
insertion/
module
extraction Cross-connect module
Laser Performan
High-speed bus Cross-connect
shutdown ce report K1/K2 byte DCC unit B

Laser K1/K2 byte DCC DCC

Line unit
control processing processing
Communication over ETH
channels
Communication between the active Other units
Communication and control module and standby boards
Another CXL
ETH port SAP
OAM interface
SEI

Power monitor
F&f interface
Phone
Phoneinterface
interface
Boot SEI
Flash RAM NVRAM S1-S4 interface
ROM
+3.3 V Power Fuse -48 V/-60 V
module -48 V/-60 V
Power
module

Figure 5-10 shows the functional block diagram of the Q3CXL4.

 Figure 1-3 Functional block diagram of the Q3CXL4
Synchronous
timing module T1 Line unit
38 MHz (SETS) T2
OSC Tributary unit
T3 SEI
SETG
T4
(clock external output) SEI
T0 Frame header
155 MHz Service unit
PLL T0 (reference clock)
Service unit
155 MHz High-speed
4x155 SDH overhead bus
Another CXL
Mbit/s processing module Cross-connect Higher order cross-
O/E High-speed
STM-4 DEMUX data unit connect unit bus
RST MST MSA HPT Line unit
4x155
E/O Mbit/s High-speed bus
STM-4 data Lower order cross-
MUX
O/E connect unit
K1/K2
converting
insertion/ Cross-connect module
module
extraction
Cross-connect
Laser High-speed bus
Performance unit B
shutdown report
K1/K2 byte DCC
Laser K1/K2 byte DCC DCC
Line unit
control processing processing
Communication over ETH
channels
Communication between the active Other units
Communication and control module and standby boards
Another CXL
ETH port SAP
OAM interface
SEI

Power monitor
F&f interface
CF Phone
Phoneinterface
interface
Boot Flash RAM NVRAM SEI
card ROM S1-S4 interface
+3.3 V Power Fuse -48 V/-60 V
module -48 V/-60 V
Power
module

1.1.4.0.5 Synchronous Timing Module

The synchronous timing module provides the system clock (T0) for the
service board, the control unit, and the cross-connect unit in centralized
timing distribution mode. This module also selects one from the reference
clock sources as the reference clock for synchronous timing. The reference
clock sources are from the line board (T1), the tributary board (T2), or the
external synchronous clock source (T3). The synchronous system clock
source (T0) and 2 Mbit/s external synchronous source (T4) are generated. The
boards adopt the 1+1 hot backup. Hence, both the active and standby boards
trace the same reference source.
The synchronous timing module can extract the clock from three types of
timing signals:
 Timing signal (T1) from the STM-N line
 Timing signal (T2) from the PDH line
 Reference signal (T3) from the external synchronous clock source (2
MHz or 2 Mbit/s)
The timing module outputs the following timing signals:
 T0, system clock (38 MHz)
 T4, external timing output signal (2 Mbit/s or 2 MHz)
1.1.4.0.6 O/E Converting Module
 Converts the received optical signals into electrical signals, in the receive
direction.
 Converts the electrical signals into SDH optical signals, and then sends
the SDH optical signals to fibers for transmission, in the transmit
direction.
 The SPI detects the R_LOS alarm and provides the laser shut down
function.

1.1.4.0.7 MUX/DEMUX Module

 In the receive direction, the DEMUX part demultiplexes the high rate
electrical signals into multiple parallel electrical signals, and recovers the
clock signal at the same time.
 In the transmit direction, the MUX part multiplexes the parallel electrical
signals received from the SDH overhead processing module into high
rate electrical signals.

1.1.4.0.8 SDH Overhead Processing Module

this module includes the RST, MST, MSA, and HPT sub-modules. This
module provides the inloop and outloop functions.
 RST sub-module
− In the receive direction, the RST sub-module terminates the
regenerator section overhead (RSOH). That is, the RST sub-module
detects the frame alignment bytes (A1 and A2), descrambles all the
bytes except the first line of the RSOH, restores and checks the
regenerator section trace byte (J0), and checks the B1 byte.
− In the transmit direction, the RST sub-module generates the RSOH.
That is, the RST sub-module writes bytes such as A1, A2, and J0,
calculates and writes the B1 byte, and scrambles all the bytes except
the first line of the RSOH.
 MST sub-module
− In the receive direction, the MST sub-module terminates the
multiplex section overhead (MSOH). That is, the MST sub-module
generates the multiplex section-alarm indication signal (MS_AIS)
alarm and detects the multiplex section-remote defect indication
(MS_RDI) alarm after detecting the K2 byte, and detects the
multiplex section-remote error indication (MS_REI) alarm and
generates the B2-excessive errors (B2_EXC) alarm after checking the
B2 byte.
− In the transmit direction, the MST sub-module generates the MSOH.
That is, the MST sub-module writes bytes such as E2, D4-D12, K1,
K2, S1, and M1, and calculates and writes the B2 byte.
 MSA sub-module
− In the receive direction, the MSA sub-module de-interleaves the
administration unit group (AUG), divides an AUG into N AU-4s,
detects the administration unit-loss of pointer (AU_LOP) alarm and
the administration unit-alarm indication signal (AU_AIS) alarm, and
performs pointer justifications.
 − In the transmit direction, the MSA sub-module assembles the AUG
and generates the AU-4. N AU-4s are multiplexed into an AUG
through byte interleaving.
 HPT sub-module
− In the receive direction, the HPT sub-module terminates the path
overhead (POH). That is, the HPT sub-module detects the higher
order path-remote error indication (HP_REI) alarm after checking the
B3 byte, generates the higher order path-trace identifier mismatch
(HP_TIM) alarm and the higher order path-signal label mismatch
(HP_SLM) alarm and detects the higher order path-remote defect
indication (HP_RDI) alarm after detecting the J1 and C2 bytes, and
generates the higher order path-unequipped (HP_UNEQ) alarm after
detecting the C2 byte.
− In the transmit direction, the HPT sub-module generates the POH.
That is, the HPT sub-module writes bytes such as J1 and C2, and
calculates and writes the B3 byte.

1.1.4.0.9 Communication and Control Module

 Traces the clock signal from the active and standby cross-connect units.
 Implements the laser controlling function.
 Selects the clock signal and frame header signal from the active and
standby cross-connect units.
 Controls the indicators on the board.
 Provides the CPU control unit, which controls and monitors the other
functional modules. The unit also initializes the other functional modules
after it is powered on.
 Provides the ETH port, which functions as the 10M/100M Ethernet port
for network management.
 Provides the OAM interface, which functions as the serial port for
network management. This port can be used as the MODEM port and
thus can be configured as a serial port for connecting to the MODEM
port that is in the running state.
 Provides the COM interface, which functions as the commissioning port.
 Provides the Ethernet port, namely, a 10 Mbit/s Ethernet port, for
inter-board communication between the active and standby CXL units.
 The Q3CXL4 supports the receiving of the check result of the NE ID and
provides the interface for querying the check result.

1.1.4.0.10 Cross-Connect Module

The cross-connect module consists of two parts:
 SNCP module, which tests relative alarms and reports the alarms to the
software to trigger the protection switching such as the SNCP switching
and MSP switching.
 Higher order and lower order cross-connect module, which performs the
functions of higher order and lower order cross-connect units.

1.1.4.0.11 Power Module

It converts the –48 V/–60 V power supply into the DC voltages that the
modules of the board require.
1.1.4.0.12 CF Card
The CF card functions as the storage carrier of the NE, and can store the
databases of the NE, system parameters, software package of the NE, NE logs,
and the data in the black box.

The Q2CXL4 does not support the CF card.

1.1.4.0.13 Other Functions

 Responses to and processes the K bytes.
 Collects the performance data of the optical module and disables the
output of the optical module.
 Collects and processes DCC signal of each board.
 Inserts the DCC signal back into each line board after processing.
 Monitors the power supply of the board.
 Performs the reset of the units.
 Mutes alarms.

1.1.5 Front Panel

The front panel of the Q2CXL4 has indicators, an optical interface, functional
button switches, a bar code, and a laser safety class label. The front panel of
the Q3CXL4 has indicators, an optical interface, a bar code, functional button
switches, and a laser safety class label.

1.1.5.0.14 Diagram of the Front Panel

Figure 5-11 shows the appearance of the front panel of the Q2CXL4.
Figure 1-4 Front panel of the Q2CXL4

CXL4
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC

CLASS 1
LASER
PRODUCT

OUT
IN

RESET

ALM CUT

CXL4

Figure 5-12 shows the appearance of the front panel of the Q3CXL4.
 Figure 1-5 Front panel the Q3CXL4

CXL4
STAT
ACTX
ACTC
PROG
SRVX
SRVL
SYNC
ALMC

CLASS 1
LASER
PRODUCT

OUT
IN

RESET

ALM CUT

CF R/W

CF ON/OFF

CXL4

1.1.5.0.15 Indicators
The front panel of the board has the following indicators:
 Board hardware status indicator (STAT) – two colors (red and green)
 Active/Standby state indicator of the cross-connect unit (ACTX) – one
color (green)
 Active/Standby state indicator of the SCC unit (ACTC) – one color
(green)
 Board software status indicator (PROG) – two colors (red and green)
 Service alarm indicator of the cross-connect unit (SRVX) – three colors
(red, green, and yellow)
 Service alarm indicator of the line unit (SRVL) – three colors (red, green,
and yellow)
 Synchronization clock status indicator (SYNC) – two colors (red and
green)
 Alarm mute indicator (ALMC) – one color (yellow)
 For the meanings of the status of the indicators, see 19 Indicators.

1.1.5.0.16 Interfaces
The front panel of the CXL4 has one optical interface and three switches.
Table 5-19 describes the types and usage of the optical interfaces and switches
of the CXL4.

Table 1-6 Optical interface and switches of the CXL4

Interface/Swit Type of Usage
ch Interface/Swi
tch

IN LC Receives optical signals.

OUT LC Transmits optical signals.

RESET Warm reset Press the switch to perform a warm reset for the SCC
switch unit.

ALM CUT Alarm cut Press the switch to mute the alarm. Press the switch for
switch five seconds to mute the alarm permanently. Press the
switch again for five seconds to resume the alarm sound.

CF ON/OFF CF card Changes the state of the CF card.

insertion/remov  When the CF card is in the read/write state, or when
al switch data is read from or written to the CF card, the indicator
changes to red and then the CF card changes to the
read/write prohibited state if the switch is pressed for
five seconds. In this case, you can remove the CF card.
 When the CF card is in the read/write prohibited state,
the indicator changes to green if the switch is pressed
for five seconds. Then, the CF card is restored to the
read/write state.

Only the Q3CXL4 supports the CF card. The Q2CXL4 does not support the CF card.

1.1.6 Jumpers and DIP Switches

The CXL4 has a jumper, which is used to set the enable state of the battery,
and a DIP switch, which is used to set the running state of the equipment.

The jumper and DIP switch are used for test and maintenance. Do not change
the setting of the jumper at random. Otherwise, the board may become faulty.

Figure 5-13 shows the jumper and DIP switch of the Q2CXL4.
Figure 1-6 Positions of the jumper and DIP switch of the Q2CXL4

3 2 1
J3

CF

card

SCC unit
1
2
3 SW1
4

Figure 5-14 shows the jumper and DIP switch of the Q3CXL4.

Figure 1-7 Positions of the jumper and DIP switch of the Q3CXL4

J7
1 2 3 SCC unit
4
3
2 SW2
1

CF

card

Table 5-20 describes jumper J3 of the Q2CXL4 and jumper J7 of the

Q3CXL4.
 Table 1-7 Jumper J3 of the Q2CXL4 and jumper J7 of the Q3CXL4
Jumper Function Description

J3/J7 To enable the 1–2: If jumper bits (positions) 1 and 2 are capped, the
battery battery is enabled.
2–3: If jumper bits (positions) 2 and 3 are capped, the
database and clock are cleared.

Table 5-21 describes DIP switch SW1 of the Q2CXL4 and DIP switch SW2 of
the Q3CXL4.

Table 1-8 DIP switch SW1 of the Q2CXL4 and DIP switch SW2 of the Q3CXL4
DIP Switch Function Description

SW1/SW2 To set the running  When a DIP switch bit is at the on position, it
state of the board indicates the binary value 1.
 SW1 is a four-bit DIP switch. The values of the DIP
switch bits are queued in the descending order of the
switch bit numbers. The DIP switch bit numbered 4 is
the most significant bit. For details, refer to Table
5-22.

Table 1-9 DIP switch SW1/SW2

Value Description

0b0000 Indicates the running state when the watchdog is started. It is the default
state.

0b0011 Indicates the commissioning state when the watchdog is stopped.

0b0100 Indicates the running state when the watchdog is stopped.

0b1011 Erases the database.

0b1100 Erases the NE software, including the patches.

0b1101 Erases the database and NE software, including the patches.

0b1110 Erases the database, NE software, and NE.ini file.

0b1111 Erases the extended BIOS and system parameter area in the file system
and flash memory.

1.1.7 Valid Slots

The CXL4 must be installed in a valid slot in the subrack. Otherwise, the
CXL4 cannot work normally.
The CXL4 can be installed in slots 9 and 10 in the subrack.
 By default, slot 9 houses the active board and slot 10 houses the standby
board.

1.1.8 Feature Code

The number code that follows the board name in the bar code is the feature
code of the board. The feature code of the CXL4 indicates the type of optical
interface.
Table 5-23 provides the relationship between the feature code of the CXL4
and the type of optical interface.

Table 1-10 Relationship between the feature code of the CXL4 and the type of
optical interface
Board Feature Code Type of Optical Interface

SSQ3CXL410 and 10 S-4.1

SSQ2CXL410

SSQ3CXL411 and 11 L-4.1

SSQ2CXL411

SSQ3CXL412 and 12 L-4.2

SSQ2CXL412

SSQ3CXL413 and 13 Ve-4.2

SSQ2CXL413

SSQ3CXL414 and 14 I-4

SSQ2CXL414

1.1.9 Configuring and Commissioning the Board

After you select a correct board, you need to configure and commission the
board. The following tasks need to be performed: checking the hardware of
the board, configuring the board, commissioning the board, and checking the
operation of the board.

1.1.9.0.17 Checking the Hardware of the Board

Required: Check the hardware of the board.
 The labels on the front panel of the board must be correct and clear.
 The daughter board of the board must be properly installed.
 All the components on both surfaces of the board must be available and
intact.
Required: Check whether the active board and standby board are installed in
the correct slots.
Required: Check whether the board is properly installed. The board must be
pushed to the bottom of the subrack along the guide rails, and the front panel
of the board must be properly locked. For the method for installing a board,
see Replacing Boards Onsite.
 Required: Check the status of the indicators of the board when and after the
board is powered on. For the meanings of the status of the indicators, see 19
Indicators.
Required: Check whether the version of the board software matches the
version of the NE software and the version of the U2000 software. Ensure that
the version of the board software is correct.
Required: Check the micro switch of the board. When the front panels of the
active and standby cross-connect boards are locked, the active/standby
switching can be realized if you unlock the front panel of the active board.
Required: Check the status of the ALM switch.
1. Press the switch to mute the current alarm sound.
2. Press the switch for five seconds to mute the alarm sound permanently.
In this case, the alarm mute indicator (ALMC) turns on (in yellow).
3. Press the switch again for five seconds to resume the alarm sound. In this
case, the ALMC indicator turns off.
----End

1.1.9.0.18 Configuring the Board

Required: Add the logical board. For details, see Adding Boards.
Required: Set parameters for the CXL on the U2000. The following parameters
need to be set:
 Clock synchronization status
 Clock source priority
 Phase-locked source output by external clock
 Clock source switching
 Clock subnet configuration
For the method for setting the parameters, see Configuring Clocks.
Optional: Configure services. For details, see Configuring the SDH Services.
Required: Set parameters for the GSCC on the U2000.
If the parameter settings of the GSCC are available on the U2000, download
the parameter settings to the GSCC. Otherwise, perform the following
operations:
 Set the NE ID. For details, see Setting the NE ID.
 Set the NE name, date, and time. For details, see Setting the NE Name,
Date, and Time.
Required: Set parameters for the line board on the U2000.
Set the SDH interface.
 J0 byte: Generally, use the default value. The default value of the J0 to be
sent is HuaWei SBS and the default value of the J0 to be received
is Disabled.
 J1 byte: The setting of the J1 byte on the interconnected equipment must
be consistent. Generally, use the default value. The default value of the
 J1 to be sent is HuaWei SBS and the default value of the J1 to be
received is Disabled.
 C2 byte: The setting of the C2 byte on the interconnected equipment
must be consistent. Set the C2 byte according to the actual service type.
Generally, use the default value, which is TUG structure.
 Laser status: Set this parameter to Open when you configure and
commission the board.
For details, see 23.7 Checking Board Parameters.
Optional: Configure a protection subnet. For details, see Configuring the
Protection Subnet.
----End

1.1.9.0.19 Commissioning the Board

Required: Commission the CXL.
 Check the setting of the jumper that controls the debugging status of the
board. For the description of the jumper, see "Jumpers and DIP
Switches".
 Check and commission the circuit status on the data ports, including the
F&f debugging serial port and OAM NM port. For details, see 23.4
Configuring the F&f Debugging Serial Port and OAM NM Port.
 Check the configurations of the data ports.
− For the configuration of the broadcast data port, see Configuring the
Broadcast Data Service.
− For the configuration of the F1 codirectional data port, see
Configuring the F1 Data Service.
 Test the 1+1 protection provided by the cross-connect, timing, and SCC
board. For details, see Testing the 1+1 Protection of the Cross-Connect
and Timing Board.
 Test the frequency accuracy of the free-run clock. For details, see 23.5
Testing the Frequency Accuracy of the Free-Run Clock.
 Test the clock holdover accuracy. For details, see 23.6 Testing the Clock
Holdover Accuracy.
Optional: Commission the line board.
 Test the specifications of the optical interface. For details, see Testing
Specifications of Optical Interfaces.
 Test the network protection switching. For details, see Testing SDH
Network Protection Switching.
 Test the point-to-point BER. For details, see Testing the Point-to-Point
BER.
----End

1.1.9.0.20 Checking the Operation of the Board

Required: Check the status of the indicators on the front panel of the board to
ensure that the board starts to work normally. When all the indicators are on
and green, the board operates normally. For the meanings of the status of the
indicators, see 19.2 Alarm Indicators on the Boards.
 Required: Query the alarms and performance events of the board. Modify the
connections or configurations of the board according to the alarms and
performance events until the alarms are cleared. For the method for querying
the alarms and performance events of a board, see Viewing the Current
Alarms.
----End

1.1.10 Parameter Settings

The physical slot that houses the CXL4 is different from the logical slot
displayed on the U2000. You can set parameters for the CXL4 by using the
U2000.

1.1.10.0.21 Displayed Slots

The CXL4 occupies one slot in the subrack.
The logical boards for the CXL4 are the Q1SL4, EXCL, and GSCC.
Table 5-24 lists the slots for the logical boards displayed on the U2000.

Table 1-11 Logical slots displayed on the U2000 for the CXL4
Board Logical Board Logical Slot

CXL4 Q1SL4 Slot 9 or slot 10

ECXL Slot 80 or slot 81

GSCC Slot 82 or slot 83

1.1.10.0.22 Board Parameters

You can set the following main parameters for the CXL4 by using the U2000:
 J0 byte
 J1 byte
 J2 byte
 C2 byte
 Clock parameters
For the description of each parameter, see 22 Parameter Settings.

1.1.11 Maintaining the Board

This topic describes the alarms and faults that may occur when the board
operates. This topic also provides the methods and precautions to be taken for
rectifying the faults.

1.1.11.0.23 Troubleshooting
Table 5-25 lists the faults that occur on the CXL4 frequently and the
troubleshooting methods.
 Table 1-12 Methods used to troubleshoot the faults that occur on the CXL4
frequently
Fault Symptom Common Fault Troubleshooting Method
Cause

Service unavailable  The type of logical See 23.2 Troubleshooting Service

board is not Unavailability.
consistent with the
type of the board that
is installed on the
NE.
 The service
configuration is
incorrect.
 The running status of
the other boards on
the NE is incorrect.

Clock tracing failure  The clock source See 23.3 Troubleshooting the Clock
priority table is Tracing Failure.
incorrectly
configured.

ECC failure  The running status of  Check whether the running status
the board becomes of the board is correct. See 19.2
abnormal. Alarm Indicators on the Boards to
 The optical fibers are obtain the meanings of the status
incorrectly of the indicators.
connected.  Check whether the optical fibers
are correctly connected.

Power supply alarm
The jumper that
controls the input
voltage is incorrectly
set.
Check whether the jumper that
controls the input voltage is
correctly set. For information on
how to set the jumper, see 5.2.6
Jumpers and DIP Switches.

Failure of the connection  An incorrect network  For information on the connection

between the NMS computer cable is used to
and the equipment connect the NMS
computer to the
equipment.
 The IP address of the  Ensure that the IP address of the
NMS computer and
the IP address of the
equipment are not in
the same network
segment.
of the network cable, see
Checking Connection Between the
U2000 Computer and the
Equipment.
NMS computer and the IP address
of the equipment are correctly set.
For details, see Setting the IP
Address of the PC.

1.1.11.0.24 Replacing the Board

See General Precautions to get familiar with the precautions to be taken for replacing
a board before you replace the board.
 For information on how to replace the CXL4, see Replacing a CXL Board.

1.1.12 List of Alarms

This topic lists the alarms that may occur when the board operates. The alarms
are reported according to the logical board on the U2000.

1.1.12.1 Q2CXL4

1.1.12.1.25 ECXL
APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HSC_UNAVAIL FPGA_ABN HARD_BAD
LPS_UNI_BI_M K1_K2_M K2_M
NO_BD_SOFT LTI MS_APS_INDI_EX
OTH_HARD_FAIL OOL OTH_BD_STATUS
SWITCH_DISABLE POWER_ABNORMAL S1_SYN_CHANGE
SYNC_F_M_SWITCH SYN_BAD SYNC_C_LOS
TEST_STATUS SYNC_LOCKOFF TEMP_OVER
W_OFFLINE W_R_FAIL TIME_NOT_SUPPORT
TIME_NO_TRACE_MOD TIME_LOS TIME_FORCE_SWITCH
E
EXT_TIME_LOC NP1_SW_INDI NP1_SW_FAIL
RPS_INDI

1.1.12.1.26 GSCC
APS_MANUAL_STOP BD_AT_LOWPOWER BD_NOT_INSTALLED
BD_STATUS BOOTROM_BAD CFCARD_FAILED
CFCARD_OFFLINE CFCARD_W_R_DISABLED COMMUN_FAIL
DBMS_ERROR DBMS_PROTECT_MODE DCC_CHAN_LACK
FPGA_ABN HARD_BAD HSC_UNAVAIL
MSSW_DIFFERENT NE_POWER_OVER NESF_LOST
NESTATE_INSTALL LAN_LOC PATCH_ERR
PATCH_PKGERR PATCH_NOT_CONFIRM PATCHFILE_NOTEXIST
POWER_ABNORMAL POWER_FAIL REG_MM
 RINGMAPM_MM RTC_FAIL SECU_ALM
SQUTABM_MM SWDL_ACTIVATED_TIME SWDL_AUTOMATCH_IN
OUT H
SWDL_INPROCESS SWDL_CHGMNG_NOMAT SWDL_COMMIT_FAIL
CH
SWDL_NEPKGCHECK TEMP_OVER SWDL_ROLLBACK_FAIL
SYNC_FAIL BIOS_STATUS WRG_BD_TYPE
CFCARD_FULL PATCH_DEACT_TIMEOUT NP1_MANUAL_STOP
PATCH_ACT_TIMEOU STORM_CUR_QUENUM_O LCS_DAYS_OF_GRACE
T VER
LCS_EXPIRED LCS_FILE_NOT_EXIST SYSLOG_COMM_FAIL
SEC_RADIUS_FAIL NE_CFG_CONFLICT

1.1.12.1.27 Q1SL4
ALM_ALS AU_AIS AU_CMM
AU_LOP B1_EXC B1_SD
B2_EXC B2_SD B3_EXC
B3_SD BD_STATUS C2_VCAIS
BIP8_ECC C2_PDI FPGA_ABN
CHIP_FAIL COMMUN_FAIL HP_RDI
FSELECT_STG HP_LOM HP_TIM
HP_REI HP_SLM J0_MM
HP_UNEQ IN_PWR_ABN LOOP_ALM
LASER_MOD_ERR LASER_SHUT LSR_WILL_DIE
LSR_COOL_ALM LSR_NO_FITED MS_REI
MS_AIS MS_RDI OH_LOOP
NO_BD_SOFT R_LOF POWER_ABNORMAL
OUT_PWR_ABN SLAVE_WORKING R_LOS
R_LOC TEM_HA SPARE_PATH_ALM
R_OOF TF TEM_LA
T_LOSEX PS TR_LOC
TEST_STATUS W_R_FAIL MOD_TYPE_MISMATCH
1.1.12.2 Q3CXL4

1.1.12.2.28 ECXL
APS_FAIL APS_INDI BD_STATUS
CHIP_FAIL BUS_ERR CHIP_ABN
EXT_SYNC_LOS CLK_NO_TRACE_MODE COMMUN_FAIL
HSC_UNAVAIL FPGA_ABN HARD_BAD
LPS_UNI_BI_M K1_K2_M K2_M
NO_BD_SOFT LTI MS_APS_INDI_EX
OTH_HARD_FAIL OOL OTH_BD_STATUS
SWITCH_DISABLE POWER_ABNORMAL S1_SYN_CHANGE
SYNC_F_M_SWITCH SYN_BAD SYNC_C_LOS
TEST_STATUS SYNC_LOCKOFF TEMP_OVER
W_OFFLINE W_R_FAIL TIME_NOT_SUPPORT
TIME_NO_TRACE_MOD TIME_LOS TIME_FORCE_SWITCH
E
EXT_TIME_LOC NP1_SW_INDI NP1_SW_FAIL
RPS_INDI

1.1.12.2.29 GSCC
APS_MANUAL_STOP BD_AT_LOWPOWER BD_NOT_INSTALLED
BD_STATUS BOOTROM_BAD CFCARD_FAILED
CFCARD_OFFLINE CFCARD_W_R_DISABLED COMMUN_FAIL
DBMS_ERROR DBMS_PROTECT_MODE DCC_CHAN_LACK
FPGA_ABN HARD_BAD HSC_UNAVAIL
MSSW_DIFFERENT NE_POWER_OVER NESF_LOST
NESTATE_INSTALL LAN_LOC PATCH_ERR
PATCH_PKGERR PATCH_NOT_CONFIRM PATCHFILE_NOTEXIST
POWER_ABNORMAL POWER_FAIL REG_MM
RINGMAPM_MM RTC_FAIL SECU_ALM
SQUTABM_MM SWDL_ACTIVATED_TIME SWDL_AUTOMATCH_IN
OUT H
SWDL_INPROCESS SWDL_CHGMNG_NOMAT SWDL_COMMIT_FAIL
CH
 SWDL_NEPKGCHECK TEMP_OVER SWDL_ROLLBACK_FAIL
SYNC_FAIL BIOS_STATUS WRG_BD_TYPE
CFCARD_FULL PATCH_DEACT_TIMEOUT NP1_MANUAL_STOP
PATCH_ACT_TIMEOU STORM_CUR_QUENUM_O LCS_DAYS_OF_GRACE
T VER
LCS_EXPIRED LCS_FILE_NOT_EXIST SYSLOG_COMM_FAIL
SEC_RADIUS_FAIL NE_CFG_CONFLICT

1.1.12.2.30 Q1SL4
ALM_ALS AU_AIS AU_CMM
AU_LOP B1_EXC B1_SD
B2_EXC B2_SD B3_EXC
B3_SD BD_STATUS C2_VCAIS
BIP8_ECC C2_PDI FPGA_ABN
CHIP_FAIL COMMUN_FAIL HP_RDI
FSELECT_STG HP_LOM HP_TIM
HP_REI HP_SLM J0_MM
HP_UNEQ IN_PWR_ABN LOOP_ALM
LASER_MOD_ERR LASER_SHUT LSR_WILL_DIE
LSR_COOL_ALM LSR_NO_FITED MS_REI
MS_AIS MS_RDI OH_LOOP
NO_BD_SOFT R_LOF POWER_ABNORMAL
OUT_PWR_ABN SLAVE_WORKING R_LOS
R_LOC TEM_HA SPARE_PATH_ALM
R_OOF TF TEM_LA
T_LOSEX PS TR_LOC
TEST_STATUS W_R_FAIL MOD_TYPE_MISMATCH

1.1.13 List of Performance Events

This topic lists the performance events that may occur when the board
operates. The performance events are reported according to the logical board
on the U2000.
1.1.13.3 Q2CXL4

1.1.13.3.31 GSCC
XCSTMPMAX XCSTMPMIN XCSTMPCUR
CPUUSAGEMAX CPUUSAGEMIN CPUUSAGECUR
MEMUSAGEMAX MEMUSAGEMIN MEMUSAGECUR

1.1.13.3.32 Q1SL4
AUPJCHIGH AUPJCLOW AUPJCNEW
HPBBE HPCSES HPES
HPFEBBE HPFECSES HPFEES
HPFESES HPFEUAS HPSES
HPUAS MSBBE MSCSES
MSES MSFEBBE MSFECSES
MSFEES MSFESES MSFEUAS
MSSES MSUAS OSPICCVCUR
OSPICCVMAX OSPICCVMIN OSPITMPCUR
OSPITMPMAX OSPITMPMIN RPLCUR
RPLMAX RPLMIN RSBBE
RSCSES RSES RSOFS
RSSES RSUAS TLBCUR
TLBMAX TLBMIN TPLCUR
TPLMAX TPLMIN

1.1.13.4 Q3CXL4

1.1.13.4.33 GSCC
XCSTMPMAX XCSTMPMIN XCSTMPCUR
CPUUSAGEMAX CPUUSAGEMIN CPUUSAGECUR
MEMUSAGEMAX MEMUSAGEMIN MEMUSAGECUR
1.1.13.4.34 Q1SL4
AUPJCHIGH AUPJCLOW AUPJCNEW
HPBBE HPCSES HPES
HPFEBBE HPFECSES HPFEES
HPFESES HPFEUAS HPSES
HPUAS MSBBE MSCSES
MSES MSFEBBE MSFECSES
MSFEES MSFESES MSFEUAS
MSSES MSUAS OSPICCVCUR
OSPICCVMAX OSPICCVMIN OSPITMPCUR
OSPITMPMAX OSPITMPMIN RPLCUR
RPLMAX RPLMIN RSBBE
RSCSES RSES RSOFS
RSSES RSUAS TLBCUR
TLBMAX TLBMIN TPLCUR
TPLMAX TPLMIN

1.1.14 Technical Specifications

The technical specifications of the CXL4 include the parameters specified for
optical interfaces, cross-connect capacity, clock access capability, laser safety
class, mechanical specifications, and power consumption.

1.1.14.4.35 Parameters Specified for Optical Interfaces

Table 5-26 lists the parameters specified for the optical interfaces of the
CXL4.

Table 1-13 Parameters specified for the optical interfaces of the CXL4
Parameter Value

Nominal bit rate 622080 kbit/s

Line code pattern NRZ

Application code I-4 S-4.1 L-4.1 L-4.2 Ve-4.2

Transmission 0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
distance (km)

Operating 1261 to 1274 to 1280 to 1480 to 1480 to

wavelength range 1360 1356 1335 1580 1580
(nm)
 Parameter Value

Type of fiber Single-mode Single-mode Single-mod Single-mode Single-mode

LC LC e LC LC LC

Mean launched -15 to -8 -15 to -8 -3 to -2 -3 to -2 -3 to -2

optical power
(dBm)

Receiver -23 -28 -28 -28 -34

sensitivity (dBm)

Minimum -8 -8 -8 -8 -13
overload (dBm)

Minimum 8.2 8.2 10 10 10.5

extinction ratio
(dB)

Maximum -20 dB – – 1 1 1
spectral width
(nm)

Minimum side – – 30 30 30
mode suppression
ratio (dB)

1.1.14.4.36 Cross-Connect Capacity

The cross-connect capacity of the CXL4 is as follows:
 Higher order cross-connect capacity: 20 Gbit/s
 Lower order cross-connect capacity: 20 Gbit/s
 Access capacity: 18.75 Gbit/s

1.1.14.4.37 Clock Access Capability

The clock access capability of the CXL4 is as follows:
 External input clock: two channels of 2048 kbit/s or 2048 kHz external
clock signals
 External output clock: two channels of 2048 kbit/s or 2048 kHz external
clock signals

1.1.14.4.38 Laser Safety Class

The safety class of the laser on the board is Class 1. The maximum launched
optical power of the optical interfaces is less than 10 dBm (10 mW).

1.1.14.4.39 Mechanical Specifications

The mechanical specifications of the CXL4 are as follows:
 Dimensions (mm): 25.4 (W) x 220 (D) x 254.1 (H)
 Weight of the Q2CXL4 (kg): 1.1
  Weight of the Q3CXL4 (kg): 1.2

1.1.14.4.40 Power Consumption

The maximum power consumption of the Q2CXL4 at room temperature
(25°C) is 40 W.
The maximum power consumption of the Q3CXL4 at room temperature
(25°C) is 46 W.