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1914 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO.

8, AUGUST 2010

Analytical Phase-Noise Modeling and Charge Pump


Optimization for Fractional-N PLLs
Frank Herzel, Sabbir A. Osmany, and J. Christoph Scheytt, Member, IEEE

Abstract—We present an analytical frequency-domain


phase-noise model for fractional- phase-locked loops (PLLs).
The model includes the noise of the crystal reference, the reference
input buffer, the voltage-controlled oscillator (VCO), the loop
filter, charge pump (CP) device noise, and sigma-delta modulator
(SDM) noise, including its effect on the in-band phase noise. The
thermal device noise of the CP and the turn-on time of the CP
output current are found to be limiting the in-band phase noise
of state-of-the-art synthesizers. Device noise considerations for
bipolar transistors and MOSFETs suggest the use of CMOS-only
CPs, even in BiCMOS technologies. We present a noise-optimized
CMOS CP specifically designed for a dual-loop PLL architecture
N synthesizer architecture.
Fig. 1. Schematic view of a fractional-

using two CPs. This PLL architecture keeps the dc output voltage
of the noise-relevant CP and the phase-noise spectrum constant,
regardless of temperature variations. In this paper, we consider only CP PLLs due to their pop-
Index Terms—Charge pump (CP), fractional- phase-locked ularity in state-of-the-art synthesizer design. For the same
loops (PLLs), phase noise. reason, we assume that the fractional- divider ratio is ob-
tained by using a sigma-delta modulator (SDM). The SDM in a
fractional- synthesizer inevitably results in large momentary
I. INTRODUCTION phase errors, even in the absence of noise. This makes the
description difficult within an analytical model. Our approach

P HASE noise limits the performance of wireless and high-


speed digital systems. Frequency synthesizers are com-
monly characterized in the frequency domain by phase-noise
is based on the linear model presented in [12], where the
quantization noise spectrum for a multistage noise shaping
(MASH) SDM was included based on the expression given in
spectra. Jitter is the corresponding time-domain equivalent and [13]. Another critical problem related to SDM noise, which has
is used for characterizing clock generation circuits, as well as been disregarded in [12], is the turn-on time of the CP, resulting
clock and data recovery (CDR) circuits. Several theoretical pub- in nonlinearities in the phase detector (PD), as described in
lications on phase noise and jitter modeling of phase-locked [14]–[20]. The combination of an SDM with a nonlinear PD
loops (PLLs) have appeared during the last decade, e.g., [1]–[4]. may fold the SDM noise from large-frequency offsets down
An accurate prediction of phase noise requires simulation on to the in-band region of the spectrum. This effect has analyt-
the transistor level. However, a complete transistor-level simu- ically been modeled in [18]–[20]. It can be interpreted as the
lation of a PLL is difficult or impossible, even in the absence self-mixing of the SDM noise in the nonlinear PD, which is
of noise sources. This is due to very different time scales of composed of a phase-frequency detector (PFD) and CP. To
the voltage-controlled oscillator (VCO) dynamics and the PLL avoid confusion with CP device noise and linear SDM noise,
settling. To simulate the PLL including nonlinear effects, be- this noise contribution will be referred to as PD noise.
havioral system-level simulations are helpful [5]–[11]. An even This paper presents an analytical phase-noise model for a
more simplified approach is linear analytical phase-noise mod- PLL including PD noise. The modeled phase-noise spectrum
eling, where the main noise contributions are described by ad- and its components are visualized by MATLAB. Finally, a
justable parameters. These models correctly reflect the depen- simple CP architecture is suggested, which allows CP device
dence of the phase-noise spectrum on design parameters such noise and PD noise to drastically be reduced.
as loop filter values, charge pump (CP) current, divider ratios,
etc., but they inevitably need some fit parameters. These can be II. PLL PHASE-NOISE SOURCES
determined from theory, simulation, or measurements.
In a CP PLL used in modern communication systems, the
output phase of the VCO is divided by and compared with
Manuscript received October 20, 2009; revised December 08, 2009; accepted a reference phase in a PFD. A CP current proportional to the
December 22, 2009. Date of publication February 17, 2010; date of current
version August 11, 2010. This paper was recommended by Associate Editor phase error is produced, low-pass filtered, and applied to the
J. Silva-Martinez. control input of the VCO, as shown in Fig. 1. In fractional-
The authors are with the IHP, 15236 Frankfurt (Oder), Germany (e-mail: PLLs, the divider ratio is controlled by an SDM.
herzel@ihp-microelectronics.com).
Color versions of one or more of the figures in this paper are available online The output voltage of a PLL can be described as
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2009.2039832 (1)
1549-8328/$26.00 © 2010 IEEE
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1915

Fig. 2. Linearized PLL model.

where is the amplitude, is the oscillation


frequency, and is the excess phase. In this paper, the
term phase-noise spectrum refers to the two-sided power spec- Fig. 3. Third-order loop filter.
tral density (PSD) of in units of square radians per hertz
or square decibel-radians per hertz, when expressed in deci-
bels. In the latter case, the phase noise is almost identical to For the third-order filter according to Fig. 3, we obtain the
the single-sideband phase noise $ in units of dBc per hertz, if transimpedance
and only if white noise sources dominate the PLL noise [4].
The presence of flicker noise results in the well-known (3)
shape of the close-in VCO phase-noise spectrum, whereas the
single-sideband phase-noise spectrum is a Voigt function, which where
resembles a Gauss function at very small offsets [21]. In this
paper, we will include the following seven noise sources: (4)
1) reference noise;
2) reference input buffer noise; (5)
3) VCO noise;
4) loop filter noise; Unlike in [12], we have incorporated a voltage divider at the
5) CP device noise; filter input here, which is useful in the context of a dual-loop
6) – quantization noise; PLL, as discussed in [23]. For a traditional single-loop PLL, R4
7) PD noise. and R5 should be omitted, or huge values should be used in the
The latter contribution represents the noise folding of the noise model.
SDM quantization noise in the nonlinear PD. Noise in the fre- In the next section, the noise sources mentioned in Section II
quency dividers is disregarded in this paper, which is focused will analytically be described.
on PD design. It could be added to the phase-noise model, if
the measured phase-noise spectra at the feedback divider output IV. PHASE NOISE PSD
and the reference divider output are available. As an alterna-
The noise sources discussed in this section are uncorrelated.
tive, the white spectrum of the input-referred divider noise can
Therefore, the phase-noise PSD at the PLL output is the super-
be modeled as a function of delay mismatch in the feedback
position of the seven mentioned noise contributions, each multi-
divider [15], [19]. Another type of noise is caused by digital cir-
plied by its specific noise transfer function. Emphasis is placed
cuits such as frequency dividers, SDM, and PFD, affecting the
on those components that are not, or only insufficiently, included
performance of noise-sensitive analog circuits through supply
in [12], i.e., input buffer noise, CP noise, and PD noise.
and substrate coupling. Supply- and substrate-induced jitter may
easily exceed device-noise-induced jitter in high-speed digital A. Reference Noise
systems [22].
The phase-noise contribution of the reference oscillator as a
function of the frequency offset is modeled by
III. LINEARIZED PLL MODEL
Fig. 2 shows the linearized model of a PLL, as presented in (6)
[12]. Of special interest in this paper is the PD composed of PFD
and CP, which converts a phase error at the input into an output where is the phase noise at a specific offset in
current averaged over one comparison period. For an ideal the 20-dB/dec region of the spectrum, and is the
PD, the gain is given by , where is noise floor of the reference. The reference noise spectrum at the
the CP current in the ON state. The loop filter transimpedance is output reads
denoted as , and the VCO gain is . is the divider
ratio of the PLL. Note that the VCO gain
refers to the angular frequency and is given in units of radians (7)
per second per volts. The forward path transfer function is
given by with the transfer function given by

(2) (8)
1916 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

filter from the CP output to ground. The resulting noise spec-


trum at the output is given by

(13)

E. CP Device Noise
For a PLL to work at a given bandwidth, a large CP current
is generally favorable in order to reduce the loop filter resis-
tance . The large current, however, produces significant cur-
rent noise. The time between two phase comparison instants is
referred to as , where is the frequency at the PFD
input at which the PLL phase error is sampled.
Fig. 4. (a) Proposed input buffer and (b) noise model. In order to qualitatively describe the thermal CP noise,
we write the two-sided thermal drain current noise PSD of a
MOSFET according to [24] as
B. Reference Input Buffer Noise
(14)
As discussed in [23], the noise of the reference buffer may
become a major contributor to the output phase noise. We use an where is the channel conductance with zero drain–source
electrostatic-discharge-protected CMOS inverter chain as input voltage, and is between 2/3 and 1 for long-channel devices
buffer shown in Fig. 4. The first CMOS inverter converts the and somewhat larger for short devices, i.e., typically ranging
crystal oscillator signal into a rectangular signal on the chip. from 1 to 3. This type of noise results in a white noise spec-
Assuming a sinusoidal reference signal with peak amplitude , trum of the CP described by one parameter. This pa-
we obtain for the phase noise at the PLL output rameter can be fitted to measurements or simulated by periodic
steady-state analysis (PSSA) [8]. Thermal noise must be multi-
(9) plied by the CP duty cycle , where is the
CP activation time.
In addition to thermal noise, CPs also exhibit flicker noise
where is the input-referred noise voltage PSD. The ( noise). The flicker noise PSD is proportional to [25].
transconductance of the MOSFETs must be large This is due to the large autocorrelation time of this type of noise,
enough to make this noise negligible. which is assumed to be much larger than . Adding the two
noise contributions, we obtain
C. VCO Noise
The phase noise of a free running oscillator is modeled by (15)

(10) where is the noise corner frequency of the transistor.


Note that the flicker noise corner of the CP scales with ,
which usually makes flicker noise small, compared with thermal
where is the phase noise at a specific offset in
noise, unless a large CP duty cycle is used. For the white noise
the 20-dB/dec region of the spectrum, is the noise
current PSD normalized to the CP current , we
corner of the VCO, and is the noise floor of the VCO. The
found a value of for the cascode CP from [23].
PLL output noise due to VCO phase noise is given by
This value was obtained by a PSSA, followed by a periodic
(11) noise analysis using the Virtuoso Analog Design Environment.
More details will be given in Section VI. The noise spectrum at
where is given by (8). the PLL output reads

D. Loop Filter Noise (16)


We model the noisy loop filter by a noise current in parallel
with a noiseless admittance. The two-sided PSD of noise current
can be expressed as F. Sigma-Delta Quantization Noise
The quantization noise spectrum for an th-order MASH-
(12) type SDM is given by [13]

where is Boltzmann’s constant, is the absolute tempera-


(17)
ture, and is the complex admittance of the
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1917

where is the order of the modulator. The SDM noise spectrum


at the PLL output is given by

(18)

G. PD Noise
If both the UP and DOWN currents are changing in the steady
state of the PLL, then the PD gain will be discontinuous, if
the UP and DOWN currents do not match. This case has been
discussed in [20]. For a low-noise PLL in fractional- mode,
an offset current at the CP output is highly recommended, as
shown in [16]. If the offset current is a sufficiently large DOWN Fig. 5. PD gain versus input phase error for cascode CP.
current, then only the UP current will respond to phase error
changes in the steady state. This improves the linearity of the
PD and significantly reduces phase noise. In this case, the output with the integrals
current of the CP is a continuous function of the phase error
at the PFD input, which is ideally a linear function. In reality, (23)
the limited turn-on time of the current will result in deviations
from this behavior. Taking the nonlinearities into account in the
lowest order, we can write the current as
(24)
(19)

where is the linear PD gain, and represents the first-order (25)


nonlinearity. It can be determined from

(20) The first term in (22) corresponds to the term discussed in


Section IV-F. The other terms describe noise-folding contribu-
resulting in . The linear term in tions. If the process is symmetric with respect to the sign,
(19) produces the quantization noise spectrum described positive and negative contributions in will cancel out. In order
in Section IV-F, and the quadratic term will cause the PD noise to calculate , we decompose into a Fourier integral
discussed in this section. Third-order nonlinearities in the PD
transfer function have been disregarded in this paper. Such
(26)
nonlinearities have been modeled in [10] in the zero-phase
offset region. Fig. 5 shows the simulated PD gain as a
function of the phase error at the PFD input for the cascode CP Equation (25) then reads
used in [23]. Here, the sampling frequency was 100 MHz,
and the CP current was as large as 8 mA for a low in-band
phase noise. As evident from Fig. 5, the PD gain is not constant
but depends on the phase error, which causes noise folding in
the PLL. More specifically, the quantization noise described
in Section IV-F is folded down to low-frequency offsets in the (27)
nonlinear PD. Note that the PD gain is a fairly linear function
of the input phase error over a wide range. In other words, the where all integrals are to be taken from to . Integration
parabolic approximation of the PD transfer function given by with respect to yields
(19) seems reasonable for this particular CP. In order to calcu-
late the two-sided spectrum of the CP current, we write it as the
Fourier transform of the autocorrelation function according to
the Wiener–Khintchine theorem, i.e.,

(21) (28)

Integration with respect to , , and results in


with and the brackets denoting the stochastic
(ensemble) average. Substituting (19) into (21), we obtain
(29)
(22)
1918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

Taking the average on both sides yields By substituting (36) and (37) into (35), we finally obtain

(30) (38)

Note that we have a close similarity to the analytical result of


The PD noise is basically a convolution of the SDM phase noise Mao [20], where corresponds to the mismatch parameter
with itself multiplied by the variance of the phase. In the context in [20] and corresponds to . The same result could
of close-in phase noise, the low-frequency limit is relevant. We not be expected since [20] considers the case of a discontinuous
obtain for PD gain due to mismatch between the UP and DOWN currents,
whereas we consider the case of a continuous PD gain realized
(31) by an offset current at the CP output. The phase noise is pro-
portional to , i.e., a reduction in by a factor of two will
lower the phase noise by 12 dB. Therefore, for a relatively poor
where we have exploited the property for the PD linearity as in [23], a single-loop SDM might be the better
real-valued process . For the PD noise, we obtain choice since the momentary phase error and are lower than
those for a MASH-type SDM [14]. A reduction in the nonlin-
(32) earity parameter by a factor of 10 will reduce the in-band PD
noise by 20 dB, as evident from (38). Therefore, a MASH-type
where the same transfer function as for the CP noise current was SDM might be the better choice for a highly linear PD, as pro-
used. posed in Section VI. It has the advantage of easy integration in
For Gaussian noise of , we can further simplify the result for CMOS or BiCMOS and is unconditionally stable.
the in-band phase noise due to the nonlinear PD. The net charge
delivered by the CP and the resulting squared phase error are V. PLL PHASE NOISE SPECTRUM
sampled at the rate of . From the Nyquist–Shannon Since the noise sources are uncorrelated, the corresponding
sampling theorem, we know that this sampled process can be noise spectra must be added to obtain the total phase-noise spec-
expressed by a continuous-time signal, the spectrum of which trum at the PLL output given by
has no Fourier components above the Nyquist frequency .
We assume similarly to [18] and [20] that the spectrum
of is white for . The variance of then (39)
follows by integration of and reads
where , , , , ,
, and are the phase-noise contributions of
(33) the previously discussed noise sources referred to the PLL
output. The rms phase error [degree] at the PLL output, which
The quadratic term in (19) results in the PD noise current spec- is sometimes called absolute phase jitter, is given by
trum

(34)
(40)
Substituting (33) into (34) and multiplying the result by the
noise transfer function, we obtain
Fig. 6 shows the simulated phase-noise spectrum and the
components for a 10-GHz frequency synthesizer, which em-
ploys a cascode CP. Here, the model parameters have been
adapted to measurements on the experimental dual-loop PLL
(35) presented in [23]. For space limitations, we only sketch this
process here. First, the noise of the 100-MHz crystal oscillator
For a high order of the SDM, the probability density of is mounted on the printed circuit board was measured by a spec-
approximately Gaussian. By using partial integration, we obtain trum analyzer. Subsequently, the noise of the input buffer was
the averages in (35) given by measured using small sinusoidal input signals to maximize
the reference buffer noise. The VCO noise spectrum was de-
termined from phase-noise measurements on the free-running
oscillator. For the noise contributions of the loop filter and the
(36) SDM, no parameters but the filter values and the SDM order are
required. In order to model the PD noise, the rms phase error
was estimated from MATLAB simulations, and the curvature
(37) parameter was obtained from transient circuit simulations
using the simulator Virtuoso Analog Design Environment. CP
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1919

amplifiers, this is not necessarily the case for other circuits like
CPs. Here, the white device noise in the output circuit (drain
or collector) must be compared for the two devices. A transfor-
mation to the gate or base terminal as typically performed in
low-noise amplifiers is not meaningful here. In the following,
we compare the white output noise PSDs for the two types of
devices.
The two-sided thermal drain current noise PSD of a MOSFET
was according to (14)

(41)

In saturation, the transconductance is given by

(42)

where the gate–source overdrive voltage was


introduced. By substituting (42) in (41), we obtain
Fig. 6. Modeled phase-noise spectrum for a 10-GHz synthesizer using a cas-
code CP.
(43)

device noise was also modeled by circuit simulation. Details of The two-sided shot noise PSD of a bipolar transistor is given
these simulations will be given in Section VI-C. by
Unlike in traditional PLLs, the VCO phase noise is band-
(44)
stop filtered due to the presence of the voltage divider R4/R5
at the CP output, as shown in Fig. 3. For the same reason, all where is the dc collector current, and is the elementary
other noise transfer functions are modified at low frequencies. charge. Assuming the same dc current for the two transistors,
These modifications are not critical, provided that the biasing we obtain from (43) and (44) for the ratio between the output
resistors are not too small. The relatively high level of PD noise current noise PSDs
can be explained by the high PLL output frequency of 10 GHz
in conjunction with strong PD nonlinearity and the employment (45)
of a MASH-type SDM, which results in a large rms phase error
in fractional- mode. In our example, the PD noise due to CP Here, we assumed that and , resulting
nonlinearity and the CP device noise dominate the in-band phase in a thermal voltage of 26 mV. We conclude
noise. This was the main motivation for improving the CP with that MOSFETs may show much less white output noise, com-
respect to linearity and device noise, as will be discussed in the pared with their bipolar counterparts, provided that the over-
next section. drive voltage is much larger than 200 mV. Obviously, the ad-
vantage of MOSFETs over bipolar transistors is particularly
VI. SUGGESTED NOVEL CP pronounced for processes with a higher CMOS supply voltage.
In this section, we will consider the output noise PSD of This advantage reduces with technology scaling, which makes
a bipolar transistor and a MOSFET. The potential of MOS- MOSFETs less attractive for low-voltage applications. We have
FETs with large gate–source voltages in the context of low-noise disregarded flicker noise in this comparison. We believe that
CPs is outlined. This is followed by a brief description of a flicker noise is less important than thermal noise for the fol-
low-noise dual-loop PLL architecture with CP output biasing. lowing reason. The CP flicker noise corner is given by
Subsequently, we describe a simple CP architecture specifically according to (15). Assuming a transistor noise corner of 1 MHz
designed for VCO fine tuning using this PLL architecture. An and a duty cycle of 10%, we obtain a CP flicker noise corner
improvement by 10 dB over the existing design from [23] with of 100 kHz. The optimum loop bandwidth is typically larger in
respect to CP thermal device noise and PD noise is predicted. a fractional- PLL, efficiently suppressing flicker noise in the
CP. We will show that the condition can be
A. Transistor Noise Considerations fulfilled by employing the modern dual-loop PLL architecture
This paper was motivated by the desire to improve the syn- from Section VI-B in conjunction with the CP architecture from
thesizer for space applications in SiGe-BiCMOS technology. Section VI-C. This architecture will allow the gate–source volt-
BiCMOS technologies offer the opportunity to choose between ages to be fully switched between ground (VSS) and CMOS
bipolar transistors and MOSFETs for the best design of each supply ( in our case). For the CP, MOSFETs
building block. Generally, bipolar transistors have the reputation might be the better choice, compared to SiGe-HBTs, whereas
to provide better high-frequency noise performance than MOS- HBTs are better suited for low-noise VCOs and frequency di-
FETs, which is only partly true. This reputation mainly results viders at high frequencies due to the large transconductance,
from the large transconductance of (hetero-) bipolar transistors, compared with MOSFETs. Moreover, the flicker noise perfor-
compared with MOSFETs. While this advantage is crucial for mance of SiGe-HBTs based on VCOs is much better [26].
1920 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

Fig. 7. Schematic view of a dual-loop frequency synthesizer.

B. PLL Architecture for Low Phase Noise


A dual-loop architecture using two parallel CPs was de-
scribed in [23] and [27]. A slightly modified version is
suggested in Fig. 7. Here, the two CPs, i.e., CP1 and CP2,
for fine and coarse tuning, respectively, are composed of five
binary weighted CPs each, which are selectable by a common
five-bit control line. Two current sources (CSs) are added to
generate offset currents and in the fine-tuning loop
and the coarse-tuning loop, respectively. They are composed of
five binary weighted CSs each, which are controlled by another
five-bit control line. The advantage of an offset current at the Fig. 8. CP architecture used in CP1.
CP output is the opportunity to shift the steady-state operation
point of the PD in order to improve its linearity [16], [28].
Since the two CPs are driven by the same PFD, the condition coarse tuning, a traditional low-current CP with a higher output
should be fulfilled in order to keep impedance could be used.
the dc value of the fine-tuning voltage constant. The noise in As shown in Section VI-A, MOSFET-based CPs can provide
the low-current CP CP2 for coarse tuning is minimized by a a low white noise, if their gate–source voltages are large. In ad-
large capacitor to ground (100 nF in [23]). As a result, the dition, they also exhibit flicker noise. However, the flicker noise
phase noise is dominated by the fast fine-tuning loop. Due to corner frequency of the CP given by according to (15) is
the low fine-tuning gain of the VCO, the overall phase noise lower than the transistor noise corner by the factor . Since
is significantly reduced, compared to a single-loop PLL with is typically lower than 10%, flicker noise is usually less
the same tuning range, as experimentally verified in [23]. This important than thermal noise in the context of CP design. The
improvement is particularly important for fractional- PLLs, CP current is usually determined from system simulations
where the large CP duty cycle increases phase noise and spurs, and results in a given drain current of the CP output tran-
particularly, if a dc offset current is added to the CP output sistors. In order to generate the drain current , either large
current. MOSFETs with moderate gate-source voltages or moder-
ately sized MOSFETs with large can be used. From (43),
C. CP Architecture for Low Phase Noise we conclude that the latter option results in a lower device noise.
In most cases, CPs have been designed and optimized for The next step in the design of a low-noise CP is to find an ar-
single-loop PLLs. A vast number of publications are devoted chitecture, where the gate–source voltages are maximized. The
to this topic (see [29], [30], and references therein). In order to simplest CP with this property consists of a pMOSFET M1 de-
obtain a good matching between the UP and DOWN currents livering the UP current and an nMOSFET M2 delivering the
over the whole PLL tuning range, a large output resistance of DOWN current. Such a circuit is shown in Fig. 8. Unlike con-
the CP is generally mandatory for single-loop PLLs. The situa- ventional CPs, it does not use cascode transistors or current mir-
tion is completely different, if a CP is used for fine tuning of the rors, which avoids additional potential noise sources. A switch-
VCO only, where its output dc voltage is almost fixed as in [23]. able CS realized by the transistor M3 between the output and
In this case, emphasis can be placed on fast current switching ground was also introduced to improve the PD linearity. At first
of the CP and on a low device noise by simplifying the CP ar- sight, this CP seems unacceptable for low-noise PLL design
chitecture. In this paper, we confine ourselves to this dual-loop since the output resistance is rather low, and the matching be-
PLL architecture and consider only the CP for fine tuning. For tween the UP and DOWN currents extremely depends on the
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1921

output voltage. In traditional single-loop PLLs, this would in-


evitably result in large spurs and a strong dependence of the
PLL phase-noise spectrum on the output frequency. However,
these problems are solved, if this CP is used for fine tuning
of the VCO (CP1 in Fig. 7), whereas a traditional low-current
CP is used for coarse tuning (CP2 in Fig. 7). The noise of the
latter can be reduced to a negligible level by loading it with
a large capacitor [23]. A voltage divider composed of two re-
sistors R4 and R5 on the order of 1 is added at the output
of CP1 to stabilize the dc output voltage at a desired value
given by . This eliminates the need
for a high output impedance of CP1 and improves its perfor- Fig. 9. Simulated UP and DOWN currents of CP1 and offset current I for
mance. At the same time, the VCO fine-tuning gain is kept al- two offset current levels.
most constant, which makes the PLL phase-noise spectrum ro-
bust with respect to device parameter variations with process,
supply voltage, and temperature (PVT variations). Note that the
PVT dependence of the CP itself is larger than that of a typical
cascode CP. However, the loop bandwidth in a CP PLL is pro-
portional to the product . In an integrated VCO, the
gain can easily vary by a factor of three or more over the tuning
range. By contrast, variations in the threshold voltage of magni-
tude cause relative changes of the CP current on the order
of only, as evident from (42). This
is much smaller than relative changes in a single-loop
PLL. The relatively constant loop bandwidth over a wide tuning
range in a dual-loop PLL using a cascode CP with output biasing Fig. 10. PD gain versus input phase error for new CP.
has experimentally been demonstrated in [27] and [23]. The low
output impedance of our new CP will reduce supply rejection.
However, we believe this drawback to be less significant than 200 ps, respectively, which is approximately one inverter delay.
the advantage of having a highly linear CP with a low thermal The turn-on time is about four times shorter than the value of
device noise. To minimize the effect of CP supply noise on the 1 ns reported for a CP in 0.35- m CMOS technology using a
VCO, an on-chip voltage regulator and a separate CP supply cascode architecture [31]. Cascode architectures can provide a
would be helpful. high output resistance and good current matching, but the swing
The CP draws an additional dc current due of the gate–source voltages of the switching MOSFETs is sig-
to output biasing. This results in a tradeoff between power con- nificantly smaller than VDD, limiting their turn-on times and,
sumption and phase noise. The fractional- PLL in [23] uses thereby, the PD linearity. Fig. 10 shows the simulated PD gain
to stabilize the output dc voltage of the CP as a function of the phase error at the PFD input for the
generating a current up to 8 mA. This choice was motivated by new CP. It was calculated by simulating the average CP output
the desire to minimize the phase noise, whereas power consump- current as a function of the input phase error and numerically
tion was considered less critical in satellite applications. By con- differentiating the result with respect to the phase error. The PD
trast, the integer- PLL for 60-GHz wireless communications gain mA is almost
in [27] used . Generally, R4 and R5 should the same as in Fig. 5 to make the two CPs comparable. The slope
be larger for integer- PLLs, compared with fractional- PLLs of this gain curve is essentially the curvature of the PD charac-
due to the lower CP duty cycle of the former. Moreover, CMOS teristic according to (20) and below. The average slope is
VCOs require larger resistors R4 and R5 than bipolar oscillators lower by a factor of 18, compared to the cascode CP gain in
to guarantee sufficient flicker noise suppression in the loop. Fig. 5. This improvement of the linearity is expected to have a
Fig. 9 shows the simulated CP currents in the fine-tuning loop significant effect on the in-band phase noise and spurs of the
for two different offset currents. Obviously, the short DOWN fractional- PLL.
current pulse is not affected by the offset current, whereas the In addition to improving the PD linearity, the new CP reduces
UP current pulse becomes broader with increasing offset cur- thermal device noise. Fig. 11 shows the simulated device noise
rent. This allows the PD to be linearized by shifting the opera- of the new CP and of the cascode CP used in [23]. Note that the
tion point into a region, where only the UP current responds to large duty cycle of 30% represents a worst case with respect to
the inevitable phase error changes in fractional- mode [16]. CP device noise. For a 100-MHz reference as in [23], this duty
In order to obtain a high linearity of the PD, the current pulses cycle corresponds to a CP activation time of 3 ns, which
should be as steep as possible. This is achieved in our CP ar- is sufficiently large to linearize the PD, even if a MASH SDM
chitecture by the large swings and the steep waveforms of the with its large rms phase error is employed. The noise plateau
gate–source voltages toggling between VSS and VDD. As a re- is reduced by 10 dB as a result of the larger gate–source volt-
sult, the turn-on time and turn-off time are as low as 250 and ages and the small number of transistors. Remember that the
1922 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

loop. Assuming a duty cycle of 20%, we obtain an


input-referred white phase noise of
. This corresponds to a phase noise of
or 159 dBc/Hz, following the remark after
(1). At the 10-GHz PLL output, this noise appears amplified by
MHz dB, resulting in an in-band
phase noise due to thermal CP noise of 119 dBc/Hz. This
noise level is negligible, compared to other noise sources, as
evident from Fig. 6.

VII. INTEGRATED PHASE ERROR AND TIMING JITTER

Timing jitter and phase noise describe the same physical ef-
fect. Timing jitter describes the fluctuations of the zero crossings
of the output signal around the ideal values, whereas phase noise
is the corresponding frequency-domain equivalent. In radio-fre-
quency synthesizer design, the rms phase error is often used as
a metric to quantify the overall phase-noise performance. We
Fig. 11. Simulated output noise current PSD for new CP (lower curve) and calculate the integrated rms phase error (in degrees) at the
cascode CP.
PLL output by using

(46)

where we employ and MHz as


integration limits.
In high-speed digital design, the absolute PLL jitter (or
tracking jitter) is often used for noise characterization. It de-
scribes the deviation of the zero crossings of the output clock
from the ideal positions, where a clean input clock is assumed.
Absolute PLL jitter is given by

Fig. 12. Simulated output current PSD at 10 MHz as a function of CP duty (47)
cycle for I =4 mA.
where is the ideal period of the PLL output signal. In
CDR circuits, the output signal is often referred to itself shifted
noise corner of the CP is proportional to according to (15). by a delay . For a very long delay , the autocorrelation of the
This long-term correlation effect is not correctly reflected by the output signal converges to zero, and the self-referenced jitter
simulation, which overestimates the noise by a factor of approaches a steady-state value . If white noise
. For typical values of , this corresponds sources dominate the phase noise, then we find for the long-term
to 10–20 dB. However, the white noise plateau is correctly mod- jitter , as shown in [32].
eled. Therefore, we can expect a reduction in the in-band noise In conclusion, the improvement of the CP will reduce not
contribution in the phase-noise plateau by 10 dB for the new CP. only the phase noise but also the rms phase error, absolute jitter,
As assumed in (15), the noise current PSD due to thermal and long-term jitter. In order to predict the expected improve-
device noise is expected to be proportional to the CP duty cycle. ment, we assume a reduction in white CP device noise by 10
In order to confirm this assumption and to determine the ratio dB and a reduction in by a factor of 10. These numbers are
, we have simulated the high-frequency consistent with the simulations presented in Section VI. Fig. 13
noise PSD over a wide range of . Fig. 12 shows the sim- shows the simulated phase-noise spectrum and its components
ulated device noise for different phase errors corresponding to for this case. The PD noise due to CP nonlinearity is now al-
different CP duty cycles. For the white noise current PSD nor- most negligible, which can be understood from (38). Since the
malized to the CP current , we found a value of PD phase noise is proportional to , the linearity improvement
for this CP, which is an order of magnitude by a factor of 10 will lower this phase-noise contribution by
lower than that for the cascode CP. 20 dB. As a result, the integrated phase error is reduced from
As an illustration, we consider a 10-GHz PLL driven by 1.43 to 0.75 . The latter value corresponds to an absolute jitter
a 100-MHz reference using a 4-mA CP in the fine-tuning of ps for our 10-GHz
HERZEL et al.: ANALYTICAL PHASE-NOISE MODELING AND CP OPTIMIZATION FOR FRACTIONAL- PLLs 1923

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1924 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, AUGUST 2010

Frank Herzel was born in Güstrow, Germany, in J. Christoph Scheytt (M’01) received the Diploma
1963. He received the M.S. degree from Berlin, Ger- degree (M.S.) and the Ph.D. degree (with highest
many, in 1989 and the Ph.D. degree from Rostock, honors) from Ruhr-University, Bochum, Germany,
Germany, in 1993, both in theoretical physics. in 1996 and 2000, respectively.
Since 1993, he has been with the IHP, Frankfurt In 2000, he cofounded advICo Microelectronics
(Oder), Germany, where he was mainly involved in GmbH, which is a German IC design house. For six
semiconductor device modeling until 1996. Since years, he served as CEO at advICo, where he was re-
then, he has been working on the design of silicon sponsible for various projects in the area of wireless
ICs for RF communications. He is currently focusing and fiber-optic IC design. Since 2006, he has been
on SiGe BiCMOS frequency synthesizers for space with the IHP, Frankfurt (Oder), Germany, where he
applications. is the Head of the Circuit Design Department, which
is a group of about 30 researchers working on high-frequency and broadband IC
design. He has authored and coauthored more than 40 papers. He is the holder
of six patents. His research interests include RFIC and broadband IC design,
Sabbir A. Osmany was born in Bangladesh in 1975. PLL techniques, and design with SiGe BiCMOS technologies.
He received the M.S. degree in communications tech-
nology from the University of Ulm, Ulm, Germany,
where he is working toward the Ph.D. degree.
Since 2005, he has been with the IHP, Frankfurt
(Oder), Germany. His research interests include
mixed-signal and RF IC design for wireless or
optical communication, with emphasis on integer-N
N
and fractional- frequency synthesizers.