Department of Electrical and Electronics Engineering

Reg. No. :
MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL
(A Constituent Institute of Manipal University, Manipal)

Fourth SEMESTER B.E. DEGREE MAKEUP EXAMINATION

(REVISED CREDIT SYSTEM)
23 January 2009

DIGITAL ELECTRONIC CIRCUITS (ELE 208)

Time: 3 hours Max. Marks: 50
Note : Answer any FIVE full questions.
Missing data, if any, may be suitably assumed.

1A. Perform the following arithmetic operation of decimal numbers in binary by representing the negative
numbers in 2’s complement form. Explain how the result is interpreted in each case.
i) 46 – 78
ii) 34 – 28 (04)

1B. Design a BCD to gray code converter and implement the circuit using NAND gates only. (06)

2A. Simplify the following logical expression using Quine – McCluskey method.
F (W,X,Y,Z) = Σm ( 1,2,3,5,9,12,14,15) + d (4,8,11) (05)

2B. Design a squarer circuit using 2 to 4 decoders (with active low enable and active low output) such that
input to the circuit is 3-bit 2’s complement number and output is square of the input number. Residual
gates may be used. (05)

3A. Write the simplified logical expression for the VEM given.
AB
CD 00 01 11 10

00 E' 1 φ E

01 E'φ φ F E+E'φ

11 F+F'φ Fφ Fφ 0

10 1 1 F'+Fφ 0

(05)

3B. Convert a JKFF to XYFF whose characteristic table is given in Table

X Y Qn+1
0 0 1
0 1 Qn
1 0 Q’n
1 1 0
(05)

4A. Design a glitch free, modulo-13, asynchronous counter using D FF (04)

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 Department of Electrical and Electronics Engineering

4B. Design one bit comparator which has two outputs S1S0 = 10, 00 and 01 for A>B, A=B and A<B
respectively. Hence design two bit comparator using residual gates which has output GEL=100, 010,
001 for A>B, A=B and A<B respectively as shown in Figure below. (06)

A1 B1 A0 B0

S0 S0
G
Output One bit One bit
E Network Comparator Comparator
L S1
S1

5A. Design a combinational circuit that implements the following functions depending on the select inputs
(S1, S0) where A and B are 3 bit inputs. Use residual gates and 4:1 multiplexers.

S1 S0 Operation
0 0 Logical AND of A and B
0 1 Complement A
1 0 Complement B
1 1 Same as A
(05)
5B. Explain the following terms:
(i) Propagation delay
(ii) Noise Margin
(iii) Fan-out
(03)
5C. Draw the ASM chart for the sequence detector which detects the sequence 1101 in a continuous
data stream. (Use Moore m/c) (02)

6A. Design a sequence generator, which cycles through the sequence 8-4-1-10-3-12-5-8… Implement
using D flip flop. (05)

6B. A sequence recognizer has a single input x and a single output z. It is desired that the network
produce a 1 output if the current input and the previous 3 inputs correspond to either of the sequences
0110 or 1001. Design and implement a minimum cost Mealey m/c for the same using 74x153 (4 i/p
dual o/p multiplexer).
(05)

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