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6 GSPS, JESD204B,
Dual Analog-to-Digital Converter
Data Sheet AD9689
FEATURES 0.975 V, 1.9 V, and 2.5 V dc supply operation
JESD204B (Subclass 1) coded serial digital outputs 9 GHz analog input full power bandwidth (−3 dB)
Support for lane rates up to 16 Gbps per lane Amplitude detect bits for efficient AGC implementation
Noise density Programmable FIR filters for analog channel loss equalization
−152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p 2 integrated, wideband digital processors per channel
−154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p 48-bit NCO
−154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p Programmable decimation rates
−155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p Phase coherent NCO switching
1.55 W total power per channel at 2.56 GSPS (default settings) Up to 4 channels available
SFDR at 2.56 GSPS encode Serial port control
73 dBFS at 1.8 GHz AIN at −2.0 dBFS Supports 100 MHz SPI writes and 50 MHz SPI reads
59 dBFS at 5.53 GHz AIN at −2.0 dBFS Integer clock with divide by 2 and divide by 4 options
full-scale voltage = 1.1 V p-p Flexible JESD204B lane configurations
SNR at 2.56 GSPS encode On-chip dither
59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS APPLICATIONS
53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS
Diversity multiband and multimode digital receivers
full-scale voltage = 1.1 V p-p
3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
SFDR at 2.0 GSPS encode
Electronic test and measurement systems
78 dBFS at 900 MHz AIN at −2.0 dBFS
Phased array radar and electronic warfare
62 dBFS at 5.53 GHz AIN at −2.0 dBFS
DOCSIS 3.0 CMTS upstream receive paths
full-scale voltage = 1.1 V p-p
HFC digital reverse path receivers
SNR at 2.0 GSPS encode
62.7 dBFS at 900 MHz AIN at −2.0 dBFS
53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD
(0.975V) (1.9V) (2.5V) (0.975V) (0.975V) (0.975V) (1.9V) (1.9V)
BUFFER
VIN+A ADC 14
VIN–A CORE
PROGRAMMABLE
CROSSBAR MUX
CROSSBAR MUX
CONVERTER SERDOUT1±
JESD204B SERDOUT2±
FAST SIGNAL LINK 8
DETECT MONITOR AND SERDOUT3±
Tx SERDOUT4±
DIGITAL DOWN- OUTPUTS SERDOUT5±
CONVERTER SERDOUT6±
VIN+B ADC 14 SERDOUT7±
VIN–B CORE
BUFFER
VREF
SYNCINB±
PDWN/STBY
JESD204B CLOCK
SYSREF± SUBCLASS 1 FD_A/GPIO_A0
CONTROL DISTRIBUTION
GPIO_A1
CLK+ GPIO MUX
FD_B/GPIO_B0
SPI AND
CONTROL GPIO_B1
REGISTERS
CLK– ÷2
÷4 AD9689
15550-001
Figure 1.
DOCUMENTATION DISCUSSIONS
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• AD9689: 14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B, Dual
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TOOLS AND SIMULATIONS
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• AD9689 S-Parameters number.
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AD9689 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 DDC Frequency Translation ..................................................... 47
Applications ....................................................................................... 1 DDC Decimation Filters ........................................................... 55
Functional Block Diagram .............................................................. 1 DDC Gain Stage ......................................................................... 61
Revision History ............................................................................... 3 DDC Complex to Real Conversion ......................................... 61
General Description ......................................................................... 4 DDC Mixed Decimation Settings ............................................ 62
Product Highlights ........................................................................... 4 DDC Example Configurations ................................................. 64
Specifications..................................................................................... 5 DDC Power Consumption ........................................................ 67
DC Specifications ......................................................................... 5 Signal Monitor ................................................................................ 68
AC Specifications.......................................................................... 6 SPORT over JESD204B .............................................................. 69
Digital Specifications ................................................................... 8 Digital Outputs ............................................................................... 71
Switching Specifications .............................................................. 9 Introduction to the JESD204B Interface ................................. 71
Timing Specifications ................................................................ 10 JESD204B Overview .................................................................. 71
Absolute Maximum Ratings.......................................................... 12 Functional Overview ................................................................. 72
Thermal Resistance .................................................................... 12 JESD204B Link Establishment ................................................. 72
ESD Caution ................................................................................ 12 Physical Layer (Driver) Outputs .............................................. 74
Pin Configuration and Function Descriptions ........................... 13 fS × 4 Mode .................................................................................. 75
Typical Performance Characteristics ........................................... 16 Setting Up the AD9689 Digital Interface................................. 76
2.0 GSPS ....................................................................................... 16 Deterministic Latency.................................................................... 83
2.6 GSPS ....................................................................................... 21 Subclass 0 Operation.................................................................. 83
Equivalent Circuits ......................................................................... 26 Subclass 1 Operation.................................................................. 83
Theory of Operation ...................................................................... 28 Multichip Synchronization............................................................ 85
ADC Architecture ...................................................................... 28 Normal Mode.............................................................................. 85
Analog Input Considerations.................................................... 28 Timestamp Mode ....................................................................... 85
Voltage Reference ....................................................................... 31 SYSREF Input .............................................................................. 87
DC Offset Calibration ................................................................ 32 SYSREF± Setup/Hold Window Monitor ................................. 89
Clock Input Considerations ...................................................... 32 Latency ............................................................................................. 91
Power-Down and Standby Mode ............................................. 35 End to End Total Latency .......................................................... 91
Temperature Diode .................................................................... 35 Example Latency Calculations.................................................. 91
ADC Overrange and Fast Detect .................................................. 37 LMFC Referenced Latency........................................................ 91
ADC Overrange .......................................................................... 37 Test Modes ....................................................................................... 93
Fast Threshold Detection (FD_A and FD_B) ........................ 37 ADC Test Modes ........................................................................ 93
ADC Application Modes and JESD204B Tx Converter Mapping JESD204B Block Test Modes .................................................... 94
........................................................................................................... 38 Serial Port Interface ........................................................................ 96
Programmable FIR Filters ............................................................. 40 Configuration Using the SPI ..................................................... 96
Supported Modes........................................................................ 40 Hardware Interface..................................................................... 96
Programming Instructions ........................................................ 42 SPI Accessible Features .............................................................. 96
Digital Downconverter (DDC) ..................................................... 44 Memory Map .................................................................................. 97
DDC I/Q Input Selection .......................................................... 44 Reading the Memory Map Register Table............................... 97
DDC I/Q Output Selection ....................................................... 44 Memory Map Register Details .................................................. 98
DDC General Description ........................................................ 44 Applications Information ............................................................ 132
Rev. A | Page 2 of 134
Data Sheet AD9689
Power Supply Recommendations .......................................... 132 Outline Dimensions ......................................................................134
Layout Guidelines .................................................................... 133 Ordering Guide .........................................................................134
AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8)........... 133
REVISION HISTORY
10/2017—Rev. 0 to Rev. A Changes to Figure 67 Caption ....................................................... 26
Added 2.0 GSPS ............................................................. Throughout Changes to Table 10 ........................................................................ 30
Changes to Features Section ............................................................ 1 Changes to Figure 87 ...................................................................... 32
Changes to Product Highlights Section ......................................... 4 Changes to Figure 96 Caption ....................................................... 35
Changes to Table 1 ............................................................................ 5 Changes to Programming Instructions Section .......................... 42
Changes to Table 2 ............................................................................ 6 Added Table 28; Renumbered Sequentially ................................. 67
Changes to Table 4 ............................................................................ 9 Changes to Table 29 Title ............................................................... 67
Added 2.0 GSPS Section and Figure 6 to Figure 11; Renumbered Changes to De-Emphasis Section ................................................. 74
Sequentially ......................................................................................16 Changes to Figure 142 .................................................................... 82
Added Figure 12 to Figure 17 ........................................................17 Changes to Reading the Memory Map Register Table Section....... 97
Added Figure 18 to Figure 23 ........................................................18 Changes to Address 0x0006, Table 46 .......................................... 98
Added Figure 24 through Figure 29..............................................19 Changes to Address 0x010A, Table 47 ......................................... 99
Added Figure 30 through Figure 35..............................................20 Changes to Table 50 ...................................................................... 105
Added 2.6 GSPS Section .................................................................21 Changes to Table 51 ...................................................................... 117
Change to Figure 41 ........................................................................21 Changes to Power Supply Recommendations Section, Figure 157,
Change to Figure 45 ........................................................................22 and Figure 158 ............................................................................... 132
Changes to Figure 52 and Figure 53 .............................................23 Changes to Ordering Guide ......................................................... 134
Changes to Figure 54, Figure 55, Figure 56, Figure 58, and
Figure 59 ...........................................................................................24 9/2017—Revision 0: Initial Version
Changes to Figure 60 and Figure 61 .............................................25
GENERAL DESCRIPTION
The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital The user can configure the Subclasss 1 JESD204B-based high
converter (ADC). The device has an on-chip buffer and a speed serialized output in a variety of one-lane, two-lane, four-
sample-and-hold circuit designed for low power, small size, and lane, and eight-lane configurations, depending on the DDC
ease of use. This product is designed to support communications configuration and the acceptable lane rate of the receiving logic
applications capable of direct sampling wide bandwidth analog device. Multidevice synchronization is supported through the
signals of up to 5 GHz. The −3 dB bandwidth of the ADC input SYSREF± and SYNCINB± input pins.
is 9 GHz. The AD9689 is optimized for wide input bandwidth, The AD9689 has flexible power-down options that allow
high sampling rate, excellent linearity, and low power in a small significant power savings when desired. All of these features can
package. be programmed using a 3-wire serial port interface (SPI).
The dual ADC cores feature a multistage, differential pipelined The AD9689 is available in a Pb-free, 196-ball BGA, specified
architecture with integrated output error correction logic. Each over the −40°C to +85°C ambient temperature range. This
ADC features wide bandwidth inputs supporting a variety of product is protected by a U.S. patent.
user-selectable input ranges. An integrated voltage reference
eases design considerations. The analog input and clock signals Note that throughout this data sheet, multifunction pins, such
are differential inputs. The ADC data outputs are internally as FD_A/GPIO_A0, are referred to either by the entire pin
connected to four digital downconverters (DDCs) through a name or by a single function of the pin, for example, FD_A,
crossbar mux. Each DDC consists of multiple cascaded signal when only that function is relevant.
processing stages: a 48-bit frequency translator (numerically PRODUCT HIGHLIGHTS
controlled oscillator (NCO)), and decimation rates. The NCO has 1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio
the option to select preset bands over the general-purpose frequency (RF) sampling of signals up to about 5 GHz.
input/output (GPIO) pins, which enables the selection of up to 2. Four integrated, wideband decimation filters and NCO
three bands. Operation of the AD9689 between the DDC modes is blocks supporting multiband receivers.
selectable via SPI-programmable profiles. 3. Fast NCO switching enabled through the GPIO pins.
In addition to the DDC blocks, the AD9689 has several functions 4. SPI controls various product features and functions to
that simplify the automatic gain control (AGC) function in a meet specific system requirements.
communications receiver. The programmable threshold detector 5. Programmable fast overrange detection and signal
allows monitoring of the incoming signal power using the fast monitoring.
detect control bits in Register 0x0245 of the ADC. If the input 6. On-chip temperature diode for system thermal management.
signal level exceeds the programmable threshold, the fast detect 7. 12 mm × 12 mm, 196-ball BGA.
indicator goes high. Because this threshold indicator has low 8. Pin, package, feature, and memory map compatible with
latency, the user can quickly turn down the system gain to avoid the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.
an overrange condition at the ADC input. In addition to the fast
detect outputs, the AD9689 also offers signal monitoring
capability. The signal monitoring block provides additional
information about the signal being digitized by the ADC.
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, sampling rate = 2.0 GHz/2.56 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) =
−2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C
(TA = 25°C).
Table 1.
2.0 GSPS 2.6 GSPS
Parameter Min Typ Max Min Typ Max Unit
RESOLUTION 14 14 Bits
ACCURACY
No Missing Codes Guaranteed Guaranteed
Offset Error 0 %FSR
Offset Matching 0 0 %FSR
Gain Error −2.9 ±1 +1.8 −4.9 ±1 +5.6 %FSR
Gain Matching ±0.2 ±0.2 %FSR
Differential Nonlinearity (DNL) −0.62 ±0.4 +0.79 −0.65 ±0.4 +0.75 LSB
Integral Nonlinearity (INL) −9.9 ±2 +8.1 −16 ±6 +13 LSB
TEMPERATURE DRIFT
Offset Error ±7.7 ±3.7 ppm/°C
Gain Error 15 58 ppm/°C
INTERNAL VOLTAGE REFERENCE 0.5 0.5 V
INPUT REFERRED NOISE 3.8 4.6 LSB rms
ANALOG INPUTS
Differential Input Voltage Range 1.1 1.7 2.0 1.1 1.7 2.0 V p-p
Common-Mode Voltage (VCM) 1.4 1.4 V
Differential Input Capacitance 0.35 0.35 pF
−3 dB Bandwidth 9 9 GHz
POWER SUPPLY
AVDD1 0.95 0.975 1.0 0.95 0.975 1.0 V
AVDD2 1.85 1.9 1.95 1.85 1.9 1.95 V
AVDD3 2.44 2.5 2.56 2.44 2.5 2.56 V
AVDD1_SR 0.95 0.975 1.0 0.95 0.975 1.0 V
DVDD 0.95 0.975 1.0 0.95 0.975 1.0 V
DRVDD1 0.95 0.975 1.0 0.95 0.975 1.0 V
DRVDD2 1.85 1.9 1.95 1.85 1.9 1.95 V
SPIVDD 1.85 1.9 1.95 1.85 1.9 1.95 V
IAVDD1 455 605 590 693 mA
IAVDD2 585 670 810 882 mA
IAVDD3 65 72 65 73 mA
IAVDD1_SR 25 41 25 43 mA
IDVDD 340 800 405 833 mA
IDRVDD1 2 320 432 390 500 mA
IDRVDD2 25 30 25 30 mA
ISPIVDD 1 5 1 5 mA
AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, sampling rate = 2.0 GHz/2.56 GHz, clock divider = 2, 1.7 V p-p full-scale differential input, input amplitude (AIN) =
−2.0 dBFS, default SPI settings, −10°C ≤ TJ ≤ +120°C, 1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C
(TA = 25°C).
Table 2.
2.0 GSPS 2.6 GSPS
Parameter 2 Min Typ Max Min Typ Max Unit
NOISE DENSITY 3
Full Scale = 1.7 V p-p −154.2 −152 dBFS/Hz
Full Scale = 2.0 V p-p −155.3 −154 dBFS/Hz
CODE ERROR RATE (CER)
AVDD1 = 0.975 V 7 × 10−15 9 × 10−9 Errors
AVDD1 = 1.0 V 3 × 10−15 4.5 × 10−10 Errors
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 155 MHz 63.7 61.3 dBFS
fIN = 155 MHz (Full Scale = 2.0 V p-p) 65.0 62.5 dBFS
fIN = 750 MHz 63.1 61.0 dBFS
fIN = 900 MHz 60.2 62.7 60.9 dBFS
fIN = 1800 MHz 60.9 56.0 59.7 dBFS
fIN = 2100 MHz 59.9 59.3 dBFS
fIN = 3300 MHz 58.3 58.0 dBFS
fIN = 4350 MHz (Full Scale = 1.1 V p-p) 54.4 54.0 dBFS
fIN = 5530 MHz (Full Scale = 1.1 V p-p) 53.1 53.0 dBFS
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 155 MHz 63.5 61.2 dBFS
fIN = 155 MHz (Full Scale = 2.0 V p-p) 64.7 62.4 dBFS
fIN = 750 MHz 62.8 60.7 dBFS
fIN = 900 MHz 59.6 62.5 60.5 dBFS
fIN = 1800 MHz 60.8 52.4 59.4 dBFS
fIN = 2100 MHz 59.7 59.1 dBFS
fIN = 3300 MHz 55.3 56.6 dBFS
fIN = 4350 MHz (Full Scale = 1.1 V p-p) 53.2 51.0 dBFS
fIN = 5530 MHz (Full Scale = 1.1 V p-p) 52.3 49.5 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 155 MHz 10.3 9.9 Bits
fIN = 155 MHz (Full Scale = 2.0 V p-p) 10.5 10.1 Bits
fIN = 750 MHz 10.1 9.8 Bits
fIN = 900 MHz 9.6 10.1 9.8 Bits
fIN = 1800 MHz 9.8 8.4 9.6 Bits
fIN = 2100 MHz 9.6 9.5 Bits
fIN = 3300 MHz 8.9 9.1 Bits
fIN = 4350 MHz (Full Scale = 1.1 V p-p) 8.6 8.2 Bits
fIN = 5530 MHz (Full Scale = 1.1 V p-p) 8.4 7.9 Bits
Rev. A | Page 6 of 134
Data Sheet AD9689
2.0 GSPS 2.6 GSPS
Parameter 2 Min Typ Max Min Typ Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD
HARMONIC 4, 5
fIN = 155 MHz 77 78 dBFS
fIN = 155 MHz (Full Scale = 2.0 V p-p) 77 78 dBFS
fIN = 750 MHz 77 73 dBFS
fIN = 900 MHz 66 78 74 dBFS
fIN = 1800 MHz 76 58 73 dBFS
fIN = 2100 MHz 76 73 dBFS
fIN = 3300 MHz 60 64 dBFS
fIN = 4350 MHz (Full Scale = 1.1 V p-p) 61 60 dBFS
fIN = 5530 MHz (Full Scale = 1.1 V p-p) 62 59 dBFS
WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC
fIN = 155 MHz −99 −96 dBFS
fIN = 155 MHz (Full Scale = 2.0 V p-p) −95 −98 dBFS
fIN = 750 MHz −100 −97 dBFS
fIN = 900 MHz −94 −80 −96 dBFS
fIN = 1800 MHz −91 −88 −74 dBFS
fIN = 2100 MHz −86 −94 dBFS
fIN = 3300 MHz −85 −85 dBFS
fIN = 4350 MHz (Full Scale = 1.1 V p-p) −83 −84 dBFS
fIN = 5530 MHz (Full Scale = 1.1 V p-p) −82 −82 dBFS
TWO-TONE INTERMODULATION DISTORTION (IMD),
AIN1 AND AIN2 = −8.0 dBFS
fIN1 = 1841 MHz, fIN2 = 1846 MHz −72 −72 dBFS
fIN1 = 2137 MHz, fIN2 = 2142 MHz −74 −76 dBFS
CROSSTALK 6 >90 >90 dB
ANALOG INPUT BANDWIDTH, FULL POWER 7 5 5 GHz
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.
2
See AN-835 for definitions and for details on how these tests were completed.
3
Noise density is measured at a low analog input frequency (30 MHz).
4
The input configuration component values are found in Table 9. Refer to Table 10 for the recommended buffer settings.
5
Figure 79 shows the differential transformer coupled configuration. Figure 80 is the input network configuration for frequencies > 5 GHz.
6
Crosstalk is measured at 950 MHz with a −2.0 dBFS analog input on one channel, and no input on the adjacent channel.
7
Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
Table 3.
Parameter Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 300 800 1800 mV p-p
Input Common-Mode Voltage 0.675 V
Input Resistance (Differential) 106 Ω
Input Capacitance 0.9 pF
Differential Input Return Loss at 2.6 GHz 2 9.4 dB
SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.675 2.0 V
Input Resistance (Differential) 18 kΩ
Input Capacitance (Differential) 1 pF
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,
FD_B/GPIO_B0, GPIO_A1, GPIO_B1)
Logic Compliance CMOS
Logic 1 Voltage 0.65 × SPIVDD V
Logic 0 Voltage 0 0.35 × SPIVDD V
Input Resistance 30 kΩ
LOGIC OUTPUTS (SDIO, FD_A, FD_B)
Logic Compliance CMOS
Logic 1 Voltage (IOH = 4 mA) SPIVDD − 0.45V V
Logic 0 Voltage (IOL = 4 mA) 0 0.45 V
SYNCHRONIZATION INPUT (SYNCINB+/SYNCINB−)
Logic Compliance LVDS/LVPECL
Differential Input Voltage 400 800 1800 mV p-p
Input Common-Mode Voltage 0.675 2.0 V
Input Resistance (Differential) 18 kΩ
Input Capacitance 1 pF
SYNCINB+ INPUT
Logic Compliance CMOS
Logic 1 Voltage 0.9 × DRVDD1 2 × DRVDD1 V
Logic 0 Voltage 0.1 × DRVDD1 V
Input Resistance 2.6 kΩ
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7)
Logic Compliance SST
Differential Output Voltage 360 560 770 mV p-p
Differential Termination Impedance 80 100 120 Ω
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.
2
Reference impedance = 100 Ω.
Table 4.
2.0 GSPS 2.6 GSPS
Parameter Min Typ Max Min Typ Max Unit
CLOCK
Clock Rate at CLK+/CLK− Pins 6 6 GHz
Sample Rate 2 1200 2000 2100 1900 2600 2700 MSPS
Clock Pulse Width High 238.096 185.185 ps
Clock Pulse Width Low 238.096 185.185 ps
OUTPUT PARAMETERS
Unit Interval (UI) 3 62.5 66.67 592.6 62.5 66.67 592.6 ps
Rise Time (tR) (20% to 80% into 100 Ω Load) 26 26 ps
Fall Time (tF) (20% to 80% into 100 Ω Load) 26 26 ps
Phase-Locked Loop (PLL) Lock Time 5 5 ms
Data Rate per Channel (Nonreturn to Zero) 4 1.6875 13 16 1.6875 13 16 Gbps
LATENCY 5
Pipeline Latency 6 75 75 Clock cycles
Fast Detect Latency 26 26 Clock cycles
NCO Channel Selection to Output 8 8 Clock cycles
WAKE-UP TIME
Standby 400 400 µs
Power-Down 15 15 ms
APERTURE
Delay (tA) 250 250 ps
Uncertainty (Jitter, tJ) 55 55 fs rms
Out of Range Recovery Time 1 1 Clock cycles
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.
2
The maximum sample rate is the clock rate after the divider.
3
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 8. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 8, M = 2, and F = 1.
6
Refer to the Latency section for more details.
Timing Diagrams
APERTURE DELAY
ANALOG
INPUT N+1
SIGNAL N – 74
N – 75 N – 73 SAMPLE N
N – 72
N–1
CLK–
CLK+
CLK–
CLK+
SERDOUT0– CONVERTER0
A B C D E F G H I J SAMPLE N – 75 MSB
SERDOUT0+
SERDOUT1– CONVERTER0
A B C D E F G H I J SAMPLE N – 75 LSB
SERDOUT1+
SERDOUT2– CONVERTER0
A B C D E F G H I J SAMPLE N – 74 MSB
SERDOUT2+
SERDOUT3– CONVERTER0
A B C D E F G H I J SAMPLE N – 74 LSB
SERDOUT3+
SERDOUT4– CONVERTER1
A B C D E F G H I J SAMPLE N – 75 MSB
SERDOUT4+
SERDOUT5– CONVERTER1
A B C D E F G H I J SAMPLE N – 75 LSB
SERDOUT5+
SERDOUT6– CONVERTER1
A B C D E F G H I J SAMPLE N – 74 MSB
SERDOUT6+
SERDOUT7– CONVERTER1
A B C D E F G H I J SAMPLE N – 74 LSB
SERDOUT7+
SAMPLE N – 75 AND N – 74
15550-002
CLK+
tSU_SR tH_SR
SYSREF–
15550-003
SYSREF+
15550-004
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE
A AVDD2 AVDD2 AVDD1 AVDD1 1 AVDD11 AGND1 CLK+ CLK– AGND1 AVDD1 1 AVDD1 1 AVDD1 AVDD2 AVDD2
B AVDD2 AVDD2 AVDD1 AVDD1 1 AGND AGND1 AGND1 AGND1 AGND1 AGND AVDD1 1 AVDD1 AVDD2 AVDD2
C AVDD2 AVDD2 AVDD1 AGND AGND AGND1 AGND1 AGND1 AGND1 AGND AGND AVDD1 AVDD2 AVDD2
D AVDD3 AGND AGND AGND AGND AGND AGND1 AGND1 AGND AGND AGND AGND AGND AVDD3
E VIN–B AGND AGND AGND AGND AGND2 AVDD1_SR AGND2 AGND AGND AGND AGND AGND VIN–A
F VIN+B AGND AGND AGND AGND AGND SYSREF+ SYSREF– AGND AGND AGND AGND AGND VIN+A
G AVDD3 AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD3
H AGND AGND AGND AGND AGND AGND AGND AGND AGND VREF AGND AGND AGND AGND
J AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND
K AGND 3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3 AGND3
DGND GPIO_B1 SPIVDD FD_B/ CSB SCLK SDIO PDWN/ FD_A/ SPIVDD GPIO_A1 DGND DGND DGND
L STBY
GPIO_B0 GPIO_A0
M DGND DGND DRGND DRGND DRVDD1 DRVDD1 DRVDD1 DRVDD1 DRGND DRGND DRVDD1 DRGND DRVDD2 DVDD
N DVDD DVDD DRGND SERDOUT7+ SERDOUT6+ SERDOUT5+ SERDOUT4+ SERDOUT3+ SERDOUT2+ SERDOUT1+ SERDOUT0+ DRGND SYNCINB+ DVDD
P DVDD DVDD DRGND SERDOUT7– SERDOUT6– SERDOUT5– SERDOUT4– SERDOUT3– SERDOUT2– SERDOUT1– SERDOUT0– DRGND SYNCINB– DVDD
AMPLITUDE (dB)
–60 –60
–75 –75
–90 –90
–105 –105
–120 –120
15550-406
15550-409
–135 –135
0 95 190 285 380 475 570 665 760 855 950 0 95 190 285 380 475 570 665 760 855 950
fIN (MHz) fIN (MHz)
Figure 6. Single-Tone FFT at fIN = 155 MHz Figure 9. Single-Tone FFT at fIN = 905 MHz
0 0
AIN = –2dBFS AIN = –2dBFS
SNRFS = 65.0dB SNRFS = 60.9dB
–15 –15
SFDR = 77dBFS SFDR = 76dBFS
ENOB = 10.5 BITS ENOB = 9.8 BITS
–30 NSD = –155.0dBFS/Hz –30 NSD = –150.9dBFS/Hz
BUFFER CURRENT = 300µA BUFFER CURRENT = 500µA
–45 –45
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–75 –75
–90 –90
–105 –105
–120 –120
15550-407
15550-410
–135 –135
0 95 190 285 380 475 570 665 760 855 950 0 95 190 285 380 475 570 665 760 855 950
fIN (MHz) fIN (MHz)
Figure 7. Single-Tone FFT at fIN = 155 MHz, Full-Scale Voltage = 2.04 V p-p Figure 10. Single-Tone FFT at fIN = 1807 MHz
0 0
AIN = –2dBFS AIN = –2dBFS
SNRFS = 63.1dB SNRFS = 59.9dB
–15 –15
SFDR = 77dBFS SFDR = 76dBFS
ENOB = 10.1 BITS ENOB = 9.6 BITS
–30 NSD = –153.1dBFS/Hz –30 NSD = –149.9dBFS/Hz
BUFFER CURRENT = 300µA BUFFER CURRENT = 700µA
–45 –45
AMPLITUDE (dB)
AMPLITUDE (dB)
–60 –60
–75 –75
–90 –90
–105 –105
–120 –120
15550-408
15550-411
–135 –135
0 95 190 285 380 475 570 665 760 855 950 0 95 190 285 380 475 570 665 760 855 950
fIN (MHz) fIN (MHz)
Figure 8. Single-Tone FFT at fIN = 750 MHz Figure 11. Single-Tone FFT at fIN = 2100 MHz
Rev. A | Page 16 of 134
Data Sheet AD9689
0 80
AIN = –2dBFS
SNRFS = 58.3dB
–15
SFDR = 60dBFS
ENOB = 8.9 BITS 70
–30 NSD = –148.3dBFS/Hz
BUFFER CURRENT = 700µA
–45 60
AMPLITUDE (dB)
SNR/SFDR (dBFS)
–60
50
–75
300µA, SFDR
300µA, SNR
–90 40 500µA, SFDR
500µA, SNR
–105 700µA, SFDR
30 700µA, SNR
–120
15550-412
15550-415
–135 20
0 95 190 285 380 475 570 665 760 855 950
355
2955
155
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
3155
2755
3355
3555
3755
3955
fIN (MHz)
INPUT FREQUENCY (MHz)
Figure 12. Single-Tone FFT at fIN = 3300 MHz Figure 15. SNR/SFDR vs. Input Frequency (fIN) for Various Buffer Currents
0 –40
AIN = –2dBFS
SNRFS = 54.4dB –45
–15
SFDR = 61dBFS
ENOB = 8.6 BITS –50
–30 NSD = –144.4dBFS/Hz 300µA
BUFFER CURRENT = 900µA –55 500µA
–45 700µA
AMPLITUDE (dB)
–60
HD2 (dBFS)
–60
–65
–75
–70
–90
–75
–105
–80
–120
15550-413
–85
15550-416
–135 –90
0 95 190 285 380 475 570 665 760 855 950
355
2955
155
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
3155
2755
3355
3555
3755
3955
fIN (MHz)
INPUT FREQUENCY (MHz)
Figure 13. Single-Tone FFT at fIN = 4350 MHz; Full-Scale Voltage = 1.1 V p-p Figure 16. HD2 vs. Input Frequency (fIN) for Various Buffer Currents
0 –30
AIN = –2dBFS
SNRFS = 53.1dB
–15
SFDR = 62dBFS
ENOB = 8.4 BITS –40
–30 NSD = –143.1dBFS/Hz 300µA
BUFFER CURRENT = 900µA 500µA
–45 –50 700µA
AMPLITUDE (dB)
HD3 (dBFS)
–60
–60
–75
–90 –70
–105
–80
–120
15550-414
15550-417
–135 –90
0 95 190 285 380 475 570 665 760 855 950
355
2955
155
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
3155
2755
3355
3555
3755
3955
fIN (MHz)
INPUT FREQUENCY (MHz)
Figure 14. Single-Tone FFT at fIN = 5400 MHz; Full-Scale Voltage = 1.1 V p-p Figure 17. HD3 vs. Input Frequency (fIN) for Various Buffer Currents
AMPLITUDE (dBFS)
–45 –45
–60 –60
–75 –75
–90 –90
–105 –105
–120 –120
15550-418
15550-421
–135 –135
0 125 250 375 500 625 750 875 1000 –60 –45 –30 –15 0 15 30 45 60
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 18. Two-Tone FFT; fIN1 = 1841 MHz, fIN2 = 1846 MHz; Figure 21. Two-Tone FFT; fIN1 = 947.5 MHz, fIN2 = 1855.5 MHz
AIN1 and AIN2 = −8 dBFS fCLK = 1.96608 GHz; Decimation Ratio = 16, NCO Frequency = 1842.5 MHz
0 0
AIN1 AND AIN2 = –8dBFS SFDR (dBc)
–10 SFDR (dBFS)
–15 SFDR = 74dBFS
IMD2 = 77dBFS –20 IMD3 (dBc)
IMD3 = 74dBFS IMD3 (dBFS)
–30 –30
SFDR/IMD3 (dBc AND dBFS)
BUFFER CURRENT = 700µA
–40
AMPLITUDE (dBFS)
–45
–50
–60
–60
–75 –70
–80
–90
–90
–105 –100
–110
–120
15550-419
15550-422
–120
–135 –130
–90
–84
–78
–72
–66
–60
–54
–48
–42
–36
–30
–24
–18
–12
0 125 250 375 500 625 750 875 1000
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 19. Two-Tone FFT; fIN1 = 2137 MHz, fIN2 = 2142 MHz; Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
AIN1 and AIN2 = −8 dBFS fIN1 = 1841.5 MHz, fIN2 = 1846.5 MHz
0 0
AIN1 AND AIN2 = –8dBFS SFDR (dBc)
–15 NCO FREQUENCY = 942.5MHz SFDR (dBFS)
SFDR = 91dBFS –20 IMD3 (dBc)
BUFFER CURRENT = 700µA IMD3 (dBFS)
–30
SFDR/IMD3 (dBc AND dBFS)
–40
AMPLITUDE (dBFS)
–45
–60 –60
–75
–80
–90
–100
–105
–120
–120
15550-420
15550-423
–135 –140
–90
–84
–78
–72
–66
–60
–54
–48
–42
–36
–30
–24
–18
–12
Figure 20. Two-Tone FFT; fIN1 = 947.5 MHz, fIN2 = 1855.5 MHz Figure 23. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fCLK = 1.96608 GHz; Decimation Ratio = 16, NCO Frequency = 942.5 MHz fIN1 = 2137.5 MHz, fIN2 = 2142.5 MHz
100 3.0
80
SNR/SFDR (dBc AND dBFS)
2.5
60
POWER (W)
2.0
40
1.5
20
AVDD1 + AVDD2 + AVDD3 POWER
SNR (dBFS) DRVDD1 + DRVDD2 POWER
SFDR (dBFS) 1.0
0 DVDD + SPIVDD POWER
SFDR (dBc) AVERAGE OF TOTAL POWER (W)
SNR (dBc)
–20 0.5
15550-424
15550-427
–40 0
–10 0 10 20 30 40 50 60 70 80 90 100 110 120
–9
–5
–85
–81
–77
–73
–69
–65
–61
–57
–53
–49
–45
–41
–37
–33
–29
–25
–21
–17
–13
JUNCTION TEMPERATURE (°C)
INPUT AMPLITUDE (dBFS)
Figure 24. SNR/SFDR vs. Input Amplitude (AIN), fIN = 900 MHz Figure 27. Power vs. Junction Temperature (TJ), fIN = 900 MHz
120 65
100 63
61
80
SNR/SFDR (dBc AND dBFS)
59
60
SNR (dBFS) 57
40
55 0.2V
0.3V
20 0.5V
SNR (dBFS) 53 0.8V
SFDR (dBFS) 1.2V
0 1.8V
SFDR (dBc) 51 2.0V
SNR (dBc)
–20 49
15550-425
15550-428
–40 47
155.3
467.8
780.3
1092.8
1405.3
1717.8
2020.3
2332.8
2645.3
2957.8
3270.3
3582.8
3895.3
–9
–5
–85
–81
–77
–73
–69
–65
–61
–57
–53
–49
–45
–41
–37
–33
–29
–25
–21
–17
–13
Figure 25. SNR/SFDR vs. Input Amplitude (AIN), fIN = 1800 MHz Figure 28. SNR vs. Analog Input Frequency (fIN) for Various Clock Amplitude
in Differential Peak-to-Peak Voltages
90 90
SFDR
80 80 SNR
70 70
60 60
SNR/SFDR (dBFS)
SNR/SFDR (dBFS)
50 SFDR
SNR 50
40 40
30 30
20 20
10 10
15550-426
15550-429
0
0
–10 0 10 20 30 40 50 60 70 80 90 100 110 120 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1
JUNCTION TEMPERATURE (°C) SAMPLE FREQUENCY (GHz)
Figure 26. SNR/SFDR vs. Junction Temperature (TJ), fIN = 900 MHz Figure 29. SNR/SFDR vs. Sample Frequency (fS), fIN = 900 MHz
60 300,000
NUMBER OF HITS
SNR/SFDR (dBFS)
50 SFDR 250,000
SNR
40 200,000
30 150,000
20 100,000
50,000
10
15550-430
15550-433
0 0
1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1
N + 18
N+2
N+4
N+6
N+8
N–8
N–6
N–4
N–2
N
N + 10
N + 12
N + 14
N + 16
N + 20
N + 22
N + 24
N – 25
N – 23
N – 21
N – 19
N – 17
N – 15
N – 13
N – 10
SAMPLE FREQUENCY (GHz)
OUTPUT CODE
Figure 30. SNR/SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz Figure 33. Input Referred Noise Histogram
3.0 6
2.5 4
POWER DISSIPATION (W)
2.0 2
INL (LSB)
1.5 0
0.5 –4
15550-434
15550-431
0 –6
1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 0 2000 4000 6000 8000 10000 12000 14000 16000
SAMPLE FREQUENCY (GHz) OUTPUT CODE
Figure 31. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz Figure 34. INL, fIN = 155 MHz
–3 0.8
–4
0.6
–5
–6 0.4
–7
AMPLITUDE (dB)
0.2
–8
DNL (LSB)
–9 0
–10
–0.2
–11
–12 –0.4
–13
–0.6
–14
15550-435
–15 –0.8
15550-232
Figure 32. Input Bandwidth (See Figure 80 for the Input Configuration) Figure 35. DNL, fIN = 155 MHz
AMPLITUDE (dB)
AMPLITUDE (dB)
–45 –45
–60 –60
–75 –75
–90 –90
–105 –105
–120 –120
15550-106
0 150M 300M 450M 600M 750M 900M 1.05G 1.20G 0 150M 300M 450M 600M 750M 900M 1.05G 1.20G
15550-109
fIN (Hz)
Figure 36. Single-Tone FFT at fIN = 155 MHz Figure 39. Single-Tone FFT at fIN = 905 MHz
0 0
AIN = –2dBFS AIN = –2dBFS
SNR = 62.5dBFS SNRFS = 59.7dB
SFDR = 78dBFS –15 SFDR = 73dBFS
–20 ENOB = 10.4 BITS ENOB = 9.6 BITS
NSD = –153.6dBFS/Hz NSD = –150.8dBFS/Hz
–30
BUFFER CURRENT = 300µA BUFFER CURRENT = 500µA
–40
AMPLITUDE (dB)
AMPLITUDE (dB)
–45
–60 –60
–75
–80
–90
–105
–120 –120
0 150M 300M 450M 600M 750M 900M 1.05G 1.20G 0 150M 300M 450M 600M 750M 900M 1.05G 1.20G
15550-107
15550-110
fIN (Hz) fIN (Hz)
Figure 37. Single-Tone FFT at fIN = 155 MHz, Full-Scale Voltage = 2.04 V p-p Figure 40. Single-Tone FFT at fIN = 1807 MHz
0 0
AIN = –2dBFS AIN = –2dBFS
SNRFS = 61.0dB SNRFS = 59.3dB
–15 SFDR = 73dBFS –15
SFDR = 73dBFS
ENOB = 10.1 BITS ENOB = 9.5 BITS
–30 NSD = –152.1dBFS/Hz –30 NSD = –150.4dBFS/Hz
BUFFER CURRENT = 300µA BUFFER CURRENT = 500µA
–45
AMPLITUDE (dB)
AMPLITUDE (dB)
–45
–60
–60
–75
–75
–90
–90
–105
–105
–120
15550-111
–120 –135
0 150M 300M 450M 600M 750M 900M 1.20G
15550-108
SNR/SFDR (dBFS)
–45
60
–60 55
50 300µA, SFDR
–75 300µA, SNR
500µA, SFDR
45
–90 500µA, SNR
700µA, SFDR
40
700µA, SNR
–105
35
–120 30
0 150M 300M 450M 600M 750M 900M 1.05G 1.20G
15550-112
355
2955
155
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
3155
2755
3355
3555
3755
3955
fIN (Hz)
15550-115
INPUT FREQUENCY (MHz)
Figure 42. Single-Tone FFT at fIN = 3300 MHz Figure 45. SNR/SFDR vs. Input Frequency (fIN) for Various Buffer Currents
0 –45
AIN = –2dBFS
SNRFS = 54.0dB
–15 SFDR = 60dBFS –50
ENOB = 8.2 BITS
–30 NSD = –145.1dBFS/Hz 300µA
BUFFER CURRENT = 700µA –55 500µA
700µA
AMPLITUDE (dB)
–45
HD2 (dBFS)
–60
–60
–65
–75
–70
–90
–105 –75
–120 –80
15550-113
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
2955
3155
2755
3355
3555
3755
3955
fIN (Hz)
15550-116
INPUT FREQUENCY (MHz)
Figure 43. Single-Tone FFT at fIN = 4350 MHz; Full-Scale Voltage = 1.1 V p-p Figure 46. Second Harmonics (HD2) vs. Input Frequency (fIN) for Various
Buffer Currents
0 –40
AIN = –2dBFS
SNRFS = 53.0dB –45
–15 SFDR = 59dBFS
ENOB = 7.9 BITS –50
–30 NSD = –144.1dBFS/Hz 300µA
BUFFER CURRENT = 700µA 500µA
–55
700µA
AMPLITUDE (dB)
–45
–60
HD3 (dBFS)
–60 –65
–75 –70
–75
–90
–80
–105
–85
–120 –90
15550-114
555
755
955
1155
1355
1555
1755
1955
2155
2355
2555
2955
3155
2755
3355
3555
3755
3955
fIN (Hz)
15550-117
Figure 44. Single-Tone FFT at fIN = 5400 MHz; Full-Scale Voltage = 1.1 V p-p Figure 47. Third Harmonics (HD3) vs. Input Frequency (fIN) for Various Buffer
Currents
–40
–40
AMPLITUDE (dB)
–50
–60
–60
–70
–80
–80
–90
–100
–100 –110
–120
–120 –130
15550-121
15550-118
0 160 320 480 640 800 960 1120 1280 –122.88 –92.16 –61.44 –30.72 0 30.72 61.44 92.16 122.88
FREQUENCY (MHz) FREQUENCY (MHz)
Figure 48. Two-Tone FFT; fIN1 = 1841 MHz, fIN2 = 1846 MHz; Figure 51. Two-Tone FFT; fIN1 = 1846.5 MHz, fIN2 = 2142.5 MHz
AIN1 and AIN2 = −8 dBFS fCLK = 2.4576 GHz; Decimation Ratio = 10, NCO Frequency = 2140 MHz
0 0
AIN1 AND AIN2 = –8dBFS IMD3 (dBc)
SFDR = 76dBFS –10 IMD3 (dBFS)
IMD2 = 78dBFS SFDR (dBc)
–20 –20 SFDR (dBFS)
IMD3 = 76dBFS
BUFFER CURRENT = 700µA –30
–40 –40
–50
–60
–60
–70
–80
–80
–90
–100
–100
–110
–120
–120 –130
15550-122
0 160 320 480 640 800 960 1120 1280 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
15550-119
Figure 49. Two-Tone FFT; fIN1 = 2137 MHz, fIN2 = 2142 MHz; Figure 52. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
AIN1 and AIN2 = −8 dBFS fIN1 = 1841.5 MHz, fIN2 = 1846.5 MHz
0 0
AIN1 AND AIN2 = –8dBFS IMD3 (dBc)
–10 NCO FREQUENCY = 1.84GHz –10 IMD3 (dBFS)
SFDR = 77dBFS SFDR (dBc)
–20 –20 SFDR (dBFS)
BUFFER CURRENT = 700µA
–30 –30
SFDR/IMD3 (dBc AND dBFS)
–40 –40
AMPLITUDE (dB)
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
15550-123
15550-120
–122.88 –92.16 –61.44 –30.72 0 30.72 61.44 92.16 122.88 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
FREQUENCY (MHz) INPUT AMPLITUDE (dBFS)
Figure 50. Two-Tone FFT; fIN1 = 1846.5 MHz, fIN2 = 2142.5 MHz Figure 53. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fCLK = 2.4576 GHz; Decimation Ratio = 10, NCO Frequency = 1840 MHz fIN1 = 2137.5 MHz, fIN2 = 2142.5 MHz
70
60
2.5
50
POWER (W)
40
2.0
30
20
1.5
10
0 1.0
–10
SNR (dBc)
–20 SNR (dBFS) 0.5
–30 SFDR (dBc)
SFDR (dBFS)
–40 0
15550-124
15550-127
–90 –82 –74 –66 –58 –50 –42 –34 –26 –18 –10 –2 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
INPUT AMPLITUDE (dBFS) JUNCTION TEMPERATURE (°C)
Figure 54. SNR/SFDR vs. Input Amplitude (AIN), fIN = 900 MHz Figure 57. Power vs. Junction Temperature (TJ), fIN = 900 MHz
110 63
0.2V 1.2V
100 0.3V 1.8V
90 61 0.5V 2.0V
0.8V
80
59
SNR/SFDR (dBc AND dBFS)
70
60
57
50
SNR (dBFS)
40
55
30
20
53
10
0 51
–10
SNR (dBc)
–20 SNR (dBFS) 49
–30 SFDR (dBc)
SFDR (dBFS)
–40 47
15550-125
–90 –82 –74 –66 –58 –50 –42 –34 –26 –18 –10 –2 155.3 655.3 1155.3 1655.3 2155.3 2655.3 3155.3 3655.3
15550-128
INPUT AMPLITUDE (dBFS) ANALOG INPUT FREQUENCY (MHz)
Figure 55. SNR/SFDR vs. Input Amplitude (AIN), fIN = 1800 MHz Figure 58. SNR vs. Analog Input Frequency (fIN) for Various Clock Amplitude
in Differential Peak-to-Peak Voltages
75 90
SNR
SFDR
80
70
70
60
SNR/SFDR (dBFS)
SNR/SFDR (dBFS)
65
50
40
60
30
55 20
10
SNR
SFDR
50 0
15550-126
15550-129
–10 0 10 20 30 40 50 60 70 80 90 100 110 120 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
JUNCTION TEMPERATURE (°C) SAMPLE FREQUENCY (MHz)
Figure 56. SNR/SFDR vs. Junction Temperature (TJ), fIN = 900 MHz Figure 59. SNR/SFDR vs. Sample Frequency (fS), fIN = 900 MHz
60 300000
SNR/SFDR (dBFS)
NUMBER OF HITS
50 250000
40 200000
30 150000
20 100000
10 50000
SNR
SFDR
0 0
15550-130
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
N – 25
N – 23
N – 21
N – 19
N – 17
N – 15
N – 13
N – 10
N–8
N–6
N–4
N–2
N+2
N+4
N+6
N+8
N + 10
N + 12
N + 14
N + 16
N + 18
N + 20
N + 22
N + 24
N
15550-133
SAMPLE FREQUENCY (MHz)
OUTPUT CODE
Figure 60. SNR/SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz Figure 63. Input Referred Noise Histogram
3.5 6
5
3.0
4
POWER DISSIPATION (W)
2.5 3
INL (LSB) 2
2.0
AVDD1 POWER/AVDD2 POWER/AVDD3 POWER 1
DRVDD1 POWER/DRVDD2 POWER
1.5 DVDD POWER/SPIVDD POWER 0
TOTAL POWER
–1
1.0
–2
0.5
–3
0 –4
15550-135
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 0 2000 4000 6000 8000 10000 12000 14000 16000
15550-131
Figure 61. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz Figure 64. INL, fIN = 155 MHz
–3 0.8
–4
0.6
–5
–6
0.4
DNL (LSB)
–7
AMPLITUDE (dB)
–8 0.2
–9
–10 0
–11
–0.2
–12
–13
–0.4
–14
–15 –0.6
15550-232
15550-134
100 2100 4100 6100 8100 10100 12100 0 2000 4000 6000 8000 10000 12000 14000 16000
FREQUENCY (MHz) OUTPUT CODE
Figure 62. Input Bandwidth (See Figure 80 for the Input Configuration) Figure 65. DNL, fIN = 155 MHz
EQUIVALENT CIRCUITS
AVDD1_SR
100Ω 10kΩ
AVDD3 AVDD3 SYSREF+
VIN+x 1.9pF
0.3pF 130kΩ
100Ω
AVDD3
LEVEL
TRANSLATOR VCM = 0.65V
VCM
BUFFER
100Ω
AVDD3 AVDD3 130kΩ
AVDD1_SR
VIN–x
100Ω 10kΩ
0.3pF SYSREF–
AIN
CONTROL
15550-039
(SPI)
15550-037
1.9pF
AVDD1 EMPHASIS/SWING
CONTROL (SPI)
CLK+ DRVDD1
DATA+ SERDOUTx+
x = 0, 1, 2, 3, 4, 5, 6, 7
106Ω
OUTPUT DRGND
AVDD1 DRIVER DRVDD1
DATA– SERDOUTx–
CLK– 16kΩ 16kΩ
15550-038
15550-040
x = 0, 1, 2, 3, 4, 5, 6, 7
VCM = 0.65V
DRGND
DRVDD1 SPIVDD
ESD
PROTECTED
100Ω 10kΩ
SYNCINB+ 56kΩ DGND
ESD
PROTECTED
1.9pF
15550-042
DGND
130kΩ
DRGND DGND
DRGND
Figure 71. SCLK Input
LEVEL
TRANSLATOR VCM = 0.65V
130kΩ
DRVDD1
100Ω 10kΩ
SYNCINB–
1.9pF
15550-041
DRGND DRGND
CSB PDWN/STBY
15550-046
15550-043
DGND
DGND DGND
SPIVDD SPIVDD
ESD
PROTECTED SDI
15550-047
DGND DGND AGND VREF PIN
DGND CONTROL (SPI)
SPIVDD SPIVDD
ESD
PROTECTED NCO BAND SELECT
DGND
FD_A/GPIO_A0,
FD_B/GPIO_B0 SPIVDD
FD
56kΩ
JESD204B LMFC
ESD
PROTECTED JESD204B SYNC~
DGND DGND
DGND
15550-045
SPIVDD
ESD
SPIVDD
PROTECTED NCO BAND SELECT
SDI
GPIO_A1/GPIO_B1
DGND
DGND
15550-247
GPIO_A1/GPIO_B1
PIN CONTROL (SPI)
THEORY OF OPERATION
The AD9689 has two analog input channels and up to eight Either a differential capacitor or two single-ended capacitors (or
JESD204B output lane pairs. The ADC samples wide bandwidth a combination of both) can be placed on the inputs to provide a
analog signals of up to 5 GHz. The actual −3 dB roll-off of the matching passive network. These capacitors ultimately create a
analog inputs is 9 GHz. The AD9689 is optimized for wide input low-pass filter that limits unwanted broadband noise. For more
bandwidth, high sampling rate, excellent linearity, and low information, refer to the Analog Dialogue article, “Transformer-
power in a small package. Coupled Front-End for Wideband A/D Converters” (Volume 39,
The dual ADC cores feature a multistage, differential pipelined April 2005). In general, the precise front-end network
architecture with integrated output error correction logic. Each component values depend on the application.
ADC features wide bandwidth inputs supporting a variety of Figure 78 shows the differential input return loss curve for the
user-selectable input ranges. An integrated voltage reference analog inputs across a frequency range of 100 MHz to 10 GHz.
eases design considerations. The reference impedance is 100 Ω.
1.0
The AD9689 has several functions that simplify the AGC
function in a communications receiver. The programmable 2.0
0.5
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input m5
signal level exceeds the programmable threshold, the fast detect m4
0.2 5.0
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input. m3 m1
SDD11
0 0
The Subclass 1 JESD204B-based high speed serialized output data
lanes can be configured in one-lane (L = 1), two-lane (L = 2), m2
four-lane (L = 4), and eight-lane (L = 8) configurations, depending
–0.2 –5.0
on the sample rate and the decimation ratio. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins. The SYSREF± pin in the AD9689 can
also be used as a timestamp of data as it passes through the –0.5 –2.0
15550-248
FREQUENCY = 3GHz
buffer is optimized for high linearity, low noise, and low power SDD11 = 0.496/175.045
IMPEDANCE = Z 0 × (0.337 – j0.038)
15550-249
NOTES:
transformer network (see Figure 79 and Table 9) is recommended 1. SEE TABLE 9 FOR COMPONENT VALUES
for optimum performance of the AD9689. Figure 79. Differential Transformer Coupled Configuration for the AD9689
25Ω
MARKI 200Ω
BAL-0009 ADC
0.1µF
25Ω
25Ω 10Ω
15550-250
0.1µF
0.25
1. Set Register 0x1908, Bit 2 to disconnect the internal
common-mode buffer from the analog input. Note that 0.24
this is a local register.
0.17
Figure 81 shows the block diagram of a dc-coupled application.
15550-253
400 500 600 700
BUFFER CURRENT SETTING (µA)
ADC
Figure 83. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1
AMP A ADC
Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)
VOCM
VREF Table 10 shows the recommended values for the buffer current
for various Nyquist zones.
VOCM
VCM EXPORT SELECT
SPI REGISTERS 0x1908, Table 10. SFDR Optimization for Input Frequencies
15550-251
100Ω
REG 1
N/A means not applicable.
(0x0008, AVDD3
AVDD3 0x1908)
VIN–x
0.3pF
REG (0x0008, 0x1A4C,
0x1A4D, 0x1910)
15550-252
15550-256
–10 10 30 50 70 90 110 130
JUNCTION TEMPERATURE (°C)
The SPI Register 0x18A6 enables the user to either use this
internal 0.5 V reference, or to provide an external 0.5 V Figure 84. Typical Reference Voltage (VREF) Drift
reference. When using an external voltage reference, provide a The external reference must be a stable 0.5 V reference. The
0.5 V reference. The full-scale adjustment is made using the SPI, ADR130 is a sufficient option for providing the 0.5 V reference.
irrespective of the reference voltage. For more information on Figure 86 shows how the ADR130 can be used to provide the
adjusting the full-scale level of the AD9689, refer to the Memory external 0.5 V reference to the AD9689. The dashed lines show
Map section. unused blocks within the AD9689 while using the ADR130 to
provide the external reference.
VIN+A/VIN+B
VIN–A/VIN–B
INTERNAL ADC
0.5V INPUT CORE
REFERENCE FULL-SCALE
GENERATOR ADJUST
INPUT FULL-SCALE
VREF RANGE ADJUST
SPI REGISTER
(0x1910)
VREF PIN
CONTROL SPI
REGISTER
15550-254
(0x18A6)
0.1µF 0.1µF
VREF PIN
AND VFS
15550-255
CONTROL
SDD11
m2
distinguish between the source of dc signals, this feature can be 0
m1
0
Figure 87 shows the differential input return loss curve for the m1 m4
FREQUENCY = 2.001GHz FREQUENCY = 4.001GHz
clock inputs across a frequency range of 100 MHz to 6 GHz. SDD11 = 0.274/–156.496 SDD11 = 0.360/139.617
IMPEDANCE = Z 0 × (0.586 – j0.139) IMPEDANCE = Z 0 × (0.518 + j0.278)
The reference impedance is 100 Ω. m2 m5
FREQUENCY = 2.602GHz FREQUENCY = 5.202GHz
SDD11 = 0.319/–176.549 SDD11 = 0.364/139.617
IMPEDANCE = Z 0 × (0.516 – j0.022) IMPEDANCE = Z 0 × (0.761 + j0.639)
m3
15550-257
FREQUENCY = 2.996GHz
SDD11 = 0.337/169.383
IMPEDANCE = Z 0 × (0.499 – j0.070)
Figure 87. Differential Input Return Loss for the CLK± Inputs
15550-258
1:2Z
CLK– CLOCK CLOCK
INPUT INPUT
15550-261
CLKOUT– CLK–
Figure 88. Transformer-Coupled Differential Clock
Another option is to ac couple a differential LVPECL or CML Figure 91. DAC Clock Output Clocking the AD9689
signal to the sample clock input pins, as shown in Figure 89 and
Figure 90, respectively.
CLK+
LVDS 100Ω ADC
DRIVER DIFFERENTIAL CLOCK
TRACE INPUT
CLK–
150Ω 150Ω
15550-259
CLK+
CML ADC
DRIVER CLOCK
INPUT
CLK–
15550-260
DIFFERENTIAL
TRACE
15550-263
a multiple of the sample clock, take care to program the appropriate
divider ratio into the clock divider before applying the clock Figure 93. Clock Divider Phase and Delay Controls
signal; this ensures that the current transients during device
The clock delay adjustment takes effect immediately when it is
startup are controlled.
enabled via SPI writes. Enabling the clock fine delay adjust in
REG 0x011C,
0x011E Register 0x0110 causes a datapath reset. However, the contents
CLK+ of Register 0x0111 and Register 0x0112 can be changed without
affecting the stability of the JESD204B link.
÷2
CLK–
Clock Coupling Considerations
÷4
The AD9689 has many different domains within the analog
15550-262
220Ω AT
The input clock divider in the AD9689 provides phase delay in 100MHz
DCR ≤ 0.5Ω A4 B4
increments of ½ the input clock cycle. Program Register 0x0109
100nF
to enable this delay independently for each channel. Changing 10Ω
this register does not affect the stability of the JESD204B link.
AVDD1
Clock Fine Delay and Superfine Delay Adjust PLANE
of Register 0x0110 enable the selection of the fine delay, or the 220Ω AT
100MHz
fine delay with superfine delay. The fine delay allows the user to DCR ≤ 0.5Ω A11 B11
100nF
15550-264
delay the clock edges with 16-step or 192-step delay options. 10Ω
The superfine delay is an unsigned control to adjust the clock
delay in superfine steps of 0.25 ps each. Figure 94. Q Factor Reduction Network Recommendation for the Clock
Domain Supply
Rev. A | Page 34 of 134
Data Sheet AD9689
63
Clock Jitter Considerations 62
61
High speed, high resolution ADCs are sensitive to the quality of
60
the clock input. Calculate the degradation in SNR at a given 59
58
input frequency (fA) due only to aperture jitter (tJ) by 57
56
SNRJITTER = −20 × log10 (2 × π × fA × tJ)
SNR (dBFS)
55
54
In this equation, the rms aperture jitter represents the root 53
mean square of all jitter sources, including the clock input, 52 25fS
51 50fS
analog input signal, and ADC aperture jitter specifications. 50 75fS
49 100 fS
Intermediate frequency (IF) undersampling applications are 48 125 fS
150 fS
particularly sensitive to jitter (see Figure 95). 47
175 fS
46
130 200 fS
45
12.5fS
15550-166
10M 100M 1G 10G
120 25fS
INPUT FREQUENCY (Hz)
50fS
110 100fS Figure 96. Estimated SNR Degradation vs. Input Frequency and RMS Jitter
200fS
100 for the 2.6 GSPS
400fS
800fS
IDEAL SNR (dB)
10 100 1000 10000 In standby mode, the JESD204B link is not disrupted and transmits
ANALOG INPUT FREQUENCY (MHz)
zeros for all converter samples. Change this transmission using
Figure 95. Ideal SNR vs. Analog Input Frequency and Jitter Register 0x0571, Bit 7 to select /K/ characters.
Treat the clock input as an analog signal when aperture jitter TEMPERATURE DIODE
may affect the dynamic range of the AD9689. Separate power
The AD9689 contains diode-based temperature sensors. The
supplies for clock drivers from the ADC output driver supplies
diodes output voltages commensurate to the temperature of the
to avoid modulating the clock signal with digital noise. If the
silicon. There are multiple diodes on the die, but the results
clock is generated from another type of source (by gating,
established using the temperature diode at the central location
dividing, or other methods), retime the clock by the original clock
of the die can be regarded as representative of the entire die.
at the last step. Refer to the AN-501 Application Note and the
However, in applications where only one channel is used (the
AN-756 Application Note for more information about jitter
other channel being in a power-down state), it is recommended
performance as it relates to ADCs.
to read the temperature diode corresponding to the channel
Figure 96 shows the estimated SNR of the AD9689 across input that is on. Figure 97 shows the locations of the diodes in the
frequency for different clock induced jitter values. Estimate the AD9689 with voltages that can be output to the VREF pin. In
SNR by using the following equation: each location, there is a pair of diodes, one of which is 20× the
−SNR ADC − SNR JITTER size of the other. It is recommended to use both diodes in a
10 10 location to obtain an accurate estimate of the die temperature.
SNR (dBFS) = −10log10 10 + 10
For more information, see the AN-1432 Application Note.
ADC
ADC ADC
A B
JESD204B DRIVER
CHANNEL A, CENTRAL,
CHANNEL B
Figure 97. Temperature Diode Locations in the Die
0.50
15550-269
CHANNEL A –40 –20 0 20 40 60 80 100
VREF CENTRAL
JUNCTION TEMPERATURE (°C)
CHANNEL B
Figure 99. Typical Voltage Response of the 1× Temperature Diode
TEMPERATURE DIODE
LOCATION SELECT the junction temperature in °C is shown in Figure 100.
SPI REGISTER (0x18E6)
150
Figure 98. Register Controls to Output Temperature Diode Voltage on the 140
VREF Pin 130
120
The SPI writes required to export the central temperature diode 110
100
are as follows (see Table 46 and Table 53 for more information): 90
80
1. Set Register 0x0008 to 0x03 to select both channels. 70
TJ (°C)
60
2. Set Register 0x18E3 to 0x00 to turn off VCM export. 50
3. Set Register 0x18A6 to 0x00 to turn off voltage reference 40
30
export. 20
10
4. Set Register 0x18E6 to 0x01 to turn on voltage export of 0
the central 1× temperature diode. The typical voltage –10
–20
response of the temperature diode is shown in Figure 99. –30
Although this voltage represents the die temperature, it is –40
15550-270
60 65 70 75 80 85 90 95 100 105 110
recommended to take measurements from a pair of diodes DELTA VOLTAGE (mV)
for improved accuracy. Step 5 explains how to enable the Figure 100. Junction Temperature vs. ΔV (mV)
20× diode.
5. Set Register 0x18E6 to 0x02 to turn on the second central
temperature diode of the pair, which is 20× the size of the
first. For the method using two diodes simultaneously to
achieve a more accurate result, see the AN-1432 Application
Note.
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER LOWER THRESHOLD
THRESHOLD
MIDSCALE
Figure 101. Threshold Settings for the FD_A and FD_B Signals
DDC 1
REAL/I REAL/I
I I
CONVERTER 2
REAL/Q Q
Q Q
I/Q CONVERTER 3 OUTPUT
CROSSBAR INTERFACE
MUX DDC 2
REAL/I REAL/I
I I
CONVERTER 4
REAL/Q Q
Q Q
CONVERTER 5
ADC B DDC 3
REAL/Q REAL/I REAL/I
SAMPLING I I
CONVERTER 6
15550-066
AT fS REAL/Q Q
Q Q
CONVERTER 7
DIGITAL DOWNCONVERSION
M=2
I
CONVERTER 0
DIGITAL JESD204B
REAL REAL DOWN
ADC Tx L LANES
CONVERSION
Q
CONVERTER 1
SIGNAL JESD204B
PROCESSING INTERFACE
BLOCKS
15550-274
CORE xyQ [n]
SIGNAL JESD204B
PROCESSING INTERFACE
BLOCKS
CORE
24-TAP FIR
FILTER
yI [n]
SIGNAL
PROCESSING JESD204B
BLOCKS INTERFACE
24-TAP FIR
FILTER
yQ [n]
15550-276
CORE xQ [n] DOUTQ [n]
48-TAP FIR
FILTER
xyI [n]
SIGNAL
PROCESSING JESD204B
BLOCKS INTERFACE
+
Q (IMAG) DINQ [n] 48-TAP FIR + DOUTQ [n]
ADC B FILTER Q′ (IMAG)
15550-277
CORE xyQ [n]
24-TAP FIR
FILTER
yI [n]
SIGNAL JESD204B
PROCESSING INTERFACE
BLOCKS
24-TAP FIR
FILTER
yQ [n]
+
Q (IMAG) 24-TAP FIR + DOUTQ [n]
ADC B FILTER Q′ (IMAG)
15550-278
1
XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.
2
When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
1
XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n.
2
When using the I path in half complex, 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
The DDCs output a 16-bit stream. To enable this operation, the • Frequency translation stage (optional)
converter number of bits, N, is set to a default value of 16, even • Filtering stage
though the analog core only outputs 14 bits. In full bandwidth • Gain stage (optional)
operation, the ADC outputs are the 14-bit word followed by two • Complex to real conversion stage (optional)
zeros, unless the tail bits are enabled.
DDC Frequency Translation Stage (Optional)
DDC I/Q INPUT SELECTION This stage consists of a phase coherent NCO and quadrature
The AD9689 has two ADC channels and four DDC channels. mixers that can be used for frequency translation of both real or
Each DDC channel has two input ports that can be paired to complex input signals. The phase coherent NCO allows an
support both real and complex inputs through the I/Q crossbar infinite number of frequency hops that are all referenced back
mux. For real signals, both DDC input ports must select the to a single synchronization event. It also includes 16 shadow
same ADC channel (that is, DDC Input Port I = ADC Channel A registers for fast switching applications. This stage shifts a
and DDC Input Port Q = ADC Channel A). For complex portion of the available digital spectrum down to baseband.
signals, each DDC input port must select different ADC DDC Filtering Stage
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B). After shifting down to baseband, this stage decimates the
frequency spectrum using multiple low-pass finite impulse
The inputs to each DDC are controlled by the DDC input selec- response (FIR) filters for rate conversion. The decimation
tion registers (Register 0x0311, Register 0x0331, Register 0x0351, process lowers the output data rate, which in turn reduces the
and Register 0x0371). See Table 48 and Table 50 for information output interface rate.
on how to configure the DDCs.
DDC Gain Stage (Optional)
DDC I/Q OUTPUT SELECTION
Because of losses associated with mixing a real input signal
Each DDC channel has two output ports that can be paired to down to baseband, this stage compensates by adding an
support both real and complex outputs. For real output signals, additional 0 dB or 6 dB of gain.
only the DDC Output Port I is used (the DDC Output Port Q is
DDC Complex to Real Conversion Stage (Optional)
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used. When real outputs are necessary, this stage converts the
complex outputs back to real by performing an fS/4 mixing
The I/Q outputs to each DDC channel are controlled by the
operation plus a filter to remove the complex component of the
DDCx complex to real enable bit, Bit 3, in the DDCx control
signal.
registers (Register 0x0310, Register 0x0330, Register 0x0350,
and Register 0x0370). Figure 109 shows the detailed block diagram of the DDCs
implemented in the AD9689.
The chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels. Figure 110 shows an example usage of one of the four DDC
When all DDC channels use real outputs, set this bit high to channels with a real input signal and four half-band filters
ignore all DDC Q output ports. When any of the DDC channels (HB4 + HB3 + HB2 + HB1) used. It shows both complex
are set to use complex I/Q outputs, the user must clear this bit (decimate by 16) and real (decimate by 8) output options.
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 126.
CONVERSION (OPTIONAL)
REAL/I I REAL/I
COMPLEX TO REAL
CONVERTER 0
GAIN = 0 OR +6dB
NCO
+ DECIMATION
MIXER FILTERS
(OPTIONAL)
REAL/I Q Q CONVERTER 1
REAL/I ADC A
SAMPLING
AT fS DDC 1
CONVERSION (OPTIONAL)
REAL/I I REAL/I
COMPLEX TO REAL
CONVERTER 2
GAIN = 0 OR +6dB
NCO
+ DECIMATION
LANES
AT UP TO
16Gbps
DDC 2
CONVERSION (OPTIONAL)
REAL/I I REAL/I
COMPLEX TO REAL
CONVERTER 4
GAIN = 0 OR +6dB
NCO
+ DECIMATION
MIXER FILTERS
(OPTIONAL)
REAL/I Q Q CONVERTER 5
REAL/Q ADC B
SAMPLING DDC 3
AT fS
CONVERSION (OPTIONAL)
REAL/I I REAL/I
COMPLEX TO REAL
CONVERTER 6
GAIN = 0 OR +6dB
NCO
+ DECIMATION
MIXER FILTERS
(OPTIONAL)
REAL/I Q Q CONVERTER 7
SYSREF±
PIN SYNCHRONIZATION SYSREF SYSREF
CONTROL CIRCUITS
DCM = DECIMATION
REGISTER MAP
CONTROLS
NCO CHANNEL NCO CHANNEL SELECTION
15550-053
GPIO PINS SELECTION
CIRCUITS
–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2
BANDWIDTH OF
INTEREST IMAGE
DIGITAL FILTER BANDWIDTH OF INTEREST (–6dB LOSS DUE TO
RESPONSE (–6dB LOSS DUE TO NCO + MIXER)
NCO + MIXER)
–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2
FILTERING STAGE
HB4 FIR HB3 FIR HB2 FIR HB1 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1) HALF- HALF- HALF- HALF-
BAND BAND BAND BAND
I FILTER 2 FILTER 2 FILTER FILTER I
2
+6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
15550-054
–fS/32 fS/32
–fS/8 –fS/16 DC fS/16 fS/8
cos(ωt)
ADC + DIGITAL MIXER + NCO REAL ADC REAL 48-BIT 90°
SAMPLING COMPLEX
REAL INPUT—SAMPLED AT fS AT fS
NCO 0°
–sin(ωt)
Q
BANDWIDTH OF BANDWIDTH OF
INTEREST IMAGE INTEREST
–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2
–fS/32 fS/32
DC
–fS/32 fS/32
DC
–sin(ωt)
MIXER + NCO REAL 90° 48-BIT 90°
PHASE NCO 0° COMPLEX
COMPLEX INPUT—SAMPLED AT fS Q
I
Q ADC Q Q
I +
Q
SAMPLING
+
AT fS
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/32 fS/32
–fS/2 –fS/3 –fS/4 –fS/8 –fS/16 DC fS/16 fS/8 fS/4 fS/3 fS/2
–fS/32 fS/32
15550-056
DC
NCO NCO
CHANNEL NCO CHANNEL
SELECTION SELECTION
CIRCUITS
48-BIT
0 FTW/POW 0
48-BIT
1 FTW/POW 1 COHERENT
REGISTER FTW/POW COS/SIN
PHASE
MAP ACCUMULATOR GENERATOR
BLOCK
15 48-BIT
FTW/POW FTW/POW
15
WRITE INDEX
–sin(x)
cos(x)
SYNCHRONIZATION SYSREF
CONTROL CIRCUITS
I I
I/O
CROSSBAR DECIMATION
MUX Q Q FILTERS
DIGITAL
QUADRATURE
FTW = FREQUENCY TUNING WORD MIXER
POW = PHASE OFFSET WORD
15550-283
• 48-bit twos complement number entered in the FTW. Note that Equation 1 to Equation 4 apply to the aliasing of
signals in the digital domain (that is, aliasing introduced when
• 48-bit unsigned number entered in the MAW.
digitizing analog signals).
• 48-bit unsigned number entered in the MBW.
M and N are integers reduced to their lowest terms. MAW and
Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are MBW are integers reduced to their lowest terms. When MAW is
represented using the following values: set to zero, the programmable modulus logic is automatically
• FTW = 0x8000 0000 0000 and MAW = 0x0000 0000 0000 disabled.
represents a frequency of −fS/2. For example, if the ADC sampling frequency (fS) is 2600 MSPS
• FTW = 0x0000 0000 0000 and MAW = 0x0000 0000 0000 and the carrier frequency (fC) is 1001.5 MHz, then
represents dc (frequency is 0 Hz).
mod(1001.5, 2600) M 2003
• FTW = 0x7FFF FFFF FFFF and MAW = 0x0000 0000 0000 = =
represents a frequency of +fS/2. 2600 N 5200
NCO CHANNEL
IN SELECTION
GPIO IN
[3:0] GPIO
CMOS
PINS SELECTION
IN
IN
[0] NCO CHANNEL SELECTION
MUX COUNTER NCO
INC
f0 f1 f2
ACTIVE
DDC
B1 B2
B0
Figure 115. NCO Coherent Mode with Three NCO Channels (B0 Selected)
SYSREF±
CLOCK
DEVICE_CLOCK± GENERATION
15550-286
CONFIGURE MASTER
AND SLAVE DEVICES ENABLE TRIGGER IN SYSTEM SYSREF
MASTER DEVICES SNTI SET HIGH SYNCHRONIZATION IGNORED
MNTO SET HIGH ACHIEVED
DEVICE
CLOCK
SYSREF
MNTO
BOARD PROPAGATION
DELAY
SNTI
INPUT DELAY
NSTE
LMFC
SYNCHRONIZED
LMFCs DON’T CARE
NCO
SYNCHRONIZED
MNTO = MASTER NEXT TRIGGER OUTPUT (CMOS)
SNTI = SLAVE NEXT TRIGGER INPUT (CMOS)
NSTE = NEXT SYNCHRONIZATION TRIGGER ENABLE
15550-287
Figure 117. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF)
FB2
FIR
(OPTIONAL)
I I I I
NCO
AND
MIXERS DCM = 5
(OPTIONAL)
Q FB2 Q Q Q
FIR
TB2
FIR
DCM = 3
HB4 HB3 HB2 HB1
FIR FIR FIR FIR
Q Q Q Q Q
DCM = 2 DCM = 2 DCM = 2 DCM = 2
TB1
Q FIR
DCM = 3
NOTES
1. TB1 IS ONLY SUPPORTED IN DDC0 AND DDC1
MAGNITUDE (dB)
filter is only used when complex outputs (decimate by 16) or
–60
real outputs (decimate by 8) are enabled; otherwise, it is
bypassed. Table 18 and Figure 119 show the coefficients and –80
15550-290
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
C2, C10 0 0 NORMALIZED FREQUENCY (× Π RAD/s)
–40
Table 20 and Figure 121 show the coefficients and response of
MAGNITUDE (dB)
–80
Table 20. HB2 Filter Coefficients
HB2 Coefficient Normalized Decimal Coefficient
–100
Number Coefficient (18-Bit)
–120 C1, C19 0.000671 88
–140 C2, C18 0 0
C3, C17 −0.005325 −698
–160
C4, C16 0 0
15550-289
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED FREQUENCY (× Π RAD/s) C5, C15 0.022743 2981
Figure 119. HB4 Filter Response C6, C14 0 0
HB3 Filter Description C7, C13 −0.074181 −9723
The second decimate by 2, half-band, low-pass, FIR filter (HB3) C8, C12 0 0
uses an 11-tap, symmetrical, fixed coefficient filter implementa- C9, C11 0.306091 40120
tion that is optimized for low power consumption. The HB3 C10 0.5 65536
20
filter is only used when complex outputs (decimate by 8 or 16)
or real outputs (decimate by 4 or 8) are enabled; otherwise, it is 0
bypassed. Table 19 and Figure 120 show the coefficients and –20
response of the HB3 filter.
–40
MAGNITUDE (dB)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
C6 0.500000 32768 NORMALIZED FREQUENCY (× Π RAD/s)
MAGNITUDE (dB)
The HB1 filter is always enabled and cannot be bypassed.
–60
Table 21 and Figure 122 show the coefficients and response of
the HB1 filter. –80
–100
Table 21. HB1 Filter Coefficients
HB1 Coefficient Normalized Decimal Coefficient –120
Number Coefficient (20-Bit) –140
C1, C63 −0.000019 −10
–160
C2, C62 0 0
15550-292
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
C3, C61 0.000072 38 NORMALIZED FREQUENCY (× Π RAD/s)
–60
–80
–100
–120
–140
–160
15550-293
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
NORMALIZED FREQUENCY (× Π RAD/s)
MAGNITUDE (dB)
filter response. TB1 is only supported in DDC0 and DDC1.
–60
15550-294
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
5, 72 0.000291 1220 NORMALIZED FREQUENCY (× Π RAD/s)
MAGNITUDE (dB)
filter response.
–60
Table 24. FB2 Filter Coefficients –80
FB2 Coefficient Normalized Decimal Coefficient
–100
Number Coefficient (21-Bit)
1, 48 0.000007 7 –120
2, 47 −0.000004 −4 –140
3, 46 −0.000069 −72
–160
4, 45 −0.000244 −256
15550-295
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
5, 44 −0.000544 −570 NORMALIZED FREQUENCY (× Π RAD/s)
0dB I
OR
6dB
cos(ωt)
90° REAL
fS/4
0°
–
sin(ωt)
0dB Q
OR
6dB
LOW-PASS
Q FILTER 0dB Q Q
2 OR
6dB
15550-057
HB1 FIR
Table 25. Sample Mapping When the Chip Decimation Ratio (DCM) Does Not Match DDC DCM
Sample Index DDC DCM = Chip DCM DDC DCM = 2 × Chip DCM DDC DCM = 4 × Chip DCM DDC DCM = 8 × Chip DCM
0 N N N N
1 N+1 N N N
2 N+2 N+1 N N
3 N+3 N+1 N N
4 N+4 N+2 N+1 N
5 N+5 N+2 N+1 N
6 N+6 N+3 N+1 N
7 N+7 N+3 N+1 N
8 N+8 N+4 N+2 N+1
9 N+9 N+4 N+2 N+1
10 N + 10 N+5 N+2 N+1
11 N + 11 N+5 N+2 N+1
12 N + 12 N+6 N+3 N+1
13 N + 13 N+6 N+3 N+1
14 N + 14 N+7 N+3 N+1
15 N + 15 N+7 N+3 N+1
16 N + 16 N+8 N+4 N+2
17 N + 17 N+8 N+4 N+2
18 N + 18 N+9 N+4 N+2
19 N + 19 N+9 N+4 N+2
20 N + 20 N + 10 N+5 N+2
21 N + 21 N + 10 N+5 N+2
22 N + 22 N + 11 N+5 N+2
23 N + 23 N + 11 N+5 N+2
24 N + 24 N + 12 N+6 N+3
25 N + 25 N + 12 N+6 N+3
26 N + 26 N + 13 N+6 N+3
27 N + 27 N + 13 N+6 N+3
28 N + 28 N + 14 N+7 N+3
29 N + 29 N + 14 N+7 N+3
30 N + 30 N + 15 N+7 N+3
31 N + 31 N + 15 N+7 N+3
Table 28. DDC Power Consumption for Example Configurations for 2.0 GSPS; fS = 2.0 GHz
Number of DDC Decimation Number of Number of Virtual Number of Octets DVDD Power (mW) DRVDD1 Power (mW)
DDCs Ratio 1 Lanes (L) Converters (M) per frame (F) Typ Max Typ Max
2 3 8 4 2 465 958 240 345
2 4 8 4 1 400 877 200 301
2 6 4 4 2 405 881 135 226
2 8 4 4 2 385 858 115 205
2 12 2 4 4 400 870 80 170
4 6 8 8 2 525 1040 240 345
4 8 8 8 2 485 970 200 295
1
See Table 17 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements.
Table 29. DDC Power Consumption for Example Configurations for 2.6 GSPS; fS = 2.56 GHz
Number of DDC Decimation Number of Number of Virtual Number of Octets DVDD Power (mW) DRVDD1 Power (mW)
DDCs Ratio 1 Lanes (L) Converters (M) per frame (F) Typ Max Typ Max
2 3 8 4 2 575 995 280 375
2 4 8 4 1 520 930 230 325
2 6 4 4 2 515 925 155 238
2 8 4 4 2 500 905 135 211
2 12 2 4 4 510 912 95 165
4 6 8 8 2 655 1090 280 380
4 8 8 8 2 630 1090 230 325
1
See Table 17 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements.
SIGNAL MONITOR
The signal monitor block provides additional information about The magnitude of the input port signal is monitored over a
the signal being digitized by the ADC. The signal monitor programmable time period, which is determined by the signal
computes the peak magnitude of the digitized signal. This monitor period register (SMPR). The peak detector function is
information can be used to drive an AGC loop to optimize the enabled by setting Bit 1 in the signal monitor control register
range of the ADC in the presence of real-world signals. (Register 0x0270). The 24-bit SMPR must be programmed
The results of the signal monitor block can be obtained either before activating this mode.
by reading back the internal values from the SPI port or by After enabling peak detection mode, the value in the SMPR is
embedding the signal monitoring information into the JESD204B loaded into a monitor period timer, which decrements at the
interface as separate control bits. A global, 24-bit programmable decimated clock rate. The magnitude of the input signal is
period controls the duration of the measurement. Figure 127 compared with the value in the internal magnitude storage
shows the simplified block diagram of the signal monitor block. register (not accessible to the user), and the greater of the two
SIGNAL MONITOR is updated as the current peak level. The initial value of the
FROM
PERIOD REGISTER DOWN IS
MEMORY
(SMPR) COUNTER COUNT = 1? magnitude storage register is set to the current ADC input signal
MAP
0x0271, 00x272, 0x0273
LOAD
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
CLEAR LOAD When the monitor period timer reaches a count of 1, the 13-bit
MAGNITUDE SIGNAL TO SPORT OVER
FROM
INPUT
STORAGE MONITOR JESD204B AND peak level value is transferred to the signal monitor holding
REGISTER HOLDING MEMORY MAP
LOAD
REGISTER register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
15550-049
COMPARE
A>B period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
Figure 127. Signal Monitor Block
input sample updates in the magnitude storage register, and the
The peak detector captures the largest signal within the comparison and update procedure, as explained previously,
observation period. The detector only observes the magnitude continues.
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
1-BIT
CONTROL
BIT
15-BIT CONVERTER RESOLUTION (N = 15) (CS = 1)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRL
S[14] S[13] S[12] S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0]
[BIT 2]
X X X X X X X X X X X X X X X X
1
CONTROL
BIT 1 TAIL
14-BIT CONVERTER RESOLUTION (N = 14) (CS = 1) BIT
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CTRL
S[13] S[12] S[11] S[10] S[9] S[8] S[7] S[6] S[5] S[4] S[3] S[2] S[1] S[0] TAIL
[BIT 2]
X X X X X X X X X X X X X X X
X
15550-050
SERIALIZED SIGNAL MONITOR
FRAME DATA
5-BIT SUBFRAMES
5-BIT IDLE
SUBFRAME IDLE IDLE IDLE IDLE IDLE
(OPTIONAL) 1 1 1 1 1
5-BIT DATA
MSB START P[12] P[11] P[10] P[9]
0
SUBFRAME
5-BIT DATA
LSB START P[0] 0 0 0
0
SUBFRAME
15550-051
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N)
IDENT. DATA DATA DATA DATA IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE
MSB LSB
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N + 1)
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N + 2)
IDENT. DATA DATA DATA DATA IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE
MSB LSB
15550-052
Figure 130. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE • K is the number of frames per multiframe;
The AD9689 digital outputs are designed to the JEDEC standard AD9689 value = 4, 8, 12, 16, 20, 24, 28, or 32.
JESD204B, serial interface for data converters. JESD204B is a • S is the samples transmitted per single converter per frame
protocol to link the AD9689 to a digital processing device over a cycle; AD9689 value is set automatically based on L, M, F,
serial interface with lane rates of up to 16 Gbps. The benefits of and N΄.
the JESD204B interface over LVDS include a reduction in • HD is the high density mode; the AD9689 mode is set
required board area for data interface routing and an ability to automatically based on L, M, F, and N΄.
enable smaller packages for converter and logic devices. • CF is the number of control words per frame clock cycle
per converter device; AD9689 value = 0.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data Figure 131 shows a simplified block diagram of the AD9689
from the ADC into frames and uses 8-bit/10-bit encoding as JESD204B link. By default, the AD9689 is configured to use
well as optional scrambling to form serial output data. Lane two converters and eight lanes. Converter A data is output to
synchronization is supported through the use of separate SERDOUT0±, SERDOUT1±, SERDOUT2± and SERDOUT3±;
control characters during the initial establishment of the link. and Converter B is output to SERDOUT4±, SERDOUT5±,
Additional control characters are embedded in the data stream SERDOUT6±, and SERDOUT7±. The AD9689 allows other
to maintain synchronization thereafter. A JESD204B receiver is configurations, such as combining the outputs of both
required to complete the serial link. For additional details on converters onto a single lane, or changing the mapping of the
the JESD204B interface, refer to the JESD204B standard. A and B digital output paths. These modes are set up via the SPI
register map, along with additional customizable options.
The AD9689 JESD204B data transmit block maps up to two
physical ADCs or up to eight virtual converters (when DDCs are By default in the AD9689, the 14-bit converter word from each
enabled) over a link. A link can be configured to use one, two, converter is broken into two octets (eight bits of data). Bit 13
four, or eight JESD204B lanes. The JESD204B specification refers (MSB) through Bit 6 are in the first octet. The second octet
to a number of parameters to define the link, and these parameters contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
must match between the JESD204B transmitter (the AD9689 can be configured as zeros or as a pseudorandom number
output) and the JESD204B receiver (the logic device input). sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output.
The JESD204B link is described according to the following
parameters: The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
• L is the number of lanes per converter device (lanes per when transmitting similar digital data patterns. The scrambler
link); AD9689 value = 1, 2, 4, or 8. uses a self synchronizing, polynomial-based algorithm defined
• M is the number of converters per converter device (virtual by the equation 1 + x14 + x15. The descrambler in the receiver is
converters per link); AD9689 value = 1, 2, 4, or 8. a self synchronizing version of the scrambler polynomial.
• F is the octets per frame; AD9689 value = 1, 2, 4, 8, or 16.
The two octets are then encoded with an 8-bit/10-bit encoder. The
• N΄ is the number of bits per sample (JESD204B word size);
8-bit/10-bit encoder works by taking eight bits of data (an octet)
AD9689 value = 8 or 16.
and encoding them into a 10-bit symbol. Figure 132 shows how
• N is the converter resolution; AD9689 value = 7 to 16. the 14-bit data is taken from the ADC, how the tail bits are added,
• CS is the number of control bits per sample; how the two octets are scrambled, and how the octets are encoded
AD9689 value = 0, 1, 2, or 3. into two 10-bit symbols. Figure 132 shows the default data format.
CONVERTER 0
CONVERTER A
ADC A SERDOUT0±
INPUT
LANE MUX SERDOUT1±
AND
MUX/ JESD204B LINK MAPPING SERDOUT2±
FORMAT CONTROL (SPI
(SPI SERDOUT3±
(L, M, F) REGISTERS
REGISTERS (SPI REGISTER 0x05B0, SERDOUT4±
0x0561, 0x058B, 0x05B2,
0x0564) SERDOUT5±
0x058E, 0x058C) 0x05B3,
0x05B5, SERDOUT6±
CONVERTER B 0x05B6)
ADC B SERDOUT7±
INPUT
CONVERTER 1
15550-058
SYSREF±
SYNCINB±
Figure 131. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
OCTET0
OCTET1
OCTET0
OCTET1
A11 CONSTRUCTION
SYMBOL0 SYMBOL1
A10
A9 a b c d e f g h i j
JESD204B SAMPLE MSB A13 A5 MSB S7 S7 a b c d e f g h i j
ADC A8 CONSTRUCTION
A7 A12 A4 S6 S6
A6 A11 A3 S5 S5
A5 A10 A2 S4 S4
TAIL BITS A9 A1 S3 S3
A4 0x0571[6]
A3 A8 A0 S2 S2
A2 A7 C2 S1 S1
A1 LSB A6 T LSB S0 S0
LSB A0
C2
15550-059
CONTROL BITS C1
C0
PROCESSED ALIGNMENT
SAMPLES SAMPLE FRAME 8-BIT/10-BIT CROSSBAR
CONSTRUCTION CONSTRUCTION SCRAMBLER CHARACTER ENCODER MUX SERIALIZER Tx OUTPUT
FROM ADC GENERATION
15550-060
SYSREF±
SYNCINB±
END OF
MULTIFRAME
●●● ●●● ●●● ●●● ●●●
15550-061
100Ω RECEIVER
0.1µF
SERDOUTx–
15550-063
ADJUSTABLE TO
1 × DRVDD1, 0.75 × DRVDD1
15550-307
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
Figure 137. Digital Outputs Jitter Histogram, External 100 Ω Terminations at
Place a 100 Ω differential termination resistor at each receiver 16 Gbps
input to result in a nominal 0.85 × DRVDD1 V p-p swing at the
receiver (see Figure 135). The swing is adjustable through the
SPI registers. AC coupling is recommended to connect to the
receiver. See the Memory Map section (Register 0x05C0 to
Register 0x05C3 in Table 51) for more details.
15550-308
The AD9689 digital outputs can interface with custom
application specific integrated circuits (ASICs) and field Figure 138. Digital Outputs Bathtub Curve, External 100 Ω Terminations at
16 Gbps
programmable gate array (FPGA) receivers, providing superior
switching performance in noisy environments. Single point to De-Emphasis
point network topologies are recommended with a single De-emphasis enables the receiver eye diagram mask to be met
differential 100 Ω termination resistor placed as close to the in conditions where the interconnect insertion loss does not
receiver inputs as possible. meet the JESD204B specification. Use the de-emphasis feature
If there is no far end receiver termination, or if there is poor only when the receiver is unable to recover the clock due to
differential trace routing, timing errors can result. To avoid such excessive insertion loss. Under normal conditions, it is disabled
timing errors, it is recommended that the trace length be less to conserve power. Additionally, enabling and setting too high a
than six inches, and that the differential output traces be close de-emphasis value on a short link can cause the receiver eye
together and at equal lengths. diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
Figure 136 to Figure 138 show an example of the digital output
the Memory Map section (Register 0x05C4 to Register 0x05CB
data eye, jitter histogram, and bathtub curve for one AD9689
in Table 51) for more details.
lane running at 16 Gbps. The format of the output data is twos
complement by default. To change the output data format, see Phase-Locked Loop (PLL)
the Memory Map section (Register 0x0561 in Table 51). The PLL generates the serializer clock, which operates at the
JESD204B lane rate. The status of the PLL lock can be checked
in the PLL locked status bit (Register 0x056F, Bit 7). This read
only bit notifies the user if the PLL achieved a lock for the
specific setup. Register 0x056F also has a loss of lock (LOL)
sticky bit (Bit 3) that notifies the user that a LOL is detected. The
15550-306
ADC0 ADC1
S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0]
TRANSPORT,
JESD204B FRAMER + PHY DATA LINK,
(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) AND PHY
LAYERS
15550-309
DATA LINK,
JESD204B FRAMER + PHY TRANSPORT,
(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0) AND PHY
LAYERS
S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0] S[N][15:0] S[N + 1][15:0] S[N + 2][15:0] S[N + 3][15:0]
S[N][11:0], S[N + 1][11:8] S[N + 1][7:0], S[N + 2][11:4] S[N + 2][3:0], S[N + 3][11:0] S[N + 4][11:0], 0000 S[N][11:0], S[N + 1][11:8] S[N + 1][7:0], S[N + 2][11:4] S[N + 2][3:0], S[N + 3][11:0] S[N + 4][11:0], 0000
(16 BITS) (16 BITS) (16 BITS) (16 BITS)
(16 BITS) (16 BITS) (16 BITS) (16 BITS)
APPLICATION
LAYER
64 BITS ADC0
SAMPLE N (12 BITS)
ADC0
SAMPLE N + 1 (12 BITS)
ADC0
SAMPLE N + 2 (12 BITS)
ADC0
SAMPLE N + 3 (12 BITS)
ADC0
SAMPLE N + 4 (12 BITS) (4 BITS)
ADC1
SAMPLE N (12 BITS)
ADC1
SAMPLE N + 1 (12 BITS)
ADC1
SAMPLE N + 2 (12 BITS)
ADC1
SAMPLE N + 3 (12 BITS)
ADC1
SAMPLE N + 4 (12 BITS) (4 BITS)
AT fS/5
0000 0000
15550-310
USER APPLICATION
SETTING UP THE AD9689 DIGITAL INTERFACE If the internal DDCs are used for on-chip digital processing, M
To ensure proper operation of the AD9689 at startup, some SPI represents the number of virtual converters. The virtual converter
writes are required to initialize the link. Additionally, these mapping setup is shown in Figure 102.
registers must be written every time the ADC is reset. Any one The maximum lane rate allowed by the AD9689 is 16 Gbps. The
of the following resets warrants the initialization routine for the lane rate is related to the JESD204B parameters using the
digital interface: following equation:
• Hard reset, as with power-up. 10
M × N ' × × f OUT
• Power-up using the PDWN pin. 8
Lane Rate =
• Power-up using the SPI via Register 0x0002, Bits[1:0]. L
• SPI soft reset by setting Register 0x0000 = 0x81. f ADC _ CLOCK
• Datapath soft reset by setting Register 0x0001 = 0x02. where fOUT =
Decimation Ratio
• JESD204B link power cycle by setting Register 0x0571 =
0x15, then 0x14. The decimation ratio (DCM) is the parameter programmed in
Register 0x0201.
The initialization SPI writes are as shown in Table 32.
Use the following procedure to configure the output:
Table 32. AD9689 JESD204B Initialization 1. Power down the link.
Register Value Comment 2. Select the JESD204B link configuration options.
0x1228 0x4F Reset JESD204B start-up circuit 3. Configure the detailed options.
0x1228 0x0F JESD204B start-up circuit in normal operation 4. Set output lane mapping (optional).
0x1222 0x00 JESD204B PLL force normal operation 5. Set additional driver configuration options (optional).
0x1222 0x04 Reset JESD204B PLL calibration 6. Power up the link.
0x1222 0x00 JESD204B PLL normal operation 7. Initialize the JESD204B link by issuing the commands
0x1262 0x08 Clear loss of lock bit described in Table 32.
0x1262 0x00 Loss of lock bit normal operation
If the lane rate calculated is less than 6.25 Gbps, select the low
The AD9689 has one JESD204B link. The serial outputs lane rate option by programming a value of 0x10 to
(SERDOUT0± to SERDOUT7±) are considered to be part of Register 0x056E.
one JESD204B link. The basic parameters that determine the
Table 33 and Table 35 show the JESD204B output configurations
link setup are
supported for both N΄ = 16 and N΄ = 8 for a given number of
• Number of lanes per link (L) virtual converters. Take care to ensure that the serial lane rate
• Number of converters per link (M) for a given configuration is within the supported range of
• Number of octets per frame (F) 3.4 Gbps to 16 Gbps.
Converters Serial Lane Rate = Lane Rate = Lane Rate = Lane Rate =
Supported Lane 1.6875 Gbps to 3.375 Gbps to 6.75 Gbps to 13.5 Gbps to
(Same as M) Rate 2
38F 3.375 Gbps 6.75 Gbps 13.5 Gbps 16 Gbps L M F S HD N N' CS K
1 20 × fOUT 2, 4, 5, 6, 8, 10, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1 1 2 1 0 8 to 16 16 0 to 3 See
12, 20, 24 10, 12 Note 4
40F
Converters Serial Lane Rate = Lane Rate = Lane Rate = Lane Rate =
Supported Lane 1.6875 Gbps to 3.375 Gbps to 6.75 Gbps to 13.5 Gbps to
(Same as M) Rate 2
38F 3.375 Gbps 6.75 Gbps 13.5 Gbps 16 Gbps L M F S HD N N' CS K
8 160 × fOUT 16, 40, 48 8, 16, 20, 24, 40, 4, 8, 12, 16, 20, 4, 8, 12, 16, 1 8 16 1 0 8 to 16 16 0 to 3 See
48 24, 40, 48 20, 24 Note 4
80 × fOUT 8, 16, 20, 24, 40, 4, 8, 10, 12, 16, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 2 8 8 1 0 8 to 16 16 0 to 3 See
48 20, 24, 40, 48 16, 20, 24 12, 16 Note 4
40 × fOUT 4, 8, 10, 12, 16, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8 4 8 4 1 0 8 to 16 16 0 to 3 See
20, 24, 40, 48 16, 20, 24 16 Note 4
40 × fOUT 4, 8, 10, 12, 16, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8 4 8 8 2 0 8 to 16 16 0 to 3 See
20, 24, 40, 48 16, 20, 24 16 Note 4
20 × fOUT 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8 2, 4 8 8 2 1 0 8 to 16 16 0 to 3 See
16, 20, 24 16 Note 4
20 × fOUT 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8 2, 4 8 8 4 2 0 8 to 16 16 0 to 3 See
16, 20, 24 16 Note 4
1
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
3
fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following
equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM ×
fOUT/SLR, DCM) ≤64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and
≥1687.5 Mbps, Register 0x056E must be set to 0x50.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
Converters Serial Lane Rate = Lane Rate = Lane Rate = Lane Rate =
Supported Lane 1.6875 Gbps 3.375 Gbps to 6.75 Gbps to 13.5 Gbps to
(Same Value as M) Rate 2
42F to 3.375 Gbps 6.75 Gbps 13.5 Gbps 16 Gbps L M F S HD N N' L K
1 15 × fOUT 3, 6, 12 3, 6, 12 3, 6 1 1 3 2 0 8 to 12 12 0 to 3 See
Note 4
4F
1
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2
fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The
following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20
× DCM × fOUT/SLR, DCM) ≤64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and
≥1687.5 Mbps, Register 0x056E must be set to 0x50.
3
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
Converters Serial Lane Rate = Lane Rate = Lane Rate = Lane Rate =
Supported Lane 1.6875 Gbps to 3.375 Gbps to 6.75 Gbps to 13.5 Gbps to
(Same Value as M) Rate 2
46F 3.375 Gbps 6.75 Gbps 13.5 Gbps 16 Gbps L M F S HD N N' CS K
1 10 × fOUT 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 1, 2, 3, 4 1, 2 1 1 1 1 0 7 to 8 8 0 to 1 See
10, 12 6, 8 Note 4
48F
1 10 × fOUT 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 1, 2, 3, 4 1, 2 1 1 2 2 0 7 to 8 8 0 to 1 See
10, 12 6, 8 Note 4
1 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 1 2 0 7 to 8 8 0 to 1 See
Note 4
1 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 2 4 0 7 to 8 8 0 to 1 See
Note 4
1 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 2 1 4 8 0 7 to 8 8 0 to 1 See
Note 4
1 2.5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 1 4 0 7 to 8 8 0 to 1 See
Note 4
1 2.5 × fOUT 1, 2, 3, 4 1, 2 1 4 1 2 8 0 7 to 8 8 0 to 1 See
Note 4
2 20 × fOUT 2, 4, 5, 6, 8, 10, 1, 2, 3, 4, 5, 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1 2 2 1 0 7 to 8 8 0 to 1 See
12, 15, 16, 20, 6, 8, 10, 12, Note 4
24, 30 15, 16
2 10 × fOUT 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 1, 2, 3, 4 1, 2 2 2 1 1 0 7 to 8 8 0 to 1 See
8, 10, 12, 15, 16 6, 8 Note 4
2 10 × fOUT 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 1, 2, 3, 4 1, 2 2 2 2 2 0 7 to 8 8 0 to 1 See
8, 10, 12, 15, 16 6, 8 Note 4
2 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 1 2 0 7 to 8 8 0 to 1 See
Note 4
2 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 2 4 0 7 to 8 8 0 to 1 See
Note 4
2 5 × fOUT 1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4 1, 2 1 4 2 4 8 0 7 to 8 8 0 to 1 See
Note 4
1
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
2
fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The
following equations must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 ×
DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤16000 Mbps and >13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is <6750 Mbps and ≥3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is <3375 Mbps and ≥1687.5
Mbps, Register 0x056E must be set to 0x50.
3
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8,
K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
VIN_A L0
14-BIT M0 M0S0[15:8]
REAL
ADC
CORE L1
M0S0[7:0]
JESD204B L2
M0S1[15:8]
LINK
(L = 8,
M = 2, L3
M0S1[7:0]
F = 1,
S = 2,
N´ = 16, L4
N = 16, M1S0[15:8]
CS = 0,
HD = 1) L5
M1S0[7:0]
L6
VIN_B M1 M1S1[15:8]
REAL 14-BIT
ADC
CORE L7
M1S1[7:0]
I = REAL COMPONENT
Q = QUADRATURE COMPONENT
DCM = DECIMATION
C2R = COMPLEX TO REAL
MX = VIRTUAL CONVERTER X
LY = LANE Y
SZ = SAMPLE Z INSIDE A JESD204B FRAME
15550-311
C = CONTROL BIT (OVERRANGE, AMONG OTHERS)
T = TAIL BIT
The AD9689 is set up as shown in Figure 141, with the following Set up the AD9689 in this mode using the following sequence:
configurations: 1. Write 0x81 to Register 0x0000 (SPI soft reset).
• Two 14-bit converters at 2.56 GSPS. 2. Wait 5 ms to 10 ms.
• Full bandwidth application layer mode. 3. Write 0x00 to Register 0x0200 (full bandwidth mode).
• Decimation filters bypassed. 4. Write 0x00 to Register 0x0201 (chip decimation ratio = 1).
5. Write 0x15 to Register 0x0571 (JESD204B link power-
The JESD204B output configuration is as follows: down).
• Two virtual converters required (see Table 33). 6. Write 0x87 to Register 0x058B (scrambling enabled, L = 8).
• Output sample rate (fOUT) = 2560/1 = 2560 MSPS. 7. Write 0x01 to Register 0x058E (M = 2).
8. Write0x00 to Register 0x058C (F = 1).
The JESD204B supported output configurations are as follows 9. Write 0x00 to Register 0x056E (lane rate = 6.75 Gbps to
(see Table 33): 13.5 Gbps).
• N΄ = 16 bits. 10. Write 0x14 to Register 0x0571 (JESD204B link power-up).
• N = 14 bits. 11. Wait 5 ms to 10 ms.
• L = 8, M = 2, and F = 1, or L = 8, M = 2, and F = 2. 12. Read Register 0x056F (PLL status register).
• CS = 0. 13. Write 0x4F to Register 0x1228.
• K = 32. 14. Write 0x0F to Register 0x1228.
15. Write 0x00 to Register 0x1222.
• Output serial lane rate = 12.8 Gbps per lane.
16. Write 0x04 to Register 0x1222.
• The PLL control register, Register 0x056E, is set to 0x00.
17. Write 0x00 to Register 0x1222.
18. Write 0x08 to Register 0x1262.
19. Write 0x00 to Register 0x1262.
SYNC~
F=4
M0(I)
M1(Q)S0[15:8]
M0(I)S0[15:8]
M1(Q)S0[7:0]
M0(I)S0[7:0]
VIN_A DDC 0
REAL (REAL INPUT, LAB0
14-BIT
ADC CORE DCM = 10
C2R = BYPASS) M1(Q)
JESD204B LINK
(L = 2 M = 4 F = 4,
S = 1, N’ = 16, N = 16,
M2(I) CS = 0, HD = 0)
M3(Q)S0[15:8]
M2(I)S0[15:8]
M3(Q)S0[7:0]
M2(I)S0[7:0]
VIN_B DDC 1
REAL 14-BIT (REAL INPUT, LAB1
ADC CORE DCM = 10
C2R = BYPASS) M3(Q)
I = REAL COMPONENT
Q = QUADRATURE COMPONENT
DCM = DECIMATION
C2R = COMPLEX TO REAL
MX = VIRTUAL CONVERTER X
LY = LANE Y
SZ = SAMPLE Z INSIDE A JESD204B FRAME
15550-312
C = CONTROL BIT (OVER RANGE, AMONG OTHERS)
T = TAIL BIT
This example shows the flexibility in the digital and lane Set up the AD9689 in this mode using the following sequence:
configurations for the AD9689. The sample rate is 2.4576 GSPS,
1. Write 0x81 to Register 0x0000 (SPI soft reset).
whereas the outputs are all combined in a combination of either
2. Wait 5 ms to 10 ms.
two, four, or eight lanes, depending on the input/output speed
3. Write 0x02 to Register 0x0200 (two DDC mode).
capability of the receiving device.
4. Write 0x06 to Register 0x0201 (chip decimation ratio = 10).
The AD9689 is set up as shown in Figure 142, with the following 5. Write 0x47 to Register 0x0310 (6 dB gain, decimation ratio
configuration: set by Register 0x0311, Bits[7:4]).
• Two 14-bit converters at 2.4576 GSPS. 6. Write 0x20 to Register 0x0311 (decimate by 10, DDC0
• Two DDC application layer mode with complex outputs (I/Q). inputs from Channel A).
• Chip decimation ratio = 10. 7. Register 0x0316 to Register 0x031B is the DDC0 NCO
tuning word.
• DDC decimation ratio = 10 (see Table 33).
8. Write 0x47 to Register 0x0330 (6 dB gain, decimation ratio
The JESD204B output configuration is as follows: set by Register 0x0331, Bits[7:4]).
• Four virtual converters required (see Table 33). 9. Write 0x25 to Register 0x0331 (decimate by 10, DDC1
inputs from Channel B).
• Output sample rate (fOUT) = 2457.6/10 = 245.76 MSPS.
10. Register 0x0336 to Register 0x033B is the DDC0 NCO
The JESD204B supported output configurations are as follows tuning word.
(see Table 33): 11. Write 0x15 to Register 0x0571 (JESD204B link power down).
• N΄ = 16 bits. 12. Write 0x81 to Register 0x058B (scrambling enabled, L = 2).
• N = 14 bits. 13. Write 0x03 to Register 0x058E (M = 4).
14. Write 0x03 to Register 0x058C (F = 4).
• L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2.
15. Write 0x00 to Register 0x056E (lane rate = 6.75 Gbps to
• CS = 0.
13.5 Gbps).
• K = 32.
16. Write 0x14 to Register 0x0571 (JESD204B link power up).
• Output serial lane rate = 9.8304 Gbps per lane (L = 2), 17. Wait 5 ms to 10 ms.
4.9152 Gbps per lane (L = 4), or 2.4576 Gbps per lane (L = 8). 18. Read Register 0x056F (PLL status register).
For L = 2, set the PLL control register, Register 0x056E, to 0x00. 19. Write 0x4F to Register 0x1228.
For L = 4, set the PLL control register, Register 0x056E, to 0x10. 20. Write 0x0F to Register 0x1228.
For L = 8, set the PLL control register, Register 0x056E, to 0x50. 21. Write 0x00 to Register 0x1222.
22. Write 0x04 to Register 0x1222.
23. Write 0x00 to Register 0x1222.
24. Write 0x08 to Register 0x1262.
25. Write 0x00 to Register 0x1262.
DETERMINISTIC LATENCY
Both ends of the JESD204B link contain various clock domains SUBCLASS 1 OPERATION
distributed throughout each system. Data traversing from one The JESD204B protocol organizes data samples into octets, frames,
clock domain to a different clock domain can lead to ambiguous and multiframes as described in the Transport Layer section.
delays in the JESD204B link. These ambiguities lead to non- The LMFC is synchronous with the beginnings of these
repeatable latencies across the link from one power cycle or link multiframes. In Subclass 1 operation, the SYSREF signal
reset to the next. Section 6 of the JESD204B specification synchronizes the LMFCs for each device in a link or across
addresses the issue of deterministic latency with mechanisms multiple links (within the AD9689, SYSREF also synchronizes
defined as Subclass 1 and Subclass 2. the internal sample dividers), as shown in Figure 143. The
The AD9689 supports JESD204B Subclass 0 and Subclass 1 JESD204B receiver uses the multiframe boundaries and
operation. Register 0x0590, Bits[7:5] set the subclass mode for the buffering to achieve consistent latency across lanes (or even
AD9689 and its default is set for Subclass 1 operating mode multiple devices), and to achieve a fixed latency between power
(Register 0x0590, Bit 5 = 1). If deterministic latency is not a cycles and link reset conditions.
system requirement, Subclass 0 operation is recommended and Deterministic Latency Requirements
the SYSREF signal may not be required. Even in Subclass 0
mode, the SYSREF signal may be required in an application Several key factors are required for achieving deterministic
where multiple AD9689 devices must be synchronized with latency in a JESD204B Subclass 1 system.
each other. This topic is addressed in the Timestamp Mode • SYSREF± signal distribution skew within the system must
section. be less than the desired uncertainty for the system.
SUBCLASS 0 OPERATION • SYSREF± setup and hold time requirements must be met
for each device in the system.
If there is no requirement for multichip synchronization while
• The total latency variation across all lanes, links, and
operating in Subclass 0 mode (Register 0x0590, Bits[7:5] = 0
devices must be ≤1 LMFC periods (see Figure 143). This
decimal), the SYSREF input can be left disconnected. In this mode,
includes both variable delays and the variation in fixed
the relationship of the JESD204B clocks between the JESD204B
delays from lane to lane, link to link, and device to device
transmitter and receiver are arbitrary, but does not affect the ability
in the system.
of the receiver to capture and align the lanes within the link.
SYSREF
DEVICE CLOCK
ALL LMFCs
15550-313
Tx LOCAL LMFC
DATA
(AT Tx INPUT) ILAS DATA
DATA
(AT Rx INPUT) ILAS DATA
SYSREF ALIGNED
GLOBAL LMFC
DATA
(AT Tx INPUT) ILAS DATA
DATA
(AT Rx INPUT) ILAS ILAS DATA
Rx LOCAL LMFC
15550-315
MULTICHIP SYNCHRONIZATION
The flowchart in Figure 147 shows the internal mechanism for In this mode, SYSREF resets the sample dividers and the
multichip synchronization in the AD9689. There are two methods JESD204B clocking. When the chip sync mode is set to 1, the
by which multichip synchronization can take place, as determined clocks are not reset; instead, the coinciding sample is timestamped
by the synchronization mode bit (Register 0x01FF, Bit 0). Each using the JESD204B control bits of that sample. To operate in
method involves different applications of the SYSREF signal. timestamp mode, these additional settings are necessary:
NORMAL MODE • Continuous or N-shot SYSREF must be enabled
The default sate of the chip synchronization mode bit is 0, which (Register 0x0120, Bits[2:1] = 1 or 2 decimal).
configures the AD9689 for normal chip synchronization. The • At least one control bit must be enabled (Register 0x058F,
JESD204B standard specifies the use of SYSREF to provide for Bits[7:6] = 1, 2, or 3 decimal).
deterministic latency within a single link. This same concept, • Set the function for one of the control bits to SYSREF:
when applied to a system with multiple converters and logic Register 0x0559, Bits[3:0] = 5 decimal if using Control Bit
devices, can also provide multichip synchronization referred to as 0, Register 0x0559, Bits[7:4] = 5 decimal if using Control
normal mode (see Figure 147). Following the process in the Bit 1, Register 0x055A, Bits[3:0] = 5 decimal if using
flowchart ensures that the AD9689 is configured appropriately. The Control Bit 2.
user must also consult the logic devices user IP guide to ensure Figure 146 shows how the input sample coincident with
that the JESD204B receivers are configured appropriately. SYSREF is timestamped and ultimately output from the ADC.
TIMESTAMP MODE In this example, there are two control bits, and Control Bit 0 is
For all AD9689 full bandwidth operating modes, the SYSREF the bit indicating which sample was coincident with the
input can also be used to timestamp samples, another method SYSREF rising edge. Note that the pipeline latencies for each
by which multiple channels and multiple devices can achieve channel are identical. If so desired, the SYSREF± timestamp
synchronization. This method is especially effective when delay register (Register 0x0123) can be used to adjust the timing
synchronizing multiple devices to one or more logic devices. The of which sample is time stamped.
logic devices buffer the data streams, identify the timestamped Note that time stamping is not supported by any AD9689
samples, and align them. When the synchronization mode bit operating modes that use decimation.
(Register 0x01FF, Bit 0) is set to 1, the timestamp method is
used for synchronization of multiple channels and/or devices.
N N – 1 00 N 01 N + 1 00 N + 2 00 N + 3 00
AINB N–1 CHANNEL B
N+1 N+3
N+2
2 CONTROL BITS
15550-316
Figure 146. AD9689 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2 Decimal), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5 Decimal)
NO NO
SYSREF
RESET NO
SYSREF YES SYSREF IGNORE
SYSREF IGNORE ENABLED? SYSREF YES N-SHOT
ASSERTED? MODE MODE COUNTER
COUNTER (0x0120) (0x0120) EXPIRED?
(0x0121)
YES
UPDATE SETUP/HOLD
DETECTOR STATUS
(0x0128)
CLOCK
INPUT
DIVIDER
CLOCK INCREMENT
ALIGN CLOCK YES CLOCK DIVIDER YES YES DIVIDER
DIVIDER PHASE AUTO ADJUST SYSREF COUNTER
ALIGNMENT
ENABLED?
>1? (0x012A)
TO SYSREF REQUIRED? (0x010B)
NO NO NO
SYSREF SYSREF
SYNCHRO- TIMESTAMP
TIMESTAMP ENABLED YES SYSREF INSERTED
NIZATION MODE
DELAY IN CONTROL BITS? IN JESD204B
MODE? (0x0559, 0x055A,
(0x0123) CONTROL BITS
(0x01FF) 0x058F)
NO
RAMP
NORMAL TEST MODE YES SYSREF RESETS
MODE ENABLED? RAMP TEST MODE BACK TO START
(0x0550) GENERATOR
NO
NO NO
SIGNAL
MONITOR YES ALIGN SIGNAL DDC NCO YES ALIGN DDC NCO
ALIGNMENT MONITOR ALIGNMENT PHASE BACK TO START
ENABLED? COUNTERS ENABLED? ACCUMULATOR
(0x026F) (0x0300)
NO NO
15550-317
15550-318
KEEP OUT WINDOW
SYSREF signal must be an integer multiple of the LMFC. LMFC
can be derived using the following formula: Figure 148. SYSREF Setup and Hold Time Requirements—SYSREF Low to
High Transition Using Rising Edge Clock (Default)
LMFC = ADC clock/(S × K) SETUP
REQUIREMENT
where: –65ps
SYSREF
S is the JESD204B parameter for number of samples per converter. HOLD
REQUIREMENT
SAMPLE POINT
K is the number of frames per multiframe. 95ps
The input clock divider, DDCs, signal monitor block, and CLK
JESD204B link are all synchronized using the SYSREF± input when
15550-319
in normal synchronization mode (Register 0x01FF, Bit 0 = 0). SYSREF
The SYSREF± input can also be used to timestamp an ADC Figure 149. SYSREF Low to High Transition Using Falling Edge Clock Capture
sample to provide a mechanism for synchronizing multiple (Register 0x0120, Bit 4 = 1’b0; Register 0x0120, Bit 3 = 1’b1)
AD9689 devices in a system. For the highest level of timing SETUP
REQUIREMENT
accuracy, SYSREF± must meet setup and hold requirements –65ps
SYSREF
relative to the CLK± input. There are several features in the HOLD SAMPLE POINT
REQUIREMENT
AD9689 that can be used to ensure these requirements are met; 95ps
15550-320
SYSREF Control Features SYSREF
SYSREF is used, along with the input clock (CLK), as part of a Figure 150. SYSREF High to Low Transition Using Rising Edge Clock Capture
source-synchronous timing interface and requires setup and (Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b0)
hold timing requirements of −65 ps and 95 ps relative to the SETUP
REQUIREMENT
–65ps
input clock (see Figure 148). The AD9689 has several features
SYSREF
that aid the user in meeting these requirements. First, the HOLD
REQUIREMENT
SAMPLE POINT
95ps
SYSREF sample event can be defined as either a synchronous
low to high transition or synchronous high to low transition. CLK
Second, the AD9689 allows the SYSREF signal to be sampled
15550-321
using either the rising edge or falling edge of the input clock. SYSREF
Figure 148, Figure 149, Figure 150, and Figure 151 show all four
Figure 151. SYSREF High to Low Transition Using Falling Edge Clock Capture
possible combinations. (Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b1)
The third SYSREF related feature available is the ability to
ignore a programmable number (up to 16) of SYSREF events.
CLK
SYSREF
15550-322
IGNORE FIRST THREE SYSREFs SAMPLE THE FOURTH SYSREF
Figure 152. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3)
SAMPLE CLOCK
15550-323
SYSREF
When in continuous SYSREF mode (Register 0x0120, Bits[2:1] = If the SYSREF negative skew window is 1 and the positive skew
1), the AD9689 monitors the placement of the SYSREF leading window is 1, the total skew window is ±1 sample clock cycles,
edge compared to the internal LMFC. If the SYSREF signal is meaning that, as long as SYSREF is captured within ±1 sample
captured with a clock edge other than the one that is aligned clock cycle of the clock that is aligned with the LMFC, the link
with the LMFC, the AD9689 initiates a resynchronization of the continues to operate normally. If the SYSREF has jitter, which
link. Because input clock rates for AD9689 can be up to 4 GHz, can cause a misalignment between SYSREF and LMFC, this
the AD9689 provides another SYSREF related feature that feature allows the system to continue running without a
makes it possible to accommodate periodic SYSREF signals resynchronization, while still allowing the device to monitor for
where cycle accurate capture is not feasible or not required. For larger errors not caused by jitter. For the AD9689, the positive
these scenarios, the AD9689 has a programmable SYSREF skew and negative skew window is controlled by the SYSREF window
window that allows the internal dividers to remain undisturbed negative bits (Register 0x0122, Bits[3:2]) and SYSREF window
unless SYSREF occurs outside the skew window. The resolution positive bits (Register 0x0122, Bits[1:0]). Figure 153 shows
of the SYSREF skew window is set in sample clock cycles. information on the location of the skew window settings relative to
Phase 0 of the internal dividers. Negative skew is defined as
occurring before the internal dividers reach Phase 0, and positive
skew is defined after the internal dividers reach Phase 0.
CLK±
INPUT
SYSREF± VALID
INPUT
FLIP FLOP
FLIP FLOP
HOLD (MIN)
SETUP (MIN)
15550-070
FLIP FLOP
HOLD (MIN)
CLK±
INPUT
SYSREF± VALID
INPUT
FLIP FLOP
FLIP FLOP SETUP (MIN)
HOLD (MIN)
15550-071
FLIP FLOP
HOLD (MIN)
LATENCY
END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS
Total latency in the AD9689 is dependent on the chip Example Configuration 1 is as follows:
application mode and the JESD204B configuration. For any
• ADC application mode = full bandwidth
given combination of these parameters, the latency is
• Real outputs
deterministic; however, the value of this deterministic latency
• L = 8, M = 2, F = 1, S = 2 (JESD204B mode)
must be calculated as described in the Example Latency
• 20 × (M/L) = 5
Calculations section.
• Latency = 31 + 44 = 75 encode clocks
Table 37 shows the combined latency through the ADC and
digital signal processor (DSP) for the different chip application Example Configuration 2 is as follows:
modes supported by the AD9689. Table 38 shows the latency • ADC application mode = DCM4
through the JESD204B block for each application mode based • Complex outputs
on the M/L ratio. For Table 37 and Table 38, latency is typical • L = 4, M = 2, F = 1, S = 1 (JESD204B mode)
and is in units of the encode clock. The latency through the
• 20 × (M/L) = 10
JESD204B block does not depend on the output data type (real
• Latency = 162 + 88 = 250 encode clocks
or complex). Therefore, data type is not included in Table 38.
To determine the total latency, select the appropriate ADC + DSP LMFC REFERENCED LATENCY
latency from Table 37 and add it to the appropriate JESD204B Some FPGA vendors may require the end user to know the
latency from Table 38. Example calculations are provided in the LMFC referenced latency to make appropriate deterministic
following section. latency adjustments. If they are required, use the latency values
in Table 37 and Table 38 for the analog in to LMFC and LMFC
to data out latency values.
Table 37. Latency Through the ADC + DSP Blocks (Number of Sample Clocks) 1
Chip Application Mode Enabled Filters ADC + DSP Latency
Full Bandwidth Not applicable 31
DCM1 (Real) HB1 90
DCM2 (Complex) HB1 90
DCM3 (Complex) TB1 102
DCM2 (Real) HB2 + HB1 162
DCM4 (Complex) HB2 + HB1 162
DCM3 (Real) TB2 + HB1 212
DCM6 (Complex) TB2 + HB1 212
DCM4 (Real) HB3 +HB2 + HB1 292
DCM8 (Complex) HB3 +HB2 + HB1 292
DCM5 (Real) FB2 + HB1 380
DCM10 (Complex) FB2 + HB1 380
DCM6 (Real) TB2 + HB2 + HB1 424
DCM12 (Complex) TB2 + HB2 + HB1 424
DCM15 (Real) FB2 + TB1 500
DCM8 (Real) HB4 + HB3 + HB2 + HB1 552
DCM16 (Complex) HB4 + HB3 + HB2 + HB1 552
DCM10 (Real) FB2 + HB2 + HB1 694
DCM20 (Complex) FB2 + HB2 + HB1 694
DCM12 (Real) TB2 + HB3 + HB2 + HB1 814
DCM24 (Complex) TB2 + HB3 + HB2 + HB1 814
DCM30 (Complex) HB2 + FB2 + TB1 836
DCM20 (Real) FB2 + HB3 + HB2 + HB1 1420
DCM40 (Complex) FB2 + HB3 + HB2 + HB1 1420
DCM24 (Real) TB2 + HB4 + HB3 + HB2 + HB1 1594
DCM48 (Complex) TB2 + HB4 + HB3 + HB2 + HB1 1594
1
DCMx indicates the decimation ratio.
TEST MODES
ADC TEST MODES If the application mode is set to select a DDC mode of
The AD9689 has various test options that aid in the system level operation, the test modes must be enabled for each DDC
implementation. The AD9689 has ADC test modes that are enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
available in Register 0x0550. These test modes are described in Register 0x0327, Register 0x0347, and Register 0x0367,
Table 39. When an output test mode is enabled, the analog section depending on which DDC(s) are selected. The (I) data uses the
of the ADC is disconnected from the digital back-end blocks, test patterns selected for Channel A, and the (Q) data uses the
and the test pattern is run through the output formatting block. test patterns selected for Channel B. For DDC3 only, the (I) data
Some of the test patterns are subject to output formatting, and uses the test patterns from Channel A, and the (Q) data does
some are not. The pseudorandom number (PN) generators not output test patterns. Bit 0 of Register 0x0387 selects the
from the PN sequence tests can be reset by setting Bit 4 or Bit 5 Channel A test patterns to be used for the (I) data. For more
of Register 0x0550. These tests can be performed with or information, see the AN-877 Application Note.
without an analog signal (if present, the analog signal is
ignored); however, they do require an encode clock.
JESD204B DATA
JESD204B LONG JESD204B LINK LAYER TEST
TRANSPORT TEST INTERFACE TEST PATTERNS
PATTERN PATTERN 0x0574[2:0]
0x0571[5] (0x0573,
0x0551 TO 0x0558)
ADC TEST PATTERNS SERDOUT0±
(0x0550, SERDOUT1±
0x0551 TO 0x0558) SERIALIZER SERDOUT2±
SCRAMBLER 8-BIT/ SERDOUT3±
MSB A13 1 + x14 + x15 10-BIT
(OPTIONAL) ENCODER a b i j a b i j
A12 FRAME
OCTET0
OCTET1
OCTET0
OCTET1
A11 CONSTRUCTION
SYMBOL0 SYMBOL1
A10
A9 a b c d e f g h i j
JESD204B SAMPLE MSB A13 A5 MSB S7 S7 a b c d e f g h i j
ADC A8 CONSTRUCTION
A7 A12 A4 S6 S6
A6 A11 A3 S5 S5
A5 A10 A2 S4 S4
TAIL BITS A9 A1 S3 S3
A4 0x0571[6]
A3 A8 A0 S2 S2
A2 A7 C2 S1 S1
A1 LSB A6 T LSB S0 S0
LSB A0
C2
15550-059
CONTROL BITS C1
C0
Figure 156. ADC Output Datapath Showing Test Pattern Injection Points
Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 2'b00)
Frame Converter Sample Alternating 1/0 Word
Number Number Number Checkerboard Toggle Ramp PN9 PN23 User Repeat User Single
0 0 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 0 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 1 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
0 1 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0]
1 0 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 0 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 1 0 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
1 1 1 0xAAAA 0xFFFF (x +1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0]
2 0 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 0 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 1 0 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
2 1 1 0x5555 0x0000 (x +2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0]
3 0 0 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 0 1 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 1 0 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
3 1 1 0xAAAA 0xFFFF (x +3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0]
4 0 0 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 0 1 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 1 0 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
4 1 1 0x5555 0x0000 (x +4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000
Data Link Layer Test Modes Test patterns inserted at this point are useful for verifying the
The data link layer test modes are implemented in the AD9689 functionality of the data link layer. When the data link layer
as defined by Section 5.3.3.8.2 in the JEDEC JESD204B speci- test modes are enabled, disable SYNCINB± by writing 0xC0
fication. These tests are shown in Register 0x0574, Bits[2:0]. to Register 0x0572.
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE Default Values
Each address in the memory map register table has eight bit After the AD9689 is reset, critical registers are loaded with
locations. The memory map is divided into the following default values. The default values for the registers are given in
sections: the memory map register tables, Table 46 to Table 53.
• Analog Devices SPI registers (Register 0x0000 to Logic Levels
Register 0x000F) An explanation of logic level terminology follows:
• Clock/SYSREF/chip power-down pin control registers
• “Bit is set” is synonymous with “bit is set to Logic 1” or
(Register 0x003F to Register 0x01FF)
“writing Logic 1 for the bit.”
• Chip operating mode control registers (Register 0x0200 to
• “Clear a bit” is synonymous with “bit is set to Logic 0” or
Register 0x0201)
“writing Logic 0 for the bit.”
• Fast detect and signal monitor control registers
• X denotes a don’t care bit.
(Register 0x0245 to Register 0x027A)
• DDC function registers (Register 0x0300 to Register 0x03CD) Channel Specific Registers
• Digital outputs and test modes registers (Register 0x0550 to Some channel setup functions, such as the buffer control
Register 0x05CB and Register 0x1222 to Register 0x01262) register (Register 0x1A4C), can be programmed to a different
• Programmable filter control and coefficients registers value for each channel. In these cases, channel address locations
(Register 0x0DF8 to Register 0x0F7F) are internally duplicated for each channel. These registers and
• VREF/analog input control registers (Register 0x18A6 to bits are designated as local. These local registers and bits can be
Register 0x1A4D and Register 0x0701 to Register 0x073B) accessed by setting the appropriate Channel A or Channel B bits in
Register 0x0008. If both bits are set, the subsequent write affects
The Memory Map Register Details section documents the default
the registers of both channels. In a read cycle, set only
hexadecimal value for each hexadecimal address shown. For
Channel A or Channel B to read one of the two registers. If both
example, Address 0x0561, the output sample mode register, has
bits are set during an SPI read cycle, the device returns the value
a hexadecimal default value of 0x01, which means that Bit 0 = 1,
for Channel A. All other registers and bits are considered global,
and the remaining bits are 0s. This setting is the default output
and changes to these registers and bits affect the entire device and
format value, which is twos complement. For more information
the channel features for which independent settings are not
on this function and others, see Table 46 to Table 53.
allowed between channels. The settings in Register 0x0005 do not
Open and Reserved Locations affect the global registers and bits.
All address and bit locations that are not included in Table 46 to SPI Soft Reset
Table 53 are not currently supported for this device. Write
After issuing a soft reset by programming 0x81 to Register 0x0000,
unused bits of a valid address location with 0s unless the default
the AD9689 requires 5 ms to recover. When programming the
value is set otherwise. Writing to these locations is required
AD9689 for application setup, ensure that an adequate delay is
only when part of an address location is unassigned (for
programmed into the firmware after asserting the soft reset and
example, Address 0x0561). If the entire address location is open
before starting the device setup.
(for example, Address 0x0013), do not write to this address
location.
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS It is not necessary to split all of these power domains in all cases.
The power supplies required to power the AD9689 are The recommended solution shown in Figure 157 provides the
shown in Table 54. A power-on sequence is not required to lowest noise, highest efficiency power delivery system for the
operate the AD9689. The power supply domains can be AD9689. If only one 0.975 V supply is available, route to AVDD1
powered up in any order. first and then tap it off and isolate it with a ferrite bead or a
filter choke, preceded by decoupling capacitors for AVDD1_SR,
Table 54. Typical Power Supplies for the AD9689 DVDD, and DRVDD1, in that order. Figure 158 shows the
Domain Voltage (V) Tolerance (%) simplified schematic. The dc resistance (DCR) of the ferrite
AVDD1 0.975 ±2.5 bead must be taken into consideration when choosing the
AVDD1_SR 0.975 ±2.5 appropriate ferrite bead. Otherwise, excessive loss across the
DVDD 0.975 ±2.5 ferrite bead can lead to a malfunctioning ADC. Adjustable LDOs
DRVDD1 0.975 ±2.5 can be employed to output a higher voltage to account for the
AVDD2 1.9 ±2.5 drop across the ferrite bead.
DRVDD2 1.9 ±2.5 Alternatively, the LDOs can be bypassed altogether and the
SPIVDD 1.9 ±2.5 AD9689 can be driven directly from the dc-to-dc converter.
AVDD3 2.5 ±2.5 Note that this approach has risks in that there may be more
For applications requiring an optimal high power efficiency and power supply noise inserted into the power supply domains of
low noise performance, it is recommended that the ADP5054 the ADC. To minimize noise, follow the layout guidelines of the
quad switching regulator be used to convert an input voltage in dc-to-dc converter.
the 6.0 V to 15 V range to intermediate rails (1.3 V, 2.4 V, and
1.3V AVDD1
3.0 V). These intermediate rails are then postregulated by very 12V FROM FMC OR ANALOG 0.975V
6.0V FROM WALL SW1 ADP1763
low noise, low dropout (LDO) regulators (ADP1763, ADP7159, SUPPLY AVDD1_SR
SW2 0.975V
and LT3045). Figure 157 shows the recommended power supply 1.3V
DIGITAL DVDD
scheme for the AD9689. ADP5054 0.975V
1.3V AVDD1
6.0V ANALOG SW3
0.975V
TO ADP1763 DRVDD1
AVDD1_SR SW4
15.0V 0.975V
0.975V
OPTIONAL
AVDD2
ADP5054 1.3V
DIGITAL
DVDD 2.4V 1.9V
ADP1763
0.975V LT3045
DRVDD2
DRVDD1 1.9V
0.975V
AVDD2
2.4V 1.9V SPIVDD
LT3045 1.9V
OPTIONAL AVDD3
DRVDD2 FERRITE BEAD
3.0V 2.5V
1.9V LDO LT3045
LT3045 SWITCHER
OPTIONAL PATH
15550-327
NOTES
SPIVDD 1. ALL VOLTAGES REFERENCED TO AGND.
1.9V
AVDD3 Figure 158. Simplified Power Solution for the AD9689
3.0V 2.5V
LT3045
The user can employ several different decoupling capacitors to
LDO cover both high and low frequencies. These capacitors must be
SWITCHER
15550-072
OPTIONAL PATH located close to the point of entry at the PCB level and close to
REFERENCED TO AGND
the devices, with minimal trace lengths.
Figure 157. High Efficiency, Low Noise Power Solution for the AD9689
CH.A
CH.B POWER
15550-328
Figure 159. Recommended PCB Layout for the AD9689
OUTLINE DIMENSIONS
12.10
12.00 SQ A1 BALL
A1 BALL 11.90 PAD CORNER
PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
7.50 SQ 10.40 REF F
SQ G
H
J
0.80 K
11.20 SQ L
M
N
P
1.53 DETAIL A
1.19
1.42 SIDE VIEW
1.09
1.31 DETAIL A 0.99
0.71
REF
0.38
0.33
0.28
0.34 REF
12-07-2015-B
PKG-004807
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9689BBPZ-2000 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-4
AD9689BBPZRL-2000 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-4
AD9689BBPZ-2600 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-4
AD9689BBPZRL-2600 −40°C to +85°C 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] BP-196-4
AD9689-2000EBZ Evaluation Board
AD9689-2600EBZ Evaluation Board
1
Z = RoHS Compliant Part.