UPV - Poliformat - Valencia

Circuitos Electrónicos De Alta Frecuencia
TEMA 2:
COMPONENTES PASIVOS Y ACTIVOS para RF
Máster Universitario en Ingeniería de Telecomunicación

Índice
• Introducción
• Componentes Pasivos
• Resistencias
• Condensadores
• Bobinas
• Componentes Activos
• Mosfet
• Bipolar
• Diodos
• Protecciones ESD
• Encapsulados
• Adaptación de Impedancias

Introducción
• Introducción. Circuitos Equivalentes (… y Resonantes)
𝐸𝑛𝑒𝑟𝑔í𝑎 𝐴𝑙𝑚𝑎𝑐𝑒𝑛𝑎𝑑𝑎
1 1 𝑸 = 𝑤𝑜
𝑌= + 𝑗𝑤𝐶 + 𝑃𝑜𝑡𝑒𝑛𝑐𝑖𝑎 𝐷𝑖𝑠𝑖𝑝𝑎𝑑𝑎
𝑅𝑃 𝑗𝑤𝐿 2
1 𝐼𝑝𝑅
𝐸𝑡𝑜𝑡 = 𝐶. (𝐼𝑝𝑅 . 𝑅𝑃 )2 𝑃𝑑 = . 𝑅𝑃
2 2
1
Resonancia 𝑤0 = Impedancia
𝐿𝐶 𝑅𝑃 𝐿/𝐶 Característica *
𝑸= =
𝐿/𝐶 𝑅𝑆
1
𝑍 = 𝑅𝑆 + 𝑗𝑤𝐿 + 1 𝑉𝑝𝑅
2
𝑗𝑤𝐶 𝐸𝑡𝑜𝑡 = 𝐿. (𝑉𝑝𝑅 /𝑅𝑆 )2 𝑃𝑑 = /𝑅𝑆
2 2
NOTA: L y C son aprox. iguales y RP ≈ RS . Q2

* Valor de la reactancia de L y C en wo 3
Introducción
• Introducción. Circuitos Equivalentes (… y Resonantes II)
1 1 𝑉 𝐼𝑖𝑛 . 𝑅𝑃
𝑌= + 𝑗𝑤𝐶 + 𝐼𝑖𝑛 = 𝐼𝐿 = 𝐼𝐶 = = 𝐼𝑖𝑛 . 𝑅𝑃 . 𝑤𝑜 𝐶
𝑅𝑃 𝑗𝑤𝐿 𝑅𝑃 𝑤𝑜 𝐿
𝐼𝐿 = 𝐼𝐶 = 𝑄. 𝐼𝑖𝑛
1
Resonancia 𝑤0 =
𝐿𝐶
1 𝑉𝑖𝑛 /𝑅𝑆
𝑍 = 𝑅𝑆 + 𝑗𝑤𝐿 + 𝑉𝑖𝑛 = 𝐼 . 𝑅𝑆 𝑉𝐿 = 𝑉𝐶 = = (𝑉𝑖𝑛 /𝑅𝑆 ). 𝑤𝑜 𝐿
𝑗𝑤𝐶 𝑤𝑜 𝐶
𝑉𝐿 = 𝑉𝐶 = 𝑄. 𝑉𝑖𝑛
Tesla Coil ++
4
Introducción
• Introducción. El Proceso de Fabricación de los Circuitos Integrados
Proceso Básico de Fotolitografía Proceso Típico CMOS

Cada paso que necesita una máscara
(etch, implantación etc.) Proceso de
Fotolitografía
www.anandtech.com 5
Introducción
• Introducción. Corte de Die de última tecnología
Componentes Pasivos
• Resistencias. El efecto pelicular (Skin Effect)
Induce corriente que se

suma a la corriente alterna
𝜕𝐽 𝜕𝐻 inicial en la superficie y se
= 𝛻× 𝐸 opone en el centro del
𝜕𝑡 𝜕𝑡
conductor
La corriente decrece de forma exponencial con la distancia a

la superficie: δ
Espesor de corona en la que se

encuentra el 60% de la corriente
7
Componentes Pasivos
• Resistencias. El efecto pelicular (Skin Effect)
resistividad
δ
Cobre (1GHz)  δ=2 µm 𝜌. 𝑙
Aluminio (1GHz)  δ=2.5 µm 𝑅≈
2𝜋𝑟. 𝛿 r
Oro (1GHz)  δ=2.38 µm
Linea bifilar Coaxial
8
Componentes Pasivos
• Resistencias. Discretas para RF
PCB
Vishay RF - Resistors
Casi
𝑅= 𝐿/𝐶 totalmente
Resistivo
OPTIMIZADO para 50Ω
(Mejor Calidad en Terminales)

9
Componentes Pasivos
• Resistencias Discretas para RF. Efecto Parásitos de Encapsulado
SMD Footprints
10
Componentes Pasivos
• Resistencias. Circuitos Integrados
• Resistencias de Polisilicio (Po2 y Po2 HR)
Tolerancia ±20%
Número mínimo de cuadros y anchura para precisión (matching)
Valores elevados con Poli .de alta resistividad (1.2 kΩ/⁭⁭
)
Coeficientes de temperatura reducidos (900 ppm/ºC)
AMS C35 11
Componentes Pasivos
• Resistencias de Pozo y Difusión
– Tolerancia ±10%
– Pozo  1 kΩ/⁭ / Difusión  10 Ω/⁭ ⁭ ~ 150 Ω/⁭⁭
– Pozo  C. Temp. (6200 ppm/ºC) / Difusión  C. Temp. (1500 ppm/ºC)
– Más difíciles de aislar. Más ruidosas
12
Componentes Pasivos
• Condensadores. Discretos
RF
MT-101 “Decoupling Techniques” – Analog Devices 13

Componentes Pasivos
• Condensadores. Discretos para RF
KEMET
Muy importantes los parásitos

derivados del package
14
Componentes Pasivos
• Condensadores Discretos. Respuesta en Frecuencia (Cerámico)
KEMET 33pF (SMD 0805)
Q=1400 SRF
Q=2
15
Componentes Pasivos
• Condensadores Discretos. Desacoplo de Alimentaciones
(Tántalo)
Impedancia de la red de alimentación
Impedancia Combinada por debajo de

Z en todo el rango de freq
Frecuencia Efectiva
Límite de frecuencia fijado por los
parásitos intrínsecos
(la red de desacoplo no tiene efecto más allá)
AN574 - Altera 16
Componentes Pasivos
• Condensadores Integrados (MIM)
 Tolerancia ±15%
 MIM presenta menor influencia del
sustrato
 Coeficiente de temperatura muy lineal
y reducido (18 ~ 45) ppm/ºC
 Coeficiente de BIAS Voltage
extremadamente bajo (-0.51 ppm/V)
Metal TOP (nivel más elevado de metalización). Muy alejado de sustrato
AMS C18
Componentes Pasivos
• Condensadores Integrados (MIM). Estructuras WOVEN y FRACTALES
 Aprovechan las capacidades laterales
 Útiles donde el proceso no incorpore
dieléctricos especiales
Con estructuras
fractales se maximiza el
ratio Perímetro / Área
para tener mayor
capacidad lateral
(Células de Koch)
“Capacity Limits and Matching Properties of Integrated Capacitors” – R. Aparicio et al. IEEE Journal of Solid State Circuits 2002
Componentes Pasivos
• Condensadores Integrados (CPOLY)
 Tolerancia ±15%
 Mucha influencia del sustrato (hasta un 30%
del valor nominal)
 Coeficiente de temperatura penoso:
(30000 ppm/ºC)
 Coeficiente de BIAS Voltage bajo:
(85 ppm/V)
Top
Plate
Bottom
Plate
OBSOLETO. No presente en tecnologías “nuevas”

Componentes Pasivos
• Bobinas. Discretas
.SUBCKT LQP02TN10NH02 port1 port2

C1 port1 port2 9.30e-14
L2 port1 1 1.17e-8
MURATA 10nH R3 port1 port2 9.00e+3
(SMD 0402) R2 1 port2 1.50
L4 port1 2 1.40e-7
R4 2 port2 800
20
Componentes Pasivos
• Bobinas Discretas. Modelos y Tecnologías
MURATA
Baja RDC
Q muy alta
Alta corriente
Q alta
SRF elevada
Tolerancia Baja (Circuitos Resonantes)
Q baja
Valores Elevados
(Choques, Filtros, Adaptación
Impedancias)
21
Componentes Pasivos
• Bobinas Integradas
AMS C35 M4 Inductor.

Igual que thick metal pero de menor espesor
22
Componentes Pasivos
• El uso de componentes discretos es muy complicado por

encima del rango de GHz.
• En soporte PCB con dimensiones comparables a λ se

emplearan las líneas de transmisión como elementos pasivos
para filtros etc.
• El uso de pasivos seguirá vigente en el entorno de los

Circuitos Integrados donde las dimensiones de las líneas no
permiten el uso anterior
23
Componentes Activos
• El transistor bipolar (BJT)
1) El diodo BE se polariza en directa. Se generan las
corrientes de portadores (h- y e++)
2) Los portadores minoritarios en la base (e++) son
acelerados por el E de la zona de deplexión de la
unión BC
3) Para evitar el proceso de recombinación en B afecte
a la corriente de portadores minoritarios (e++) B
debe ser delgada (ttran < trecomb )
PNP Vertical
Las NPN Vertical
estructuras
de fabricación
integrada son
complejas
Necesario aislamiento por deep-trenches o por dieléctricos

24
“The art of Analog Layout” – Alan Hastings
Componentes Activos
• El transistor bipolar (BJT). Modelo Lineal (PS)
𝐴𝐸 Área de la unión de Emisor
𝐴𝐸 𝑞𝐷𝑛 𝑛𝑖2 𝑣𝑉𝐵𝐸 𝐷𝑝 𝑁𝐴 𝑊𝐵 𝑊𝐵2 𝑣𝐵𝐸
𝐷𝑛 Coeficiente de Difusión 𝑖𝑐 ≈ .𝑒 𝑇 𝑖𝐵 ≈ 𝐼𝑆 . ( + ). 𝑒 𝑉𝑇
𝑁𝐴 𝑊𝐵 𝐷𝑛 𝑁𝐷 𝐿𝑝 2𝐷𝑛 𝜏𝑏
𝑊𝐵 Ancho de Base
𝑁𝐴 Densidad de impurezas 𝐼𝑆 𝛽 −1
𝐿𝑝 Longitud de la Difusión
𝜏𝑏 Tiempo vida de cargas en Base
𝐼𝐶
𝑔𝑚 =
𝑉𝑇
Efecto Early
𝑉𝐴
𝑟𝑜 =
𝑣𝐶𝐸 𝑣𝑉𝐵𝐸 𝐼𝐶
𝑖𝑐 = 𝑖𝑆 (1 + )𝑒 𝑇
𝑉𝐴 𝑟𝜇 = 𝑟𝑜 𝛽𝐵𝐼𝐴𝑆
𝛽𝐵𝐼𝐴𝑆
𝜕𝑉𝐶𝐸 𝑟𝜋 =
𝑉𝐴 = −𝑊𝐵 𝑔𝑚
𝜕𝑊𝐵
𝐶𝜋 = 𝜏𝐹 𝑔𝑚 + 𝐶𝑗𝑒
25
“Analysis and Design of Analog Integrated Circuits” P. Gray et al.
Componentes Activos
• El transistor bipolar (BJT). Modelo No Lineal (Modified Gummel-Poon )
Se puede obtener directamente la matriz de parámetros S a partir del modelo de

pequeña señal de Gummel *
“Improved Closed-Form Expressions for S-Parameters of BJTs Using Modified Gummel-Poon Model”
“RF Front-end” J. Sullivan A.E. Nadeem – IEEE INMIC 2003 26
Componentes Activos
• El transistor de efecto de campo (MOSFET)
n-MOS PoliSi Al / Cu p-MOS PoliSi Al / Cu
thinox thinox
D Substrato Substrato
D
n-MOS p-MOS
G G
Acumulación Acumulación
S S
27
Componentes Activos
Índice de
Inversión Región Saturación VDS  VGS  VT
INVERSIÓN FUERTE (Ic>10) INVERSIÓN MODERADA (Ic = 1)
𝑊 𝑉𝐺𝑆 −𝑉𝑇
Kp W
I DS  . [(VGS  VT ) 2 ] 𝐼𝐷 = 𝐼0 𝐿𝑛 1 + 𝑒 2𝑛𝑈𝑇
2.n L 𝐿
Kp
I DS  .[(VGS  VT ) 2 ].[1   .VDS ]
2.n INVERSIÓN DÉBIL (Ic < 0.1)
Modulación de la Longitud de Canal
𝑊 𝑉𝐺𝑆 −𝑉𝑇
𝐼𝐷 = 𝐼0 𝑒 𝑛𝑈𝑇
Región Lineal VDS  VGS  VT 𝐿
Kp W 2
VDS 𝑉𝐵𝐸
I DS  . [(VGS  VT ).VDS  ] BJT  𝐼𝐶 = 𝐼𝑆 𝑒 𝑈𝑇
2.n L 2
Las áreas de puerta necesarias para Moderada y Débil hacen imposible trabajar en RF
28
Componentes Activos
D
Cgd Cdb
G B
Cgs Csb
Cgb
S
Inversión Fuerte
1
𝐾𝑃 𝑊 𝑟𝑑 =
𝑔𝑚 = 2𝐼𝐷
𝑛 𝐿
𝜆. 𝐼𝐷
Inversión Débil λ depende inv. con L

𝐼𝐷
𝑔𝑚 =
𝑛. 𝑈𝑇
Inversión Moderada
𝐾𝑃 𝑊
𝑔𝑚 = 2 𝐼𝐷 − 𝐼𝐷𝑚𝑖𝑛
𝑛 𝐿
29
Componentes Activos
Velocidad de Saturación:
Cuando la zona de pinch-off es comparable a L (VD >> VG)
v   .E vSAT Velocidad máxima de las cargas en el canal
iD
𝑄𝐶 = 𝐶𝑜𝑥 . 𝑊. 𝐿. (𝑉𝐺𝑆 − 𝑉𝑡 )
W
I DS  vSAT .COX .W .[(VGS  VT )]   n Ecrn .COX .W .[(VGS  VT )]   n .COX . .[(VGS  VT )].VDS ( vsat )
L
L.vSAT nMOS (L=130n) ↓↓

VDS ( vsat) 
n VDS(Vsat) = 0.34V
VGS
 Para NMOS la VDS es más restrictiva
 Con VDS elevadas (AMSC35 > 0.8 V) podemos tener serios problemas
 Con VDS cercana a ΔV el efecto es sólo patente en tecnologías < 180nm
30
Componentes Activos
• El MOSFET. Figura de Mérito (fT)
Frecuencia a la que la corriente de entrada al MOSFET es igual a la de salida
n: Slope Factor
K W
2.I D . PP .
1 g m .VGS 1 n L 1
fT   fT  fT 
2 Cgs .VGS 2 2 C  L3/2 La L es el factor más
W.L.C ox   GSO 
 3 LCox  1 limitante en fT
f T  1/2
2 C  W
Cgs  W.L.C ox   GSO 
 3 LCox 
Para el caso de alcanzar la vSAT la

dependencia con L no es tan fuerte pero
2/3 de CG + W.CGSO L sigue dominando
31
Componentes Activos
• El MOSFET. Frecuencia máxima útil (fc)
La frecuencia de atenuación a -3 dB de la señal en la puerta

(La resistencia y capacidad parásitas de la puerta actúan como una RC distribuida)
* 0.124 Mucho cuidado con W

fc 
R sh Cox W 2 SOLUCIÓN: MULTIFINGER
Rpoly Capacidad Óxido

puerta
AMS C35 / NMOS (40u/0.35u)  1,1 GHz
Para poder alcanzar 5GHz  2 x finger W=20u
32
* “Fundamentals of High-Frequency CMOS Analog Integrated Circuits” D. Leblebici, Y. Leblebici
Componentes Activos
• El MOSFET. TRADE-OFFs
L mínima
K PP W
2.I D . .
1 n L
fT 
2 2 C 
W.L.C ox   GSO 
 3 LCox 
Gm ↓
0.124
fc  ¿ Cómo se Id  VGS  VDS 
R sh Cox W 2
obtiene
Más Cuidado con
ganancia ?
W reducida consumo la velocidad
de saturación
33
Componentes Activos
• Transistores de RF. HBT, MESFET y HMET
MESFET: MOSFET sin aislamiento de puerta. Esto

obliga a trabajar en regiones de polarización
concretas para evitar la conducción por puerta
(JFET con unión Metal-SemiCond)
HMET: Se crea un canal físico con un dopaje muy

elevado empleando un semicond con movilidad
elevada (GaAs)
HBT: Transistor Bipolar con diferentes tipos de

semiconductores y perfiles de dopado que
favorecen el transporte de portadores
mayoritarios reduciendo la resistencia de base
34
Componentes Activos
• Diodos PIN
• Diodo con una zona intermedia de semiconductor
intrínseco.
• Funciona por “inundación” de la zona Intrínseca.
• En RF la alta densidad de cargas provoca una Req
modulable por la polarización (se pueden obtener
valores muy bajos y muy lineales)
• Se puede usar como interruptor en RF o atenuador
variable
• Varactores
• Diodo en polarización inversa.
• La tensión modula el tamaño de la zona de
deplexión. Menor tensión, menor zona dep, mayor
capacidad
• Como toda unión PN sufre grandes variaciones con
la temperatura
• La Q no permanece constante en el rango de ajuste.
Suele empeorar con el valor de la capacidad. Por lo
tanto se usa asociado a otra capacidad fija y se
limita el rango de ajuste
35
Protecciones ESD
• Human Body Model
Evento de descarga electrostática producida por un humano “típico”
cargado eléctricamente al tocar un componente
CLASS 1 HV < 2kV

CLASS 2 2kV < HV < 4kV
CLASS 3 HV > 4kV
Otros modelos incorporan efectos

inductivos en la descarga:
- Machine Model
- Charged Device Model
36
Protecciones ESD
• Componentes Integrados para Protección
Los mecanismos básicos de protección

buscan provocar una gran descarga de
B corriente:
- A tensión de codo cte (A) (V aumenta)
- A tensiones < Vbreakdown para evitar daños
A en los dieléctricos (B)
SCR
(Latchup!)
Snap-back BJT Snap-back MOSFET (BJT parasitics)

Diodos (Clamp)
37
“On chip ESD Protection for Integrated Circuits” – A. H. Wang
Protecciones ESD
• Esquema básico de protecciones ESD
Cuidado en aplicaciones
RF o de Zin ↓
38
Encapsulados
QFP-80
QFN: Tamaño reducido, sin pines

salientes (pocos pines).
Menos parásitos
Frecuencias hasta 20 GHz
39
“Design Optimization of QFP Structure for over 8Gbps Package Applications” – H. Sun et al.
Adaptación de Impedancias
• ¿Cuál es el origen de los valores 50Ω y 75Ω?
MÁXIMA POTENCIA CONDUCIDA POR UN CABLE COAXIAL
𝑉 b  mejora la
𝐸𝑚𝑎𝑥 = potencia pero
b 𝑎. 𝐿𝑛(𝑏/𝑎) La rotura del
dieléctrico marca aumenta Zo
a 𝜇 𝐿𝑛(𝑏/𝑎) Pmax (ÓPTIMO para
𝑍𝑜 = . POTENCIA MAX
𝜀 2𝜋
ENTREGADA???)
𝑉2 𝑏
𝑃𝑚𝑎𝑥 ∝ = 𝑒 𝒁𝒐 = 𝟑𝟎 Ω
𝑍𝑜 𝑎
40
40
MÍNIMA ATENUACIÓN EN UN CABLE COAXIAL
𝑅 La atenuación es proporcional a la resistencia

𝛼 ≈
b 2𝑍𝑜 por unidad de longitud*
a
R es debida al efecto a  reduce R pero 𝜇 𝐿𝑛(𝑏/𝑎)
𝑍𝑜 = .
pelicular (skin-effect) también reduce Zo 𝜀 2𝜋
Empleando una expresión aproximada

𝑏
para el efecto resistivo pelicular y = 3.6 𝒁𝒐 ≈ 𝟕𝟓 Ω
derivando para obtener el óptimo de a 𝑎
* “Design of CMOS RF Integrated Circuits”- T. Lee 41

MÁXIMA POTENCIA MÍNIMA ATENUACIÓN

30 Ω 75 Ω
BALANCE ENTRE LAS

DOS
Zo = 50 Ω
42
High Frequency Electronic Circuits
Noise & Low Noise Amplifiers (LNA)
Departamento de Ingeniería Electrónica

Universitat Politècnica de València (UPV)

Index
• Introduction
• Noise Types and Sources
• Noise in Electronic Components
• Generic Noise Equivalent Circuits
• System Level Noise Treatment
• Low Noise Amplifiers (LNAs)

• Design specs
• Subsystem Level issues
• Device Level issues

Introduction
• Introduction. Useful things to remember (I)
SNRIN
NF  NF2  1 NFm  1
SNROUT FRIIS : NFT  NF1   ... 
NFPASSIVE  L( LOSSES ) A1 A1A 2 ...A m
Maximum Available Noise Power

2
 Zin 
Impedance Matched
2
v onRs  4kTRs    kTRs
System  Rs  Zin 
kTRs
PonRs   kT ( 174 dBm/Hz) . B
Zin = Rs Zin
3
Introduction
• Introduction. Useful things to remember (II)
Amplifier with source Ideal impedance match conditions MTP
*
P kT.G  PnoAMP PniAMP TeqAMP v n2 OUT(total)
NF  in .  1  1 NF 
kT Pin .G kT To A 2kTR
MT-052 TUTORIAL /
Analog devices 4
Noise
• Noise Types. SHOT NOISE

- Realted to PN unions working under direct 𝑖 2 = 2𝑞𝐼𝐷 . ∆𝑓
biasing (ON state).
- Charges require a certain energy to pass the
union voltage barrier. Noise Current White Noise
- Since this is a statistical process (…) a certain Spectral Density
variance is associated (NOISE) 𝜏𝑒,ℎ << (1/Fworking )
Interpretación
Interpretation
Sigue
Followsuna
a
𝑖 = 𝐼 + 𝑑𝐼 distribución
Gaussian
Gaussiana
Distribution
2
5
Gray-Meyer – “Analysis and Design of Analog Integrated Circuits”
Noise
• Noise Types. THERMAL NOISE
- Random charge movement inside a resistive

Voltage/ Current
element. Noise Spectral
- Bias current independent. Density
- Temperature proportional.
White Noise
Useful Data for napkin calculations:
1kΩ  4 nV/√Hz
Thermal Noise 1kΩ ≡ Shot Noise 50uA
6
Noise
Other Noise types
• Flicker Noise (1/f)

- Active Devices and some passives (semicon. based)
- Charge Traps (Si crystal failures). Noise Current
- Higher in Low Freq. (below MHz) though can have a Spectral Density
strong effect if thermal noise is low.
• Popcorn Noise
- Low Frequency.
- Comes from heavy (high Z) dopants (gold)
• Avalanche (Dark Noise)

100 nV/√Hz
- Associated to OFF state PN unions (zeners).
- BIAS circuitry critical.
- Constant p.s.d (white) but not Gaussian (Poisson)
7
Noise
• Noise Equivalent Circuit. DIODES
Thermal Noise due to

difussion resistivity
Shot noise in PN union

+ Flicker Noise
AC diode
resistance
8
Noise
• Noise Equivalent Circuit. Bipolar Transistor
Shot Noise in Base-

Base Resistor Collector PN Union
Corner Frequency
Flicker noise in BJT is low

and fa is low
9
Noise
• Noise Equivalent Circuit. MOSFET
Thermal Noise
1 1
R .
4kT MOSFET n. g m
2
i
nT  f channel has
R a resistive
nature n Slope Factor (1.3)
Thermal Noise in
resistive element 
Weak Inv.: 0.5 2
inT  4kT .n..g m f
Strong Inv.: 0.67
Flicker Noise
Due to the charges K f

interaction in the SiO2 vnf2 
interphase
CoxWL f AF
AF  Freq. coefficient ( ~ 1 ) 10
Noise
• Noise Equivalent Circuit. Equivalent Simplifications
Gate related Total Noise (MOSFET)
𝑣𝑔𝑠 = 𝑅𝑠 𝑖𝑛 − 𝑔𝑚 𝑣𝑔𝑠 𝑣0 = −𝑔𝑚 𝑣𝑔𝑠 𝑅𝐷
𝑣0 = 𝑔𝑚 𝑣𝑔𝑠 − 𝑖𝑛 𝑅𝐷
𝑣𝑛 − 𝑔𝑚 𝑣𝑔𝑠 ⋅ 𝑅𝑠 = 𝑣𝑔𝑠
𝑅𝐷
𝑣0 = 𝑖 𝑔𝑚 𝑅𝐷
1 + 𝑔𝑚 𝑅𝑠 𝑛 𝑣0 = 𝑣
in2 1 + 𝑔𝑚 𝑅𝑠 𝑛
v 
2
n
( gm )2
Both circuits are equivalent TOTAL referido a puerta
THERMAL
2
inT  4kT .n..g m f
2
 i  4kT .n. K f
2
 i  4kT .n vn2  n   f 
vnT2   nT   f  gm  gm CoxWL f AF
 gm  gm
11
Noise
- Non-correlated sources
• Noise Calculations. Example 1 - Reactances don’t add noise
(only change its freq. shape)
Zx vn22
in2
2
inREF in21 RFTE
g m1v gs g m 2 v gs
rd
1 gm2 2
ZX 
2
inREFo  inREF
2
( )
• The goal is to obtain de transfer g m1
g m1
function from each noise source to the
output.
gm2 2
2
inEQo  inREFo
2
 in21o  in22 o in21o  in21 ( )
• Remember we deal with quadratic g m1
magnitudes
• Each source will be analyzed

2
inEQo in22o  vn22 ( g m 2 ) 2
i2

disconnecting the other ones nEQi
gm2
( )2
g m1 12
Noise
• Noise Calculations. Example 2
v2nRb
What is the maximum equivalent
Rb
noise level of the amplifier if a 12
Ra
effective bits resolution is
ADC required?
2 Fondo Escala 2V
v nRa v2An 12 bits
DATA: BW = 100MHz // 4kT=1,65E-20 []
Rb=12KΩ // Ra=1.2KΩ
2 2 2 2 2
2
𝑅𝑏 2 𝑣𝑛𝑂𝑈𝑇 = 𝑣𝑛𝑅𝑎_𝑂𝑈𝑇 + 𝑣𝑛𝐴_𝑂𝑈𝑇 + 𝑣𝑛𝑅𝑏_𝑂𝑈𝑇
𝑣𝑛𝑅𝑎_𝑂𝑈𝑇 = . 𝑣𝑛𝑅𝑎
𝑅𝑎
2
2 2 0.2 uV2 0.020 uV2
2
𝑅𝑏 2 212
𝑣𝑛𝐴_𝑂𝑈𝑇 = 1+ . 𝑣𝑛𝐴 0.0184 uV2 (136 uVrms)
𝑅𝑎
2
𝑣𝑛𝑅𝑏_𝑂𝑈𝑇 2
= 𝑣𝑛𝑅𝑏 0.0184 uV2
2 = 1.23 𝑛𝑉
11 . 100 𝑀𝐻𝑧 𝐻𝑧
13
Noise
• Generic Noise Equivalents.
SOURCE IMPEDANCE EFFECT
Zin
2
 Zin  2 Zin.Rs 2
(v    in (
2
) ) Valid for any

n
Zin  Rs  Zin  Rs ( v n2  i n2 (Rs)2 )
NF  1  2
 1 impedance
 Zin  4kTRs
4kTRs  
 Zin  Rs 
4kTRs v n2 2 (Rs)2
v n2 OUT(total)  (  in ) v2
Rs ↓↓ NF  Impedance NF  4 4 4  2
nOUT(total )
2
A 4kTRs 4kTRs A kTRs
Matching
4
14
Noise
• Generic Noise Equivalents.
Generic Equivalent valid for

any source impedance
15
Noise
• Noise Equivalent. BJT rb << rπ 𝑔𝑚 𝑣𝑏 + 𝑖𝑐 = 𝑔𝑚 𝑣𝑖
𝑖𝑐2
𝑣𝑖2 = 𝑣𝑏2 + 2
𝑔𝑚
𝐼
𝑔𝑚 = 𝑘𝑇𝑐
𝑞
Noise Req
Shot Noise - Ieq
16
Noise
• Noise Equivalent. BJT (Calculations)
𝑣𝑖𝑁 𝑍𝑖𝑛 𝑣𝑠 𝑍𝑖𝑛 𝑣𝑖 𝑍𝑖𝑛 𝑅𝑠 𝑍𝑖𝑛

= + + 𝑖𝑖
𝑍𝑖𝑛 + 𝑅𝑠 𝑍𝑖𝑛 + 𝑅𝑠 𝑍𝑖𝑛 + 𝑅𝑠 𝑍𝑖𝑛 + 𝑅𝑠
17
Noise
• Noise Equivalents. MOSFET 𝑖𝑑 = 𝑔𝑚 𝑣𝑖
2
𝑖 𝑑
𝑣𝑖2 = 2
𝑔𝑚
1
( )
n.
Noise Req
Gray-Meyer – “Analysis and Design of Analog Integrated Circuits” 18

Noise
• Noise in transistors: MOSFET vs BJT
MOSFET BJT
0.7
(
1
n.
)
> rb ↓↓
gmBJT > gmMOSFET
0
<
MOSFET is better with high source impedances (i2)
BJT is better with lower source impedances (v2) *
* This is a general conclusion. It might depend on specific design conditions 19

Noise
• Noise Equivalents. Amplifiers
Equivalent Short-circuit
 Equivalent noise voltage
at the input
Equivalent Open-circuit
 Equivalent noise current
at the input
20
Noise
• In homogeneus systems, the NF and the Friis eq are
enough for noise calculations. However in
heterogeneus systems with different impedances… Source Impedance =
500 Ohms
With negligible i2n components, translating With non-negligible i2n the noise
NF(50Ω) to NF(500Ω): equivalent is required:
(page 14)
NF ¿?
𝑣𝑛2 𝑣𝑛2 (𝑁𝐹𝐴𝑖𝑓_50 −1) 50 500
𝑁𝐹𝐴 = 1 + 𝑁𝐹𝐵 = 1 + 𝑁𝐹500 = 𝑁𝐹𝑚𝑖𝑥𝑒𝑟 +
4𝑘𝑇𝑅𝑠𝐴 4𝑘𝑇𝑅𝑠𝐵 𝑉2 𝑉2
( 𝑜 500)/( 𝑖 50)
(𝑁𝐹𝐴 −1)𝑅𝑠𝐴 = (𝑁𝐹𝐵 −1)𝑅𝑠𝐵 (𝑵𝑭𝑨𝒊𝒇_𝟓𝟎 −𝟏)

𝑵𝑭𝟓𝟎𝟎 = 𝑵𝑭𝒎𝒊𝒙𝒆𝒓 +
𝑨𝟐𝑽𝒎𝒊𝒙𝒆𝒓
Razavi – “RF Microelectronics” 21
Noise
50 Ω 500 Ω
NFE (dB )  NF6(500 ) (dB )  L 5 (dB )  15 dB

NFE  1
NFD  NF4(500 )   25.53 (14.1 dB )
A P4
NFC (dB )  NFD (dB )  L 3 (dB )  20.1 dB
NFC  1
NFB  NF2(50 )   4.78 (6.79 dB )
(A V2 ) 2
NFA (dB )  NFB (dB )  L1 (dB )  8.79 dB
Regla: Rout1≠RNF2  Divide by Av2

Distorsion Measurements. SFDR
• Compresion. IP3
Compresion
Point 3 4 1
1A IP3   3A 3IP3  A IP3 
(-1 dB) 4 3 3
A w1,w2 1A in 4 1 1
A w1,w2  
A IM3 (3/4) 3A in 3  3 A in2
3
A IM3 A IM3 A w1,w2 A 2IP3

 2
A IM3 A in
1
20log(A IP3 )  (20log A w1, w2 - 20log A IM3 )  20log A in
2
A1 = A2
P  PIM3out P  PIM3in 3PIN  PIM3in
PIIP3  PIN  OUT  PIN  IN 
2 2 2
2P  PIM3in
PIN  IIP3 Input Equivalent
3 Noise Power for
IM3out (assuming
a linear system)

Distorsion Measurements. SFDR
• Spurious Free Dynamic Range (SFDR)

Intermodulation Maximum Input in a 2 tone test for
Distortion IM3 = noise floor
Spurious Free (IM3 are the key!! (2f0 – f1) ≈ f0)
Dynamic Range
Sensitivity Noise Floor
Inermodulation 2PIIP3  PIM3in

PINmax   PIM3in  174 dBm  NF  10log(B) Noise equals IM3out
Distortion 3
Minimum signal for

Sensitivity PINmin  174 dBm  NF  10log(B)  SNR out-min SNRout-min
2(PIIP3  174 dBm  NF  10log(B))

SFDR  - SNR out -min
3
24
Low Noise Amplifiers (LNA)
• Design Specifications for a LNA
• Noise Figure
• Gain
• Matching
• Bandwidth
• Linearity
• Dynamic Range
Factors to be
considered in a LNA
design process
Microelectrónics Subsystem (PCB)

25
• LNA Design Specifications
Receptor
Input
SFDR with the highest

interference signal in the
receptor
26
Tim Das (Freescale Semi.) – “Practical Considerations for Low Noise Amplifier Design”
• LNA Design Specifications
2PIIP3  PIM3in
PIN 
3
Input Referred PIM3in  3PIN  2PIIP3
G1   NF ↓↓
G1 TRADE-OFF
 P1dBinput ↓↓
LNA gain should be enough to control the noise chain without clipping the dynamic range
Prin (sensitivity ≡ noise floor) shows that for a given NF is better to reduce bandwidth to the lowest
affordable for the application
In presence of interferring signals (desensitivization), LNA linearity reduces IMD3 allowing a higher
SFDR. A 1 dB improvement in IIP3 translates into a 2 dB increase in the SFDR
27
• Design Constraints (Subsystem Level)
IMPEDANCE MATCHING
Noise (POV)  Impedance which minimizes NF (impedance translator?)
Power (POV)  Impedance Matching (MPT)
Usually a mixed approach strategy is used (impedance, noise and

maximum available gain)
GOAL: Obtain an impedance matching with the lowest NF
28
IMPEDANCE MATCHING – NOISE - GAIN

In the traditional approach the admitance model
and Y parameters are used
Fmin  Minimum Noise Factor
rn  Noise Req normalized
yopt  Admitancia obtenida para Fmin
gs  real part of Ys
Usually Γopt doesn’t provide impedance matching

nor the highest gain
! f NFmin Gammaopt rn/50

! GHz dB MAG ANG - Touchstone File
1.900 0.60 0.15 39 0.15
2.400 0.63 0.15 46 0.14 Noise Data
3.500 0.73 0.13 57 0.13
H.A. Haus et al., “Representation of noise in linear two-ports,”

Proc. IEEE, Vol. 48, Iss. 1, Jan. 1960, pp. 69–74. 29
Microwave and RF Design. A systems approach – Michael Steer 30

GMA
31
STABILITY
Oscillation limit for extreme cases (ΓL=1 y Γs =1). STABILITY CIRCLES
S
STABILITY
Input Circles  Γs stable zone Output circles  ΓL stable zone
But BE CAREFUL, the stability conditions must be

fulfilled for ALL the frequencies (including those
out of the band of interest)
Usually an absolutely stable design is preferred
even if some gain is sacrificed (see Rollet (k) &
Edwards-Sinsky (µ) criteria)
IMPEDANCE MATCHING
H. M. Cheema, A. Shamim – “The Last Frontier”

IEEE Microwave Magazine
34
• Device Level Issues
IMPEDANCE MATCHING
• Antenna plus LNA Integration inside the same device allows a better optimization
(LNA + Antenna optimization). Ideal Case: Antenna-On-Chip
• More design freedom. Impedance matching can be relaxed (50 Ω).
• Kirchhoff “friendly” up to many GigaHertz.
• Transistor level optimization (sizing etc) to enhance performance reducing external
components.
• Feedback techniques can be employed in order to enhance stability and meet all the
specs (see Inductive Source Degeneration)
• Parasitics are lower and better characterized. Sometimes can be even used as a
part of the design (see bonding wire inductance).
35
IMPEDANCE MATCHING (Antennas).

F-1 Antenna Specs and matching
GOAL: Cancel reactance & match RA / Ri

36
Impedance Matching Design Options

TERMINAL RESISTOR see page 4
RP RS
4kTR S ( ) 2  4kTR P ( )2
2
VnOUT R P  RS R P  RS R
NF  2   1 S
A 4kTR S RP RP
( ) 2 4kTR S
R P  RS
NF = 2 (3 dB)
Resistor Divider only
FEEDBACK (voltage – current)
Achieve stability conditions is VERY DIFFICULT in RF

Circuit complexity increases NF
37

Common Gate Configuration
4kT .γ
v 2n 
gm
2
γ L  γ
3
VnOUT _ MOSFET 2 MTP

VnOUT_MOSFET  g m .v gs .Z L 
gmZ L VnOUT
NF  2  1 γ
v gs  vn  g m .v gs .Rs vn 1  g m .Rs A kTR S
A  gmZ L
vn
v gs  2
1  g m .Rs 2
VnOUT  1  4kT .
2
  
 1  g .R  g  kT .RS    kT .Rs (1   )
Adaptación _ MTP
A  m s  m
38

Inductive Source Degeneration
1 L
Zin   L.j  gm
C GS .j C GS
Cancel Reactance Match R
MTP
• Gain reduction γ
• Can be used for stabilization NF  1 
• L is usually very low, same order or even g m RA
lower than parasitics ground bond wire Same as Commun Source without
matching (BEST??)
39
Inductive Source Degeneration. EXAMPLE:
x
Fijamos la ganancia como parámetro
Inductive Source Degeneration.
Potentially Unstable
NFmin = 0.75 dB
Unconditionally Stable NFmin = 0.89 dB
L=0.3 nH
Inductive Source Degeneration. Conclusions
Gmax=23dB
Gmax=15 dB
Useful Topologies
Common – SOURCE CASCODE

Inductive Degeneration
48
Useful Topologies
49
• Other design issues
Load Tuning (Output swing)
Microwave and RF Design. A systems approach – Michael Steer 50

Device parameter behavior as a function of BIAS point.
WATCH OUT!! DO NOT FORGET ABOUT POWER CONSUMPTION (BATTERY POWERED DEVICES)
51
CHOOSING DEVICE TECHNOLOGY
52
Chapter 8 – Oscillators (I)
Feedback oscillators. Negative resistance oscillators.

Máster Universitario en Ingeniería de Telecomunicación (MUIT)
2/43
 Outline
 Basic concepts
 Positive Feedback Oscillators
 Negative Resistance Oscillators
 Appendix – Matching Networks
 Voltage Controlled Oscillators (VCOs)

 Phase Noise
 Practical Considerations
High Frequency Electronic Circuits 2016/2017

3/43
 Basic concepts

4/43
 Introduction
 Oscillators are one-terminal circuits producing a periodical output upon power up

 They are used in numerous applications: signal sources, modulation and demodulation,
frequency conversion,…,
 They can be generally divided into two types:
― R-C or relaxation oscillators
― L-C or harmonic oscillators
Relaxation oscillators have two unstable states and the circuit switches back-and-forth
between them usually producing square waves
Harmonic oscillators can produce nearly sinusoidal outputs due to the use of resonant
L-C selective circuits and can be seen from two different perspectives:
― Positive feedback oscillators (Control Theory)
― Negative resistance oscillators
 Typical resonant circuits are based on lumped elements and quartz crystal (< 500 MHz),
transmission lines (<5 GHz) or dielectric resonators (from 2 up to 40 GHz).

5/43
 Positive feedback oscillators

Positive Feedback Oscillators 6/43
 Principles of Operation
 This is the classical approach based on control theory concepts

If we assume a high impedance at the input of both feedback network H(s) and amplifier
A(s) a simple transfer function can be extracted
+ E(s)
VI(s) A(s) VO(s) 𝑉0 𝑠 = 𝐴(𝑠)𝑉𝐼 𝑠 + 𝐻 𝑠 𝐴 𝑠 𝑉𝐼 (𝑠)
+
𝑉𝑜 (𝑠) 𝐴(𝑠)
=
𝑉𝐼 (𝑠) 1 − 𝐴 𝑠 𝐻(𝑠)
H(s)
Loop gain
 We can get a non-zero output at VO(s) if loop gain A(s)H(s) = 1, then the circuit oscillates
at s=jw where this condition holds
 VI(s) is either thermal noise or the step response due to circuit power up

 The conditions for sustained oscillation are from the positive feedback perspective:
ℜ 𝐴 𝑠 𝐻 𝑠 =1
Barkhausen criterion Total shift around
ℑ 𝐴 𝑠 𝐻 𝑠 =0
the loop is zero
 However, for oscillation to start-up the loop gain must be greater than unity due to gain
reduction when the oscillator begins to saturate
𝐴 𝑠 𝐻 𝑠 >1 Start-up condition
 The steady state condition is then reached when A(s)H(s) = 1
 For preventing multiple simultaneous oscillations, the Barkhausen criterion must be

satisfied at just one frequency
 Usually the amplifier A(s) is designed as a wideband device, while the oscillation
frequency is selected by the feedback network H(s)

 In general, P or T networks are used for implementing the feedback network H(s)
 It can be demonstrated that reactances X1, X2 and X3 must fulfill the following condition:
𝑋1 + 𝑋2 = −𝑋3
+ E(s)
VI(s) A(s) VO(s)
+
X3
X1 X2

 General Analysis for Transistor Oscillators
 A general analysis can be performed for transistor oscillator circuits
 We have assumed a unilateral transistor, real input/output admittances and a bridged-T

feedback network based on reactive elements Y1, Y2 and Y3
 Common-emitter/source, common-base/gate and common-collector/drain configurations

can be obtained by grounding V2, V1 or V4 respectively
 A feedback path can be introduced by connecting the corresponding input/output nodes

 General Analysis for Transistor Oscillators
 The indefinite admittance matrix can be computed by applying KCL to the four nodes of
the circuit
෍ 𝐼𝑘 = 0
𝑖=0
 From this 4-port admittance matrix, a simplified 2-port matrix can be obtained by
considering the grounded node (Vi = 0) and the feedback path (Vj=Vk)
 If a node is grounded the corresponding row and column can be annihilated
 If two nodes are short-circuited the corresponding rows and columns can be combined
 Thus, the order of the matrix can be reduced by two in a feedback transistor oscillator

 Example: BJT Common Emitter
 In this case we have V2 = 0 and collector feedback V3 = V4

 For a bipolar transistor we can assume Go = 0
 We can reduce the indefinite admittance matrix of the general equivalent circuit as
If the feedback network is based on purely reactive elements then Y1 = jB1, Y2 = jB2 and
Y3 = jB3

The former equations must be satisfied for non-zero values of V1 and V = V3 = V4, so the
determinant of the matrix must be zero
By separating the real and imaginary parts of the determinant we can get the following
two equations:
Set the oscillation frequency
Necessary condition for oscillation
 Similar approach can be applied to other transistors (e.g. FET with Gi = 0)

 Different oscillators depending on the feedback network implementation
Colpitts Clapp Hartley
 For instance, in a Colpitts oscillator

 Summary
 At higher frequencies, the loading effect of the amplifier and feedback

network cannot be neglected and must be included in the actual loop gain
equation.
 Obtaining loop gain can be difficult at very high frequencies.
 Multiple feedback paths can be present due to parasitic elements and

couplings. It can be very difficult to distinguish between amplifier and
feedback path in some cases.
 Eventually, the positive feedback approach is restricted to operating

frequencies below 500 MHz.

15/43
 Negative resistance oscillators

Negative Resistance Oscillators 16/43
 Introduction
 The oscillator can be seen as an amplifier producing an output when no

input is present  Unstable amplifier
 For destabilizing an amplifier the load ZL or source ZS impedance is

chosen within the unstable regions resulting in |G1| > 1 or |G2| > 1
respectively
A reflection coefficient magnitude greater than one corresponds to a

negative resistance on that particular port
 For instance, if a load impedance has been chosen for |G1| > 1 then the
source impedance ZS is designed to enforce |G1 Gs|> 1
 In a fixed frequency oscillator, this condition only holds at one frequency

 Negative Resistance Analysis
 Oscillation conditions can be studied in terms of terminal impedances
 Consider a series network for modelling source and input of the amplifier
𝑅1 + 𝑗𝑋1
𝑉= ·𝑉
𝑅𝑠 + 𝑅1 + 𝑗(𝑋𝑠 + 𝑋1 ) 𝑠

Let consider without loss of generality a series R-C network for the source and a series
R-L network for the amplifier circuit
 In the Laplace domain the voltage V(s) can be expressed as
𝑅1 + 𝑠𝐿1
𝑉(𝑠) = · 𝑉𝑠 (𝑠)
1
𝑅𝑠 + 𝑅1 + 𝑠𝐿1 +
𝑠𝐶𝑠

 The former equation can be written in a canonical form as:
𝑉(𝑠) 1 𝑠(𝑅1 + 𝑠𝐿1 ) 𝑠𝐶𝑠 (𝑅1 + 𝑠𝐿1 )𝜔𝑛2

= = 2
𝑉𝑠 (𝑠) 𝐿1 𝑠 2 + 𝑠(𝑅1 + 𝑅𝑠 ) + 1 𝑠 + 2𝜔𝑛 𝛿𝑠 + 𝜔𝑛2
𝐿1 𝐿𝑠 𝐶𝑠
𝑅1 + 𝑅𝑠 1
𝛿= Damping Factor 𝜔𝑛 = 2 Natural Frequency
2 𝐿1 𝐿1 𝐶𝑠
ൗ𝐶
𝑠
 Corresponds to a 2nd order system with two poles given by
𝑝1,2 = −𝛿𝜔𝑛 ± 𝜔𝑛 𝛿 2 − 1
Thus, if (R1+Rs) < 0 then the damping factor d is negative. If the system is under-damped
|d|<1, the poles will be complex and located at the right-hand side of the complex plane
 A proper negative value of R1 can be obtained by conveniently modifying the amplifier
circuit: introducing local positive feedback or choosing a convenient ZL

 A small perturbation will result in an oscillating signal that grows exponentially with
frequency:
𝜔𝑛 𝛿 2 − 1
 When the signal amplitude increases, non-linear phenomena will occur limiting the gain
of the device and reducing the magnitude of the negative resistance R1
 Atsteady-state the damping factor is d = 0 and the poles are then located on the
imaginary axis
 The steady-state oscillation frequency is the natural frequency of the system and
corresponds to
1
𝜔𝑛2 = ⇒ 𝑋1 + 𝑋𝑠 = 0
𝐿1 𝐶𝑠

 Summary
 Conditions for the oscillation to start-up and reach steady-state
(𝑅1 +𝑅𝑠 )|𝜔0 < 0 (𝑅1 +𝑅𝑠 )|𝜔0 = 0

Start-up Steady-state
(𝑋1 +𝑋𝑠 )|𝜔0 = 0 (𝑋1 +𝑋𝑠 )|𝜔0 = 0
 The steady-state frequency of oscillation is fixed by the series network that is

also called the resonator circuit. It has a direct impact on the performance of
the oscillator (i.e. phase noise)
 Oscillation will always occur at both ports simultaneously

 Design Procedure
Step 1) Design the amplifier circuit
Step 2) De-stabilize the amplifier by introducing local feedback
Step 3) Obtain the active circuit S-parameters at the desired frequency
Step 4) Choose GL in the unstable region to fix R1 < 0 with the aid of load stability circles
Step 5) Compute Z1 = R1 + jX1 and find Rs and Xs in order to meet the start-up oscillation
conditions. A rule of thumb is typically used for fixing Rs at one-third of the initial negative
resistance
Step 6) Design proper impedance matching networks for Zs and ZL

23/43
 Appendix – A review on impedance

matching

Matching Networks 24/43
 Introduction
Goal
 Maximize RF power transfer between system blocks

 In lossless reciprocal two-port networks this implies to maximize
transmission while minimizing reflection
 Cascaded connection of different blocks with the same characteristic
impedance does not present any problem
 This ideal scenario rareley happens at component level:
 Examples:
 RF Transistor -> Rin = 10 – 1kW // Xin highly capactiive
 SAW filter
In some cases other goals can be considered when matching impedances
between components (e.g. minimum noise)

 Lumped element networks
1) Complex load impedance with RS = RL

 This is a very common scenario when we have parasitic elements:
 Assembly or packaging stray capacitances
 Parasitic series indutors (e.g. leads, bondwires,…)
 Adding the proper type and amount of reactance in order to set the
net total value to zero

Example
C AP
PO R T
ID= C1
P=1
C =1.59 pF
Z =50 O hm
Matching
Network
PO R T
P=2
Z =50 O hm
Matching frequency f0 = 100 MHz

L = 1.59 mH
What is the frequency response of the network?

 Complex conjugate matching happens strictly at a single frequency
 Transmitted power rolls off at a rate depending on the loaded Q-factor of the
circuit:
𝑓0 𝑋𝐿
𝑄𝐿 = 𝑄𝐿 =
𝐵𝑊 2𝑅
 Bandwidth is essentially determined by the termination that needs to be

matched and not on the circuit itself (!)
 Low/high resistive loads can lead to very challenging matching problems

2) Resistive load with uneven terminations (RS ≠ RL)
 We need to step up/down the load resistance to match it with the

source termination
 Example
Would it be possible to solve this problem using resistor

networks?

Series/parallel RC and RL equivalent networks

CAP RES
RES CAP
RP
RS CS
CP
RP
RS LS
LS
LP
RES
IND
High Frequency Electronic Circuits RES 2016/2017
Design procedure
1) Add a series reactive element with the lowest resistance r, and a shunt
reactive element to the highest resistance R of opposite reactance
2) We force a same Q factor for both series and shunt networks

𝑅
𝑄𝑆 = 𝑄𝑃 = −1
𝑟
3) From the obtained Q-factor we get the values of L and C for a given
matching frequency

L-match networks
Each matching problema admits two different solutions with low-pass and high-pass
response respectively. The appropiate scheme will depend on the application

 Example
Design the matching network at 850 MHz while guaranteeing a DC coupling between both
ports
PORT
P=1
Z = 5 O hm
PORT
P=2
Z = 50 O hm

3) Complex impedances
 We need to transform one termination into the complex conjugate of
the other
Two main approaches:
1) Absorption
1) Resonance

Absorption
 Load and source reactances/susceptances can be absorbed by the elements of

the matching network
 Only inductive/capacitive elements smaller than the corresponding element of

the matching network can be absorbed
Example

Resonance
 It is possible to introduce elements resonating with the source/load complex

impedance
 Two main approaches can be employed:

 Resonate out all the reactive part of the impedance
 Resonante only the excess that cannot be absorbed
 Resonance can reduce drastically the bandwidth of the matching network and
must be avoided when a wider band is preferable
.

 Example
Design a matching network at 850 MHz
We resonate the reactive load by a

PORT PORT single component of opposite sign
P=1 P=1
Z=5 Ohm Z=5 Ohm
Matching
Network
PORT PORT
P=2 P=2
Z=50 Ohm Z=50 Ohm
CAP IND CAP
ID=C1 ID=L1 ID=C1
C=20 pF L=LR nH C=20 pF

 Example
Design a matching network at 850 MHz
PORT CAP
P=1 ID=C2
Z=5 Ohm C=CM pF
PORT
P=2
Z=50 Ohm
IND IND CAP
ID=L2 ID=L1 ID=C1
L=LM nH L=LR nH C=20 pF
Matching and resonance inductors can

be grouped in a single component

Resonance
 We could use part of the load reactance for the matching network, and
resonate only the excess

 Multi-section impedance matching
Increased bandwidth
 It is possible to increase the bandwidth of the matching network by using
multiple cascaded sections
 The approach consists on reducing the ratio between termination impedances

by transforming in several steps, reducing the Q-factor of the LC networks
𝑅𝐼𝑁𝑇 = 𝑅𝑆 𝑅𝐿

Increased bandwidth
 More than 2 sections can be employed even if the improvements are
progressively smaller (i.e. typically no more than 5 stages are used)
 Impedance level of stage index m of a network with a total of n stages would
be given by the geometric mean:
(𝑛−𝑚)/𝑛 𝑚/𝑛
𝑅𝑚 = 𝑅𝑆 𝑅𝐿
 The stage behaviour (i.e. low-pass or high-pass) can be chosen and combined
in order to get a particular out-of-band response

Reduced bandwidth
 In some applications (e.g. tuned amplifiers) we are interested in
limiting the matching network bandwidth
 The approach consists on increasing the ratio between the
impedances by transforming to intermediate impedances outside
the range between RS and RL
RINT < RS RINT > RL

 Matching with transmission lines
 A transmission line has 2 degrees of freedom: characteristic

impedance and electrical length
 It is possible to match a broad range of terminations with physically
realizable values:
 Equal resistance values: not workable solution
 Real terminations  l/4 transformer

 Matching with transmission lines
 A proper combination of a parallel stub with a transmission line can

solve any impedance matching problem

Chapter 8 – Oscillators (II)
Phase Noise

2/21
 Phase Noise

3/21
 Introduction
 Oscillators should theoretically produce a series of harmonics in frequency domain
 However, in real oscillators the instantaneous frequency and magnitude of the

oscillation are not constant
 These random fluctuations represent noise contributions, and translate to the

frequency domain

4/21
 Basic Concepts
 There is both magnitude and phase modulation of the otherwise harmonic output
Magnitude fluctuation is kept small by the non-linear self-limiting process of the oscillator
and it can be usually neglected.
Instantaneous phase variation is the main contributor to frequency smearing and it is
known as Phase Noise
 It is measured with respect to the signal level at a particular offset frequency
 The units are dBc/Hz @ foffset and the power is measured at a 1 Hz resolution bandwidth

5/21
 Basic Concepts
 Considering these small frequency fluctuations as a frequency modulation (wm) of

the carrier, we would have
 For qp<<1 the former expression can be written as
It results in two sidebands located on either side of the carrier at frequency w

6/21
 Leeson’s Model
 For oscillators using high-Q resonant circuits in the feedback loop, the feedback
transfer function can be represented as
Considering a noise-free amplifier with Av = 1, the input and output spectral

power densities are given by

7/21
 Noise spectrum of a typical transistor amplifier is dominated by flicker noise (1/f)

at low frequencies
 This flicker noise will modulate any applied signal (at f0) due to amplifier non-
linearities, thus producing an input power spectral density for the oscillator given
by
 Then, the power spectral density of the phase noise can be computed as

8/21
 Noise power close to the carrier drops as 1/f3

 At frequencies beteween fa and fh
 If the resonator has a low-Q (i.e. fh > fa), the noise power drops as 1/f2
 If the resonator has a high-Q (i.e. fa > fh), the noise power drops as 1/f
 At higher frequencies the noise is predominantly thermal
 In all cases, the noise close to the carrier is proportional to 1/Q2

9/21
 Phase noise degrades receiver selectivity by causing down conversion of signals

located nearby the desired frequency
 This problem is called reciprocal mixing
 The maximum allowable phase noise is in dBc/Hz at offset frequency fm given by

10/21
 Phase Noise Example

Chapter 7 – Power Amplifiers (I)
Circuitos Electrónicos de Alta Frecuencia

2/31
n  Introduction
Circuitos Electrónicos de Alta Frecuencia CURSO 2014/2015

Introduction 3/31
n  Definition
Power amplifier: Amplifier intended to provide maximum power at

n 
the output for a given active element
n  High
output power levels are involved (i.e. usually Pout > 30 dBm) and this
has a lot of implications at circuit and system levels
n  Lineartechniques can be employed

as a first design guess…
n  …but
they will present a non-linear
behavior at some extent
. Corona discharge due to high power levels

Introduction 4/31
n  Linear amplifier
n  Transistor:
2-port network that can be represented by its S-parameters
assuming linear regime
n  Input
and output impedance levels (or reflection coefficient) can be adjusted
using passive networks

Introduction 5/31
n  Input match:
n  Output match:
n  In general, a solution can be found satisfying:
Complex Conjugate Match

Introduction 6/31
n  A
potential solution employing passive circuitry can be found if some
conditions are met
n  K-factor (Rollet Factor)
n  If
k>1 then the device will not present an input/output reflection coefficient
higher than unity
n  The
former results is verified for any source and/or load (i.e. the amplifier is
unconditionally stable)

Introduction 7/31
n  Some practical considerations about Rollet factor
1) If k is slightly higher than unity, device gain/matching are higher than the
unilateral equivalent
2) Circuit losses can compensate a k-factor slightly lower than unity for a given
active device
3) Circuit implementation and parasitics can impact the active device S-parameters
(in particular S12) and then stability
4) Rollet factor is applicable strictily to single-stage amplifiers

Introduction 8/31
n  Non-linear effects
n  Weakly
nonlinear behavior: Output is expressed as a power series
(memoriless) or a Volterra series (with memory)
n  It
characterizes the amplifier behavior around the DC bias point (e.g.
harmonic distorsion, intermodulation, etc.) and close to the 1dB compression
point

Introduction 9/31
n  Stronglynonlinear behavior: Output waveform distorsion as a result of the

limiting behavior of the active device
n  Clipping effects are more gradual
n  Modeling weak and strong non-

linear effects in the same expression
is complicated
n  Behavioural
statements are needed
to model hard saturation and cut-off
behaviour

Introduction 10/31
n  A FET-model example of strong non-linear behaviour:
Combined weak and

strong nonlinear
model
Power series coefficients

Introduction 11/31
n  Non-linear device CAD models
n  Power amplifier design is quite sensitive to CAD models than other RF
devices
n  Model
devices for CAD applications can be divided into the following
categories:
n  Physical models: Device physics and manufacturing geometries are

modelled from the bottom-up
n  Circuital models: Device physics is translated into equivalent circuit
elements
n  Behavioral models: A set of equations is fitted to the measured DC
characteristics of the device

Introduction 12/31
n  Non-linear device CAD models
n  Main difficulties in modeling active devices for RF power amplifiers:

n  Circuital models are difficult to scale
n  I-V curve measurement is complicated at RF frequencies
n  Impedances are much lower than 50Ω resulting in calibration and de-
embedding problems
n  Prototyping,
circuit measurement and model adjustment through fitting is the
only suitable approach
n  As
an exception, CAD models provided by RFIC and MMIC foundries are
satisfactory

Introduction 13/31
n  Conjugate Match
n  A generator delivers maximum power into an external load when:

-  Load resistance is equal to the real part of the generator impedance
-  Reactive parts have been resonated out
n  However the limitations of a real-world active device generator need to be

taken into account:
n  Maximum current it can supply
n  Maximum voltage it can sustain across its terminals (limited by the
available DC supply)
Example: Vmax = 10 V, Imax=1 A, Rgen = 100Ω

Introduction 14/31
n  Loadline Match
n  A lower value of load resistance is needed to employ the maximum current and
the maximum voltage swing
n  The loadline match is a fundamental trade-off for obtaining the maximum power
from a particular RF transistor
Optimum Load

Introduction 15/31
n  Loadline Match
n  Without excursion into the strongly non-linear

region:
-  Class A amplifier
-  Reflection coefficient at the output close to
small-sigjnal S22
n  With excursion into the cut-off or saturation

regions:
-  Example: Class AB amplifier
-  Abrupt changes of the output impedance
(open-circuit)

16/31
n  Quasi-linear power amplifier

Class A Amplifier 17/31
n  Class A amplifier: Linear operation between cut-off and saturation
n  Biasedat the mid-point of the

linear range
n  Weakly non-linear in the range of

operation with stronger effects close
to hard clipping limits
n  Low-pass matching networks help

to clean the amplifier output when
single-tone drive signals are used

n  Powertransfer function for conjugate (solid) and loadline (dashed) matching
conditions
n  1dB
compression point is lower for the
conjugate matched device
n  For
stronger driving signals the power
match can guarantee 2 – 4 dB of increased
output power

n  Load-Pull measurements
n  Relationship between power and output matching represented in the

Smith Chart
n  Measurementsetup comprises the DUT and an

output impedance tuner
n  Contours
show boundaries of specific output
power levels
n  Load-Pull contours at 1dB and 2dB are generally

used

n  Loadline theory
n  Basic loadline theory can be used to predict load-pull contours

n  This approach can be used as an a priori design method for PAs
n  The starting point is a heavily idealized model of the PA

n  Loadline Theory
Loadline match: Optimum load resistor for power match
Efficiency = 50%

n  Example: Determine load terminations giving an output power Popt/p
a) Resistive part

b) Series reactance
Constant current excursion while variable voltage swing

c) Shunt reactance
Constant voltage swing and variable current excursion

n  Load-Pull Contours

n  Additional considerations
n  Several issues must be taken into account for reaching a good matching
between theoretical and measured load-pull contours
a) Package parasitics

n  Additional considerations
b) Optimum resistance
A minimum drain voltage is needed for the current to be effectively

controlled by the gate voltage (i.e. turn-on voltage)

n  Design Procedure
n  Example: Power amplifier 1W @ 1.75 – 1.85 GHz
a) Select device and obtain Ropt
GaAs MESFET P1dB = 29 dBm

Clase A: 4.8V y 375 mA

b) Schematic and output matching network for Ropt

b) Schematic and output matching network for Ropt
Match at center frequency and study the broadband

behaviour of the amplifier

c) Design input matching network using S-parameter techniques

Appendix 32/31
n  Drawing Load-Pull Contours

Chapter 7 – Power Amplifiers (II)
Circuitos Electrónicos de Alta Frecuencia

2/12
n  Reduced conduction angle

Reduced conduction angle 3/12
n  Motivation
n  Highly
efficient PAs are demanded in several applications (e.g. mobile
handset) in order to conserve battery power
n  Increase
the amplifier efficiency by reducing the quiescent current with a
properly biased active device
n  Additional cost is to be paid:

n  Driving power level must be substantially increased in some cases
n  Harmonic content must be shorted out
n  Moreovera high PUF (Power Utilization Factor) must be kept as a trade-off
between efficiency and delivered power

n  Waveform analysis
n  The
device is biased to a quiescent point beyond the Class A condition
toward cut-off
n  Normalized to:
n  Driving level for peak current Imax:

n  Waveform analysis
n  The
conduction angle α indicates the proportion of the RF cycle for which
conduction is happening
n  The RF current waveform can be expressed as:
n  Taking into account that:
n  And finally:

n  Modes of operation
n  The
fundamental and n-th harmonic content can be obtained from the
former expression using Fourier analysis:
n  Different modes of operation can be identified depending on the conduction

angle:

n  Modes of operation
n  From the Fourier analysis of the reduced conduction angle waveform:

n  Output termination
n  The
output waveform for a given load condition is a complex expression
consisting on eventually infinite harmonics
n  Inorder to simplify the drawing of the output waveform we will consider that
all the harmonics are shorted at the output:

n  Output termination
n  The waveforms for the former circuit are simple and can be represented as:
Drain Efficiency
Power Added
. Efficiency

n  Drain efficiency
n  Results for perfect harmonic shorts, maximum linear current and voltage
swings:
Output match for maximum

output power
.
n  Conclusions
n  Some considerations about the different modes of operation:
1) Class AB operation shows an almost constant fundamental RF output power
2) Class B condition delivers the same output power as Class A but with a DC
supply reduced by a factor π/2
3) Class C condition shows an ever-increasing efficiency as the conduction angle

is reduced to lower values; however this is accompanied by a substantial reduction
on the output RF power

Bibliography 12/12
n  RFPower Amplifiers for Wireless Communications, S.C. Cripps, 2nd

Ed., Artech House, 2006
Practical RF Circuit Design for Modern Wireless Systems, L. Besser

n 
and R. Gilmore, Vol. II, 2nd Ed., Artech House, 2003.

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Circuitos Electrónicos De Alta Frecuencia

Máster Universitario en Ingeniería de Telecomunicación

Máster Universitario en Ingeniería de Telecomunicación

NOTA: L y C son aprox. iguales y RP ≈ RS . Q2

Proceso Básico de Fotolitografía Proceso Típico CMOS

Induce corriente que se

La corriente decrece de forma exponencial con la distancia a

Espesor de corona en la que se

Linea bifilar Coaxial

OPTIMIZADO para 50Ω

(Mejor Calidad en Terminales)

MT-101 “Decoupling Techniques” – Analog Devices 13

Muy importantes los parásitos

KEMET 33pF (SMD 0805)

Impedancia de la red de alimentación

Impedancia Combinada por debajo de

Metal TOP (nivel más elevado de metalización). Muy alejado de sustrato

OBSOLETO. No presente en tecnologías “nuevas”

.SUBCKT LQP02TN10NH02 port1 port2

AMS C35 M4 Inductor.

• El uso de componentes discretos es muy complicado por

• En soporte PCB con dimensiones comparables a λ se

• El uso de pasivos seguirá vigente en el entorno de los

Necesario aislamiento por deep-trenches o por dieléctricos

Se puede obtener directamente la matriz de parámetros S a partir del modelo de

n-MOS PoliSi Al / Cu p-MOS PoliSi Al / Cu

INVERSIÓN FUERTE (Ic>10) INVERSIÓN MODERADA (Ic = 1)

Inversión Débil λ depende inv. con L

v   .E vSAT Velocidad máxima de las cargas en el canal

L.vSAT nMOS (L=130n) ↓↓

Frecuencia a la que la corriente de entrada al MOSFET es igual a la de salida

Para el caso de alcanzar la vSAT la

La frecuencia de atenuación a -3 dB de la señal en la puerta

* 0.124 Mucho cuidado con W

Rpoly Capacidad Óxido

AMS C35 / NMOS (40u/0.35u)  1,1 GHz

Para poder alcanzar 5GHz  2 x finger W=20u

MESFET: MOSFET sin aislamiento de puerta. Esto

HMET: Se crea un canal físico con un dopaje muy

HBT: Transistor Bipolar con diferentes tipos de

CLASS 1 HV < 2kV

Otros modelos incorporan efectos

Los mecanismos básicos de protección

Snap-back BJT Snap-back MOSFET (BJT parasitics)

QFN: Tamaño reducido, sin pines

• ¿Cuál es el origen de los valores 50Ω y 75Ω?

MÁXIMA POTENCIA CONDUCIDA POR UN CABLE COAXIAL

• ¿Cuál es el origen de los valores 50Ω y 75Ω?

MÍNIMA ATENUACIÓN EN UN CABLE COAXIAL

𝑅 La atenuación es proporcional a la resistencia

Empleando una expresión aproximada

* “Design of CMOS RF Integrated Circuits”- T. Lee 41

• ¿Cuál es el origen de los valores 50Ω y 75Ω?

MÁXIMA POTENCIA MÍNIMA ATENUACIÓN

BALANCE ENTRE LAS

Departamento de Ingeniería Electrónica

Máster Universitario en Ingeniería de Telecomunicación

• Low Noise Amplifiers (LNAs)

Máster Universitario en Ingeniería de Telecomunicación

• Introduction. Useful things to remember (I)

Maximum Available Noise Power

• Noise Types. SHOT NOISE

• Noise Types. THERMAL NOISE