CONTENTS

Page no.
Abstract i
List of Figures ii
List of Tables iii
Nomenclaure iv
CHAPTER 1: INTRODUCTION 1
1.1 Description 2
1.2 History 2
1.3 Operation 3
1.4 Working 4
1.5 Functions 5
CHAPTER 2: EXISTING METHOD 6
2.1 CMOS 7
2.1.1 Duality 10
2.1.2 Static Dissipation 12
2.1.3 Dynamic Dissipation 13
2.2 DCVSL 14
CHAPTER 3: PROPOSED METHOD 16
3.1 Manchester Carry Chain 17
3.1.1 Performance Analysis 19
3.2 DCVSL 23
3.3 Advantages of DCVSL 26
3.3.1 Differential Logic 26
3.3.2 Positive Feedback 26
3.3.3 Zero Static Power Dissipation 26
CHAPTER 4: TANNER TOOL 27
4.1 Schematic Edit(S-Edit Tool) 28
4.1.1 Beginning a Design 28
4.1.2 T-Space Pro Circuit Analysis 29
4.2 Circuit Simulator 29
4.2.1 DC Operating Point Analysis 30
4.2.2 DC Transfer Analysis 31
4.2.3 Transient Analysis 31
4.2.4 AC Analysis 31
4.2.5 Noise Analysis 32
4.3 Waveform Edit 32
4.4 Layout Edit 33
4.4.1 L-Edit 33
 4.4.2 Cells 33
4.4.3 Hierarchy 34
4.5 L-Edit Modules 35
4.5.1 L-Edit 35
4.5.2 L-Edit Extract Creates Spice 36
4.5.3 L-Edit DRC Features User 36
CHAPTER 5: SIMULATION RESULTS 37
5.1 Full Adder Using 28 Transistors 38
5.1.1 Full Adder Using 28 Transistors Graph 39
5.2 Full Adder 40
5.2.1 Full Adder Graph 41
5.3 DCVSL 42
5.3.1 DCVSL Graph 43
5.4 MLM 44
5.4.1 MLM Graph 45
5.5 MCC 46
5.5.1 MCC Graph 47
5.6 ALU 1-Bit 48
5.6.1 ALU 1-Bit Graph 49
5.7 4 Bit ALU 50
CHAPTER 6: POWER AND DELAY ANALYSIS 51
6.1 Full Adder28 52
6.2 Full Adder 52
6.3 Multi Logic Module 53
6.4 MLM 53
6.5 MCC 54
6.6 ALU 1-Bit 55
6.7 ALU 4-Bit 56
6.8 Overview 57
CONCLUSION 58
REFERENCES 60