THE WIND

IGNITION+

1
 FACULTY OF ENGINEERING AND TECHNOLOGY

IGNITION+
FIRST EDITION: JANUARY 2016

COMPILED AND EDITED BY:

THE WIND:
TEM STRONGBERT BAMA
JUNIOR AZEH NDIFOR
FORCHA PETER AKEM OBEN
TABE BAIYE BISMAC
NDI DENIS NDI
MOUDJI FERDINAND
NGORAN CLARE-JOYCE
MBUA PETER
FOMAGA TATOU MOHAMED
TEKE HANNETE
BISZAN MUKWELLE

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Contents
Forward 5
Introduction 5
1. FIRST SEMESTER CONTINUOUS ASSESSMENT 10
1. EEF 301: QUESTIONS(2014/2015)…………………………………………………………………..11
2. EEF 301:SOLUTIO NS(2014/2015)…………………………………………………………………..13
3. EEF 313:QUESTION S(2014/2015)…………………………………………………………………..18
4. EEF 313:SOLUTIONS (2014/2015)…………………………………………………………………..19
5. EEF 313:QUESTION S(2014/2015)TEST2………………………………………………………..22
6. EEF 313:SOLUTIONS(2014/2015)TEST2….……………………………………………………..23
7. EEF 313:QUESTIONS (2013/2014)…………………………………………………………………..27
8. EEF 313:SOLUTIONS (2013/2014)…………………………………………………………………..28
9. EEF 303: (2014/2015)TEST1…………………………………………………………………………..32
10. EEF 303: (2014/2015) TEST2……………………………………………………….……………..….34
11. EEF 303: (2013/2014)……………………………………………………………………………………..36
12. EEF 315:QUESTIONS (2014/2015)…………………………………………………………………..38
13. EEF 315:SOLUTIONS (2014/2015)…………………………………………………………………..40
14. EEF 315:QUESTIONS (2013/2014)…………………………………………………………………..47

2. FIRST SEMESTER EXAMINATIONS 49

15. EEF 301: QUESTIONS(2014/2015)…………………………………………………………………..50
16. EEF 301:SOLUTIO NS(2014/2015)…………………………………………………………………..52
17. EEF 313:QUESTION S(2014/2015)…………………………………………………………………..57
18. EEF 313:SOLUTIONS (2014/2015)…………………………………………………………………..59
19. EEF 303:QUESTIONS (2013/2014)…………………………………………………………………..66
20. EEF 303: SOLUTIONS (2013/2014)….……………………………………………………………….67
21. EEF 303:SOLUTIONS(2014/2015)….………………………………………………………………..72
22. EEF 315:QUESTIONS (2014/2015)…………………………………………………………………..81
23. EEF 315: SOLUTIONS (2014/2015)…………………………………………………………………..84
24. EEF 315:QUESTIONS (2013/2014)…………………………………………………………………..90
25. EEF 311:QUESTIONS (2013/2014)…………………………………………………………………..92
26. EEF 311: SOLUTIONS (2013/2014)…………………………………………………………………..94

3. SECOND SEMESTER CONTINUOUS ASSESSMENT 96

27. EEF 302: QUESTIONS(2013/2014)…………………………………………………………………..97
28. EEF 302:SOLUTIO NS(2013/2014)…………………………………………………………………..99
29. EEF 302:SOLUTION S(2015/2015)…………………………………………………………………..104

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 30. EEF304:QUESTION S(2013/2014)…………………………………………………………………..110
31. EEF 304:SOLUTIONS(2013/2014)…………………………………………………………………...111
32. EEF 304: QUESTIONS(2014/2015)…………………………………………………………………..114
33. EEF 304: SOLUTI NS(2014/2015)……………………………………………………………………..115
34. EEF 312: QUESTIONS(2012/2013)…………………………………………………………………..117
35. EEF 312:SOLUTIO NS(2012/2013)…………………………………………………………………..118

4. SECOND SEMESTER EXAMINATIONS 122

36. EEF 302: QUESTIONS(2013/2014)…………………………………………………………………..123
37. EEF 302:SOLUTIO NS(2013/2014)…………………………………………………………………..126
38. EEF 302:QUESTION S(2012/2013)…………………………………………………………………..135
39. EEF 302:SOLUTIONS(2014/2015)…………………………………………………………………...137
40. EEF 304: QUESTIONS(2014/2015)…………………………………………………………………..145
41. EEF 304: SOLUTINS(2014/2015)…………………………………..………………….……………..147
42. EEF 304: QUESTIONS(2013/2014)…………………………………………………………………..152
43. EEF 304: SOLUTINS(2013/2014)……………………………………………………………………..154
44. EEF 310:QUESTION S(2012/2013)…………………………………………………..……………...157
45. EEF 310:SOLUTIONS(2012/2013)…………………………………………………...………………158
46. EEF 308…………………………………………………………………………………………………………..169

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 FOREWARD
Engineering is the application of maths and science by which the properties of matter and the
sources of energy in nature are made useful to people.
Engineers apply math and science for the betterment of the society through; design, manufacturing,
management, research and development.
While scientists discover a world that already exists engineers create a world that never was
Given the goal of our nation to attain the status of an emergent economy by the year 2035 a lot of
technical development and development in infrastructure would be in high demand in the coming
years. Also the world is facing a lot of energy crises that requires solutions to be drafted by great
and innovative minds
Engineering is a noble profession, offering countless job opportunities while permitting creative
spirit in its practitioner .It is therefore without doubt that the input into our engineering school is
worthwhile
THE FACULTY OF ENGINEERING AND TECHNOLOGY, the first Anglo-Saxon engineering institution
of its kind in the country is indeed promising.
With the rapid growth of its two equipped and competent departments in its first 5 years of
existence, there is no doubt of what it has to offer to our country CAMEROON. Being here may
definitely be a stepping stone to a wonderful career in engineering
Every king was once a crying baby , every great building was once a blue print and every giant tree
once existed as a seed .It is not important where or how YOU are today but where and what you
will be tomorrow.
Dream big for that is what determines the level of our motivation
Do not weep over a single failure and don’t let what you can’t do interfere with what you can.

ABOUT THE AUTHORS

This package was compiled by members of THE WIND group of the FACULTY OF ENGINEERING
AND TECHNOLOGY
Its contains ‘suggested’ solutions and answers to past examination questions , especially in the
electrical engineering department
As it is always said a system is only perfect at the period just after it’s made and faults can only be
detected when its in use.
This means we are open to constructive criticism from any individual.

INTRODUCTION

What is an Electrical Engineer?

Did you know that electrical engineers are involved in creating cell phones, lasers, the Internet,
PDAs, hybrid cars, video games, and satellite TV? Technologies developed by electrical engineers
have enriched our lives in countless ways and revolutionized our daily environment.
Electrical engineers gave the world modern virtual reality and spanned power distribution
networks across vast rural areas in developing countries. Electrical engineers develop new
pacemakers for ailing hearts, ultrasonic diagnostic devices for detection of tumors, and NMR
machines. They provide secure and reliable communication to expeditions in remote and
dangerous locations and to astronauts in space. They are responsible for numerous household and
personal items, from your electronic wristwatch to your iPod.

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Electrical engineers work in multimedia, telecommunications, electric power, signal processing and
control. They work with physicians on new diagnostic devices and with urban planners on new
efficient vehicles. Their work makes our lives more interesting, effective and safe, and increases our
productivity and standard of living.

Electrical Engineers Work on Aerospace Vehicles, Aeronautics and Avionics

Carolyn Kerr: Electrical Systems Engineer, Boeing Commercial Airplane Group

“I came into a group that did a lot of the fun things that I like to do. I like to work with people; I like
to travel a little bit. And so I’ve lucked out. I am responsible for procuring generators, contractors,
and control units, the main sources of electrical power on an airplane.”
Many designs of airplanes and aircraft are undergoing dramatic transformation. Subsystems that
depended in the past on bulky mechanical and hydraulic devices are replaced by small electronic
circuits and high density computer chips. Better and smaller sensors, digital control units and
“computers on a chip” make airplanes lighter, more capable and safer. Electrical engineers are at
the forefront of this transformation, and new technologies keep making their professional life more
exciting. Some of these new technologies include Nanotechnology, Mechatronics, and MEMS
(Microelectromechanical Systems).

Electrical Engineers Work with Computers and Software

Wesley Driver: Software Engineer Harris Corporation

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“I’m a software engineer and it’s cool. They stick me in a lab or office with tons of toys— computer
gadgets. I get to play with them all day…and they pay me for it. It’s a bit of cloak and dagger
atmosphere.”
Computers and software are everywhere—in our cars, embedded in bridges and roads, installed in
the bodies of patients to regulate biological mechanisms, and integrated into ID cards and
passports. Electrical engineers are involved in the design and manufacture of these devices, and
often (as computer or software engineers) they take part in creating the scripts that control these
devices and determine their capabilities. Many electrical engineers are engaged in writing
computer code and testing and debugging it, to ensure that it works according to specifications and
that its operation is predictable, error free and safe.

Academic studies

John Harding: Hardware Development. Engineer, Hewlett Packard Company (hp)

“Some non-engineering courses that have proved to be helpful are management, business, and
entrepreneurship classes. I also took a psychology class on behavior and personal adjustment
which I use almost every day. It teaches you about people and about your behavior with people.
These are very important because you’re working with a team, and you need to understand how to
deal with other people.”
Most electrical engineers begin their career by earning a Bachelor of Science (B.Sc.) degree in
electrical engineering or a closely-related field (electronics, power, control, telecommunication or
computer engineering; or computer science). The B.Sc. degree usually requires 4-5 years in an
undergraduate program at an accredited university. A Bachelor of Science degree in electrical
engineering or closely-related disciplines expands career options and can open the door to other
professions. While many graduates of electrical engineering programs spend their entire career
working on technical and engineering projects, others continue their education in other diverse.

An Early Start

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Jeff Cannon, Telecommunications Engineer ADC Telecommunications
“In high school I got into computers and tried my hand at programming. It’s been surprising how
applicable a lot of the seemingly abstract math and science concepts taught in high school have
been in my engineering career.”
Education, interest, training, and experience lead the way to a career in electrical engineering.
Throughout high school, students can begin preparing for an engineering career by laying a solid
academic foundation. Taking courses in mathematics, science, and communication can be very
helpful for future study of engineering at a university and should include:
Algebra Geometry
Biology Physics
Business writing Public speaking
Calculus Trigonometry
Chemistry
Computer science
Electronics
Taking an active role in extra-curricular activities can enhance classroom studies by providing
hands-on experience with engineering design and practice. Such activities include: competing in
science and technology fairs; robot, rocket, and other design competitions, and active membership
in engineering clubs. The following competitions are representative of the many opportunities
available to students who wish to explore engineering:

Careers with options

Electrical engineering—and its closely related fields (electronics engineering, power engineering,
telecommunications engineering, computer science, computer engineering, and control
engineering)—provide career opportunities in many industries and branches of business. There
are electrical engineers in manufacturing plants, control rooms of large petrochemical plants,
monitoring rooms of space flights, and hospitals. Here are some of the challenges that electrical
engineers of the future are likely to be taking up.

Field Activity Example

Aerospace and Aeronautics Develop new sensors, control
systems and power supplies for
the next generation of space
vehicles
Communications Develop new networks that
allow instant unlimited voice
and audio communication with
anyone, anywhere, anytime
Transportation Develop remote control cars
that can be driven
automatically on “smart

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 highways”
Medicine Develop new sensing and drug
delivery techniques that allow
diabetics to regulate their
blood sugar levels without
injections
Homeland Security Develop imaging techniques
that allow error free detection
of all explosive devices within
10 kilometers of an airport
Entertainment Develop new multimedia
techniques to enhance visual,
smell, and tactile effects in
concerts and on the Internet
Power Develop a new longer-lasting
battery that allows a cell phone
to operate for a year without
recharging
Robotics Develop smart robots that can
detect and locate survivors in
earthquakes and accidents
Military Engineering Develop reliable and secure
communication methods for
special force units operating
underground
Geosciences and Remote Develop highly-reliable
Sensing networks to detect and predict
earthquakes and tsunamis

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 FIRST SEMESTER
CONTINUOUS ASSESSMENT

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 EEF 301: ELECTROMAGNETIC WAVES (2014/2015)

PART 1

QUESTION 1
a) What new concept did Maxwell’s generalized form of the Ampere’s law include?
b) Do Maxwell’s equations allow for the existence of magnetic monopoles? Explain.
c) When light or other electromagnetic radiation travels through a given region, what is it that
oscillates? What is it that is transported?
d) Which of the following parameters increases, decreases or stays constant when the distance
from the point source of electromagnetic radiation increases? i) frequency ii) wavelength
iii) speed iv) intensity v) amplitude

QUESTION 2
1.
a) An electromagnetic wave of wavelength 435nm is travelling in vacuum in the z-direction. The
electric field has magnitude 270 ∗ 10−3 V/m and is parallel to the x-axis. What are (a) the frequency
and
(b) the magnetic field amplitude? (c) Write vector equations for E(z, t) and B(z, t).
2- An electromagnetic wave with frequency 65𝐻𝑧 propagates through an insulator whose dielectric
constant and relative permeability are 3.64 and 5.18 respectively. The electric field amplitude of
propagation of the wave is 7.2 ∗ 10−3 V/m. Find (a) the speed of propagation of the wave in the
insulator (b) the wavelength (c) the amplitude of the magnetic field (d) the intensity of the wave.

QUESTION 3
1-A very long, thin rod carries electric charge with linear density 35𝑛𝐶/m. It lies along the x- axis
and moves in the x-direction at a speed of 15𝑀𝑚/s. (a) find the electric field the rod creates at the
point (x=0, y=20cm, z=0). b) Find the magnetic field the rod creates at the same point. (c) Find the
force exerted on an electron at this point, moving with a velocity of (240𝑖)𝑀𝑚/s.
2-A proton moves through a uniform electric field given by 𝐸 = 50𝑗𝑉/m and a uniform magnetic
field 𝐵 = (0.2𝑖 + 0.3𝑗 + 0.4𝑘)T. Determine the acceleration of the proton when it has a
velocity𝑉 = 200𝑖𝑚/s
3-How much electromagnetic energy per cubic meter is contained in sunlight if the intensity of
sunlight at the Earth’s surface under a fairly clear sky is 1000𝑊/𝑚2 ?
4-The filament of an incandescent lamp has a 150Ω and carries a direct current of 1.00𝐴. The
filament is 8.00cm long and 0.900mm in radius. (a) Calculate the Poynting vector at the surface of
the filament, associated with the static electric field producing the current and the current’s static
magnetic field.
(b) Find the magnitudes of the static electric and magnetic fields at the surface of the filament.
5-In a region of free space, the electric field at an instant of time is 𝐸 = (80𝑖 + 32𝑗 − 64𝑘)𝑉/m and
the magnetic field is 𝐵 = (0.20𝑖 + 0.08𝑗 + 0.29𝑘)𝑇. (a) Show that the two fields are perpendicular
to each other. (b) Determine the Poynting vector for these fields.

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PART 2

QUESTION 1
1-For a transmission line of characteristic impedance z0 connected to a load impedance zl (a)
Provide a definition of the reflection and transmission coefficients R and T in the time domain. (b)
Derive a relationship between z0, zl and R and a relationship between z0, zl and T.
2-Consider a transmission line of characteristic impedance z0 that is terminated by a load zl. (a)
What is the condition on the values of the VSWR and of the (complex) reflection coefficient so that
 All the power incident will be dissipated in the load
 No power will be dissipated in the load.

QUESTION 2
The standing wave ratio on a lossless 300Ω transmission line terminated in an unknown load
impedance is 2.0 and the nearest voltage minimum is at a distance of 0.3 ⋋ from the load.
Determine (a) the reflection coefficient of the load. (b) the unknown load impedance zl.

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 SOLUTION TO EEF 301: ELECTROMAGNETIC WAVES (2014/2015)

PART 1

QUESTION 1
a) Maxwell added the concept of displacement current.
𝑑𝐼
𝐼=ɛ
𝑑𝑡
This was as a result of the fact that Ampere’s law is valid only if the electric fields present is
constant with time. Maxwell sorted out this limitation and modified Ampere’s equation
( 𝐵 𝑑𝑠 = 𝜇𝐼) to include the time varying electric field.
b) Maxwell’s equations do not allow for the existence of magnetic monopoles. This is because
they do not exist and all attempts to isolate the different poles of a magnet have been to no
avail.
c) When electromagnetic radiations pass through a region, the electric and magnetic fields in
that region turn to oscillate. Energy and momentum are transported to the particles found
along the path of propagation of the radiation. The rate of energy flow is described by the
Poynting vector.
d)
I. Frequency remains constant
II. Wavelength remains constant
III. Speed is also constant
IV. Intensity decreases
V. Amplitude increases

QUESTION 2
1- Wavelength, ⋋ = 435nm

𝐸 max = 270 ∗ 10−3 𝑉/m

a) the frequency, f
108 𝑚
𝑐 3∗ 𝑠
𝑓= =
⋋ 435 ∗ 10−9 𝑚
2. the magnitude of the magnetic field, B
𝐸 max/𝐵max= 𝑐
10−3 𝑉
Emax 270 ∗ 𝑚
Bmax = = = 0.9 ∗ 10−9𝑇
c 108𝑚
3.0 ∗
𝑠
𝐵𝑚𝑎𝑥 = 0.9𝑛𝑇
b) vector equations;
𝐸 𝑥(𝑧, 𝑡) = 𝐸𝑚𝑎𝑥𝐶𝑜𝑠(𝑘𝑥 − 𝑤𝑡)𝑖
𝐵𝑦(𝑧, 𝑡) = 𝐵𝑚𝑎𝑥𝐶𝑜𝑠(𝑘𝑥 − 𝑤𝑡)(−𝑗)
2𝜋 2𝜋
𝑘= = = 1.4 ∗ 107 𝑟𝑎𝑑𝑠/𝑚
⋋ 435 ∗ 10−9 𝑚

𝑤 = 2𝜋𝑓 = 2𝜋 ∗ 6.89 ∗ 1014 𝐻𝑧 = 4.33 ∗ 1015 𝑟𝑎𝑑𝑠/𝑠

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 𝐸 𝑥(𝑧, 𝑡) = 270 ∗ 10−3 𝐶𝑜𝑠(1.4 ∗ 107 𝑧 + 4.33 ∗ 1015 𝑡)𝑖𝑉/𝑚

𝐵𝑦(𝑧, 𝑡) = 0.9 ∗ 10−9 𝐶𝑜𝑠(1.4 ∗ 107 𝑧 + 4.33 ∗ 1015 𝑡)(−𝑗)𝑇

2-a) propagation speed of the wave in the insulator
𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦, 𝑓 = 65𝐻𝑧
𝑑𝑖𝑒𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 = ɛr = 3.64
𝑟𝑒𝑙𝑎𝑡𝑖𝑣𝑒 𝑝𝑒𝑟𝑚𝑖𝑡𝑖𝑣𝑖𝑡𝑦 =µr= 5.18
𝐸𝑚𝑎𝑥 = 7.2 ∗ 10−3 𝑉/𝑚
Let 𝑐𝑖 = 𝑝𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝑠𝑝𝑒𝑒𝑑 𝑖𝑛𝑠𝑖𝑑𝑒 𝑡𝑕𝑒 𝑖𝑛𝑠𝑢𝑙𝑎𝑡𝑜𝑟
ɛi = 𝑝𝑒𝑟𝑚𝑖𝑡𝑖𝑣𝑖𝑡𝑦 𝑜𝑓 𝑡𝑕𝑒 𝑖𝑛𝑠𝑢𝑙𝑎𝑡𝑜𝑟 ɛo
µi= 𝑝𝑒𝑟𝑚𝑒𝑎𝑏𝑖𝑙𝑖𝑡𝑦 𝑜𝑓 𝑡𝑕𝑒 𝑖𝑛𝑠𝑢𝑙𝑎𝑡𝑜𝑟
ɛi = ɛrɛo, µi =µrµo
using the formula for calculating the speed of electromagnetic radiation in vacuum, with the
relative permeability and permittivity, we can calculate the speed of the wave in the insulator.
𝑐 = 𝑠𝑝𝑒𝑒𝑑 𝑜𝑓 𝑙𝑖𝑔𝑕𝑡 𝑖𝑛 𝑣𝑎𝑐𝑢𝑢𝑚
1
And is given by 𝑐 = , hence
ɛ0µ0
108 𝑚
1 1 𝑐 3∗
𝑐𝑖 = = = = 𝑠 = 0.69 ∗ 108 𝑚/𝑠
ɛiµi ɛr ɛoµr µo ɛrµr 3.64 ∗ 5.18
b) wavelength of the wave
𝑐𝑖 = 𝑓 ⋋
108 𝑚
𝑐𝑖 0.69 ∗ 𝑠
⋋= = = 1.1 ∗ 106 𝑚
𝑓 65𝐻𝑧
c)amplitude of the magnetic field
10−3 𝑉
𝐸𝑚𝑎𝑥 7.2 ∗ 𝑚
𝐵𝑚𝑎𝑥 = = = 0.104𝑛𝑇
𝑐 108 𝑚
0.69 ∗
𝑠
c) intensity of the wave
2
𝐸𝑚𝑎𝑥 2 1 108 𝑚 10−12 𝐹 10−3 𝑉
𝐼 = 𝑐𝑖 ∗ ɛ𝑜ɛ𝑟 ∗ = 0.69 ∗ ∗ 8.85 ∗ ∗ 3.64 ∗ 7.2 ∗
2 2 𝑠 𝑚 𝑚
−8
10 𝑊
= 5.76 ∗
𝑚2

QUESTION 3
𝑞
1) a)-charge density, 𝑙 = 35.0𝑛𝐶/𝑚
To calculate the electric field at the given point, we consider a Gaussian surface of radius
𝑟 = 20𝑐𝑚 and length 𝑙 and apply Gauss’ law to the cylinder.
𝐸 𝑑𝑠 = 𝑞/ɛ𝑜
𝑞 = 𝑒𝑛𝑐𝑙𝑜𝑠𝑒𝑑 𝑐𝑕𝑎𝑟𝑔𝑒
𝑞
𝐸(2𝜋𝑟𝑙) =
ɛ𝑜

14
 𝑞 10−9 𝐶
𝑞 35 ∗
𝑚
𝐸= = 𝑙 = = 3.147 ∗ 103 𝑉/𝑚
ɛ𝑜(2𝜋𝑟𝑙) ɛ𝑜(2𝜋𝑟) 10−12 𝐹
2 ∗ 8.85 ∗ 𝑚 ∗ 20 ∗ 10−2 𝑚
b) magnetic field at this same point
𝐵𝑑𝑠 = 𝜇𝑜𝐼
𝐵(2𝜋𝑟) = 𝜇𝑜𝐼
𝜇𝑜𝐼
𝐵=
2𝜋𝑟
𝑞
But 𝐼 = ∗ 𝑣, 𝑣 = 𝑠𝑝𝑒𝑒𝑑 𝑜𝑓 𝑝𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝑜𝑓 𝑡𝑕𝑒 𝑤𝑎𝑣𝑒
𝑙
10−9 𝐶 106 𝑚
𝐼 = 35 ∗ ∗ 15 ∗ = 0.525𝐴
𝑚 𝑠
4𝜋∗10 −7 (0.525𝐴)
Hence 𝐵 = 2𝜋∗20∗10 −2 𝑚 = 0.0525 ∗ 10−5 𝑇
c) force exerted on an electron
using Lorentz’s force law, given by
𝐹 = 𝑞𝐸 + 𝑞𝑣 × 𝐵
10 3 𝑉 10 6 𝑚
𝐹 = (−1.6 ∗ 10−19 𝐶)(3.147 ∗ 𝑚
𝑗)+(−1.6 ∗ 10−19 𝐶) 240 ∗ 𝑠
𝑖 0.0525 ∗ 10−5 𝑘𝑇
𝐹 = 4.83 ∗ 10−16 (−𝑗)𝑁
2- calculating the acceleration of the electron
𝐸 = 50𝑗𝑉/𝑚
𝑣 = 200𝑖𝑚/𝑠
𝐵 = 0.2𝑖 + 0.3𝑗 + 0.4𝑘
Still using the Lorentz’s force law associated with Newton’s second law of motion, we are
able to calculate the acceleration of the particle.
𝐹 = 𝑞𝐸 + 𝑞𝑣 × 𝐵
𝑣 × 𝐵 = (200𝑖) × 0.2𝑖 + 0.3𝑗 + 0.4𝑘
𝑣 × 𝐵 = −80𝑗+60𝑘
𝐹 = 𝑞(50𝑗 − 80𝑗+60𝑘)
𝐹 = 30(−1.6 ∗ 10−19 )(𝑗 − 2 𝑘 )𝑁
𝑞 𝑖𝑠 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑏𝑒𝑐𝑎𝑢𝑠𝑒 𝑤𝑒 𝑎𝑟𝑒 𝑐𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑖𝑛𝑔 𝑡𝑕𝑒 𝑓𝑜𝑟𝑐𝑒 𝑒𝑥𝑒𝑟𝑡𝑒𝑑 𝑜𝑛 𝑎𝑛 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛
𝐹 = −48 ∗ 10−19 𝑗 − 2 𝑘 𝑁 = 𝑚𝑎
𝑚 = 𝑚𝑎𝑠𝑠 𝑜𝑓 𝑡𝑕𝑒 𝑒𝑙𝑒𝑐𝑡𝑟𝑜𝑛 = 1.67 ∗ 10−27 𝑘𝑔
48 ∗ 10−19 𝑁
𝑎= (𝑗 − 2𝑘 )
1.67 ∗ 10−27 𝑘𝑔
𝑎 = 28.74 ∗ 108 (𝑗 − 2𝑘 )𝑚/𝑠 2

3-a) calculating the total electromagnetic energy, U

𝐼 = 1000𝑊/𝑚2
𝑐 = 𝑠𝑝𝑒𝑒𝑑 𝑜𝑓 𝑙𝑖𝑔𝑕𝑡 𝑖𝑛 𝑣𝑎𝑐𝑢𝑢𝑚 = 3 ∗ 108 𝑚/𝑠

15
 1000𝑊
𝐼 𝑚2
𝐼 = 𝑈. 𝑐 ↔ 𝑈 = = = 0.33 ∗ 10−5 𝐽
𝑐 108 𝑚
3.0 ∗
𝑠

4-𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑅 = 150Ω, 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝐼 = 1.0𝐴, 𝑙𝑒𝑛𝑔𝑡𝑕 𝑙 = 8.0𝑐𝑚 𝑟𝑎𝑑𝑖𝑢𝑠 𝑟 = 0.9 ∗ 10−3 𝑚

a) calculating the Poynting vector
𝑃 𝐼2 𝑅 150𝑊
𝑃 = 𝐼𝐴, 𝐼 = = = = 3.316 ∗ 105 𝑊/𝑚2
𝐴 2𝜋𝑟𝑙 2𝜋(0.9 ∗ 10−3 𝑚)(8 ∗ 10−2 𝑚)
The intensity I is equal to the average magnitude of the Poynting vector
𝐼 = 𝑆 = 3.316 ∗ 105 𝑊/𝑚2
b) calculating the magnitude f the electric and magnetic fields
𝑐
𝐼= ɛ𝑜𝐸 2
2
2𝐼 𝐼𝑅 150𝐴Ω
𝐸= = = = 1875𝑉/𝑚
𝑐ɛ𝑜 𝑙 8 ∗ 10−2 𝑚
𝜇𝑜𝐼 4𝜋 ∗ 10−7 ∗ 1𝐴
𝐵= = = 2.22 ∗ 10−4 𝑇
2𝜋𝑟 2𝜋 ∗ 0.9 ∗ 10−3 𝑚

5-𝐸 = 80𝑖 + 32𝑗 − 64𝑘

𝐵 = 0.2𝑖 + 0.08𝑗 + 0.29𝑘
a) show that the two fields are perpendicular
To show that these two fields are perpendicular, it suffices for us to show that their dot
product is zero. i.e
𝐸. 𝐵 = 0
𝐸 . 𝐵 = 80𝑖 + 32𝑗 − 64𝑘 . 0.2𝑖 + 0.08𝑗 + 0.29𝑘 = 16 + 2.56 − 18.56 = 0
Hence the two fields are perpendicular.
b) Calculating the Poynting vector S
1
𝑆= 𝐸×𝐵
𝜇𝑜
Verify that 𝐸 × 𝐵 = 14.4𝑖 − 36𝑗
1
𝑆= (14.4𝑖 − 36𝑗)𝑊/𝑚2
4𝜋 ∗ 10−7
𝑆 = (11.5 ∗ 106 𝑖 − 28.6 ∗ 106 𝑗)𝑊/𝑚2

PART 2

QUESTION 1
b) Relationship between Zo, Zl and R
Zo is the characteristic impedance
Zl is the load impedance
R = reflection coefficient

16
 2) a) i) condition for all the power supplied to be dissipated in the load
if all the power is dissipated in the load, this implies that no power is reflected
𝑉(−) 0
𝑅= = =0
𝑉(+) 𝑉(+)

Where V(-) is representing the reflected power, V(+) is representing the power supplied.
𝑍𝑙−𝑍𝑜 𝑍𝑙−𝑍𝑜
From 𝑅 = 𝑍𝑙+𝑍𝑜 ⟺ 0 = 𝑍𝑙+𝑍𝑜 ⟺ 𝑍𝑙 = 𝑍𝑜
And the voltage standing wave ratio (S) which is given by
1+ 𝑅
𝑆= =1
1− 𝑅
Therefore for all the power to be dissipated in the load
1-the reflection coefficient, R=0
2-𝑍𝑙 = 𝑍𝑜
3-𝑆 = 1
ii) Conditions for all the power to be reflected
If all the power is reflected ie𝑉(−) = 𝑉(+)
Then the reflection coefficient 𝑅 = 1
𝑍𝑙−𝑍𝑜 𝑍𝑙−𝑍𝑜
From 𝑅 = ⟺1= ⟺ 𝑍𝑜 = 0
𝑍𝑙+𝑍𝑜 𝑍𝑙+𝑍𝑜
And the voltage standing wave ratio
1+ 𝑅 2
𝑆= = =∞
1− 𝑅 0

QUESTION 2
𝑍𝑜 = 300Ω, 𝑙 = 0.3 ⋋, 𝑆 = 2
a) calculating the value of the reflection coefficient of the load
1+ 𝑅 1+ 𝑅 1
𝑆= ⟺2= ⟺ 𝑅 =
1− 𝑅 1− 𝑅 3
b) calculating the unknown impedance Zl
𝑍𝑙 − 𝑍𝑜 −2𝑗𝛽𝑙
𝑅 = 𝑒
𝑍𝑙 + 𝑍𝑜
2𝜋 2𝜋𝑙 2𝜋(0.3 ⋋)
𝛽= ⟺ 𝛽𝑙 = = = 0.6𝜋
⋋ ⋋ ⋋
𝑍𝑙 − 𝑍𝑜 −2𝑗 (0.6𝜋)
1/3 = 𝑒
𝑍𝑙 + 𝑍𝑜

17
 EEF 313: LINEAR ALGEBRA (2014/2015) TEST 1

QUESTION 1
A. Use the Row Echelon method to
i. Find the solution set of the following systems of equation.
4 x1  8 x2  12 x3  44 x1  x2  5 x3  3 3x1  3x2  3x3  9
a) 3x1  6 x2  8 x3  32 b) x2  3x3  1 c) 2 x1  x2  4 x3  7
2 x1  x2  7 x1  2 x2  8 x3  3 3x1  5 x2  x3  7
ii. Find the inverse of the matrix
1 3 0 2
 
 2 5 7 4
 3 5 2 1
 
 1 1 2 3 
B. Find the inverse by (looking for the cofactor matrix) of the matrix below:
1 2 3 4
 
3 5 7 9
A
 1 1 2 1
 
0 1 0 1
C. Find the value(s) of k for which the system below is consistent.
x1  3x2  x3  2
2 x1  kx2  x3  5
x1  2 x2   k  2  x3  6

QUESTION 2
Find an elementary matrix E that satisfies the equation EA  B . Where
 5 6 1  3 10 1 
   
A   3 7 4 B   3 7 4
 1 2 0   1 2 0 
   

18
 SOLUTION TO EEF 313: LINEAR ALGEBRA (2014/2015) TEST 1

QUESTION 1
4 x1  8 x2  12 x3  44
i. a. 3x1  6 x2  8 x3  32
2 x1  x2  7
the matrix equation formed from this system is
 1 2 3  x1   11  1 2  3 11 
      
 3 6 8  x2    32  , the augmented matrix is  3 6  8 32 
 2 1 0  x   7   2  1 0  7 
  3     
1 2  3 11  1 2  3 11 
  R2  R2  3R1  
 3 6  8 32  R  R  2R 0 0 1 1 
 2  1 0  7  3 3 1  0 3  6 15 
   
1 2  3 11 
 
R2  R3  0 3 6 1 
0 0 1  1 

Using Rows Operations, we can reduce the augmented system to Row Echelon form:
1 2  3 11 
 
 0 3  6 15 
 0 0 1 1 
 
Therefore the system has a unique solution which is x1  2, x2  3, x3  1

x1  x2  5 x3  3
b. x2  3x3  1
x1  2 x2  8 x3  3
1 1 5 3
 
The augmented matrix obtained from this system is 0
 1 3  1
1 2 8 3 

1 1 5 3  1 1 5 3  1 1 5 3
     
 0 1 3  1 R3  R3  R1  0 1 3  1 R3  R3  R2  0 1 3  1
1 2 8 3  0 1 3 0  0 0 0 1 
    
Using Rows Operations, we can reduce the augmented system to Row Echelon form:
1 1 5 3 
 
 0 1 3  1
0 0 0 1 
 
Now, since 0  1 , it means that system has No solution.

19
 3x1  3x2  3x3  9
a. 2 x1  x2  4 x3  7
3x1  5 x2  x3  7

1  1 1 3

The augmented matrix obtained from the above system is 2  1
 R2  R2  2R1
 4 7
3  5 R  R3  3R1
  1 7  3
1  1 1 3   1 1 1 3   1 1 1 3
     
 2  1 4 7    0 1 2 1  , R3  R3  2 R2   0 1 2 1
 3  5  1 7   0 2 4 2  0 0 0 0 
    
Using Rows Operations, the augmented system is reduced to Row Echelon form to obtain:
1  1 1 3 
 
0 1 2 1 
0 0 0 0 

Therefore , the system has infinitely many solutions which is
1 3 0 2  x1  4  3t , x2  1  2t , x3  t
 
2 5 7 4
ii. Finding the inverse of the matrix  ,we obtain the following results
 3 5 2 1
 
 1 1 2 3 
1 3 0 2 1 0 0 0
R2  R2  2 R1  
0 1 7 8 2 1 0 0
R3  R3  3R1 
 0 4 2 5 3 0 1 0
R4  R4  R1  
 0 4 2 5 2 0 1 1 
1 3 0 2 1 0 0 0
 
0 1 7 8 2 1 0 0
iii. using Row operations ;  , clearly we see that the
 0 4 2 5 3 0 1 0 
 
0 0 0 0 2 0 1 1 
matrix HAS NO INVERSE.

1 2 3 4
 
B. 3 5 7 9
 1 1 2 1
 
0 1 0 1
1 3 4 1 2 3
Using R4 to find A  A  1 3 7 9  1 3 5 7  2 .
1 2 1 1 1 2

20
  6 1 2 1   6 2 2 4 
   
2 1 0 1  1 1 2 3 
AC    the adj A  
 2 2 2 2   2 0 2 6 
   
 4 3 6 5   1 1 2 5 
 6 2 2 4 
 
1 1 1 2 3 
Therefore , A1   
2  2 0 2 6 
 
 1 1 2 5 
x1  3x2  x3  2
C. 2 x1  kx2  x3  5
x1  2 x2   k  2  x3  6
1 3 1  2
 
The augmented matrix formed is  2 k 1 5
1 2  k  2  6 
 
Using Row operations , the system can be reduce to Row Echelon form as
 
1 3 1 2 
 
0 1 
1

1 
 k 6 k 6 
 
0 0 k  9k  17
2
8k  49 
 
 k 6 k 6 
For this system to be consistent , the values of k would not be specific since it could have a
unique solution or infinitely many solution . Therefore , the question is not very specific.

QUESTION 2
 5 6 1  3 10 1 
   
A   3 7 4  and B   3 7 4 
 1 2 0   1 2 0 
   
Now the elementary matrix E is gotten from I 3 , by carrying out the same row operation
on I 3 that were carried out on A to obtain B as follows;
1 0 0 1 0 2
   
I 3   0 1 0  R1  2 R3  R1  0 1 0 
0 0 1 0 0 1
   
1 0 2
 
E  0 1 0
0 0 1
 

21
 EEF 313: LINEAR ALGEBRA (2014/2015) TEST 2

QUESTION 1
a. Is the set U   x  2z, x  3 y, x  y  z  | x, y, z    a subspace of  3
, the set of real
numbers ? Justify. Find also, the dimension of U .
b. What does it mean for a set of vectors to be linearly independent and linearly dependent ?
Verify whether the vectors : X 1  1, 2, 2  , X 2   0,1,1 and X 3   4,0,1 are linearly
dependent or independent in  3 .

QUESTION 2
Given the matrix , D below ,answer the question that follow :
1  3 4 2 5 4
 
 2  6 9 1 8 2
D
 2  6 9 1 9 7
 
 1 3 4 2 5 4 
a. If Col D is a subspace ofℝ𝑘 , find k .
b. If Nul D is a subspace of ℝ𝑘 , find k .
c. Find a nonzero vector in Nul D and a nonzero vector in Col D .
d. Find the basis for the column space of D .

QUESTION 3
Given that 𝑇: ℝ3 → ℝ3 such that T  a, b, c    2a  6b, a  2b, 5c  .
i. Show that T is a linear transformation.
1
Find the matrix, A, of T relative to the ordered unit basis for  and T if it exists.
3
ii.
iii. Compute ker T and ImT

22
 SOLUTION TO EEF 313: LINEAR ALGEBRA (2014/2015) TEST 2

QUESTION1
U   x  2 z, x  3 y, x  y  z  | x, y, z    a subspace of  3 ,
a.
Let U1 ,U 2 ,U | U1   x1  2 z1 , x1  3 y1 , x1  y1  z1 | x1 , y1 , z1    ,
U 2   x2  2 z2 , x2  3 y2 , x2  y2  z2 | x2 , y2 , z2   
We see that U  0 as 1,1,1 U .
Also U1  U 2    x1  2 z1 , x1  3 y1 , x1  y1  z1     x2  2 z2 , x2  3 y2 , x2  y2  z2 
  x1  2 z1     x2  2 z2  ,   x1  3 y1     x2  3 y2  , 
 
  x1  y1  z1     x2  y2  z2  
 U

Hence U is a subspace of ℝ3 .
U   x  2 z , x  3 y, x  y  z  | x, y, z   
Now,   x 1,1,1 , y  0, 3,1 , z  2, 0,1 | x, y, z   
 1,1,1 ,  0, 3,1 ,  2, 0,1  .

b. –Linearly independent: Given any set of vectors 1 2 V ,V ,...,V  , these vectors are said
p

to be linearly independent if the solution of the equation,

c1V1  c2V2  ...  c pVP  0
Is only the Trivial solution.

Linearly dependent : The set of vectors V ,V ,...,V  , are said to be linearly dependent
1 2 p

c1 , c2 ,..., c p
if there exist scalars not all zeroes that satisfy the equation;
c1V1  c2V2  ...  c pVP  0
X1  1, 2, 2  , X 2   0,1,1 and X 3   4,0,1
1  0  4  1 0 4  c1   0 
          
 c1  2   c2  1   c3  0   0   2 1 0  c2    0 
 2 1 1  2 1 1  c   0 
        3   
1 0 4 0
 
0 1 8 0 
Reducing this system to Echelon, we obtain 
 0 0 1 0 
 

c1  0, c2  0, c3  0; therefore the vectors are linearly independent

23
QUESTIONS 2
ColD is a subspace of   k  4 .
k
a.
b. NulD is a subspace of   k  6 .
k

1  3 4 2 5 4
 
 2  6 9 1 8 2
c. D 
 2  6 9 1 9 7
 
 1 3 4 2 5 4 
Let X   x1 , x2 , x3 , x4 , x5 , x6  , using this we can find a non-zero vector in NulD
 x1 
 
1  3 4 2 5 4   x2   0 
   
2  6 9 1 8 2   x3   0 
 
 2  6 9 1 9 7   x4   0 
   
 1 3 4 2  5  4   x5   0 
 
 x6 

Reducing the this system to Echelon form ,we obtain

 1 3 4 2 5 4 
 
0 0 1 3 2 6 
we see that x2 , x4 , x6 are free variables
0 0 0 0 1 5 
 
0 0 0 0 0 0
 3a  10b  13c 
 
 a 
 3b  4c 
X  
 b 
  5 c 
Hence the system has solutions  
 c 

therefore a non-zero vector in NulD is  3,1,0,0,0,0  , when a  1, b  0, c  0

Also , a non-zero vector in ColD is 1, 2, 2, 1
d. From the row echelon form of D , we see that the columns containing the leading one’s is are
columns: 1,3, and 5; these columns form a basis for ColD .

QUESTION 3
T  a, b, c    2a  6b, a  2b, 5c 
i.
let U   a1 , b1 , c1  and V   a2 , b2 , c2 

24
T U  V    2  a1  a2   6  b1  b2  ,  a1  a2   2  b1  b2  , 5  c1  c2  
  2a1  6b1 , a1  2b1 , 5c1    2a2  6b2 , a2  2b2 , 5c2  
 T U   T V  .
Also let c  scalar ; T  cU   T  ca1 , cb1 , cc1 
  2ca1  6cb1 , ca1  2cb1 , 5cc1 
 c  2a1  6b1 , a1  2b1 , 5c 
 cT U 
hence , T is a linear transformation
ii. T 1,0,0  ,  0,1,0  ,  0,0,1   2,1,0  ,  6, 2,0  ,  0,0, 5
Therefore, the matrix of transformation A is given by :
 2 6 0 
 
A   1 2 0 
 0 0 5 
 
Now, let us find A1 ; A  2 10   6  5   10
 10 5 0 10 30 0 
   
The cofactor matrix, C   30 10 0   adjA   5 10 0 
 0 0 2  0 0 2 
 
 
 1 3 0 
 
1
A1    1 0 
 2 
 1
 0 0  
 5
 
 1 3 0 
  a
 1    1 1 
T   a, b, c   
1
1 0   b    a  3b,  a  b,  c 
 2    2 5 
 1   c
 0 0  
 5
 1 1 
 T 1  a, b, c    a  3b,   b,  c 
 2a 5 
KertT  T  a, b, c   0 | a, b, c   
 2a  6b  0, a  2b  0, 5c  0 .
Solving this gives a  0, b  0, c0
 KerT   0, 0, 0  .

25
Im T  U   3 | T  X   U , X   a, b, c  | a, b, c   
 2a  6b, a  2b, 5c
 a  2,1, 0   b  6, 2, 0   c  0, 0, 5 
therefore, Im T   2,1, 0  ,  6, 2, 0  ,  0, 0, 5   .

26
 EEF 313: LINEAR ALGEBRA (2013/2014)

QUESTION 1
1 2 −1
a) Express 𝐴 𝑎𝑛𝑑 𝐴−1 as products of elementary matrices given that −1 1 2
2 8 0
0 1 7 8
b) Factor the matrix 𝐵 = 1 3 3 8 as 𝐵 = 𝐶𝐷𝐸𝐹 𝑤𝑕𝑒𝑟𝑒 𝐶, 𝐷, 𝐸 𝑎𝑟𝑒 elementary
−2 −5 1 8
matrices and 𝐹 is in row echelon form. Hence find the solution of the system of equations
given below
𝑏 + 7𝑐 = 8;
2𝑎 + 6𝑏 + 6𝑐 = 16;
−2𝑎 − 5𝑏 + 𝑐 = 8;

c) By row reduction to echelon form, find

1 3 0 2
−2 −5 7 4
3 5 2 1
1 −1 2 −3
QUESTION 2
a) By partitioning the matrix below into blocks, find its inverse
2 0 0 0 0
0 1 2 0 0
0 3 7 0 0
0 0 0 4 9
0 0 0 2 3

b) Consider the system of equations below

𝑥 + 𝑦 + 3𝑧 = 𝑎;
−𝑥 + 5𝑦 + 𝑧 = 5;
2𝑥 + 2𝑦 + 𝑘𝑧 = 4;

Using any matrix method of your choice, find the set of value(s)
i. Of k for which the system has a unique solution ;
ii. Of a for which the system has no solution ;
iii. Of a for which the system has infinitely many solutions

27
 SOLUTION TO EEF 313: LINEAR ALGEBRA (2013/2014)

QUESTION 1
a) We have to carry out row operations on the matrix to obtain the identity matrix , while
doing this on the identity matrix as well we obtain the inverse of the matrix A . The
elementary matrices leading to the inverse can also be multiplied with A to obtain the
inverse .The row operations on A to obtain the inverse has been done and these are the
same operations being done on the identity matrix

𝐴𝐵𝐶𝐷𝐸𝐹 = 𝐴−1
𝑊𝐻𝐸𝑅𝐸
1 0 0
𝐵 = 1 1 0 𝑅1 + 𝑅2 𝑎𝑛𝑑 − 2𝑅1 + 𝑅3
−2 0 1
1 0 0
𝐶 = −2 0 1 𝑅3 ↔ 𝑅2
1 1 0
1 0 0
1 1 1
𝐷= − 0 𝑅2
2 4 5
1 1 0
1
2 0 −
2
1 1
𝐸= − 0 − 2𝑅2 + 𝑅1 𝑎𝑛𝑑 − 3𝑅2 + 𝑅3
2 4
5 3
1 −
2 4
1
2 0 −
2
1 1
𝐹= − 0 − 2𝑅3
2 4
3
−5 −2
2
−8 −4 5/2
𝐴−1 = 2 1 −1/2
−5 −2 3/2
b) To factor B , we first reduce B into F , its row echelon equivalent is
0 1 7 8
𝐵= 1 3 3 8
−2 −5 1 8

1 3 3 8
𝑅1 → 𝑅2 0 1 7 8
−2 −5 1 8

1 3 3 8
2𝑅1 + 𝑅3 0 1 7 8
−2 −5 1 8

28
 1 3 3 8
−𝑅1 + 𝑅3 0 1 7 8 =𝐹
0 0 0 16

1 0 0
𝐸 = 𝑅2 + 𝑅3 = 0 1 0
0 0 1

1 0 0
𝐷 = −2𝑅1 + 𝑅3 = 0 1 0
−2 0 1
1 0 0
𝐶 = 𝑅2 − 𝑅1 = 0 1 0
−2 0 1

Hence we have 𝐵 = 𝐶𝐷𝐸𝐹

For the system of equation below we use the row reduced matrix F since the
augmented matrix of the system is equal to B , hence we obtain

𝑎 + 3𝑏 + 3𝑐 = 8
𝑏 + 7𝑐 = 8
0 = 16
Hence system of equations has no solution

c) Reducing the matrix to its echelon form

1 3 0 2
−2 −5 7 4
3 5 2 1
1 −1 2 −3

2𝑅1 + 𝑅2
1 3 0 2
0 1 7 8
−3𝑅1 + 𝑅3
0 −4 2 −5
0 −4 2 −5
−𝑅1 + 𝑅4

1 3 0 2
0 1 7 8
4𝑅2 + 𝑅3
0 0 30 27
0 0 30 27

4𝑅2 + 𝑅4

29
 1 3 0 2
0 1 7 8
−𝑅3 + 𝑅4
0 0 30 27
0 0 0 0

𝑇𝐻𝐸 𝐷𝐸𝑇𝐸𝑅𝑀𝐼𝑁𝐴𝑁𝑇 𝑂𝐹 𝑇𝐻𝐸 𝑀𝐴𝑇𝑅𝐼𝑋 = 1 ∗ 1 ∗ 30 = 30

QUESTION 2
Observe that the matrix is block diagonal and has the form
𝐷1 0
0 𝐷2

2 0 0
𝐷1 = 0 1 2
0 3 7

4 9
AND 𝐷2 =
2 3
𝐷1−1 0
𝐼𝑁𝑉𝐸𝑅𝑆𝐸 =
0 𝐷2−1

1
0 0
𝐷1−1 = 2
0 7 −2
0 −3 1
1 3
−
𝐷2−1 = 2 2
1 2
−
3 3
1
0 0 0 0
2
0 7 −2 0 0
0 −3 1 0 0
𝐻𝐸𝑁𝐶𝐸 𝐼𝑁𝑉𝐸𝑅𝑆𝐸 = 1 3
0 0 0 −
2 2
1 2
0 0 0 −
3 3

b) 𝑠𝑜𝑙𝑣𝑖𝑛𝑔 𝑡𝑕𝑒 𝑚𝑎𝑡𝑟𝑖𝑥 𝑏𝑦 𝑟𝑜𝑤 𝑟𝑒𝑑𝑢𝑐𝑡𝑖𝑛 𝑡𝑜 𝑒𝑐𝑕𝑒𝑙𝑜𝑛 𝑓𝑜𝑟𝑚

1 1 3 𝑎
𝑡𝑕𝑒 𝑒𝑐𝑕𝑒𝑙𝑜𝑛 𝑓𝑜𝑟𝑚 𝑜𝑓 𝑡𝑕𝑒 𝑎𝑢𝑔𝑚𝑒𝑛𝑡𝑒𝑑 𝑚𝑎𝑡𝑟𝑖𝑥 𝑖𝑠 0 6 4 5+𝑎
0 0 −6 + 𝑘 −2𝑎 + 4

30
i) For the system to have a unique solution −6 + 𝑘 ≠ 0 𝑘≠6
ii) For the system to have infinitely many solutions −6 + 𝑘 = −2𝑎 + 4 = 0
𝑘 = 6 𝑎𝑛𝑑 𝑎 = 2
iii) For the system to have no solution 𝑘 = 6 𝑎𝑛𝑑 𝑎 ≠ 2

31
 EEF 303: OPERATING SYSTEM (2014/2015) TEST 1
Instructions: choose the best answer (letter) from those provided.

Question A B C Answer
1 Is not the direct concern of the OS Running user Input Operations Access to the C
program cache
2 Is not concerned with data movement PC MBR I/OBR A
3 Takes care of short-term scheduling The Scheduler The Dispatcher Both B
4 Serial Processing was characterized by Single Tasking Multitasking Multiuser A
5 Multiprogramming is synonymous with Interrupt Enable Multiprocessors Both A
6 Multiprocessor systems depend on Interrupts The Scheduler Both B
7 A Process Image has to do with Its state Its complete Its location B
description
8 The Trace of a process has to do with its State Location Movements C
9 Concurrency is synonymous to Controlled access Deadlock Competition A
10 Race condition disfavors Deadlock Mutual exclusion Starvation C

11 Process cooperation by communication A Deadlock Mutual exclusion Starvation B

cannot cause
12 Processor scheduling ensures Multiprocessors Multiprogramming Either C
13 The degree of Multiprogramming is Short term Medium term Long term C
determined by scheduler scheduler scheduler
14 In Asymmetric multiprocessing there Single processor Multiprocessor Specialized C
is/are processor
15 In Multiprocessor scheduling there is likely Load sharing Deadlock Starvation A
to be
16 Processor affinity is all about Load sharing Processor Processor B
preference scheduling
17 Push migration is effected by An OS Routine A Processor A Process A
18 Multicore Processor systems are Many Processors Chip SMP B
characterized by having Multiprocessors
19 A Real Time processing is interested in Timeless Correctness Both C
20 Memory management is all about Keeping process Movement of Virtual memory B
in memory processes btw
memories
21 Internal Fragmentation is found in Fixed Paging Both C
Partitioning
22 External Fragmentation is found in Segmentation Paging Both A
23 The memory management is performed by OS Processor Both C
the
24 Compaction is performed by the OS Processor Both A
25 The lazy swapper is associated with Demand paging Swapping Paging A
26 Valid bits are used in association with Memory Hits/Misses/Faults Locality of B
Hierarchy reference
27 OS design is concerned with User System efficiency Both C

32
 Convenience
28 A time sharing system is multiuser because Human reaction Multiprocessor Multiprogramming A
of
29 Multithreading mostly results from Spawning Interrupt Multiprocessor A
30 In the five state process models some states Running The Blocked The New C
are abstraction this include the
state

33
 EEF 303: OPERATING SYSTEM (2014/2015) TEST 2

Question A B C Answer
1 The processor suspend state results Swapping Blocking Both
from
2 The fetch state of program execution Memory PC IR
cycle follows directions from the
3 Multiple interrupts is particularly Interrupt handler Priority Both
possible because of schemes
4 One of the reasons why Windows has It is coded in a lower Its proprietor Both
remained mostly proprietary is because language has reserved
unlike others rights
5 The success of Linux stems its being Less cumbersome Open source Non-
modular
6 A process is a program in Memory Execution Both A
7 The following is used to manage Tables Process image Process A
processes trace
8 Process switching leads to Multiprogramming Multithreadin Mode
g switchin
g
9 OOP is the mean producer of Multithreading Multiprogram Modulari
ming ty
10 Part of the OS executing like a process is Non process kernel Execution Process
called mode within user based OS
processes
11 In a cluster, CPU’s are Loosely coupled Specialized Tightly
coupled
12 Processor scheduling is performed by Processor OS Both
the
13 Concurrency has to do with the Existence of multiple Management Any
processes of multiple
processes
14 Makes interrupts possible PCB Process tables Process
trace
15 The mode of the OS is stored in IR PC PSW
16 Is OS specific Device controller Device driver Ports
17 Dynamic loading loads to Pages Routines Both
memory on demand
18 A bus comprise of Wires Protocols Both
19 Shared I/O uses Special instructions Same Both
instructions
20 A disk track is Circular An arc Both
21 In a RAID scheme, the disk can carry Independent data Related data Both
22 A file is a document Rest Abstract Both
23 Truncating a file means Releasing its spaces Deleting the Both
file

34
24 A system user who escalates his Masquerader Clandestine Misfeaso
privileges is a user r
25 The following attack is not directly Spyware Virus Trap
aimed at immediate(financial) gain door
26 Secret key encryption uses One key Two keys Both
27 A firewall can be a System Component Both
28 Protection mainly targets Intruders Processes Both
29 A secure OS has most services Enable Disable Free
by default
30 The following attack is mostly accidental Logic bomb Phishing DOS
Instructions: choose the best answer (letter) from those provided.

35
 EEF 303: OPERATING SYSTEM (2013/2014) TEST
Instructions: choose the best answer (letter) from those provided.
Question A B C Answer
1 A process image has to do State Attributes Location B
with its
2 A middleware aids in Program Program User logging A
development execution
3 Is a best description of an OS Helps in A software that Helps to B
program groups manage users
development common user
functions
4 A reason for OS development Difficulty in use Program System booting A
of hardware development
5 An interrupt is possible Interrupt Stack memory PCB C
mostly because of service routine
6 Multiprogramming resulted Existence of Increase in Existence of B
from multiple main memory multiple
programs size processes
7 Multiprocessing resulted Multiple Increase in Multiple C
from processes memory size processors
8 Process suspend state results Blocking Swapping Limited B
from memory
9 A process in the new state is Main memory Disk Both B
in
10 A process in the Main memory Disk Both B
ready/suspend state is in
11 In a nonprocess kernel mode Main memory Disk Kernel C
of OS execution, all modules
of the OS stay in
12 A thread is A miniature A miniature Both A
process program
13 Is not concerned with data of PC MBR I/OBR A
multiprogramming
14 Determines degree of Short-term Mid-term Long-term C
multiprogramming scheduler scheduler scheduler
15 Mid-term scheduler is A process exits When all When the B
invoked when the system processes are higher priority
blocked process arrives
16 Load balancing and Yes No Neither B
processor affinity are
complementary
17 Fail-soft has to do with Failure Failing while Failing while B
prevention preserving data reporting
18 Real-time scheduling is Yes No Neither A
synonymous with deadline
scheduling
19 The following problem Overlapping Sharing of Race condition A
doesn’t result from resources

36
 concurrency
20 The success of Linux stems Less Open source Modular B
from its being cumbersome
21 Mutual exclusion is not Compete Cooperate by Cooperate by C
produced when processes sharing communication
22 Takes care of short-term The scheduler The dispatcher Both B
scheduling
23 Serial processing was Single tasking Multitasking Multi-users A
characterized by

37
 EEF 315: SEQUENCE CONTROL (2014/2015)

QUESTION 1
Consider the chemical processor below

The sequence of operation is as follows;

i) When the operator presses the start button VA opens until the level of product A in
tank 1 reaches lsa
ii) VBopens until the level of product B in tank 1 reaches lsb
iii) VCopens until the level of product C in tank 2 reaches lsc
iv) VD opens until the level of product D in tank 2 reacheslsd
v) V01 and V02 open until the levels in tank 1 and tank 2 are ls1 and ls2 respectively
vi) The mixer and heater are turned on
vii) The mixer is turned off two minutes later
viii) The heater is turned off 27 minutes later
ix) VR opens until the level in the reactor islr.
When any of the product A,B,C or D is being fed into a tank, the corresponding light emitting diode
LA, LB, LC, or LD is turned on. Also, when tank 1 and 2 are feeding the mixtures into the reactor the
light emitting diode LR is turned on.

QUESTION 1
a. Draw a diagram to show the generalized structure of the control system
b. Construct a table to show the variables of the system
c. Design a Grafcet for the operation of the system

QUESTION 2
The sequence in question 1 is modified as follows
a) When the operator presses the start button, VA and VC open.
b) When the level in tank 1 reaches lsa, VA closes and VB opens until the level reacheslsb.
c) When the level in tank 2 reaches lsc, VC closes and VD opens until the level on tank 2
reaches lsd.

38
 d) When the level in tank 1 and 2 are lsb and lsdrespectively V01 and V02 open until the levels
in tank 1 and 2 are ls1 and ls2respectively
e) The mixer and heater are turned on
f) The mixer is turned off two minutes later
g) The heater is turned off 27 minutes later
h) VR opens until the level in the reactor is lr
1) Design a Grafcet for this sequence
2) Design a Grafcet to repeat the sequence 100 times

QUESTION 3
Re-consider the system in question 1. It is required to model the operation of the four valves VA, VB,
VC, and VD, as described by the first four items of the sequence (a,b,c,d).
a) Draw a timing diagram for the operation of the four valves
b) Design a state transition diagram for the operation of the four valves
c) Design a ladder network for the operation of the four valves

39
 SOLUTION TO EEF 315: SEQUENCE CONTROL (2014/2015)

QUESTION 1
a. Generalized Structure

40
 b. Table of variables

Input variables Output variables

Start VA

ls1 VB
ls2 VC
Lsa VD
Lsb VO1
Lsc VO2
Lsd MIXER
lr HEATER
LA
LB
LC

LD
LR

41
Grafcet

42
QUESTION 2
a. Grafcet

43
 b. Repeated sequence of 100 times.

n = number of times the sequence repeats itself

QUESTION 3
a. Timing diagram of the four valves

44
b. State transition diagram for the operation of the four valves
S0 = start of the sequence
S1 = VA is Active
S2 = VB is Active
S3 = VC is Active
S4 = VD is Active
S5 = end of sequence

45
c.

46
 EEF 315: SEQUENCE CONTROL (2013/2014)

QUESTION 1
Traffic lights are installed at the intersection of two roads A and B. A is a major road with high
traffic density, while B is a minor road. The green light on road A has a duration of 90 seconds while
the green light on road B has a duration of 60 seconds. The orange light on both roads have an
equal duration of 20seconds. Design
a) A timing diagram for the system.
b) A state transition diagram for the system.
c) A grafcet for the system.

QUESTION 2
Figure 1 shows a wagon which transport components on a production line. The wagon is driven by
a bi-directional motor M. limit switches lso, ls1, ls2 are installed at position 0, 1, and 2 respectively.
Light emitting diodes lo, l1, l2 indicate when the wagon stops at position 0, 1, and 2 respectively.
The sequence of operation is as follows;
I. Initially, the wagon is at position 0
II. When the operator presses the start button, the wagon moves to the right and stops at
position 2 for 30 seconds
III. The wagon moves to the left and stops at position 1 for 50 seconds
IV. The wagon returns to position 0
a) Draw a diagram to show the generalized structure of the system
b) Construct a table to show the variables of the system
c) Design a grafcet to model the sequence of operation.

Start Wagon M
Lo
L1
L2

47
QUESTION 3
Re-consider the system in Question 2. Design
a) A timing diagram for the system
b) A ladder network for the system
c) A state transition diagram for the system

48
FIRST SEMESTER
EXAMINATIONS

49
 EEF 301: ELECTROMAGNETIC WAVES (2014/2015)
QUESTION 1
a) Distinguish briefly between the transmission line approach and the electromagnetic wave
approach to signal transfer analysis.
b) What do you understand by transient time effect?
c) Using the line parameters, R, G, L and C, establish the relation for the characteristic
impedance of a transmission line.
d) S lossless transmission line is 200cm long and operates at a frequency of 5000Hz. The line
parameters are 𝐿 = 2.5 ∗ 10−3 𝐻/𝑚 and 𝐶 = 25𝜇𝐹/𝑚. Find the characteristic impedance,
the phase constant, the velocity on the line. Find also the input impedance for 𝑍𝐿 = 50Ω

QUESTION 2
1. A standing wave ratio on a lossless200Ω transmission line terminated in the unknown load
impedance is 1.5, and the nearest voltage minimum is at a distance of 0.4𝜆 from the load.
a) Determine the reflection coefficient Γ of the load and the unknown load impedance 𝑍𝐿 .
b) Determine also the position for a voltage maximum on the line if the reflection
coefficient has a phase angle of 𝜋 at that point.

QUESTION 3
1. Two hand-held radio transceivers with dipole antennas are separated by a large fixed
distance. If the transmitting antenna is vertical, what fraction of the maximum received
power will appear in the receiving antenna when it is inclined from the vertical by (a) 30°?
(b) 60°? (c) 90°?
2. A large flat sheet carries a uniformly distributed electric current with current per unit width
𝐽𝑠 .It is demonstrated that the current creates a magnetic field on both sides of the sheet,
1
parallel to the sheet and perpendicular to the current, with magnitude 𝐵 = 2 𝜇0 𝐽𝑠 . If the
current oscillates in time according to 𝐽𝑚𝑎𝑥 (cos 𝜔𝑡)𝑱 = 𝐽𝑚𝑎𝑥 (cos(−𝜔𝑡)) 𝑱 the sheet radiates
an electromagnetic wave as shown in Fig 1 .The magnetic field of the wave is described by
1
the wave function 𝑩 = 𝜇0 𝐽𝑚𝑎𝑥 (cos(𝑘𝑥 − 𝜔𝑡)) 𝒌
2
a) Find the wave function for the electric field in the wave.
b) Find the Poynting vector as a function of x and t.
c) Find the intensity of the wave.
d) What If? If the sheet is to emit radiation in each direction (normal to the plane of the
sheet) with intensity 570 W/m2, what maximum value of sinusoidal current density is
required?

Fig 1

50
QUESTION 4
1. A dish antenna having a diameter of 20.0 m receives (at normal incidence) a radio signal
from a distant source, as shown in Fig 2. The radio signal is a continuous sinusoidal wave
with amplitude 𝐸𝑚𝑎𝑥 = 0.2𝜇𝑉/𝑚. Assume the antenna absorbs all the radiation that falls on
the dish.
a) What is the amplitude of the magnetic field in this wave?
b) What is the intensity of the radiation received by this antenna?
c) What is the power received by the antenna?
d) What force is exerted by the radio waves on the antenna?

Fig 2
2. Suppose the above radio signal is a linearly polarized radio wave of wavelength 2km and is
directed along the positive x-axis. Assuming the electric field vector vibrates in the xy plane
and the magnetic field wave can be written in the form 𝐵 = 𝐵𝑚𝑎𝑥 sin(𝑘𝑥 − 𝜔𝑡),
a) Give values for k and 𝜔. Also determine in which plane the magnetic field vector
vibrates.
b) Calculate the average value of the Poyting vector for this wave.
c) What radiation pressure would this wave exert if it were directed at normal incidence
onto a perfectly reflecting sheet?

QUESTION 5
1.
a) Consider a sinusoidal electromagnetic wave with fields 𝑬 = 𝐸𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡) 𝒋 and
𝑩 = 𝐵𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡 + 𝜙) 𝒌 with −𝜋 ≤ 𝜙 ≤ 𝜋. Show that if 𝑬 and 𝑩 are to satisfy the
𝜕𝐸𝑦 (𝑥,𝑡) 𝜕𝐵𝑧 (𝑥,𝑡) 𝜕𝐵𝑧 (𝑥,𝑡) 𝜕𝐸𝑦 (𝑥,𝑡)
relations =− and − = 𝜇0 𝜀0 , then 𝐸𝑚𝑎𝑥 =c𝐵𝑚𝑎𝑥 and
𝜕𝑥 𝜕𝑡 𝜕𝑥 𝜕𝑡
𝜙 = 0.
(The result 𝜙 = 0 means that 𝑬 and 𝑩 fields oscillate in phase)
b) Show that the magnetic field B(x , t) in a plane electromagnetic wave propagating in the
+ x-direction satisfies the electromagnetic wave equation in the vacuum.
𝜕𝐸𝑦 (𝑥,𝑡) 𝜕𝐵𝑧 (𝑥,𝑡)
(Hint: Take partial derivative of 𝜕𝑥
=− 𝜕𝑡
with respect to t and the partial
𝜕𝐵𝑧 (𝑥,𝑡) 𝜕𝐸𝑦 (𝑥,𝑡)
derivative of − 𝜕𝑥
= 𝜇0 𝜀0 𝜕𝑡
with respect to x. Then combine the results.)
2. The microwaves in a certain oven have a wavelength of 12.2cm.
a) How wide must this oven be so that it will contain five anti-nodal planes of the electric
field along its width in the standing wave pattern?
b) What is the frequency of these microwaves?
c) Suppose a manufacturing error occurred and the oven was made 5.0cm longer than
specified in part (a). In this case what would be the frequency of the microwaves for
there will still be five anti-nodal planes of the electric field along the width of the oven?

51
 SOLUTION TO EEF 301: ELECTROMAGNETIC WAVES (2014/20015)
All characters in bold are vectors.

PROBLEM 1
a) The transmission line approach of signal transfer deals with the phenomena of low
frequencies and high power while the electromagnetic wave approach of signal transfer
deals with phenomena of high frequency and low power.
b) Given a two parallel conductor transmission line, there will always be a potential difference
between two points on the line, no matter how close they may appear to be. This implies
there will always be a time difference for a signal to travel from one point on the line to
another. This is known as the transient time effect.
c) We know that for a transmission line,
𝑑𝑉 𝑑𝐼
= −(𝑅 + 𝑗𝑤𝐿)𝐼 , = −(𝐺 + 𝑗𝑤𝐿)𝑉 𝑎𝑛𝑑 𝑉(𝑥) = 𝑉 + 𝑒 −𝛾𝑥 + 𝑉 −𝑒 𝛾𝑥
𝑑𝑥 𝑑𝑥
𝑑𝑉(𝑥)
= −𝛾𝑉 +𝑒 −𝛾𝑥 + 𝛾𝑉 − 𝑒 𝛾𝑥 = −(𝑅 + 𝑗𝑤𝐿)𝐼(𝑥), 𝑎𝑛𝑑 𝐼(𝑥) = 𝐼 + 𝑒 −𝛾𝑥 + 𝐼 − 𝑒 𝛾𝑥
𝑑𝑥
𝑑𝐼(𝑥)
= −𝛾𝐼 + 𝑒 −𝛾𝑥 + 𝛾𝐼 − 𝑒 𝛾𝑥 = −(𝐺 + 𝑗𝑤𝐿)𝑉(𝑥)
𝑑𝑥
From the two preceding equations we have
−𝛾𝑉 + 𝑒 −𝛾𝑥 + 𝛾𝑉 − 𝑒 𝛾𝑥 = −(𝑅 + 𝑗𝑤𝐿)(𝐼 + 𝑒 −𝛾𝑥 + 𝐼 − 𝑒 𝛾𝑥 )
Following rigorous expansion and simplification, we obtain
𝑉 + (𝑅 + 𝑗𝑤𝐿) (𝑅 + 𝑗𝑤𝐿)
+
= = = , 𝑠𝑖𝑛𝑐𝑒 𝛾 = (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿)
𝐼 𝛾 (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿)
Also we are going to have
𝑉 − −(𝑅 + 𝑗𝑤𝐿) (𝑅 + 𝑗𝑤𝐿)
−
= =−
𝐼 𝛾 (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿)
Hence the characteristic impedance 𝑍0 will be given as
𝑉+ (𝑅 + 𝑗𝑤𝐿) (𝑅 + 𝑗𝑤𝐿)
𝑍0 = = =
𝐼+ (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿) (𝐺 + 𝑗𝑤𝐿)

𝑉− (𝑅 + 𝑗𝑤𝐿) (𝑅 + 𝑗𝑤𝐿)
𝑍0 = −
=− =−
𝐼 (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿) (𝐺 + 𝑗𝑤𝐿)
d) For lossless transmission line ,𝑅 = 𝐺 = 0. Therefore 𝑍0 will become
𝑗𝑤𝐿 𝐿 2.5 ∗ 10−3
𝑍0 = = = = 10Ω
𝑗𝑤𝐶 𝐶 25 ∗ 10−6
𝑍0 = 10Ω
𝛾 = 𝛼 + 𝑗𝛽 = (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿)

For lossless transmission line, 𝛾 = 𝛼 + 𝑗𝛽 = (𝑅 + 𝑗𝑤𝐿)(𝐺 + 𝑗𝑤𝐿) = (𝑗𝑤)2 𝐿𝐶 = 𝑗𝑤 𝐿𝐶

𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝛼 = 0, 𝛽 = 𝑤 𝐿𝐶 = 2𝜋𝑓 𝐿𝐶 = 𝑝𝑕𝑎𝑠𝑒 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡.
𝛽 = 𝑤 𝐿𝐶 = 2𝜋𝑓 𝐿𝐶 = 2𝜋 ∗ 5000 2.5 ∗ 10−3 ∗ 25 ∗ 10−6 = 7.85𝑟𝑎𝑑/𝑚

52
 𝑤 2𝜋𝑓 5000
𝑆𝑝𝑒𝑒𝑑 = 𝑣 = = 𝑓𝜆 = = 2𝜋 ∗ = 4002.03 𝑚/𝑠
𝛽 𝛽 7.85
𝑣 = 4002.03 𝑚𝑠 −1

The input impedance is given by

𝑍𝐿 cos 𝛽𝑙 + 𝑗𝑍0 sin 𝛽𝑙 50 cos(7.85 ∗ 2) + 𝑗50 sin(7.85 ∗ 2)
𝑍𝑖𝑛 = = = 49.92 + 𝑗1.91
𝑍0 cos 𝛽𝑙 + 𝑗𝑍𝐿 sin 𝛽𝑙 10 cos(7.85 ∗ 2) + 𝑗10 sin(7.85 ∗ 2)
𝑍𝑖𝑛 = 49.92 + 𝑗1.91

PROBLEM 2
a) The voltage at a point l on the transmission line(lossless) is given by
𝑉(𝑙) = 𝑉 +𝑒 𝑗𝛽𝑙 1 + Γ𝑒 −2𝑗𝛽𝑙 , 𝑎𝑛𝑑 Γ = Γ ej∅
VSWR − 1 1.5 − 1 1
Γ = = =
VSWR + 1 1.5 + 1 5
𝑉(𝑙) = 𝑉 + 𝑒 𝑗𝛽𝑙 1 + Γ𝑒 −2𝑗𝛽𝑙 = 𝑉 + 𝑒 𝑗𝛽𝑙 1 + Γ ej∅ 𝑒 −2𝑗𝛽𝑙 = 𝑉 + 𝑒 𝑗𝛽𝑙 1 + Γ ej(∅−2𝛽𝑙 )
𝐹𝑜𝑟 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑚𝑖𝑛𝑖𝑚𝑢𝑚, (∅ − 2𝛽𝑙) = 𝜋 , 3𝜋 , 5𝜋, ….
𝐿𝑒𝑡 (∅ − 2𝛽𝑙) = 𝜋 , 𝑖. 𝑒 ∅ = 𝜋 + 2𝛽𝑙

2𝜋
∅=𝜋+2∗ 0.4𝜆 = 2.6𝜋 = 0.6𝜋
𝜆
1
𝐵𝑢𝑡 Γ = Γ ej∅ = ej0.6𝜋
5
1 j0.6𝜋
𝑍0 (1 + Γ) 200 1 + 5 e
𝑍𝐿 = = = −2.8 ∗ 10−14 − 𝑗309.04
1−Γ 1 j0.6𝜋
1− e
5
𝑍𝐿 = −2.8 ∗ 10−14 − 𝑗309.04
b) 𝑉 = 𝑉 +𝑒 𝑗𝛽𝑙 1 + Γ ej(∅−2𝛽𝑙 ) , for voltage maximum (∅ − 2𝛽𝑙) = 0 , 2𝜋 , 4𝜋, ….

∅
𝐿𝑒𝑡 (∅ − 2𝛽𝑙) = 𝜋 , 𝑖. 𝑒 ∅ = 2𝛽𝑙 , 𝑖. 𝑒 𝑙 =
2𝛽
𝜋 𝜆 2𝜋
𝑊𝑖𝑡𝑕 ∅ = 𝜋 , 𝑙 = = , 𝑠𝑖𝑛𝑐𝑒 𝛽 =
2𝜋 4 𝜆
2∗
𝜆

PROBLEM 3
1) Consider the two transceivers below

When one of the transceivers is inclined at angle 𝜃 with respect to the other one, the amount of power it
receives reduces. The fraction of the maximum received power that appears in the receiving is determined as
follows.

53
 𝜀2
𝑝𝑜𝑤𝑒𝑟 = 𝑃 = , 𝑤𝑕𝑒𝑟𝑒 𝜀 𝑖𝑠 𝑡𝑕𝑒 𝑖𝑛𝑑𝑢𝑐𝑒𝑑 𝑒𝑚𝑓. 𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑃 𝛼 𝜀 2
𝑅
𝐹𝑟𝑜𝑚 𝐹𝑎𝑟𝑎𝑑𝑎𝑦 ′ 𝑠 𝑙𝑎𝑤, ∆𝑉 = −𝐸 ∗ ∆𝑙 = −𝐸 ∗ 𝑙 ∗ cos(𝜃) = 𝜀
𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝜀 𝛼 cos 𝜃 . 𝑇𝑕𝑒𝑟𝑒𝑓𝑜𝑟𝑒 𝑃 𝛼 𝑐𝑜𝑠𝜃, 𝑖. 𝑒. 𝑃 = 𝑃𝑚𝑎𝑥 𝑐𝑜𝑠𝜃
a) 𝜃 = 30°, 𝑃 = 𝑃𝑚𝑎𝑥 𝑐𝑜𝑠30° = 𝑃𝑚𝑎𝑥 (0.866). 𝑇𝑕𝑢𝑠 𝑃 = 86.6% 𝑜𝑓 𝑃𝑚𝑎𝑥
b) 𝜃 = 60°, 𝑃 = 𝑃𝑚𝑎𝑥 𝑐𝑜𝑠60° = 𝑃𝑚𝑎𝑥 (0.5). 𝑇𝑕𝑢𝑠 𝑃 = 50% 𝑜𝑓 𝑃𝑚𝑎𝑥
c) 𝜃 = 90°, 𝑃 = 𝑃𝑚𝑎𝑥 𝑐𝑜𝑠90° = 𝑃𝑚𝑎𝑥 (0). 𝑇𝑕𝑢𝑠 𝑃 = 0% 𝑜𝑓 𝑃𝑚𝑎𝑥
2)
1
a) We have 𝐵 = 2 𝜇0 ∗ 𝐽𝑠 , 𝑱𝒔 = 𝐽𝑚𝑎𝑥 cos(−𝑤𝑡) 𝒋 = 𝐽𝑚𝑎𝑥 cos(𝑤𝑡) 𝒋
1
𝑩 = 𝜇0 ∗ 𝐽𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) 𝒌, 𝑎𝑛𝑑 𝑡𝑕𝑒 𝑤𝑎𝑣𝑒 𝑡𝑟𝑎𝑣𝑒𝑙𝑠 𝑖𝑛 𝑡𝑕𝑒 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑥 − 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛.
2
𝑖. 𝑒. 𝒄 = 𝑐𝒊
𝐸 1
𝑬𝑥𝑩 = 𝑪 = 𝑐, 𝑡𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝐸 = 𝑐𝐵. 𝑇𝑕𝑢𝑠 𝑬 = 𝜇0 𝑐 ∗ 𝐽𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) 𝒋
𝐵 2
1 1 1 1 2
b) 𝑺 = 𝜇 𝑬𝑥𝑩 𝒏 = 𝜇 𝐸𝐵𝑠𝑖𝑛(90°)𝒊 = 𝜇 𝐸𝐵𝒊 = 4𝜇 𝐽 𝑚𝑎𝑥 cos 2 (𝑘𝑥 − 𝑤𝑡) 𝒊
0 0 0 0
1 1 1
c) 𝐼𝑛𝑡𝑒𝑛𝑠𝑖𝑡𝑦 = 𝐼 = 𝐸 𝐵 , 𝑎𝑛𝑑 𝐸0 = 𝜇 𝑐 ∗ 𝐽𝑚𝑎𝑥 , 𝐵0 = 𝜇0 ∗ 𝐽𝑚𝑎𝑥
2𝜇 0 0 0 2 0 2
1 1 1 1
𝐼= ∗ 𝜇0 𝑐 ∗ 𝐽𝑚𝑎𝑥 ∗ 𝜇0 ∗ 𝐽𝑚𝑎𝑥 = 𝜇0 𝑐 ∗ 𝐽2 𝑚𝑎𝑥
2𝜇0 2 2 8
1
d) 𝐼 = 8 𝜇0 𝑐 ∗ 𝐽2 𝑚𝑎𝑥 𝑎𝑛𝑑 𝐼 = 570𝑊/𝑚2 ,

𝐼 570
𝐽𝑚𝑎𝑥 = 8∗ = = 3.48𝐴/𝑚
𝜇0 𝑐 4 ∗ 𝜋 ∗ 10−7 ∗ 3 ∗ 108

PROBLEM 4
1)
a) 𝑊𝑒 𝑕𝑎𝑣𝑒
𝐸𝑚𝑎𝑥 𝐸𝑚𝑎𝑥 10−6
= 𝑐, 𝑡𝑕𝑢𝑠 𝐵𝑚𝑎𝑥 = = 0.2 ∗ = 6.67 ∗ 10−16 𝑇
𝐵𝑚𝑎𝑥 𝑐 3 ∗ 108
b)
1 1 1 ∗ 0.2 ∗ 10−6
𝑆𝑎𝑣 = 𝐼 = 𝐸𝑚𝑎𝑥 𝐵𝑚𝑎𝑥 = 𝐸 2 𝑚𝑎𝑥 =
2𝜇0 2𝜇0 𝑐 2 ∗ 4 ∗ 𝜋 ∗ 10−7 ∗ 3 ∗ 108
𝑆𝑎𝑣 = 5.31 ∗ 10 𝑊/𝑚2
−17

c) 𝑃𝑜𝑤𝑒𝑟 𝑟𝑒𝑐𝑒𝑖𝑣𝑒𝑑,
2
20
𝑃 = 𝑆𝑎𝑣 ∗ 𝐴 = 𝑆𝑎𝑣 ∗ 𝜋 ∗ 𝑅 2 = 5.31 ∗ 10−17 ∗ 𝜋 = 1.67 ∗ 10−14 𝑊
2
d) We have

54
 𝐹 𝑆𝑎𝑣 𝑆𝑎𝑣 𝐴 𝑃
𝑃𝑟 = = 𝑓𝑜𝑟 𝑝𝑒𝑟𝑓𝑒𝑐𝑡 𝑎𝑏𝑠𝑜𝑟𝑏𝑒𝑟. 𝑇𝑕𝑢𝑠 𝐹 = =
𝐴 𝑐 𝑐 𝑐
1.67 ∗ 10−14
𝐹= = 5.56 ∗ 10−23
3 ∗ 108
2)
a) We have
2∗𝜋 2∗𝜋
𝑘= = = 3.14 ∗ 10−3 𝑟𝑎𝑑/𝑚
𝜆 2 ∗ 103
𝑤 = 𝑘𝑐 = 3.14 ∗ 10−3 ∗ 3 ∗ 108 = 9.42 ∗ 105 𝑟𝑎𝑑
b)
1
𝑆𝑎𝑣 = 𝐼 = 𝐸 𝐵 = 5.31 ∗ 10−17 𝑊/𝑚2
2𝜇0 𝑚𝑎𝑥 𝑚𝑎𝑥
c)
2𝑆𝑎𝑣 2 ∗ 5.31 ∗ 10−17
𝑃𝑟 = = = 3.54 ∗ 10−25
𝑐 3 ∗ 108

PROBLEM 5

1)
a) 𝑬 = 𝐸𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡) 𝒋 , 𝐸𝑦 (𝑥, 𝑡) = 𝐸𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡) 𝑎𝑛𝑑
𝑩 = 𝐵𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡 + ∅) 𝒌, 𝐵𝑧 (𝑥, 𝑡) = 𝐵𝑚𝑎𝑥 sin(𝑘𝑥 − 𝑤𝑡 + ∅)
𝜕𝐸𝑦 (𝑥, 𝑡) 𝜕𝐵𝑧 (𝑥, 𝑡)
= 𝑘𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) , = −𝑤𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅)
𝜕𝑥 𝜕𝑡
𝜕𝐸𝑦 (𝑥, 𝑡) 𝜕𝐵𝑧 (𝑥, 𝑡)
𝐼𝑓 =− , 𝑡𝑕𝑒𝑛
𝜕𝑥 𝜕𝑡
𝑘𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) = 𝑤𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅) . 𝐵𝑢𝑡 𝑤 = 𝑘𝑐 , 𝑡𝑕𝑢𝑠
𝑘𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) = 𝑘𝑐𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅)
𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) = 𝑐𝐵𝑚𝑎 𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅)
𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝐸𝑚𝑎𝑥 = 𝑐𝐵𝑚𝑎𝑥 𝑎𝑛𝑑 ∅ = 0
𝜕𝐸𝑦 (𝑥, 𝑡) 𝜕𝐵𝑧 (𝑥, 𝑡)
= −𝑤𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡) , = 𝑘𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅)
𝜕𝑡 𝜕𝑥
𝜕𝐵𝑧 (𝑥, 𝑡) 𝜕𝐸𝑦 (𝑥, 𝑡)
− = 𝜇0 𝜀0 , 𝑡𝑕𝑒𝑛
𝜕𝑥 𝜕𝑡
−𝑘𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅) = −𝑤𝜇0 𝜀0 𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡)
−𝑘𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅) = −𝑘𝑐𝜇0 𝜀0 𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡)
𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅) = 𝑐𝜇0 𝜀0 𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡)
1 1
𝐵𝑢𝑡 2 = 𝜇0 𝜀0 , 𝑡𝑕𝑢𝑠 = 𝑐𝜇0 𝜀0
𝑐 𝑐
1
𝐵𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡 + ∅) = 𝐸𝑚𝑎𝑥 cos(𝑘𝑥 − 𝑤𝑡)
𝑐
𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝐸𝑚𝑎𝑥 = 𝑐𝐵𝑚𝑎𝑥 𝑎𝑛𝑑 ∅ = 0

55
 b) We have
𝜕𝐸𝑦 (𝑥, 𝑡) 𝜕𝐵𝑧 (𝑥, 𝑡)
=−
𝜕𝑥 𝜕𝑡
𝜕𝐸𝑦 (𝑥, 𝑡) 𝜕𝐵𝑧 (𝑥, 𝑡)
𝜕 𝜕
𝜕𝑥 𝜕𝑡
=−
𝜕𝑡 𝜕𝑡
𝜕 2 𝐸𝑦 (𝑥, 𝑡) 𝜕 2 𝐵𝑧 (𝑥, 𝑡)
=−
𝜕𝑥𝜕𝑡 𝜕𝑡 2
Also
𝜕𝐵𝑧 (𝑥, 𝑡) 𝜕𝐸𝑦 (𝑥, 𝑡)
− = 𝜇0 𝜀0
𝜕𝑥 𝜕𝑡
𝜕𝐵 (𝑥, 𝑡) 𝜕𝐸 𝑦 (𝑥, 𝑡)
𝜕 − 𝑧 𝜕 𝜕 2 𝐸𝑦 (𝑥, 𝑡) 𝜕 2 𝐵𝑧 (𝑥, 𝑡)
𝜕𝑥 𝜕𝑡
= 𝜇0 𝜀0 = 𝜇0 𝜀0 == −𝜇0 𝜀0
𝜕𝑥 𝜕𝑥 𝜕𝑥𝜕𝑡 𝜕𝑡 2
2 (𝑥, 2 (𝑥, 2 (𝑥,
𝜕 𝐵𝑧 𝑡) 𝜕 𝐵𝑧 𝑡) 1 𝜕 𝐵𝑧 𝑡)
𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 2
= 𝜇0 𝜀0 2
= 2
𝜕𝑥 𝜕𝑡 𝑐 𝜕𝑡 2
𝜕 2 𝐵𝑧 (𝑥, 𝑡) 1 𝜕 2 𝐵𝑧 (𝑥, 𝑡)
=
𝜕𝑥 2 𝑐2 𝜕𝑡 2
2)
a) The distance between two anti-nodal points of E is 𝜆/2. For the oven to contain five
anti-nodal planes of E, the width must be equal to
𝜆 4 ∗ 12.2 ∗ 10−2 𝑚
𝑤=4 = = 24.4 ∗ 10−10
2 2
b)
𝑐 3 ∗ 108
𝑐 = 𝑓𝜆, 𝑓= = = 2.459 ∗ 109 𝐻𝑧 = 2.459𝐺𝐻𝑧
𝜆 0.122
c) With this error, we have
𝜆1 𝜆2
4 + 5𝑐𝑚 = 4 , 𝜆1 = 12.2𝑐𝑚
2 2
𝑇𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝜆2 = 14.7𝑐𝑚
𝑐 3 ∗ 108
𝑓= = = 2.041𝐺𝐻𝑧
𝜆2 14.7𝑐𝑚

56
 EEF 313: LINEAR ALGEBRA (2014/2015)
QUESTION 1
a) Solve the system

2𝑥 + 2𝑦 + 2𝑧 + 2𝑡 = 6
2𝑥 − 𝑦 − 𝑧 − 𝑡 = 3
𝑥 − 𝑦 + 2𝑧 − 𝑡 = 10
3𝑥 + 𝑦 + 𝑧 + 2𝑡 = 6
Using the row-echelon method.

b) Show that the system :

𝑥 + 4𝑦 + 3𝑧 = 𝑝
−𝑥 + 5𝑦 + 𝑧 = 5
3𝑥 + 3𝑦 + 𝑘𝑧 = 3
Has a unique solution unless k=5
If k=5 give the values of p such that the solution shall be
i. Empty
ii. Infinite
c) Let 𝑥, 𝑦, 𝑧 be real numbers. Show that
1 𝑥 𝑥2
i. 1 𝑦 𝑦 2 = (𝑦 − 𝑥)(𝑧 − 𝑦)(𝑧 − 𝑥)
1 𝑧 𝑧2

1 1 1
ii. 𝑥 𝑦 𝑧 = (𝑥 − 𝑦)(𝑦 − 𝑧)(𝑧 − 𝑥)
𝑦𝑧 𝑧𝑥 𝑥𝑦

1 2 3
d) Find the cofactor matrix of the of the matrix 𝐵 = −1 0 4
3 −2 5

QUESTION 2
a) Show that the set 𝐴 = *(1,1,0), (1,2, −1), (0,1,2)+ is a basis for 𝑅 3
b) Find the dimension of the subspace constituted by the set of all solutions of the system
X1 + X2 + 5X3 + 2X4 = 0
X1 − 2X3 + 4X4 = 0

c) Find the basis for

i. The null space of A
ii. The column space of A

57
 2 2 −1 0 1
−1 −1 2 −3 1
𝐴=
1 1 −2 0 −1
0 0 1 1 1

d) Suppose X, Y, U, V are linearly independent vectors in a real vector space . Show that the vectors
X−U+V, 2X−Y+U, X+Y−4U+3V, are linearly dependent
QUESTION FIVE ([3, 3, 4, 3, 5, 2], [3, 5]) = 28 marks
i. Given the map 𝑇: 𝑅 3 𝑅 3 defined by 𝑇 (𝑎, 𝑏, 𝑐 ) = (3𝑎 + 2𝑏 − 2𝑐, −𝑎 + 𝑐, 𝑎 + 𝑏)
a) Show that T is a linear transformation
b) The matrix A of this linear transformation relative to the ordered unit bases for 𝑅 3
;
c) The characteristic polynomial;
d) The characteristic roots ;
e) The corresponding characteristic vectors ;
f) a diagonal matrix for T

ii. Let 𝑇(1,0,0) = (2,0, −1)

𝑇(0, 1, 0) = (0, −2, 0) ,
𝑇(𝑂, 𝑂, 1) = (1, −1, 1)

a) Find 𝑇(𝑋, 𝑌, 𝑍) for any vector 𝑋, 𝑌, 𝑍

b) Find the nullity and the rank of T.

58
 SOLUTION TO EEF 313: LINEAR ALGEBRA (2014/2015)
QUESTION 1
1 x x2 1 x x2 1 x x2
a. i. 1 y y2  0 yx y  x   y  x  z  x  0 1
2 2
yx
1 z z2 0 zx z 2  x2 0 1 zy
1 x x2
  y  x  z  x  0 1 yx
0 0 zy
  y  x  z  x  z  y  QED
1 1 1 1 1 1 1 1 1
ii. x y z  0 yx zx  0 yx zx
yz zx xy 0 zx  yz xy  yz 0 0 y  z  x  z  z  x
  y  x  z  y  z  x 
  x  y  y  z  z  x  QED

x  2 y  4z  6  1 2 4  x   6 
b. i.
    
y  z  1   0 1 1  y    1 
x  3 y  5 z  10  1 3 5  z  10 
    
1 2 4 6

The augmented matrix formed from this system is 0 1

 1 1
1 3 5 10 

1 2 4 6

Reducing this matrix to echelon form , we obtain 0 1

 1 1
0 0 0 3 

Therefore , the system has No solution.
x  y  2z  0 1 1 2  x   0 
ii. 3 x  y  2 z  2  3
    
 1 2  y    2 
2 x  2 y  z  6 2 2 1    
  z   6 
1 1 2 0

The augmented matrix is 3

 1 2 2
2 2 1 6 


59
 1 1 2 0 

Reducing this matrix to echelon form , we obtain 0 1 2 1

 
 0 0 5 10 
 
Therefore the system has a Unique solution, which is
x  2y  0  1 2 0  x   0  x  1, y  3, z  2
ii.
    
y  z  2   0 1 1 y    2 
x  y  z  2  1 1 1  z   2 
    
1 2 0 0
 
The augmented matrix formed from this system is 0
 1 1 2 
1 1 1 2 

1 2 0 0
 
Reducing this system to echelon form , we obtain 0
 1 1 2 
0 0 0 0 

Therefore , the system has Infinitely many solutions given by
x1  3x2  x3  2 1 3 1   x1   2  x  4  2t , y  2  t , z  t
    
c. 2 x1  kx2  x3  5   2 k 1   x2    5 
x1  2 x2   k  2   6 1 2
  k  2    x3   6 
1 3 1 
 
Let A   2 k 1  , Cramer’s Rule is NOT applicable for values of k such that A  0 .
 1 2  k  2 
 
A  0  k  k  2   2  3  2  k  2   1  4  k  0
 k 2  9k  17  0
9  13
k
2
 9  13 
Hence, Cramer's Rule is applicable for all k     
 2 
1 3 1 
 
when k  0;  A   2 0 1  ,  A  17
 1 2 2 
 
2 3 1 1 2 1 1 3 2
5 0 1 2 5 1 2 0 5
6 2 2 18 1 2 6 11 1 2 6 49
x1   , x2   , x3   .
17 17 17 17 17 17

60
  2 1 3  2 5 4 
 
d. A  0 4 5  A  3 .The cofactor matrix
 
  C  4 7 5 
 1 2 2   7 10 8 
   
 2 4 7   2 4 7 
  1 1 
 adjA  C   5 7 10   A   5
T
7 10 
 4 5 8  3
   4 5 8 
 2 6 2
 
B   3 8 0 
 4 9 2
 
U L
1 3 1 2 0 0
   
 3 8 0   0
4 9 2   
  
1 3 1  2 0 0
   
0 1 3  3 0
0 3 2  4 
  
1 3 1  2 0 0
   
0 1 3  3 1 0 
0 0 7  4 3 
   

1 3 1  2 0 0
   
0 1 3  3 1 0 
0 0 1   4 3 7 
  
2 0 0  1 3 1 
  
 B   3 1 0  0 1 3   LU .
4 3 7  
  0 0 1 
a  3b  c  1  2 6 2  a   2   2 0 0  1 3 1  a   2 
 3a  8b  2   3 8 0  b    2    3 1 0  0 1 3  b    2   LUy  b
          
4a  9b  2c  3  4 9 2  c   3   4 3 7  0 0 1  c   3 
          
Let X  Uy | X   x, y, z   LX  b
 2 0 0  x   2 
    
 3 1 0  y    2   x  1, y  5, z  2.
 4 3 7  z   3 
    

61
 1 3 1  a   1 
    
 0 1 3  b    5  a  2, b  1, c  2
 0 0 1  c   2 
    

QUESTION 2
U   x  2 z, x  3 y, x  y  z  | x, y, z    a subspace of  3 ,
a.
Let U1 ,U 2 ,U | U1   x1  2 z1 , x1  3 y1 , x1  y1  z1 | x1 , y1 , z1    ,
U 2   x2  2 z2 , x2  3 y2 , x2  y2  z2 | x2 , y2 , z 2   
We see that U  0 as 1,1,1 U .
Also U1  U 2    x1  2 z1 , x1  3 y1 , x1  y1  z1     x2  2 z2 , x2  3 y2 , x2  y2  z2 
  x1  2 z1     x2  2 z2  ,   x1  3 y1     x2  3 y2  , 
 
  x1  y1  z1     x2  y2  z2  
 U

Hence U is a subspace of  3 .

U   x  2 z , x  3 y, x  y  z  | x, y, z   
Now,   x 1,1,1 , y  0, 3,1 , z  2, 0,1 | x, y, z   
 1,1,1 ,  0, 3,1 ,  2, 0,1  .

-Linearly independent: Given any set of vectors

V ,V ,...,V  , these vectors are said to be linearly independent
1 2 p

if the solution of the equation,

c1V1  c2V2  ...  c pVP  0
Is only the Trivial solution.

-Linearly dependent : The set of vectors

V ,V ,...,V  ,
1 2 p
are said to be linearly dependent if there exist scalars
c1 , c2 ,..., c p
not all zeroes that satisfy the equation;
c1V1  c2V2  ...  c pVP  0
1  0  4   0   1 0 1  c1   0 
            
c1  2   c2  1   c3  0    0    2 1 0  c2    0 
b. we have ;
 2 1  0   0   2 1 0  c   0 
          3   
solving this gives
c1  4t , c2  8t , c3  t. therefore the vectors are linearly dependent

QUESTIONS 3
ColD is a subspace of   k  4 .
k
a.
b. NulD is a subspace of   k  6 .
k

62
 1  3 4 2 5 4
 
2  6 9 1 8 2
c. D
 2  6 9 1 9 7
 
 1 3 4 2 5 4 
Let X   x1 , x2 , x3 , x4 , x5 , x6  , using this we can find a non-zero vector in NulD
 x1 
 
1  3 4 2 5 4   x2   0 
   
2  6 9 1 8 2   x3   0 
 
 2  6 9 1 9 7   x4   0 
   
 1 3 4 2  5  4   x5   0 
 
 x6 

Reducing the this system to Echelon form ,we obtain

 1 3 4 2 5 4 
 
0 0 1 3 2 6 
we see that x2 , x4 , x6 are free variables
0 0 0 0 1 5 
 
0 0 0 0 0 0
 3a  10b  13c 
 
 a 
 3b  4c 
X  
 b 
 5c 
Hence the system has solutions  
 c 

therefore a non-zero vector in NulD is  3,1,0,0,0,0  , when a  1, b  0, c  0

Also , a non-zero vector in ColD is 1, 2, 2, 1
d. From the row echelon form of D , we see that the columns containing the leading one’s is
are columns: 1,3, and 5; these columns form a basis for .

63
QUESTION 4
a. i.
T  x, y    5 x  y, 2 y    5, 0  x  1, 2  y 
the matrix of transformation is
 5 1 
A .
 0 2
let X be the characteristics vector: AX   X
 5 1  1   2  1
       2   .
 0 2  7  14  7
Hence, X  1, 7  is the characteristic vector of the transformation
with the characteristic root   2.

ii.
T  x, y, z    x  2 y,3x  6 y, 5 z   1,3, 0  x   2, 6, 0  y   0, 0, 5  z 
 1 2 0 
 
the matrix of the transformation A   3 6 0 
 0 0 5 
 
If X is the characteristic vector of the linear transformation, AX   X .
 1 2 0   1   5  1
      
  3 6 0  3    15   5  3  .
 0 0 5  1   5  1
      
Hence, the vector X is the characteristic vector of the linear transformation and its
coresponding characteristic root is   5.
b.
i. T  x, y, z    3x  6 y, x  2 y, 5z  . let U   a1 , b1 , c1  and V   a2 , b2 , c2 
T U  V   T  a1  a2 , b1  b2 , c1  c2 
 3  a1  a2   6  b1  b2  ,  a1  a2   2  b1  b2  , 5  c1  c2  
 3a1  6b1 , a1  2b1 , 5c1   3a2  6b2 , a2  2b2 , 5c2 
 T U   T V 

Also, let c be a constant;

T  cU   T  ca1 , cb1 , cc1   3ca1  6cb1 , ca1  cb1 , 5cc1 
 c 3a1  6b1 , a1  b1 , 5c1   cT U  .
Hence, T is a linear transformation.

64
 T  x, y, z    3,1, 0  x   6, 2, 0  y   0, 0, 5  z 
 3 6 0 
 
the matrix of transformation A   1 2 0 
ii.  0 0 5 
 
Now, A  3 10   6  5   0
Hence, the inverse transformation does not exist since A  0.
let  be the characteristic vector such that A   I  0
3 6 0
iii. 1 2   0 0
0 0 5  
solving this gives 1  0, 2  5 and 3  1.
 3 6 0  a   a  3a  6b  5a 8a  6b  0
      
 1 2 0  b   5  b    a  2b  5b   a  3b  0
 0 0 5  c   c   5c  5c 
       c0
let b  t ;
 3 6 0  a   a  3a  6b  a 2a  6b  0 a  3b  0
       
 1 2 0  b    b    a  2b  b   a  3b  0  a  3b  0
 0 0 5  c   c   5c  c  
       c0  c0
let b  t ; a  3t.  Generally, the characteristic vector  3t , t , 0    3,1, 0  t.
 3 6 0  a  a
    
 1 2 0  b   0  b   0
 0 0 5  c  c
    
3a  6b  0 a  2b  0
 
  a  2b  0  a  2b  0; let t  b  the characteristic vector is  2,1, 0  t
 5c  0 
  c0

65
 EEF 303: OPERATING SYSTEM (2013/2014)
Instructions: Answer Question 1 and 3 others. Marks are allocated as shown.
1. a) What is the difference between multiprogramming and multiprocessing?
2marks
b) What is an instruction cycle? 2marks
c) Name 4 modern derivatives of the UNIX OS? 2marks
d) What is race condition? 2marks
e) What is logic bomb? 2marks
2. What is a process and its characteristics? One of its most popular models is the 5 state
models. Give the states and their transition.
20marks
3. What is concurrency and the problems that arise because of it? What solutions are provided
by the OS? 20marks
4. What is processor scheduling? How can it be classified and what are the policies used?
5. What is memory management? What issues are addressed?
What techniques are used? 20marks
6. How is the file system organized? Using examples where possible, give some file attributes
and operation. 20marks

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 SOLUTION TO EEF 303: OPERATING SYSTEM (2013/2014)
1. a) With Multiprogramming only one process can be executed at a time whereas with
Multiprocessing, more than one process can be running simultaneously each on different
processors.

b) A program to be executed by the processor consist of a set of instructions stored in memory.An

instruction cycle is the processing require for a single instruction. It is as follows:

Fetch stage Execute stage

Execute instruction
Fetch next HALT
Start instruction
c) Four modern derivatives of the UNIX OS are;
 SVR4 (System V Release 4)
 BSD (Barkeley Software Distribution)
 Solaris
 Linux

d) Race condition takes place when several processes access and manipulate same data and the outcome of
execution depends on the particular order in which the access takes place.
e) Logic bomb is

2. A process is a program in execution.

It is characterised by:
 An identifier: identity that distinguishes it from other processes.
 State: its state of execution i.e running or not running.
 Priority: relative to other processes.
 Program Counter: contains address of next instruction to be executed.
 Context data: data present in register while process is still executing.
 I/O Status Information: includes I/O requests =, list of files used by process, etc.
 Accounting: amount of processor time, account numbers, etc.

The 5 state-model is the most popular model of a process and the states involved are:
 New: process that has just been created but not yet admitted into the pool of executable
processes by the OS. It has not been loaded into main memory, although its PCB has been
created.
 Ready: The process has all its resources at its disposal and is ready to be executed but has
not been given the opportunity.
 Running: process that is currently been executed. Assume a computer with a single
processor, where at most one process can be in this state.
 Blocked/Waiting: a process cannot be executed until an event occurs. For example the
completion of I/O operation.

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  Exit: process is released from the pool pf executable processes by the OS either because it
has been completed or aborted or halted.
The transitions include the following:
 Null-New: a new process is created to execute a program, while on disk.
 New-Ready: OS moves a process from new to ready when it is ready to take an additional
process.
 Ready-Running: when it is time to select a process, the OS chooses one of the processes in
the ready state and executes it. This is jointly done by the scheduler and dispatcher.
 Running-Ready: the running process has reached its maximum allowable time for
uninterrupted execution. It is also caused by the priority level of processes. Whereby a low
priority process is pre-empted by a high priority process.
 Running-Exit: currently running process is terminated by the OS if it is completed or
aborted.
 Running-Blocked: when a process request for something and must wait for it. For example a
process may for an I/O operation that must be completed before the process can continue.
Also in the case where processes communicate, the process could be waiting for another
process to provide data.
 Blocked-Ready: process move blocked state to ready state when event it has been waiting
for occurs.
 Ready-Exit: a parent process may terminate child process or a parent process terminates
and the other children processes associated with the parent may terminate.
 Blocked-Exit:a parent process may terminate child process or a parent process terminates
and the other children processes associated with the parent may terminate.

3. Concurrency is defined as the management of multiple processes and the corresponding problems that ensue.
Concurrency includes communication among processes, sharing and competing for resources, synchronization of the
activities of multiple processes, allocation of processor time to processes and more.
The problems that arise because of concurrency include:
 The sharing of global resources between processes are endangered.
 It is quite difficult for the OS to manage the allocation of resources to running processes.
 It is difficult to locate a programming error as results cannot be localised process wise.
 There is competition among processes for resources.
 Process speed depends on other processes.
The various solutions provided by the OS to these problems are:

4. Processor scheduling is assigning processes to be executed by the processor over time in a way that meets systems
objectives; like response time throughput and processor efficiency.
It is classified into:
 Long-term scheduling
 Medium-term scheduling

68
  Short-term scheduling
Long-term scheduling: Is performed when a new process is created. The decision is whether to add a new process to
the set of process to the set of processes that are currently running. Thus it determines which programs are admitted
to the system for processing. As a result it controls the degree of multiprogramming.
Medium-term scheduling: is a part of the swapping function. The decision here is whether to add a process to those
who are at least partially in main memory and therefore available for execution. The swapping in decision is based
on the need to manage the degree of multiprogramming.
Short-term scheduling: is the actual decision to which ready process to execute next. Is invoked whenever an event
occurs that may lead to the blocking of the current process or that may provide an opportunity to pre-empt a
currently running process in favour of another.
Scheduling policies used in processor scheduling are:
 Priorities:
In many systems, each process is assigned a priority and the scheduler will always choose a
process of higher priority over one of lower priority. If there is steady supply of higher
priority process, lower priority process will suffer from starvation. It could be:
 Non-pre-emptive: once a process is in the running state, it continues to execute until
it is blocked or terminated.
 Pre-emptive: currently running process may be interrupted and moved to ready
state by the OS.
 First-Come-First-Serve (FCFS):
Also known asFirst-In-First-Out (FIFO). As each process becomes ready, it joins the ready
queue. When the currently running process ceases to execute, the process that has been in
the ready queue longest is selected for running. This policy favours long processes than
short ones. So it is non-pre-emptive.
 Round Robin (Time slicing)
This technique is a pre-emptive policy which is also known as time slicing because each
process is allocated a slice of time before being pre-empted. When the interrupt occurs the
currently running process is placed in the ready queue and the next process is selected on
the FCFS basis. This policy reduces the penalty that short processes face in FCFS scheduling.
 Shortest Process Next (SPN)
This is a non-pre-emptive policy in which the process with the shortest processing time is
selected next. This policy reduces the bias in favour of long processes in FCFS. Overall
performance is significantly improved in terms of response time. The risk with SPN is
possibility of starvation of long processes as long as there is a steady supply of short
processes.
 Shortest Remaining Time (SRT)
It is a pre-emptive version of SPN. The scheduler always chooses the process that has the
shortest expected remaining processing time. The scheduler pre-empts the currently
running process for the process with the shorter remaining time than the currently running
process. In this policy scheme there is a risk of starvation of longer processes.
 Highest Response Ratio Next
The ready process with the highest normalised turnaround time is chosen. The scheme
accounts for the age of processes so eventually long processes will get past competing with
shorter processes.
 Feedback

69
 Also known as multilevel feedback as the OS allocates processor to a process and when it is
blocked or pre-empted, it feeds it back into one of the several priority queues. When it
reaches the lowest priority queue

5. Memory Management: It is a very important responsibility of the OS. It involves the allocation of memory to
processes and the movement of processes within and between memories. A good memory management system is
therefore essential to enhance system performance.
Memory Management addresses issues like:
Relocation
Protection
Sharing
Logical Organisation
Physical Organisation

 Relocation: In multiprogramming system, memory is shared among processes. So when

processes are swapped, it is relocated to a different memory location. So the hardware (in
the processor) and OS must be able to translate memory references found in code of
program into actual physical memory addresses reflecting current location of program in
main memory.
 Protection: This requirement must be satisfied by the processor rather than the OS. As it
should protect each process from interference by other processes whether accidentally or
incidentally. Programs in other processes should not be able to reference memory location
in a process without permission. The processor must be able to abort such instructions at
the point of execution.
 Sharing: Memory management must therefore allow controlled access to shared areas pf
memory without compromising essential protection. Thus must be flexible to allow several
processes that are cooperating on some task to share access to same portion of main
memory (data structure)
 Logical Organisation: Organises memory into sequences of words which encourages user
program modularity with numerous advantages as:
Modules can compile independently.
Different degree of protection can be given to different modules.
It is possible for modules to be shared among processes.
 Physical Organisation: The memory is organised into two; main memory (fast, high cost,
small) which is volatile and holds programs and data that is currently in use. Secondary
memory (slower, cheaper, large capacity) which is not volatile and provide for long term
storage of data. The system’s responsibility is the task of moving information between two
levels of memory. This task is the essence of memory management.
The techniques used in memory management are divided into two main groups namely; Virtual Memory techniques
and Memory Partitioning techniques.
Memory Partitioning Techniques:
 Fixed Partitioning
It is the managing of memory by diving it into regions with fixed boundaries. In this
technique, we can use either Equal size partitions or unequal size partitions.

70
 - Using Equal Size Partitions implies all the processes will be loaded into fixed boundaries
of equal sizes. Its disadvantage is that a program might be too big to fit into the
partition. Also, when the program is small it occupies just a portion of the partition.
Thus there is a waste of memory space. This is known as internal fragmentation.
- Using Unequal Size Partitions always assign partitions in a way to minimise memory
space wastage within partitions occupied by small programs. However, it is
disadvantageous as the number of partitions limits the number of active processes in
the system and also small processes will not utilize partition space efficiently.

 Dynamic Partitioning
Partitions are of variable lengths and numbers. Each process is allocated exactly as much
memory as it requires, no more no less. This might leave a “hole” at the end of the memory
that is too small for any additional process. This leads to many holes scattered in memory.
As time goes on, memory becomes more and more fragmented, this is known as External
Fragmentation. This external fragmentation is overcome by the technique called
Compaction (i.e. all free memory is brought together in one block). Three algorithms are
considered when OS decides how to plug holes; best-fit, first-fit and next-fit. Of all the 3,
first-fit is the simplest, the best and fastest.

 Buddy System
This technique splits memory into equal halves called Buddies and each half continues to
split into two in a tree manner depending on the memory request made by the processes.

Virtual Memory Techniques:

 Segmentation
Processes are divided into segments. The segments

71
SOLUTION TO EEF 303: OPERATING SYSTEM (2014/2015)
Question1.
a) Multiprogramming: the execution or running of multiple processes simultaneously by a single
processor. For example, the processor has two programs to execute.
b) Multiprocessing: execution of multiple programs or processes simultaneously by multiple
processors on the same machine.
c) Scheduler: selects the process from a queue of readyprocesses to allocate the resource to.
d) Dispatcher: control the allocation of time for the running or execution of each process.
e) Real-time OS: OS that performs real-time operations. Such as in embedded systems, that
operates in real time systems characterized by; deterministic, responsive, user controlled, reliable.
f) Process trace: the sequence of instructions executed for that process.
g) A deadlock: a situation where two or more processes are blocked by each other. That is one is
waiting for the other to execute and vice versa.
h) Process image: the attributes, state of a process.
i) Process affinity: the ability for a processor to admit many processes.
j) Process thrashing: a condition where processes are continuously being swapped into and out of
main memory without eventually executing. This situation reduces the throughput of a system.

Question2.
a) A process is a program in execution.
The conditions for process creation include;
 The submission of a new job in a batch environment leads to process creation.
 When a new user logs in such as in an interactive system.
 An OS can also create a process on the behalf of an application.
 When the OS creates a process at the explicit request of another process. That is
spawning. Such that there exist the parent and child process.
Below are some conditions for process termination.
 When the parent process terminates then the child process terminates too as in the case of
spawning.
 Power interruption where the system is failed to be supplied, all processes die
(terminate).
 When the user consciously or accidentally terminate a process.
 OS errors can also terminate a process.
b) The figure below is an explicit illustration of a five-state model of process modeling. The various
states and transitions are explained below.
 Null-New: new process is created to execute a program while on disk.
 New-Ready (admit): OS moves a process from the new state to the ready state when it is
ready to take on an additional process.
 Ready-Running: when it is time to select a process to run, the OS chooses one of the
processes in the ready state. The dispatcher and scheduler take care of this. On the
contrary if the process execution time relinquishes as in a time sharing system the process
is moved to the ready state (time out) or preempted.

72
 Process state transition diagram with suspended states

 Ready-Exit (release): currently running process is terminated by the OS if the process

indicates that it has completed or it aborts.
 Ready suspend-Ready: when there are no ready processes in the main memory, the OS
will need to bring one in to continue execution. A process in the ready suspend state has a
higher priority than a process in the ready state.
 Ready-Ready/suspend: the OS may choose to suspend a lower priority ready process
rather than a higher priority blocked process if it anticipates that the process will be ready
soon.
 Blocked/suspend- Ready/suspend: this can take place when an event being waited to
occur.

Question3. I/O system

Question4.
A distributed OS is one in which operates computers usually smaller computers, are dispersed throughout an
organization. The objective is to process info in a way that is most effective based on operational considerations.
The advantages of a distributed OS include;
• Responsiveness: Local computing facilities can be managed in such a way that
they can more directly satisfy the needs of local organizational management
than one located in a central facility and intended to satisfy the needs of the
total organization.
• Availability: With multiple interconnected systems, the loss of any one system
should have minimal impact. Key systems and components (e.g., computers
with critical applications, printers, and mass storage devices) can be replicated so
that a backup system can quickly take up the load after a failure.

73
 • Resource sharing: Expensive hardware can be shared among users. Data files
can be centrally managed and maintained, but with organization-wide access.
Staff services, programs, and databases can be developed on an organizationwide basis and
distributed to the dispersed facilities.
• Incremental growth: In a centralized facility, an increased workload or the
need for a new set of applications usually involves a major equipment purchase or a major
software upgrade. This involves significant expenditure. In
addition, a major change may require conversion or reprogramming of existing applications, with
the risk of error and degraded performance. With a distributed system, it is possible to gradually
replace applications or systems,
avoiding the “all-or-nothing” approach. In addition, old equipment can be left
in the facility to run a single application if the cost of moving the application to
a new machine is not justified.
• Increased user involvement and control: With smaller, more manageable
equipment physically located close to the user, the user has greater opportunity to affect system
design and operation, either by direction interaction with
technical personnel or through the user’s immediate superior.
• End-user productivity: Distributed systems tend to give more rapid response
time to the user, since each piece of equipment is attempting a smaller job. Also,
the applications and interfaces of the facility can be optimized to the needs of the
organizational unit. Unit managers are in a position to assess the effectiveness of
the local portion of the facility and to make the appropriate changes.

Question5.

While surveying the various mechanisms and policies associated with memory management, it is helpful to
keep in mind the requirements that memory management is
intended to satisfy. Suggests five requirements:
• Relocation
• Protection
• Sharing
• Logical organization
• Physical organization
Relocation
In a multiprogramming system, the available main memory is generally shared
among a number of processes. Typically, it is not possible for the programmer to
know in advance which other programs will be resident in main memory at the time
of execution of his or her program. In addition, we would like to be able to swap active
processes in and out of main memory to maximize processor utilization by providing
a large pool of ready processes to execute. Once a program has been swapped out to
disk, it would be quite limiting to declare that when it is next swapped back in, it
must be placed in the same main memory region as before. Instead, we may need to
relocate the process to a different area of memory.
Thus, we cannot know ahead of time where a program will be placed, and we
must allow that the program may be moved about in main memory due to swapping.
These facts raise some technical concerns related to addressing, as illustrated. For simplicity, let us assume
that the

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process image occupies a contiguous region of main memory. Clearly, the operating
system will need to know the location of process control information and of the execution stack, as well as
the entry point to begin execution of the program for this
process. Because the operating system is managing memory and is responsible for
bringing this process into main memory, these addresses are easy to come by. In
addition, however, the processor must deal with memory references within the program. Branch
instructions contain an address to reference the instruction to be
executed next. Data reference instructions contain the address of the byte or word
of data referenced. Somehow, the processor hardware and operating system software
must be able to translate the memory references found in the code of the program
into actual physical memory addresses, reflecting the current location of the program in main memory.
Protection
Each process should be protected against unwanted interference by other processes,
whether accidental or intentional. Thus, programs in other processes should not be
able to reference memory locations in a process for reading or writing purposes
without permission. In one sense, satisfaction of the relocation requirement increases
the difficulty of satisfying the protection requirement. Because the location of a program in main memory
is unpredictable, it is impossible to check absolute addresses
at compile time to assure protection. Furthermore, most programming languages
allow the dynamic calculation of addresses at run time (for example, by computing
an array subscript or a pointer into a data structure). Hence all memory references
generated by a process must be checked at run time to ensure that they refer only
to the memory space allocated to that process. Fortunately, we shall see that mechanisms that support
relocation also support the protection requirement.
Normally, a user process cannot access any portion of the operating system,
neither program nor data.Again, usually a program in one process cannot branch to
an instruction in another process. Without special arrangement, a program in one
process cannot access the data area of another process. The processor must be able
to abort such instructions at the point of execution.
Note that the memory protection requirement must be satisfied by the processor (hardware) rather than the
operating system (software). This is because the operating system cannot anticipate all of the memory
references that a program will
make. Even if such anticipation were possible, it would be prohibitively time consuming to screen each
program in advance for possible memory-reference violations. Thus, it is only possible to assess the
permissibility of a memory reference
(data access or branch) at the time of execution of the instruction making the reference. To accomplish this,
the processor hardware must have that capability.
Sharing
any protection mechanism must have the flexibility to allow several processes to
access the same portion of main memory. For example, if a number of processes are
executing the same program, it is advantageous to allow each process to access the
same copy of the program rather than have its own separate copy. Processes that
are cooperating on some task may need to share access to the same data structure.
The memory management system must therefore allow controlled access to shared
areas of memory without compromising essential protection. Again, we will see that
the mechanisms used to support relocation support sharing capabilities.
Logical Organization
Almost invariably, main memory in a computer system is organized as a linear, or

75
 one-dimensional, address space, consisting of a sequence of bytes or words. Secondary memory, at its
physical level, is similarly organized. While this organization
closely mirrors the actual machine hardware, it does not correspond to the way in
which programs are typically constructed. Most programs are organized into modules, some of which are
modifiable (read only, execute only) and some of which
contain data that may be modified. If the operating system and computer hardware
can effectively deal with user programs and data in the form of modules of some
sort, then a number of advantages can be realized:

1. Modules can be written and compiled independently, with all references from
one module to another resolved by the system at run time.

2. With modest additional overhead, different degrees of protection (read only,

execute only) can be given to different modules.

3. It is possible to introduce mechanisms by which modules can be shared among

processes. The advantage of providing sharing on a module level is that this
corresponds to the user’s way of viewing the problem, and hence it is easy for
the user to specify the sharing that is desired.
The tool that most readily satisfies these requirements is segmentation, which is one
of the memory management techniques explored in this chapter.

Physical Organization
As was explained computer memory is organized into at least two levels, referred to as main memory and
secondary memory. Main memory provides fast
access at relatively high cost. In addition, main memory is volatile; that is, it does not
provide permanent storage. Secondary memory is slower and cheaper than main
memory and is usually not volatile. Thus secondary memory of large capacity can be
provided for long-term storage of programs and data, while a smaller main memory
holds programs and data currently in use.
In this two-level scheme, the organization of the flow of information between
main and secondary memory is a major system concern. The responsibility for this
flow could be assigned to the individual programmer, but this is impractical and undesirable for two
reasons:
1. The main memory available for a program plus its data may be insufficient. In
that case, the programmer must engage in a practice known as overlaying, in
which the program and data are organized in such a way that various modules
can be assigned the same region of memory, with a main program responsible
for switching the modules in and out as needed. Even with the aid of compiler
tools, overlay programming wastes programmer time.
2. In a multiprogramming environment, the programmer does not know at the
time of coding how much space will be available or where that space will be.
It is clear, then, that the task of moving information between the two levels
of memory should be a system responsibility. This task is the essence of memory
management.
The memory management schemes used includes;
Fixed Partitioning
In most schemes for memory management, we can assume that the operating system occupies some fixed

76
portion of main memory and that the rest of main memory is available for use by multiple processes. The
simplest scheme for managing this
available memory is to partition it into regions with fixed boundaries.
Partition Sizes
One possibility is to make use of equal-size partitions. In this case, any
process whose size is less than or equal to the partition size can be loaded into any
available partition. If all partitions are full and no process is in the Ready or Running state, the operating
system can swap a process out of any of the partitions and
load in another process, so that there is some work for the processor.
There are two difficulties with the use of equal-size fixed partitions:
• A program may be too big to fit into a partition. In this case, the programmer
must design the program with the use of overlays so that only a portion of the
program need be in main memory at any one time. When a module is needed
that is not present, the user’s program must load that module into the program’s partition, overlaying
whatever programs or data are there.
• Main memory utilization is extremely inefficient. Any program, no matter how
small, occupies an entire partition. In our example, there may be a program
whose length is less than 2 Mbytes; yet it occupies an 8-Mbyte partition whenever it is swapped in.This
phenomenon, in which there is wasted space internal
to a partition due to the fact that the block of data loaded is smaller than the
partition, is referred to as internal fragmentation.
Both of these problems can be lessened, though not solved, by using unequal size partition. In this example,
programs as large as 16 Mbytes can be
accommodated without overlays.
Partitions smaller than 8 Mbytes allow smaller
programs to be accommodated with less internal fragmentation.
Placement Algorithm With equal-size partitions, the placement of processes in
memory is trivial. As long as there is any available partition, a process can be loaded
into that partition. Because all partitions are of equal size, it does not matter which
partition is used. If all partitions are occupied with processes that are not ready to run,
then one of these processes must be swapped out to make room for a new process.
Which one to swap out is a scheduling decision; this topic is explored in Part Four.
With unequal-size partitions, there are two possible ways to assign processes
to partitions. The simplest way is to assign each process to the smallest partition
within which it will fit.1 In this case, a scheduling queue is needed for each partition, to hold swapped-out
processes destined for that partition advantage of this approach is that processes are always assigned in
such a way as to
minimize wasted memory within a partition (internal fragmentation).
Although this technique seems optimum from the point of view of an individual partition, it is not optimum
from the point of view of the system as a whole. In
Figure 7.2b, for example, consider a case in which there are no processes with a size
between 12 and 16M at a certain point in time. In that case, the 16M partition will
remain unused, even though some smaller process could have been assigned to it.
Thus, a preferable approach would be to employ a single queue for all process.When it is time to load a
process into main memory, the smallest available partition that will hold the process is selected. If all
partitions are occupied,
then a swapping decision must be made. Preference might be given to swapping out
of the smallest partition that will hold the incoming process. It is also possible to

77
consider other factors, such as priority, and a preference for swapping out blocked
processes versus ready processes.
The use of unequal-size partitions provides a degree of flexibility to fixed partitioning. In addition, it can be
said that fixed-partitioning schemes are relatively
simple and require minimal operating system software and processing overhead.
However, there are disadvantages:
• The number of partitions specified at system generation time limits the number of active (not suspended)
processes in the system.
• Because partition sizes are preset at system generation time, small jobs will not
utilize partition space efficiently. In an environment where the main storage
requirement of all jobs is known beforehand, this may be reasonable, but in
most cases, it is an inefficient technique.
The use of fixed partitioning is almost unknown today. One example of a successful operating system that
did use this technique was an early IBM mainframe
operating system, OS/MFT (Multiprogramming with a Fixed Number of Tasks).
Dynamic Partitioning
To overcome some of the difficulties with fixed partitioning, an approach known as
dynamic partitioning was developed. Again, this approach has been supplanted by
more sophisticated memory management techniques. An important operating system that used this
technique was IBM’s mainframe operating system, OS/MVT
(Multiprogramming with a Variable Number of Tasks).
With dynamic partitioning, the partitions are of variable length and number.
When a process is brought into main memory, it is allocated exactly as much memory
as it requires and no more. An example, using 64 Mbytes of main memory, initially, main memory is
empty, except for the operating system
(a). The first three processes are loaded in, starting where the operating system ends
and occupying just enough space for each process (b, c, d).This leaves a “hole” at the
end of memory that is too small for a fourth process. At some point, none of the
processes in memory is ready. The operating system swaps out process 2 (e), which
leaves sufficient room to load a new process, process 4 (f). Because process 4 is
smaller than process 2, another small hole is created. Later, a point is reached at which
none of the processes in main memory is ready, but process 2, in the Ready-Suspend

state, is available. Because there is insufficient room in memory for process 2, the
operating system swaps process 1 out (g) and swaps process 2 back in (h).
As this example shows, this method starts out well, but eventually it leads to a
situation in which there are a lot of small holes in memory. As time goes on, memory
becomes more and more fragmented, and memory utilization declines. This phenomenon is referred to as
external fragmentation, indicating that the memory that is
external to all partitions becomes increasingly fragmented. This is in contrast to internal fragmentation,
referred to earlier.
One technique for overcoming external fragmentation is compaction: From
time to time, the operating system shifts the processes so that they are contiguous
and so that all of the free memory is together in one block. For example,
compaction will result in a block of free memory of length 16M. This may well be
sufficient to load in an additional process. The difficulty with compaction is that it is
a time consuming procedure and wasteful of processor time. Note that compaction
implies the need for a dynamic relocation capability. That is, it must be possible to
move a program from one region to another in main memory without invalidating

78
the memory references in the program.
Placement Algorithm Because memory compaction is time consuming, the
operating system designer must be clever in deciding how to assign processes to
memory (how to plug the holes).When it is time to load or swap a process into main
memory, and if there is more than one free block of memory of sufficient size, then
the operating system must decide which free block to allocate.
Three placement algorithms that might be considered are best-fit, first-fit, and
next-fit. All, of course, are limited to choosing among free blocks of main memory
that are equal to or larger than the process to be brought in. Best-fit chooses the
block that is closest in size to the request. First-fit begins to scan memory from the
beginning and chooses the first available block that is large enough. Next-fit begins
to scan memory from the location of the last placement, and chooses the next available block that is large
enough. The last block that was used was a 22-Mbyte
block from which a 14-Mbyte partition was create.
Buddy System
Both fixed and dynamic partitioning schemes have drawbacks. A fixed partitioning
scheme limits the number of active processes and may use space inefficiently if
there is a poor match between available partition sizes and process sizes. A dynamic
partitioning scheme is more complex to maintain and includes the overhead of compaction.

Free representation of the Buddy system.

Page Memory Management

Relocatable partition memory management has the attractive property of having no external
fragmentation. Internal fragmentation is at the lowest possible
level, too. In terms of memory alone, relocatable partition memory offers the
highest possible utilization amongst non-virtual policies. Its major drawback

79
is the excessive processing overhead due to frequent relocation of programs.
Page memory management is another policy with advantages similar to relocatable partition
memory management. It does not produce any external fragmentation either and the size of
unusable main memory is often equal to that
of relocatable partition memory management.
Solves many of the problems inherent in partitioning.
7.4 SEGMENTATION
A user program can be subdivided using segmentation, in which the program and its
associated data are divided into a number of segments. It is not required that all segments of all programs
be of the same length, although there is a maximum segment
length. As with paging, a logical address using segmentation consists of two parts, in
this case a segment number and an offset.
Because of the use of unequal-size segments, segmentation is similar to dynamic
partitioning. In the absence of an overlay scheme or the use of virtual memory, it
would be required that all of a program’s segments be loaded into memory for execution. The difference,
compared to dynamic partitioning, is that with segmentation a
program may occupy more than one partition, and these partitions need not be contiguous. Segmentation
eliminates internal fragmentation but, like dynamic partitioning, it suffers from external fragmentation.
However, because a process is broken up
into a number of smaller pieces, the external fragmentation should be less.
Whereas paging is invisible to the programmer, segmentation is usually visible
and is provided as a convenience for organizing programs and data. Typically, the
programmer or compiler will assign programs and data to different segments. For
purposes of modular programming, the program or data may be further broken
down into multiple segments. The principal inconvenience of this service is that the
programmer must be aware of the maximum segment size limitation.
Another consequence of unequal-size segments is that there is no simple relationship between logical
addresses and physical addresses. Analogous to paging, a
simple segmentation scheme would make use of a segment table for each process and
a list of free blocks of main memory. Each segment table entry would have to give the
starting address in main memory of the corresponding segment. The entry should also
provide the length of the segment, to assure that invalid addresses are not used. When
a process enters the Running state, the address of its segment table is loaded into a
special register used by the memory management hardware. Consider an address of
n+m bits, where the leftmost n bits are the segment number and the rightmost m bits
are the offset.

80
 EEF 315: SEQUENCE CONTROL (2014/2015)
QUESTION 1
Consider the chemical processing system shown in the figure below;

The sequence of operation is as follows;

i) When the operator presses the start button VA opens until the level of product A in
tank 1 reaches lsa
ii) VB opens until the level of product B in tank 1 reaches lsb
iii) VCopens until the level of product C in tank 2 reaches lsc
iv) VD opens until the level of product D in tank 2 reacheslsd
v) V01 and V02 open until the levels in tank 1 and tank 2 are ls1 and ls2 respectively
vi) The mixer and heater are turned on
vii) The mixer is turned off two minutes later
viii) The heater is turned off 27 minutes later
ix) VR opens until the level in the reactor islr.
When any of the product A,B,C or D is being fed into a tank, the corresponding light emitting diode LA, LB, LC, or
LD is turned on. Also, when tank 1 and 2 are feeding the mixtures into the reactor the light emitting diode LR is
turned on.
a) Draw a diagram to show the generalized structure of the control system
b) Construct a table to show the variables of the system
c) Design a Grafcet for the operation of the system
d) Modify the Grafcet in (c) to repeat the sequence 100 times

QUESTIO 2
Consider the Grafcet in figure below.
a) Draw the diagram to show the generalized structure of the control system
b) Construct a table to show the variables of the system
c) Design a timing diagram for the system
d) Design an electronic circuit to implement Action p1
e) Design an electronic circuit to implement Action V

81
QUESTION 3

The drill press below is driven by two motors.M1 is a bi directional motor which raises and lowers the drill press.
M2 drills the work piece. Limit switches Lmin and Lmax indicate when the switch reaches the min and max
positions respectively. LEDs L1 and L2 indicate when the press is being lowered or raised respectively. L3 indicate
when M2 is in operation.

The sequence of operation is as follows;

I. Initially, the drill press is at Lmax

II. When the operator presses the start button, M2 is turned on and given 50seconds to reach
operational speed.
III. The drill press is lowered while maintaining M2 in operation
IV. When the drill press reaches Lmin, it is raised back to Lmax
V. The sequence repeats 50 times.
a. Draw a diagram to show a generalized structure of a sequence control system
b. Construct a table show the variables of the system
c. Design a grafcet to model the sequence

82
QUESTION 4
a) List the most commonly used Grafcet structures
b) Identify the structures used in the Grafcet of Question 1(d)

83
 SOLUTION TO EEF 315: SEQUENCE CONTROL (2014/2015)
QUESTION 1
a)

b)

84
c)

85
d)

86
QUESTION 2
a)

b)

c) Notice that P is a stored variable and so is represented by a J-K flip flop;

d) V is a delayed variable and is represented as below;

87
QUESTION 3
a)

b)

c)

88
QUESTION 4
a) The most used data structures are;
 Stand-alone actions
 Looping sequence
 Non-looping sequence
 Parallel sequence
 Data initialisation
 Sequence jumping
 Sequence selection
b) The data structures used in this grafcets are;
 Data initialization.
 Looping sequence

89
 EEF 315: SEQUENCE CONTROL (2013/2014)
QUESTION 1
300 students of the faculty of Engineering and Technology have recently acquired TSX27 programmable logic
controller for the implementation of sequential control systems. The PLC manufactured by Schneider gas I/O
modules.
a) How many inputs can the PLC process? How many outputs can it process?
b) Draw a diagram to show the hardware structure of the PLC
The grafcet below is implemented on the PLC. Inputs variables a, b, and c are assigned to channels 1, 2, and 3 of I/O
module 2. Output variables are M1, LED1, M2, and LED2 are assigned to channels 1, 2, 3 and 4 of I/O module 3.
I. Draw a diagram to show how the variables are interfaced to the PLC
II. Write a program to implement the grafcet on the PLC
III. What are the main differences between the hardware of this PLC and that of the TSX37?

QUESTION 2
a) list the commonly used grafcet structures
b) Re–consider the grafcet in figure above. It is required to modify the grafcet to include the
following aspects;
I. Incorporate a safety monitoring condition which activates an output variable
ALARM whenever the am input variable d1
II. Skip the action LED1 if an input variable f1
III. Repeat the sequence 100 times

Modify the grafcet to include these functionalities.

QUESTION 3

The drill press below is driven by two motors.M1 is a bi directional motor which raises and lowers the drill press.
M2 drills the work piece. Limit switches Lmin and Lmax indicate when the switches reaches the min and max
positions respectively. LEDs L1 and L2 indicate when the press is being lowered or raised respectively. L3 indicate
when M2 is in operation.

The sequence of operation is as follows;

I. Initially, the drill press is at Lmax

II. When the operator presses the start button, M2 is turned on and given 50seconds to reach
operational speed.
III. The drill press is lowered while maintaining M2 in operation
IV. When the drill press reaches Lmin, it is raised back to Lmax
V. The sequence repeats 50 times.

90
 lmax
Start M1
a) (
w
L1 M2
b) Mi
Mt
L2 mh
mo
L3
mu lmin
mt
m
workpiecee
mr
me
1p
(e
wa
QUESTION 4 it
ti
Re-consider the drill press above. hn
a) Design a state transition diagram for the system
og
b) Design a timing diagram for a single sequence(without
u repeating the sequence)
c) Design a ladder network for a single sequence(without
tt repeating the sequence)
d) Design electronic circuits to implement the following
h actions
I. The operation of motor M2 re
II. Lowering the drill press e
III. Raising the drill press ps
ee
aq
tu
ie
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91
 EEF 311: PHYSICS FOR ENGINEERING 2 (2014/2015)
SECTION A

QUESTION 1
a)
i) Two charged particles are projected into a magnetic field perpendicular to their velocities.
If the charges are deflected in opposite directions, what can you say about them? (2 marks)
ii) Can a constant magnetic field set into motion an electron initially at rest? Explain your
answer. (2 marks)
b) An electron is accelerated through2400V from rest and then enters a uniform 1.70 T
Magnetic field. What are (i) the maximum and (ii) the minimum values of the magnetic
force this charge can experience? (2, 2marks)
c) A cyclone designed to accelerate protons has a magnetic field of magnitude 0.450 T over a
region of radius 1.20m, what are (i) the cyclotron frequency and (ii) the maximum speed
acquired by the protons? (2, 2 marks)
d) A current of 17.0 Ma is maintained in a single circular loop of 2.00m circumference. A
magnetic field of 0.800T is directed parallel to the plane of the loop .(i) calculate the
magnetic moment of the loop,(ii)what are the magnitude of the torque exerted by the
magnetic field on the loop? (2, 2 marks)

QUESTION 2
a)
i) Explain why two parallel wires carrying currents in the same directions attract each
other. (2 marks)
ii) Two long, parallel wires are attracted to each other by a force per unit length of
320𝜇N/m when they are separated by a vertical distance of 0.500m. The current in
the upper wire is 20.0A to the right . Determine the location of the line in the plan e
of the wires along which the total magnetic field is zero. (3 marks)
b)
i) Two solenoids are connected in series so that each carries the same current at any
instant is mutual inductance present? Explain. (2 marks)
ii) A long solenoid with 1000 turns per meter and radius 2.00cm carries an oscillating
current given by = (5.00𝐴) sin(100𝜋𝑡) . What is the electric field induced at a radius
r=1.00cm from the axis of the solenoid? What is the direction of this electric field
when the current is increasing counter clockwise in the coil? (2, 2 marks)
iii) An air core solenoid with 68 turns is 8.00cm long and has a diameter of
1.20cm.How much energy is stored in its magnetic field when it carries a current of
0.770A? (2 marks)
c) A series RL circuit with L=3.00H and a series RC Circuit with C=3.00F have equal time
constants. if the two circuits contain the same resistance R,(I) What is the value of R and(ii)
what is the time constant?. (3, 3 marks)

92
SECTION B

QUESTION 1
𝑘𝑥 2 1
In a spring mass system the particle has potential energy 𝑉(𝑥) = and kinetic energy 𝑚𝑣 2 . Show that the total
2 2
𝑚 𝜔 0 𝐴2
energy for the system 𝐸 = which remains constant. . (11 marks)
2
HINT: [cos 𝜃 2 = 1/2(1 + cos 2𝜃)]

QUESTION 2
𝑋2
A particle of mass m= 0.3kg in the potential 𝑉(𝑥) = 2𝑒 𝐿 2 J (L=0.1m) is found to behave like a SHO for small
displacement from equilibrium. Determine the period of this oscillator. (8 marks)

QUESTION 3
An over -damped oscillator has an exponentially decaying solution 𝑋(𝑡) = 𝐴1 𝑒 −𝛾1 𝑡 + 𝐴2 𝑒 −𝛾2 𝑡
Determine the constant 𝐴1 𝑎𝑛𝑑 𝐴2 for initial positions 𝑥0 and velocity 𝑣0 . (8 marks)

QUESTION 4
An over- damped oscillator with 𝐴𝑒 𝑖(𝜔 −𝛽 )𝑡 has initial displacement and velocity 𝑥0 𝑎𝑛𝑑 𝑣𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑣0 respectively.
Calculate 𝐴 and obtain 𝑋(𝑡) in terms of the initial conditions. (8marks)

93
 SOLUTION TO EEF 311: PHYSICS FOR ENGINEERING 2 (2014/2015)
QUESTION 1
ai) if the charges are projected in opposite directions we can conclude that the charges of opposite charge sign.
ii) No. Changing the velocity of a particle requires an accelerating force. The magnetic force is proportional
to the speed of the particle. If the particle is not moving, there can be no magnetic force on it.

b) First we find the velocity of the electron;

1
∆𝑘 = 𝑚𝑣 2 = 𝑒∆𝑣 = ∆u
2
2𝑒∆𝑢
Making v the subject 𝑣 = = 2.90 ∗ 107 𝑚/𝑠
𝑚
−12
i)𝐹𝐵𝑚𝑎𝑥 = 𝑞𝑣𝐵 = 7.90 ∗ 10 𝑁
ii)𝐹𝐵𝑚𝑖𝑛 = 0 This occurs when v is either parallel or anti parallel to B.

𝑚 𝑣2 𝑣 𝑞𝐵𝑅 𝑞𝐵
C) i) 𝐹𝐵 = 𝑞𝑣𝐵 = ,𝜔 = = = = 4.31 ∗ 107 𝑟𝑎𝑑𝑠/𝑠
𝑅 𝑅 𝑀𝑅 𝑚
𝑞𝐵𝑅
ii) 𝑣 = = 5.17 ∗ 107 𝑚/𝑠
𝑚

d)𝑖) 2𝜋𝑟 = 2.00𝑚 𝑟 = 0.318𝑚

𝜇 = 𝐼𝐴 = 5.41𝑚𝐴. 𝑚2
ii)𝜏 = 𝜇 × B = 433mN. m

2) The magnetic field created by wire 1 at the position of wire 2 is into the paper. Hence, the magnetic force on wire
2 is indirection down into the paper to the right, away from wire1. Now wire 2 creates a magnetic field into the
page at the location of wire 1, so wire 1 feels force up into the paper left, away from wire 2.

94
ii)

b) The answer depends on the orientation of the solenoids. If they are coaxial, such as two solenoids End-to-end,
then there certainty will be mutual induction. If, however, they are oriented in such a way that the magnetic field of
one coil does not go through turns of the second coil, then there will be no mutual induction. Consider the case of
two solenoids physically arranged in a “T” formation, but still connected electrically in series. The magnetic field
lines of the first coil will not produce any net flux in the second coil, and thus no mutual induction will be present.

ii)
1 𝐷
iii) 𝐿 = 𝜇0 𝑛2 𝐴𝑙, 𝐸 = 𝐿𝐼 2 , 𝑁 = 68, 𝑅 = = 0.6𝑐𝑚, 𝐼 = 0.770𝐴 𝑙 = 8.00𝑐𝑚
2 2
2
1 68
𝐸 = (4𝜋 ∗ 10−7 ) 𝜋(. 06)2 ∗ 0.08 ∗ 0.7702
2 . 08

95
 SECOND SEMESTER
CONTINUOUS ASSESSMENT

96
 EEF 302: POWER ELECTRONICS (2013/2014)

QUESTIONS
1) Give the symbol of the following power semiconductors: n-MOSFET, IGBT,TRIAC
2) Give the turn on conditions of a thyristor
3) Define in your own words an electric power converter
4) Give the power semiconductor devices which have the following characteristics
 Bipolar voltage withstanding capability
 Controlled turn on and off
 Unidirectional current capability
5) Answer by TRUE OR FALSE :
a) The on-state resistance of a MOSFET is greater than that of a bipolar junction
transistor
b) To turn off a thyristor you need a high negative current
c) Silicon grease is put in between the case of a power semiconductor and the heat
sink to increase thermal contact
6) Give two major advantages of a MOSFET and one limitation
7) When is a freewheeling diode used in an AC-DC converter?
8) Represent a thyristor with a RCD snubber circuit and indicate the role of each component
9) Fill in the blanks with the appropriate words
i) The frequency a three phase full wave uncontrolled rectifier connected to AES
Sonel power lines is _________________
ii) In a three phase half wave uncontrolled rectifier each diode conducts for
______________radians
iii) Three phase full wave fully controlled rectifiers uses _______________diode

EXERCISE 1
Consider the following circuit

Let the voltage at the primary 𝑉𝑃 = 220 2 sin 100𝜋𝑡 and the secondary voltage
𝑉𝑠 = 64 2 sin 100𝜋𝑡 , 𝑅 = 100Ω
1) What name do you give to this converter
2) Analyze it and sketch the waveforms of 𝑉𝑠 and 𝑉0 . Indicate on the graphs the conduction
intervals of each diode

97
 3) Derive the average and rms values of the output voltage
4) Find the FF and RF of the output voltage
5) Find the efficiency 𝜂 of the converter
6) A battery ( E= 12 v , 50 AH ) is put in series with the resistor
i) Give the graph of VS and the current IO through the battery
ii) Calculate :
a) Conduction angle of a diode
b) The charging time
c) The PIV of the diode

EXERCISE 2
𝜋
A single phase half wave rectifier has a purely resistive load of R and the delay angle is 𝛼 =
2
a) Give the schematic diagram of the rectifier
b) Draw the waveform of the output voltage and the voltage across the thyristor over two
periods
c) Determine the average and rms value of the output voltage
d) Derive
 The efficiency
 The form factor FF
 The ripple factor RF

e) Determine the peak inverse voltage of the thyristor

98
 SOLUTIONS TO EEF 302: POWER ELECTRONICS (2013/2014)

QUESTIONS
1.

ii) INSULATED GATE BIPOLAR

TRANSISTOR

i) Enhancement type n- channel MOSFET

iii)

2. Two conditions must be fulfilled for a thyristor to turn on

 Forward biased voltage
 Positive gate current

3. Its an electric circuit that converts voltage and current from one form to another
Note that the above answer is not unique !
4.
 Bipolar voltage withstanding capability: GTO
 Controlled turn on and off : BJT, FET, GTO
 Unidirectional current capability: DIODE AND THYRISTOR

5.
a. TRUE
b. FALSE
c. TRUE

6. Advantages:
 very small switching time
 No need for snubber circuit

99
 Disadvantage:
 high on- state resistance
7. A freewheeling diode is used when the load has a substantial inductive component . This is important
since it will help provide a continuous path for the load current to flow when the diode or thyristor is
switched off
8.

ROLE OF COMPONENTS
 C sets the rate of variation of the positive voltage across TH hence preventing the
variation of the voltage from exceeding a certain limit
 R limits the capacitance current when TH turns on
 D1 reduces 𝜏 ( the time constant or charging time of the capacitor) ,so instead of 𝜏 = 𝑅𝐶
we have 𝜏 = 𝑅𝐷𝐹 𝐶 where 𝑅𝐷𝐹 is the forward biased resistance of D1
 L limits the rate of variation of the positive current through TH to prevent it from being
damaged by excessive heat
 D2 provides an alternative part to dissipate excess magnetic energy stored in L
9.
i. 300 Hz
2𝜋
ii. 3
𝑟𝑎𝑑𝑖𝑎𝑛𝑠
iii. Zero
EXERCISE 1
1. Single phase full wave uncontrolled bridge rectifier
2.

100
 𝜋
1 128 2
𝑉𝑜𝑎𝑣 = 64 2 sin 𝜔𝑡 𝑑𝜔𝑡 = = 57,62 𝑉
𝜋 𝜋
0
𝜋
1 64 2
𝑉𝑜𝑟𝑚𝑠 = (64 2 sin 𝜔𝑡 )2 𝑑𝜔𝑡 = = 45.25
𝜋 2
0

4)
𝑉𝑜𝑟𝑚𝑠
𝐹𝐹 = = 1,107
𝑉𝑜𝑎𝑣
𝑅𝐹 = 𝐹𝐹 2 − 1 = 0,4834
𝑃 𝐷𝐶 2
𝑉𝑜𝑎𝑣
5) 𝜂 = = 2 = 0.811
𝑃𝐿 𝑉𝑜𝑟𝑚𝑠

101
6)
i)

a) 𝑉𝑚 sin 𝜃0 = 𝐸
𝐸
𝜃0 = = 0.13297 𝑟𝑎𝑑𝑠
𝑉𝑚
𝜃1 = 𝜋 − 𝜃0 = 2.876 𝑟𝑎𝑑𝑠
b) Charging time
𝜃1
𝑄 1 𝑉𝑚 sin 𝜔𝑡
𝑡= , 𝐼𝑐𝑎𝑣 = 𝑑𝜔𝑡 = 1.793 ∗ 10−3 𝐴
𝐼𝑐𝑎𝑣 𝜋 𝑅
𝜃0
C) 𝑃𝐼𝑉 = 𝑉𝑚 = 64 2

EXERCISE 2
a)

102
b)

1 𝜋 𝑉𝑚 𝑉𝑚
c) 𝑉𝑜𝑎𝑣 = 2𝜋 𝑉
𝜑 𝑚
sin 𝜔𝑡 𝑑𝜔𝑡 = 2𝜋 (1 + cos 𝜑) = 2𝜋
𝜋
1 𝑉𝑚2
𝑉𝑜𝑟𝑚𝑠 = 𝑉𝑚2 sin2 𝜔𝑡 𝑑𝜔𝑡 = (2 + 𝜋)
2𝜋 8𝜋
𝜑

𝑃𝑑𝑐 2
𝑉𝑜𝑎𝑣
d) 𝜂 = 𝑃𝑙
= 2
𝑉𝑜𝑟𝑚𝑠
𝑉𝑜𝑎𝑣
𝐹𝐹 =
𝑉𝑟𝑚𝑠
𝑅𝐹 = 𝐹𝐹 2 − 1
e) 𝑃𝐼𝑉 = 𝑉𝑚

103
 SOLUTION TO EEF 302: POWER ELECTRONICS (2014/2015)
QUESTIONS
1) Structure of a thyristor and its turn on conditions

Thyristors are three-terminal devices with four layers of alternating p- and n-type material (i.e.
three p-n junctions) in their main power handling section. The control terminal of the thyristor,
called the gate (G) electrode, may be connected to an integrated and complex structure as part of
the device. The other two terminals, anode (A) and cathode (K), handle the large applied Potentials
and conduct the major current through the thyristor. When the anode is made more positive than
the cathode, the two outer p-n junctions are forward biased and the middle p-n junction is reversed
biased hence current cannot flow. When a small gate current is applied, it forward biases the
middle p-n junction.

Turn on conditions.
Positive gate current
Forward biased

2) Symbols - n-MOSFET

-IGBT

104
 -TRIAC

3) Power losses
- Forward conduction losses: exhibited during turn-ON
- Blocking state losses: occurs during turn-OFF due to leakage current
- Switching losses: voltage requires time to fall and current requires time to rise during
switching

4) A power converter is a device used to convert and control the flow of power by supplying
currents and voltages that are suitable for the user loads.
5) Classification of power switches
- Uncontrolled - diodes
- Semi-controlled – thyristors (SCR,TRIAC)
- Controlled – transistors (BJT, MOSFET, IGBT, GTO)
6) Comparing BJT and MOSFET
-switching time – MOSFET has a smaller switching time
-ON-state resistance – BJT has a smaller ON-state resistance

105
 -power rating capability – reducing on-state resistance implies reducing the voltage rating
capability. Hence MOSFET has a higher power rating capability.

7) a) false
b) true
c) true
8) The rule of the snubber circuit
It smoothens the transitions and makes the switch voltage rise more slowly. It dampens the high
voltage spike to a safe voltage.
9) a free-wheeling diode is used to get rid of the negative voltage across the load.
10) i) 50Hz
ii) 2pi/3
ii) no diodes used

Exercise 1
a)

b) sketch Uc(t)
𝐷1 𝑎𝑛𝑑 𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡 𝑖𝑓 𝑉1 𝑎𝑛𝑑 𝑉2 𝑎𝑟𝑒 𝑔𝑟𝑒𝑎𝑡𝑒𝑟 𝑡𝑕𝑒 𝐸
𝑓𝑟𝑜𝑚 0 < 𝑤𝑡 <∝: 𝑉1 𝑟𝑖𝑠𝑒𝑠 𝑡𝑜 𝐸
∝< 𝑤𝑡 < 𝛽 ∶ 𝐷1 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑠
Exercise 2

106
1) Schematic diagram of the circuit

2) Waveforms of the voltage across the load R,L(𝑈𝑐(𝑡)) and the current through the
load(𝑖𝑐(𝑡)).

During the interval 0 to π/2

The source voltage Vs increases from zero to its positive maximum, while the voltage across
the inductor VL opposes the change of current through the load. It must be noted that the
current through an inductor cannot change instantaneously; hence, the current gradually
increases until it reaches its maximum value. The current does not reach its peak when the
voltage is at its maximum, which is consistent with the fact that the current through an
inductor lags the voltage across it. During this time, energy is transferred from the ac source
and is stored in the magnetic field of the inductor.
For the interval π/2 and π
The source voltage decreases from its positive maximum to zero. The induced voltage in the
inductor reverses polarity and opposes the associated decrease in current, thereby aiding
the diode forward current. Therefore, the current starts decreasing gradually at a delayed
time, becoming zero when all the energy stored by then inductor is released to the circuit.

107
 Again, this is consistent with the fact that current lags voltage in an inductive circuit. Hence,
even after the source voltage has dropped past zero volts, there is still load current, which
exists a little more than half a cycle.

3) The average output voltage and current, 𝑈𝑐𝑎𝑣 𝑎𝑛𝑑 𝐼𝑐𝑎𝑣

𝜋
1 𝑉𝑚 120
𝑈𝑐𝑎𝑣 = 𝑉𝑚𝑆𝑖𝑛𝑤𝑡𝑑𝑤𝑡 = = 2∗ = 54.0𝑉
2𝜋 𝜋 𝜋
0

EXERCISE 3
a) Schematic diagram of the rectifier

T1 and T2 are thyristor number 1 and 2.

b) Output waveform and conduction intervals of the switches
-0 < 𝑤𝑡 < 𝜋: 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒 𝑕𝑎𝑙𝑓 𝑐𝑦𝑐𝑙𝑒 𝑜𝑓 𝑉𝑠
-𝑇1 𝑎𝑛𝑑 𝐷2 𝑎𝑟𝑒 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑
-𝑎𝑡 𝑤𝑡 =∝: 𝑎 𝑔𝑎𝑡𝑒 𝑝𝑢𝑙𝑠𝑒 𝑡𝑢𝑟𝑛𝑠 𝑇1 𝑂𝑁
-∝< 𝑤𝑡 < 𝜋: 𝑇1 𝑎𝑛𝑑 𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡 → 𝑈𝑐(𝑡) = 𝑉𝑠
-𝑎𝑡 𝑤𝑡 = 𝜋: 𝑉𝑠(𝑡) 𝑐𝑟𝑜𝑠𝑠𝑒𝑠 𝑧𝑒𝑟𝑜 𝑡𝑜 𝑏𝑒𝑐𝑜𝑚𝑒 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒
-𝐷1 𝑡𝑢𝑟𝑛𝑠 𝑂𝑁 𝑎𝑛𝑑 𝐷2 𝑔𝑜𝑒𝑠 𝑂𝐹𝐹
-𝜋 < 𝑤𝑡 < 2𝜋: 𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒 𝑕𝑎𝑙𝑓 𝑐𝑦𝑐𝑙𝑒 𝑜𝑓 𝑉𝑠
-𝑇2 𝑎𝑛𝑑 𝐷1 𝑎𝑟𝑒 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑
-𝜋 < 𝑤𝑡 < 𝜋+∝ 𝑇1 𝑎𝑛𝑑 𝐷1 𝑐𝑜𝑛𝑑𝑢𝑐𝑡 → 𝑓𝑟𝑒𝑒 𝑤𝑕𝑒𝑒𝑙𝑖𝑛𝑔 𝑝𝑕𝑎𝑠𝑒 → 𝑈𝑐(𝑡) = 0
-𝑎𝑡 𝑤𝑡 = 𝜋+∝: 𝑎 𝑠𝑒𝑐𝑜𝑛𝑑 𝑔𝑎𝑡𝑒 𝑝𝑢𝑙𝑠𝑒 𝑡𝑢𝑟𝑛𝑠 𝑂𝑁 𝑇2 𝑎𝑛𝑑 𝑇1 𝑡𝑢𝑟𝑛𝑠 𝑂𝐹𝐹
-𝜋+∝< 𝑤𝑡 < 2𝜋: 𝑇2 𝑎𝑛𝑑 𝐷1 𝑐𝑜𝑛𝑑𝑢𝑐𝑡
-𝑎𝑡 𝑤𝑡 = 2𝜋: 𝑉𝑠 𝑏𝑒𝑐𝑜𝑚𝑒𝑠 𝑧𝑒𝑟𝑜 𝑠𝑜 𝑎𝑠 𝑡𝑜 𝑐𝑕𝑎𝑛𝑔𝑒 𝑖𝑡𝑠 𝑠𝑖𝑔𝑛
-𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑠 𝑎𝑛𝑑 𝐷1 𝑡𝑢𝑟𝑛𝑠 𝑂𝐹𝐹
-2𝜋 < 𝑤𝑡 < 2𝜋+∝: 𝑇2 𝑎𝑛𝑑 𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡, 𝑈𝑐(𝑡) = 0, 𝑓𝑟𝑒𝑒 𝑤𝑕𝑒𝑒𝑙𝑖𝑛𝑔
𝑝𝑕𝑎𝑠𝑒

108
c) 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 𝑎𝑛𝑑 𝑟𝑚𝑠 𝑣𝑎𝑙𝑢𝑒𝑠 𝑜𝑓 𝑡𝑕𝑒 𝑜𝑢𝑡𝑝𝑢𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒.
1 𝜋 𝑉𝑚(1 + 𝐶𝑜𝑠 ∝) 𝜋
𝑈𝑐𝑎𝑣 = ( ) 𝑉𝑚𝑆𝑖𝑛𝑤𝑡𝑑𝑤𝑡 = , ∝=
𝜋 ∝ 𝜋 4
1.707𝑉𝑚
→ 𝑈𝑐𝑎𝑣 = = 0.543𝑉𝑚
𝜋
𝜋
1
𝑈𝑐𝑟𝑚𝑠 = (𝑉𝑚𝑆𝑖𝑛𝑤𝑡)2 𝑑𝑤𝑡 = 0.674𝑉𝑚
𝜋 ∝

d) 𝑡𝑕𝑒 𝑓𝑜𝑟𝑚 𝑓𝑎𝑐𝑡𝑜𝑟 𝑎𝑛𝑑 𝑡𝑕𝑒 𝑟𝑖𝑝𝑝𝑙𝑒 𝑓𝑎𝑐𝑡𝑜𝑟

𝑈𝑐𝑟𝑚𝑠 0.674𝑉𝑚
𝐹𝐹 = = = 1.24
𝑈𝑐𝑎𝑣 0.543𝑉𝑚
𝑅𝐹 = 𝐹𝐹 2 − 1 = 0.5407 = 0.74
e) 𝑃𝐼𝑉 𝑜𝑓 𝑡𝑕𝑒 𝑡𝑕𝑦𝑟𝑖𝑠𝑡𝑜𝑟
𝑃𝐼𝑉 = 𝑉𝑚
f) 𝑊𝑎𝑣𝑒𝑓𝑜𝑟𝑚 𝑜𝑓 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑡𝑕𝑟𝑜𝑢𝑔𝑕 𝐷1 𝑎𝑛𝑑 𝑇1
g) 𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝑎𝑛𝑑 𝑟𝑚𝑠 𝑣𝑎𝑙𝑢𝑒𝑠 𝑜𝑓 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑡𝑕𝑟𝑜𝑢𝑔𝑕 𝐷1 𝑎𝑛𝑑 𝑇1
𝐼𝑓 𝑡𝑕𝑒 𝑙𝑜𝑎𝑑 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑠 𝑟𝑖𝑝𝑝𝑙𝑒 𝑓𝑟𝑒𝑒 𝑖𝑡 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡𝑕𝑎𝑡 𝑖𝑡 𝑖𝑠 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑖. 𝑒 𝑖𝑐(𝑡) = 𝐼𝑐
2𝜋
1 𝐼𝑐 𝐼𝑐
𝐼𝐷1𝑎𝑣 = ( ) (2𝜋 − 𝜋) =
𝐼𝑐𝑑𝑤𝑡 =
2𝜋
𝜋 2𝜋 2
∝+𝜋
1 𝐼𝑐
𝐼𝑇1𝑎𝑣 = ( ) 𝐼𝑐𝑑𝑤𝑡 =
2𝜋 ∝ 2
𝐼𝐷1𝑟𝑚𝑠 = 𝐼𝑇1𝑟𝑚𝑠 = 𝐼𝑐/ 2

109
 EFF 304: BASIC TELECOMMUNICATION (2013/2014)
Question 1(8 marks)
A loss of 3dB is measured between the emitting end and a given point on a transmission line.
a. Compare the power obtained at that point to the emitted power
b. Give the corresponding voltage drop if the initial value was 1V
c. What is the link between the bandwidth limits and the maximum power contained in a
signal.

Question 2 (12 marks)

An analog signal is sampled using a n n bit word
a. Give in dB units the expression of the quantization noise to power as function of n.
b. If we add one bit to the data word representing a linear sample value , discuss the following:
i. We double the number of quantizing levels
ii. We cut the maximum quantizing error in half.
iii. We increase the S/N by 6dB.
iv. We reduce the quantizing noise power by a factor of 4.

Question 3( 10 marks)
a. Compare the FM and PM modulations based on the followings :
Instantaneous pulsation, instantaneous phase , phase excursion, frequency excursion,
modulation index.
b. With the aid of a diagram, discuss the differences between FM and PM.

110
 SOLUTIONS TO EEF 304: BASIC TELECOMMUNICATION (2013/2014)
QUESTION 1
a. If a loss of 3dB is measured between the emitting end and the point, it means that the power atthat point
is half the power at the emitting end. That is

1
P PM
2

Where PM is the power at the emitting end.

P   V 2 out Zin 
b. g dB  10 log  out   10 log   2
 Pin   Z out Vin 
2
V  Z 
 g dB  10 log  out   10 log  in 
 Vin   Z out 
V  Z 
 20 log  out   10 log  in  .
 Vin   Z out 
Now, g dB  3dB; Vin  1V ; Z out  Z in  since we are on the same transmission line  .
V   Zin 
 3  20 log  out   10 log  
 1   Zin 
3

 Vout  10 20

Vout  0.707V
C.

We see from the diagram above that at the limits of the bandwidth, the power of the signal
is always half the maximum value. That is, if PM is the maximum power, the power at
limits of the bandwidth would be,

1
Plim its  PM
2

111
QUESTION 2.
1
 N   N 
a. N dB  10log 
 1mW


 10log  3 
 10 
But N 
1
3q 2
  3q 
2 1
 3  2 n  2 
 
1
 N dB  10log103  10log N  10log103  10log 3  2n  
2

 

N  10log103  10log  3 2n 

b i. the quantizing level; q  2n. where n is number of bits.

adding one bit  q  2 n 1  2  2n   2q.
 adding one bit, doubles the number quantizing levels.
Vmax Vmax
ii. the quantizing error, Eerror   n . Adding one bit;
q 2
Vmax 1  Vmax  Eerror
 E error     .
2n 1 2  2n  2
 Adding an additional bit, reduces the Eerror by half.

K
1
iv. N  , q  2n 1.
3q 2
1 1 1 N
 N     .
3 2 
n 1 2 4 3 2  4
n

 increasing the quantizing level by one bit, decreases the noise power.

QUESTION 3
a.

112
b. with the aid of diagrams, the difference between FM and PM can clearly be shown. In general, a PM and FM

have a phase shift between them of . The figure below illustrates the difference between PM and FM.
2

113
 EEF 304: BASIC TELECOMMUNICATION (2014/2015)
QUESTION 1.
1- a. Define the following: Teledensity, SCDSB.
b.Briefly describe the principle of the SCDSB modulation and give its advantage as
compare to the AM.

2- A loss of 3dB is measured between the emitting and a given point on a transmission line.
a. Compare the power obtained at that point to the emitted power.
b. Give the corresponding voltage drop if the initial value was 1V.
c. What is the link between the bandwidth limits and maximum power contained in a
signal (case of the human voice for example).

QUESTION 2
The input power of a 50-km cable system is 2.5W (power at the beginning of the cable). An
amplifier with a 64-dB gain is installed 26km from the input. Define:
a- The signal power level in dBm
b- The absolute power at
- The input of the amplifier.
- The output of the system. The attenuation of the cable is 2.5dB/km.

QUESTION 3
The output signal from an AM modulator is
s  t   10cos 1800 t   20cos  2000 t   10cos  2200 t 
Determine the modulating signal,
x  t  , carrier, c  t  , the modulating index,m, and the ratio of the
power in the sidebands to the power in the carrier.

114
 SOLUTION TO EEF 304: BASIC TELECOMMUNICATION (2014/2015)
QUESTION 1
1- a. Teledensity: It is the fixed telephone density in a given locality .i.e the number of persons
using fixed telephones per 1000 inhabitants in a given locality.
SCDSB:Supressed Carrier double side Bands.
b.SCDSB is a modulation technique that suppresses the carrier wave and transmits only the
side bands that carry the information. The advantage of this technique over the AM
modulation is that power is not wasted to transmit the carrier.

2- See question 1 of CA-2014.

QUESTION 2
a. the power levels in dBm is given by
 Pi   2.5 
PidBm  10 log  3 
 10 log  3 
 34dBm
 110   110 
b. the attenuation on line, L   2.5  26   65dB.
at the input of the amplifier, we have
 PAi dBm  34dBm  65dB  31dBm.
 PAi 
 31  10 log  3 
 110 
Solving gives PAi  7.9 107 W .
at the output of the amplifier:
 PAo dBm  34dB  65dBm  64dB  33dBm.
 P 
 33  10 log  Ao 3 
 110 
solving gives PAo  1.995W .
the attenuation of the line ,L  2.5  50   125dB.
the output power at end of of the line is
PO ,dBm  34  125  64  27 dBm.
 PO 
 27  10 log  3 
 110 
solving gives PO  2W .

115
 QUESTION 3
S  t   10 cos 1800 t   20 cos  2000 t   10 cos  2200 t 
 20 cos  2000 t   10  cos 1800 t   cos  2200 t  
 20 cos  2000 t   20  cos  2000 t  cos  200 t  
 20 1  cos  200 t   cos  2000 t  .
comparing this expressing with s  t   Ac 1  mu  t   cos c t
the modulating signal, x  t   200 t
the carrier; c  t   20 cos  2000 t 
the modualating index; m  1
 m 2   Ac2  m 2 
Generally, P  PC 1   1
2  2  2 
.

 Ac2  400 
Pc      200W .
2  2 
 Ac2  m 2 
PDSB     100W .
2  2 
P 100 1
the ratio ; DSB   .
Pc 200 2

116
 EEF 312: NUMERICAL METHODS FOR ENGINEERING (2012/2013)
1. Use Gauss Elimination to solve the system
2 x1  x2  1, x1  2 x2  x3  0, x2  2 x3  x4  0, x3  2 x4  1
for the solution x1 , x2 , x3 , and x4 .
1 4  4 1 1
2. Let A    and B    be 2  2 matrices and b    be a column vector. It is
3 2  2 3  2
required to solve the two systems  i  Ax  b  ii  Bx  b for the vector x in  .
2

a. Show that a unique solution does exist for the two problems (i) and (ii) and use any
direct method to find the two solutions.
b. To solve problems (i) and (ii) by iteration we may split the matrices A and B in the
1 0  4 0
form A  N1  P1 and B  N2  P2 where N1    and N2   .
 0 2  0 3
i. Construct the iteration matrices for the system with A and B respectively .
ii. Calculate the spectral radius of the iteration matrix for each of the iterations and
then determine which iteration schemes will converge.
iii. Approximate the solution by applying two steps of the convergent iteration
scheme. What is the error in the computed solution after the two steps?
3. Given that f  t  has the form f  t   ae  be , where a and b are unknowns. Use least
2t t

squares approximation to find a and b if it known that,

f  0   1, f  ln  2    7 and f  ln 3  9.
4. Use the intermediate value Theorem and other properties of continuously differentiable
functions to show that the equation 2sin  x   x has exactly three solutions in the interval

  ,   . Use the bisection method to localize the interval containing the positive non-zero
solution nd setup Newton’s iteration to approximate the non-zero. What value do you get
after two steps of Newton?.
5. Find the quadratic function that interpolates the function f on the interval 1, 2 given that
2
f 1  0; f 1.5  3 and f  2   1. Hence, find the approximate value of  f  x  dx.
1

 
6. Consider the polynomial p  x   3   x  1 4   x  1 5   x  2 . 
(i) Use the nested multiplication algorithm to write the polynomial in the shifted
power form with unique centre 3
(ii) Evaluate p '  3.001 and p  3.001 .

117
SOLUTION TO EEF 312: NUMERICAL METHODS FOR ENGINEERING
(2012/2013)

1.  2 x1  x2  1, x1  2 x2  x3  0, x2  2 x3  x4  0, x3  2 x4  1
the augmented matrix formed for this system is
 2 1 0 0   x1   1 
    
 1 2 1 0   x2    0  .
 0 1 2 0   x3   0 
    
 0 0 1 2   x4   1 
using the Guass elimination, the system is reduced to
 2 1 0 0 1
 
 0 3 1 0
1
 2 2
 4 1
 0 0  1 
 3 3
 5 5
 0 0 0  
 4 4
and solving this gives
x1  1; x2  1; x3  1 and x4  1.

1 4  4 1 1
2. A    and B    and b   
3 2  2 3  2
 a  A  10 and B  10.
A  0 and B  0 have a unique solution exist for the two problems.
case 1:
1 4 1 1
1 4 2 2 3 3 2 1
A  , x1   and x2  
3 2 10 5 10 10
1 1 4 1
4 1 2 3 1 2 2 3
B  , x1   and x2   .
2 3 10 10 10 5

118
 3 i. A  N1  P1  Ax   N1  P1  x  b
x  N 1 P1 x  N 1b  Hx  c
Case 1:
1 4 1 0  0 4 
A , N   ; P  N1  A   .
3 2 0 2  3 0 
1 0  0 4 
 N 
1  ; H  N 1 P    and c  N 1b  1 .
0 1  3  
0
1
1
 2  2 
 4 1  4 0  0 1
B  , N2    and P2  N 2  B   
 2 3  0 3  2 0 
1   1 1
 0  0   4
4 4
N 21    , H  N 21 P1    and c2    .
 0 1  2 0  2
     
 3  3  3
ii. spectral radii
case 1;
 0 4 
H1   3  , let  be the spectral radius, then H   I  0
 0
1 1 1

 2 
 0 4   0
 3  1 
    0 solving this gives 1   6.
0   0 1 
 2 
Hence, since   H1   6  1, the iteration will NOT converge.
Case 2;
 0 4 
H2   3  , let  be the spectral radius, then H   I  0
 0
2 2 2

 2 
 1
 0  4   2 0  1
    0 solving this gives 2   .
  3 0   0 2  6
 
 2 
1
Hence, since   H 2    1, the iteration will converge.
6

119
 3. the iteration equation is ; x k 1  Hx k  c
case1: lets consider the first matrix.
 0 4 
x  H x  c1   3
1 0   0    1   1
      
0   0   1  1
1 1 1

 2 
 0 4  3
   1  1  
x1  H1 x1  c1  3
2 1
      11 .
 0   1  1  
 2  2
 3  12 
   3   
the error: e 2  exact solution  x12      11   
5 5
.
 1     27 
  2  
 10   5 
case 2:
1
4 0
x12  H 2 x20  c2    ; considering that x20   
2 0
 
3
1  7 
 3    30 
x2  H 2 x2  c2     e  exact solution  x2  
2 1 2 2
.
1  1 
   
2  10 
5. lets use the method of Undetermined coefficients:
p  x   a0  a1 x  a3 x 2 .
p 1  0  a0  a1  a3  0................... 1
3 3 9
p    3  a0  a1  a3  3..............  2 
2 2 4
p  2   1  a0  2a1  4a2  1......................  3
the augmented system formed from this system is
1 1 1
   a0   0 
1 3 9    
a1  3 .
 2 4     
1 2 4 
a2   1 
 
solving this system gives a0  10; a1  31; a2  21.
 p  x   21  31x  10 x 2 .
2 2

 p  x dx    21  31x  10 x dx 

2 13
.
0 0
6

120
 6. using the nested mulplication algorithm to move from nested power form of the
of a polynomial to shifted power form centered at 3.

p  x   3   x  1 4   x  1 5   x  2 
 3  4  x  1  5  x  1 x  1   x  1 x  1  x  2  .
a0  3, a1  4, a2  5, a3  1
c1  1, c2  1, c3  2. z  2.
recall, a 'n  an .
for i  n  1, n  2,...,1
a 'i  ai   z  ci 1  ai' 1
a3'  a3  1
a2'  5   2  2  1  1
a1'  4   2  11  1
a0'  3   2  1 1  2

a3'  a3  1
a2'  4   3  2  1  6
a1'  12   3  3 6   12
a0'  5
p  x   5  12  x  3  6  x  3   x  3 .
2 3

p '  x   12  12  x  3  3  x  3 .
2

 p3'  3.001  12.012003

 p  3.001  5.012006001.

121
SECOND SEMESTER
EXAMINATIONS

122
 EEF 302: POWER ELECTRONICS (2013/2014)
QUESTIONS
1) Give the I-V characteristics of the different triggering modes of a TRIAC
2) Define the following terms related to a thyristor : 𝐼𝐺𝑇 , 𝑉𝐵𝑂 , 𝐼𝑇𝐻
3) Give the different possibilities to turn off a thyristor
𝑑𝑣 𝑑𝑖
4) For a thyristor what represents the following limitations 𝑑𝑡
max ,
𝑑𝑡
max

5) Give the different types of electric power conversions and give the name of each converter
6) A UPS is an electrical system used to supply power to a computer or to your laptop . What
does the term UPS stand for ? give its block diagram
7) Among these power semiconductors ( diodes , thyristors , Mosfets , IGBT , BJT ) identify
those with the following characteristics :
 Bipolar voltage withstanding capability
 Controlled turn on and turn off
 Unidirectional current capability

8) Give two applications of an AC chopper

9) It’s not advisable to let power semiconductor devices work around their ratings values .
Give two reasons to justify this statement

EXERCICE 1
A center-tapped single phase full wave controlled rectifier has an inductive load
𝑅 = 2Ω 𝑎𝑛𝑑 𝐿 = 10𝑚𝐻 . The transformer has the following ratings : 220v/2* 60v at 50Hz
Assume the following operating conditions:
 Continuous conduction mode
 Ripple free output current
𝜋
 Firing delay angle 𝜑 = 4 for the two thyristors
a) Give the schematic diagram of this rectifier
b) Draw the output waveform and indicate the conduction intervals of the switches over
one period
c) Determine the average and the rms values of the output voltage
d) Sketch the current through one thyristor and calculate its average value
A freewheeling diode is put in parallel across the load
e) Draw tehe waveform of the output voltage and determine its average value
f) Sketch the waveform of the current through one thyristor and the diode

EXERCICE 2
The following dc-dc converter has input voltage 𝑉𝑆 = 5𝑉. The required output voltage is
𝑉𝐶 = 15𝑉 and the average load current 𝐼𝑂 = 0.5𝐴 .Assume that the switch S is a MOSFET with a

123
switching frequency 𝑓 = 50𝑘𝐻𝑍. The switch is ON for 0 ≤ 𝑡 ≤ 𝛼𝑇 and OFF for 𝛼𝑇 ≤ 𝑡 ≤
𝑇 . 𝐿𝑒𝑡 𝐿 = 150𝑢𝐻
And 𝐶 = 220𝑢𝐹

a) Redraw the circuit with the MOSFET and give the precise name of this converter
b) Give the role of L D and C
c) Describe the operation of the converter over one period
d) Assume that the voltage across the capacitor is constant and equal to Vc . Give the
expressions of vL IL IS and IC for 0 ≤ 𝑡 ≤ 𝛼𝑇 then sketch their waveforms
e) Determine
 The duty cycle 𝛼
 The ripple current of the inductor ∆𝐼
 The peak current of inductor 𝐼2 given that the average current through a
capacitor is equal to zero
 The power delivered by the input voltage source

EXERCICE 3
A three phase bridge rectifier has a purely resistive load of R and is connected to the AES Sonel
power lines . It delivers an average output current 𝐼𝑂 = 60𝐴 and an output voltage of 𝑉𝑑𝑐 = 280.7𝑣
a) Draw on the same diagram waveforms of the three voltages 𝑉𝑟𝑛 𝑉𝑏𝑛 , 𝑉𝑦𝑛 at the secondary of
the transformer and the voltage 𝑉𝑂 across the load . Give a label to the three diodes and
indicate on the diagram their conduction sequences
Determine ;
b) The efficiency of the rectifier
c) The form factor FF

124
d) The ripple factor RF
e) The peak inverse voltage PIV of each diode
f) The peak current 𝐼𝐹𝑅𝑀 through a diode

125
 SOLUTION TO EEF 302: POWER ELECTRONICS (2013/2014)
QUESTIONS
1)

The following are the different triggering modes of a

triac
𝑉𝐴2𝐴1 > 0 𝑎𝑛𝑑 𝐼𝐺 > 0 ( 𝑣𝑒𝑟𝑦 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑒 )
𝑉𝐴2𝐴1 > 0 𝑎𝑛𝑑 𝐼𝐺 < 0 ( 𝑙𝑒𝑠𝑠 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑒 )
𝑉𝐴2𝐴1 < 0 𝑎𝑛𝑑 𝐼𝐺 < 0 ( 𝑣𝑒𝑟𝑦 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑒 )
𝑉𝐴2𝐴1 < 0 𝑎𝑛𝑑 𝐼𝐺 > 0 ( 𝑣𝑒𝑟𝑦 𝑙𝑒𝑠𝑠 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑒 )
2)
𝐼𝐺𝑇 : 𝑔𝑎𝑡𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 (𝑚𝑖𝑛𝑖𝑚𝑢𝑚)
𝑉𝐵𝑂 : 𝑏𝑟𝑒𝑎𝑘 𝑜𝑣𝑒𝑟 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 ( 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝑝𝑜𝑠𝑖𝑡𝑖𝑣𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑)
𝐼𝐻 : 𝑕𝑜𝑙𝑑𝑖𝑛𝑔 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 ( 𝑡𝑕𝑒 𝑚𝑖𝑛𝑖𝑚𝑢𝑚 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑎𝑛𝑜𝑑𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑛𝑒𝑐𝑒𝑠𝑠𝑎𝑟𝑦 𝑡𝑜 𝑘𝑒𝑒𝑝 𝑡𝑕𝑒 𝑑𝑒𝑣𝑖𝑐𝑒 𝑖𝑛 𝑓𝑜𝑟𝑤𝑎𝑟𝑑
𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑎𝑓𝑡𝑒𝑟 𝑖𝑡 𝑕𝑎𝑠 𝑏𝑒𝑒𝑛 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑛𝑔 𝑎𝑡 𝑎 𝑕𝑖𝑔𝑕 𝑎𝑛𝑜𝑑𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑣𝑎𝑙𝑢𝑒
3) i) When 𝐼𝐴 is inferior to 𝐼𝐻
II) When a negative voltage is applied across the thyristor : here there are two possibilities ;
Line commutation ( ac-ac or ac- dc )
Forced commutation ( dc-dc or dc – ac)
𝑑𝑣
4) 𝑑𝑡 MAX indicates the maximum rate of variation of positive voltage across the thyristor which if
exceeded will cause the SCR to turn on without the need of a gate current
𝑑𝑖
MAXindicates the maximum rate of variation of the positive current flowing through the SCR
𝑑𝑡
which if exceeded could destroy the SCR due to excessive heat
5) AC-DC : Rectifier
AC-AC : Cycloconverter or voltage controller
DC-DC : DC Chopper
DC- AC : Inverter

126
6) Uninterruptible power supply
7)
 Thyristor , specifically the gate turn of thyristor
 BJT , MOSFET , IGBT
 Diode , thyristor

8) Heating and control of low speed motor

9) To ensure that the devices work reliably i.e. working around the ratings could drastically reduce
its life span and the device could be damaged completely when sudden current or voltage surges
occur
( note this answer is not unique)
EXERCISE 1
a)

127
b)

1 𝜋+𝜑 2𝑉𝑚
c) 𝑉𝑜𝑎𝑣 = 𝜋 𝜑
𝑉𝑚 sin 𝜔𝑡 𝑑𝜔𝑡 = 𝜋
cos 𝜑 = 31,83𝑣

𝜋
1
𝑉𝑜𝑟𝑚𝑠 = (𝑉𝑚 sin 𝜔𝑡 )2 𝑑𝜔𝑡 = 60𝑣
𝜋
0

d)

128
 𝐼𝐶𝐴𝑉
𝐼𝑇𝐻𝐴𝑉 =
2

𝑉𝑜𝑎𝑣 𝑉𝑜𝑎𝑣
𝐼𝐶𝐴𝑉 = 𝐼𝑇𝐻𝐴𝑉 = = 7.9
𝑅 2𝑅
e)

𝜋
1 𝑉𝑚
𝑉𝑜𝑎𝑣 = 𝑉𝑚 sin 𝜔𝑡 𝑑𝜔𝑡 = (1 + cos 𝜑) = 59.6𝑣
𝜋 𝜋
𝜑

129
 f)

EXERCISE 2

a) The following circuit represents a boost converter

130
 b) L: transfers to the load and to C the energy stored when the switch S is closed hence
adding to Vs and increasing the supply voltage to the load to be more than Vs
D: prevents C from discharging through the source and the inductor L when S is closed
C: it’s a high capacitance capacitor which supplies current to the load when the switch S is
closed

c) 0 ≤ 𝑡 ≤ 𝛼𝑇 S is closed
vs supplies some current to L which will then store some energy in its magnetic field
𝛼𝑡 ≤ 𝑡 ≤ 𝑇 S is open

L in series with VS transfers to the load and C the energy previously stored

d) 𝑉𝐶 𝑖𝑠 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
0 ≤ 𝑡 ≤ 𝛼𝑇 𝑆 𝑖𝑠 𝑐𝑙𝑜𝑠𝑒𝑑
𝑉𝐿 = 𝑉𝑆 , 𝐼𝑆 = 𝐼𝐿 𝑎𝑛𝑑 𝐼𝐶 = −𝐼𝑂
𝐿𝑑𝐼𝐿 𝑉𝑆 𝑡
= 𝑉𝑆 𝐼𝐿(𝑡) = + 𝐼𝑚
𝑑𝑡 𝐿
𝑤𝑕𝑒𝑟𝑒 𝐼𝑚 𝑖𝑠 𝑡𝑕𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑎𝑡 𝑡 = 0 (𝑎𝑠𝑠𝑢𝑚𝑖𝑛𝑔 𝑎 𝑠𝑡𝑒𝑎𝑑𝑦 𝑠𝑡𝑎𝑡𝑒 𝑎𝑛𝑎𝑙𝑦𝑠𝑖𝑠)
𝐼𝐿(𝑡) 𝑖𝑛𝑐𝑟𝑒𝑎𝑠𝑒𝑠 𝑙𝑖𝑛𝑒𝑎𝑟𝑙𝑦
𝛼𝑇 ≤ 𝑡 ≤ 𝑇 𝑆 𝑖𝑠 𝑜𝑝𝑒𝑛
𝐷 𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑠 𝐼𝑆 = 0 , 𝐼𝐶 = 𝐼𝐿
𝑉𝐿 = 𝑉𝑆 − 𝑉𝐶
𝐿𝑑𝑖
= 𝑉𝑆 − 𝑉𝐶
𝑑𝑡
𝑉𝑆 − 𝑉𝐶
𝐼𝐿(𝑡) = (𝑡 − 𝛼𝑇) + 𝐼𝑀
𝐿
𝐼𝑀 𝑏𝑒𝑖𝑛𝑔 𝑡𝑕𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑎𝑡 𝑡 = 𝛼𝑇
𝐼𝐿(𝑡) 𝑑𝑒𝑐𝑟𝑒𝑎𝑠𝑒𝑠 𝑙𝑖𝑛𝑒𝑎𝑟𝑙𝑦

Waveforms of the above calculated parameters

131
(note that DT is same as 𝛼𝑇)
e)
i) using faradays law for boost converter
𝛼𝑇 𝑇
1 1
𝑉𝐿𝐴𝑉 = 𝑉𝑠 𝑑𝑡 + (𝑉𝑆 − 𝑉𝐶 )𝑑𝑡
𝑇 𝑇
0 𝛼𝑇
𝑉𝐶 − 𝑉𝑆
𝑏𝑢𝑡 𝑉𝐿𝐴𝑉 = 0, 𝛼= = 0.6667
𝑉𝐶
ii) 𝑅𝑖𝑝𝑝𝑙𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑠 𝐼𝑀 − 𝐼𝑚 = ∆𝐼

𝑉𝑆 𝑡
𝑓𝑟𝑜𝑚 𝐼𝐿(𝑇) = + 𝐼𝑚 𝑤𝑕𝑒𝑛 𝑡 = 𝛼𝑇
𝐿
𝑉𝑆 𝛼𝑇
𝐼𝑀 = 𝐼𝐿(𝑇) ∆𝐼 =
𝐿

iii) the consideration that the average current across a capacitor is zero is very useful

132
 𝑇
1
𝐼𝐶 𝑑𝑡 = 0
𝑇
0

𝑇
1
𝑡𝑕𝑖𝑠 𝑖𝑚𝑝𝑙𝑖𝑐𝑖𝑡𝑒𝑙𝑦 𝑚𝑒𝑎𝑛𝑠 𝑡𝑕𝑎𝑡 𝐼𝐿 𝑑𝑡 = 0
𝑇
𝛼𝑇

1 (𝑉𝑆 − 𝑉𝐶 ) 2 𝛼𝑇(𝑉𝑆 − 𝑉𝐶 ) 𝑇 (1 − 𝛼)(𝑉𝑆 − 𝑉𝐶 )

𝑡 − 𝑡 + 𝐼𝑀 𝑡 = 0, 𝐼𝑀 = = −0.56𝐴
𝑇 2𝐿 𝐿 𝛼𝑇 2𝐿𝑓

𝑡𝑕𝑎𝑡 𝑖𝑠 0.56𝐴 𝑖𝑛 𝑡𝑕𝑒 𝑜𝑝𝑝𝑜𝑠𝑖𝑡𝑒 𝑑𝑖𝑟𝑒𝑐𝑡𝑖𝑜𝑛 𝑡𝑜 𝑡𝑕𝑎𝑡 𝑠𝑕𝑜𝑤𝑛 𝑜𝑛 𝑡𝑕𝑒 𝑑𝑖𝑎𝑔𝑟𝑎𝑚

iv)The power delivered by the source voltage is given by

𝑃 = 𝑉𝑆 𝐼𝑂 = 2.5𝑊

(energy is conserved , changing the frequency at which this energy is delivered is what is essential
in boosting the voltage hence the name boost converter)

EXERCISE 3
a)

b)
2
𝑃𝑑𝑐 𝑉𝑑𝑐
𝜂= = 2
𝑃𝑙 𝑉𝑙
𝑉𝑑𝑐 = 280.7𝑉

133
 1
5𝜋 2
6
3
𝑉𝑙 = (𝑉𝑚 sin 𝜔𝑡)2 𝑑𝜔𝑡
2𝜋
𝜋
6
2𝜋
But 𝑉𝑚 = 𝑉𝑑𝑐
3 3
𝑉𝑙 = 285.1 𝑣
𝜂 = 0.97
(note 𝑣𝑙 = 𝑣𝑜𝑟𝑚𝑠 𝑎𝑛𝑑 𝑣𝑑𝑐 = 𝑣𝑜𝑎𝑣 )
𝑉
c) 𝐹𝐹 = 𝑉 𝑙 = 1.015
𝑑𝑐

d) 𝑅𝐹 = 𝐹𝐹 2 − 1 = 0.174

e) 𝑃𝐼𝑉 = 𝑉1 − 𝑉2 𝑚𝑎𝑥 = (𝑉𝑚 3 cos(𝜔𝑡 + 𝜑))𝑚𝑎𝑥 = 𝑉𝑚 3 = 587.2𝑣

𝑉𝑚
f) 𝐼𝐹𝑅𝑀 =
𝑅

𝑉𝑑𝑐 2𝜋𝐼𝑑𝑐
𝐴𝑛𝑑 𝑅 = 𝐼𝐹𝑅𝑀 = = 72.5𝐴
𝐼𝑑𝑐 3 3

134
 EEF 302: POWER ELECTRONICS (2012/2013)
QUESTION 1
A) A single-phase full-wave uncontrolled bridge rectifier connected to ENEO 220V-50Hz line
through a transformer with a purely resistive load of R and an average output current ICav =
10A and average power UCav=120V.
1) Give the schematic diagram of the circuit
2) Draw the waveform Uc(t) of the voltage across the load
3) Determine:
- The rms voltage at the secondary of the transformer
- The value of the load R
- The form factor FF
- The ripple factor RF
- The ratings of the diodes : IFRM, IFAV, IFRMS, VRRM considering a safety marging 50%
for the current and 100% for the voltage
B) Two diodes are replaced by two thyristor so as to have an asymmetric half-controlled
bridge rectifier. The load is now inductive R-L with L=50mH is on series with R. the rectifier
is in continuous conduction mode.
4) Give the schematic diagram of the rectifier
5) Draw the waveform of the output voltage if the thyristor are triggered with a delay
angle 30^0
6) Indicate the conduction sequence of the different semi-conductor switches
7) Find the new average output current ICav

QUESTION 2
The DC-DC converter given below has an input source voltage U=50V. The required
output voltage is Vs=250V and the average load current is Is=10A. The switching
frequency is 25Kz, L=150mH and C=470µF. let tON be the conduction time interval of
the switch K.

a) Give the specific name for the DC-DC converter

b) Give the role of the inductor, the diode and the capacitor.

135
 c) Describe qualitatively (no equation) the operating mode of the converter over a
period 0<t<tON and tON<t<T.
d) Give the expression of iL(t) for 0<t<tON and tON <t<T, considering that I1 and I2
are the maximum and minimum values respectively.
e) Determine the duty cycle δ
f) Draw the waveform of the current iLthrough the inductor and iD through the
diode.
g) Draw the waveform of the voltage VL across the inductor.
h) Derive the expression of the output voltage Vs as a function of U and the duty
cycle δ.
i) Determine the expression of the average current through the diode as a function
of I1 and I2
j) Derive the expression of the ripple inductance current ΔiL
k) Determine the values of I1 and I2
Note: the average current through a capacitor is equal to zero.

QUESTION3
Consider the following three phase bridge uncontrolled rectifier: Van=120(root2)sinωt; The load is
R=4Ω; L=10H. The graph of the input voltage is given on a separate sheet to be returned with your script.

1. Give the expression of Vbn and Vcn as a function of time

2. Sketch on graph I provided, the waveform of the output voltage Vo
3. Indicate on the graph the conduction sequence of the diodes
4. Calculate Voav and Vorms.
5. Derive the ripple factor RF of the output voltage
6. Determined the average current Ioav of through the load
Consider the load is highly inductive and the current is constant:
7. Sketch in graph I provided the waveform of the current through D1 and D6 and calculate
the rms value
Replace the diodes by thyristors. The delay firing angle is 60degree.
8. Sketch on graph II provided the waveform of the voltage across the load and indicate
the conduction intervals of the thyristor
9. Determine the average current through the load
10. Determine the PIV of the thyristor

136
 SOLUTION TO EXAM 2014/2015
EXERCISE 1
A) 1) Schematic diagram of the circuit

2) Waveform of the voltage across the load

Let VL = Uc(t)

During the positive half cycle of the transformer secondary voltage, the current flows to the
load through diodes D1 and D2. During the negative half cycle, D3 and D4 conduct.

3) -Therms voltage at the secondary of the transformer

1 𝜋
Ucav = ( ) 𝑉𝑚𝑆𝑖𝑛𝑤𝑡𝑑𝑤𝑡 = 2𝑉𝑚/𝜋
π 0

𝜋𝑈𝑐𝑎𝑣 120
≫ 𝑉𝑚 = =𝜋∗ = 60𝜋
2 2
2𝜋
1 𝑉𝑚 60𝜋
𝑉𝑟𝑚𝑠 = 𝑉𝑚2 𝑆𝑖𝑛2 𝑤𝑡𝑑𝑤𝑡 = = = 133.3𝑉
2𝜋 0 2 2

137
-calculating the value of the load current
𝜋
1 𝑉𝑚𝑆𝑖𝑛𝑤𝑡 2𝑉𝑚 2𝑉𝑚
𝐼𝑐𝑎𝑣 = 𝑑𝑤𝑡 = →𝑅= = 12Ω
𝜋 0 𝑅 𝜋𝑅 𝜋𝐼𝑐𝑎𝑣
-the form factor
𝑈𝑐𝑟𝑚𝑠 60𝜋
𝐹𝐹 = = = 1.11
𝑈𝑐𝑎𝑣 2 ∗ 120
-the ripple factor
𝑅𝐹 = 𝐹𝐹 2 − 1 = 1.112 − 1 = 0.482

-the ratings of the diode

IFRM = maximum repetitive forward current withstand able
𝑉𝑚𝑎𝑥
𝐼𝑚𝑎𝑥 = = 𝐼𝑑𝑚𝑎𝑥
𝑅
50 1.5𝑉𝑚𝑎𝑥 60𝜋
𝐼(𝐹𝑅𝑀) = 𝐼(𝐷𝑚𝑎𝑥) + 𝐼(𝐷𝑚𝑎𝑥) = = 1.5 ∗ = 23.56𝐴
100 𝑅 12
IFAV = maximum forward average current
Observe the graph and notice that the current through each diode is half the current through the load.
Hence 𝐼(𝐷𝑎𝑣) = 𝐼𝑐𝑎𝑣/2
50 1.5 ∗ 𝐼𝑐𝑎𝑣 30
𝐼(𝐹𝐴𝑉) = 𝐼(𝐷𝑎𝑣) + ∗ 𝐼(𝐷𝑎𝑣) = = = 7.5𝐴
100 2 4
IFRMS = maximum rms current
𝜋 2
1 𝑉𝑚𝑆𝑖𝑛𝑤𝑡 𝑉𝑚
𝐼(𝐷𝑟𝑚𝑠) = 𝑑𝑤𝑡 =
2𝜋0 𝑅 𝑅 2
50 𝑉𝑚 60𝜋
𝐼(𝐹𝑅𝑀𝑆) = 𝐼(𝐷𝑟𝑚𝑠) + ∗ 𝐼(𝐷𝑟𝑚𝑠) = 1.5 ∗ =3∗ = 16.6𝐴
100 𝑅 2 2 2 ∗ 12
VRRM = maximum repetitive reverse voltage
𝑃𝐼𝑉 = 𝑉𝑚
100
𝑉(𝑅𝑅𝑀) = 𝑉𝑚 + ∗ 𝑉𝑚 = 2𝑉𝑚 = 120𝜋𝑉
100
B) 4) schematic of the modified circuit
This circuit will be replaced with the real circuit

5)- 0<wt<𝜋 : TH1 and D2 are forward biased

138
 -At wt= 𝜋/6, a gate pulse turns TH1 ON
𝜋
- 6 < 𝑤𝑡 < 𝜋; TH1 and D2 conduct
Uc(t) = Vs=𝑉𝑚𝑆𝑖𝑛𝑤𝑡

-at 𝑤𝑡 = 𝜋; 𝑉𝑠 = 0
- at𝑤𝑡 > 𝜋;
𝑉𝑠 𝑐𝑕𝑎𝑛𝑔𝑒𝑠 𝑠𝑖𝑔𝑛, 𝐷1 𝑏𝑒𝑐𝑜𝑚𝑒𝑠 𝑓𝑜𝑟𝑤𝑜𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑 𝑎𝑛𝑑 𝑡𝑢𝑟𝑛𝑠 𝑂𝑁 𝑎𝑛𝑑 𝑇𝐻1 𝑡𝑢𝑟𝑛𝑠 𝑂𝐹𝐹
-𝜋 < 𝑤𝑡 < 2𝜋, 𝑉𝑠 < 0, 𝑇𝐻2 𝑖𝑠 𝑓𝑜𝑟𝑤𝑎𝑟𝑑 𝑏𝑖𝑎𝑠𝑒𝑑
𝜋
-𝜋 < 𝑤𝑡 < 𝜋 + 6 ; 𝐷1 𝑎𝑛𝑑 𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡
𝑈𝑐(𝑡) = 0; 𝑡𝑕𝑒 𝑓𝑟𝑒𝑒 𝑤𝑕𝑒𝑒𝑙𝑖𝑛𝑔 𝑝𝑕𝑎𝑠𝑒
𝜋
𝑎𝑡 𝑤𝑡 = 𝜋 + ; 𝑎𝑛𝑜𝑡𝑕𝑒𝑟 𝑔𝑎𝑡𝑒 𝑝𝑢𝑙𝑠𝑒 𝑡𝑢𝑟𝑛𝑠 𝑇𝐻2 𝑂𝑁, 𝐷1 𝑡𝑢𝑟𝑛𝑠 𝑂𝐹𝐹
6
𝜋
𝜋 + < 𝑤𝑡 < 2𝜋; 𝑇𝐻2 𝑎𝑛𝑑 𝐷2 𝑐𝑜𝑛𝑑𝑢𝑐𝑡
6
Graph
7) the average output current
𝜋
1 𝑉𝑚𝑆𝑖𝑛𝑤𝑡 𝑉𝑚 𝜋
𝐼𝑐𝑎𝑣 = ( ) 𝑑𝑤𝑡 = ( )(1 + 𝐶𝑜𝑠( )
𝜋 𝜋/6 𝑅 𝜋 6

Exercise two
a) A boost converter
b) - inductor transfers the energy previously stored to the load
- The diode D prevent the capacitor from discharging through K when K is closed
- Capacitor supplies current to the load when K is closed
c) 0 < 𝑡 < 𝑡ON : K is ON, U supplies a current to L which stores energy
𝑡ON < 𝑡 < 𝑇 :K is OFF, D conducts, L in series with U transfers energy previously stored
to the load and C.
d) 0 < 𝑡 < 𝑡ON:
VL = U, VD = -Vs
The voltage across the diode being negative implies diode is off and the diode current is zero
⟺𝑖 D= 0
𝐿𝑑𝑖 𝑑𝑖 𝑈 𝑈
=𝑈⟺ = ⟺ 𝑖(𝑡) = 𝑡 + 𝑚
𝑑𝑡 𝑑𝑡 𝐿 𝐿

m is the integration constant

𝑎𝑡 𝑡 = 0, 𝑖(𝑡) = 𝐼 1
𝑈 𝑈
⟺ 𝑖(𝑡) = 𝑡 + 𝑚 ⟺ 𝐼 1= (0) + 𝑚 ⟺ 𝑚 = 𝐼 1
𝐿 𝐿
𝑈
⟺ 𝑖(𝑡) = 𝑡 + 𝐼1
𝐿
𝑡ON < 𝑡 < 𝑇:
𝑖 D= 𝑖 L, K is OFF and D conducts
𝑉 K = 𝑉 S ⟺ 𝑉 L= 𝑈 − 𝑉 S
𝐿𝑑𝑖 𝑑𝑖 1
⟺ = 𝑈 − 𝑉𝑠 ⟺ = (𝑈 − 𝑉𝑠)
𝑑𝑡 𝑑𝑡 𝐿

139
 𝑈 − 𝑉𝑠
⟺ 𝑖(𝑡) = 𝑡+𝑚
𝐿
𝑎𝑡 𝑡 = 𝑡ON, 𝑖 L(𝑡) = 𝐼 2
𝑈−𝑉𝑠 𝑈−𝑉𝑠
⟺ 𝐼 2= (𝑡ON) + 𝑚 ⟺ 𝑚 = 𝐼 2− (𝑡ON)
𝐿 𝐿
𝑈−𝑉𝑠
⟺ 𝑖(𝑡) = (𝑡 − 𝑡ON) + 𝐼 2
𝐿
e) Duty cycle, Ϩ
𝑈 𝑈 50 4
𝑉𝑠 = ⟺Ϩ=1− =1− =
1−Ϩ 𝑉𝑠 250 5
f) Waveform of 𝑖 L and 𝑖 D

g) Waveform of the voltage across the inductor

h) Expression of the output voltage as a function of the duty cycle and U

1 𝑡𝑜𝑛 1 𝑇
𝑉𝑙𝑎𝑣 = ( ) 𝑈𝑑𝑡 + ( ) (𝑈 − 𝑉𝑠)𝑑𝑡
𝑇 0 𝑇 𝑡𝑜𝑛
𝑈𝑡𝑜𝑛 𝑈 − 𝑉𝑠 𝑡𝑜𝑛
𝑉𝑙𝑎𝑣 = + (𝑇 − 𝑡𝑜𝑛) 𝑤𝑕𝑒𝑟𝑒 Ϩ =
𝑇 𝑇 𝑇
𝑏𝑢𝑡 𝑡𝑕𝑒 𝑎𝑣𝑒𝑟𝑎𝑔𝑒 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑜𝑟 𝑎𝑛 𝑜𝑛𝑑𝑢𝑐𝑡𝑜𝑟, 𝑉𝑙𝑎𝑣 = 0
⟺ 𝑈Ϩ + (𝑈 − 𝑉𝑠)(1 − Ϩ) = 0

𝑈
𝑉𝑠 =
1−Ϩ
i) Average current through the diode as a function of I1 and I2
1 𝐼2
𝐼𝑑𝑎𝑣 = (𝑇 ) 𝐼1 D
𝐼 𝑑𝑡
Method used to calculate the average: area of a triangle

140
 1 1
𝐴= 𝐵𝑕 = ( )(𝑇 − 𝑡𝑜𝑛)(𝐼2−𝐼1)
2 2
1 1
𝐼𝑑𝑎𝑣 = (𝑇 )(2)(𝑇 − 𝑡𝑜𝑛)(𝐼2−𝐼1)

1
⟺ 𝐼𝑑𝑎𝑣 = (10 )(𝐼2−𝐼1)
j) Ripple current, Δ𝑖 L
𝑈−𝑉𝑠 𝑈−𝑉𝑠
Δ𝑖 L= 𝐼 2−𝐼1= 𝐿
∗ 𝑡𝑜𝑛 = 𝐿
∗ Ϩ𝑇
1
But 𝑓 = 𝑇 , 𝑓 𝑏𝑒𝑖𝑛𝑔 𝑡𝑕𝑒 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
𝑈−𝑉𝑠
⟺ Δ𝑖L= 𝐿𝑓 Ϩ
k) Determine the values of I1 and I2
The average current Isis given by
1
𝐼𝑠 = (𝐼 2+𝐼1) … … … . (1)
2
And the ripple current whose value has been calculated above
Δ𝑖 L= 𝐼 2−𝐼1……….(2)
From 1 and 2 the values of I1 and I2 can be calculated.

EXERCISE 3
𝑉𝑎𝑛 = 120 2𝑠𝑖𝑛𝑤𝑡, 𝑅 = 4Ω, 𝐿 = 10𝐻
2𝜋 4𝜋
1) 𝑉𝑏𝑛 = 120 2 sin 𝑤𝑡 − 3 , 𝑉𝑐𝑛 = 120 2sin⁡
(𝑤𝑡 − 3
)
2) The waveform of the output.
3) The conduction sequences of the diodes

141
The output average value can be calculated from

Where 𝑉dc= 𝑉0av, 𝑎𝑛𝑑 𝜃 = 𝑤𝑡

The r.m.s value can as well be calculated from

4) The average and r.m.s values

142
 3 3𝑉𝑚 2
Voav= 𝜋
= 3 3 ∗ 120 ∗ 𝜋
= 280.69𝑉
3 9 3
𝑉rms= 𝑉𝑚 2
+ 4𝜋
= 1.655𝑉𝑚 = 1.655 ∗ 120 2 = 280.86
5) Derive the ripple factor
𝑅𝐹 = 𝐹𝐹 2 − 1
280.86
𝐹𝐹 = = 1.00061
280.69
𝑅𝐹 = 1.000612 − 1 = 0.035

6) Average current through the load

𝑉𝑜𝑎𝑣 280.69
𝐼𝑐𝑎𝑣 = = = 70.2𝐴
𝑅 4
7) U
8) Replace diodes with thyristors with a delay firing angle 60
Draw the output waveform

143
9) The average current through the load

But ∝= 𝜋/3
𝜋/2
3𝑉𝑚𝑎𝑥 3𝑉𝑚 120 2
𝑉𝑑𝑐 = ( ) 𝐶𝑜𝑠𝑤𝑡𝑑𝑤𝑡 = =3∗ = 81.018𝑉
𝜋 𝜋/6 2𝜋 2𝜋
𝑉𝑑𝑐 81.018
𝐼𝑑𝑐 = = = 20.25𝐴
𝑅 4

144
 EEF 304: BASIC TELECOMMUNICATIONS (2013/2014)

Question 1-(18 marks)

1. With the aid of a graph, show that the main components of a transmission line and give the
usefulness of each (20 lines maximum).
2. i. Define PCM and state the Nyquist theorem.
ii. The analog signal x  t    2cos  600 t   4cos 1600 t  V is sampled with a 16 bits
1
AD converter operating between 5 V . The converter has a non-linearity of  LSB. The
2
numerical values of the AD converter are transmitted through a line with a rate of
200 oct/sec.
Expectations:
ii-1 Does it appear any spectral overlapping.
ii-2 Determine the resolution and the quantization step of the converter.
ii-3 Determine the power of the signal x  t  and its root mean square.
ii-4 Determine the signal to noise ratio of the AD conversion.

Question 2-(20 Marks)

An information signal x  t   cos  200 t  is AM modulated.
i. Calculate the message power Px .
ii. Give the expression of A  t  the amplitude of the AM signal as a function of
Ac , m and x  t  .
iii. Determine the peak envelope power P and deduce its relationship Px and with PDSB .
iv. Consider a radio transmitter rated for 4kW peak envelope power. Find the maximum
value of the modulation index for the 1kW average transmitted power of the AM signal.
v. Let U M and U m be the maximum and minimum values of A  t  respectively. Express m
as a function U M and U m . Deduce U m knowing that U M = U m +4.

Question 3-(20 Marks)

1. Explain how PSK could be used to increase the bit rate without increasing the bandwidth.
Give one negative consequence of this increased data rate.
2. How would you transmit a bit sequence 0111 0101 0010 1011 using BPSK signaling
 
technique? Sketch the modulated signal if the carrier signal is c  t   sin  2 f ct  .
 2
3. i. Describe the 16-QAM frame in terms of amplitude and phase.
0
ii. Draw the constellation diagram of a 16-QAM signal where a carrier with 45 phase shift
and high amplitude corresponding to a bit combination of 1100.

145
 4. For baseband PSK signals, we use a square pulse of amplitude A and a duty cycle  . Give
expression of the energy  E  in this pulse if the duration is one period (t=T). Deduce the
relationship between A and T for E=2.

Question 4-(12 Marks)

a. Discuss the pertinence of line encoding.
b. Use a bit sequence of your choice to describe the advantage of Manchester code over AMI
code.
c. Use the HBD3 to encode the following pattern of bits. 0000110000110000111000001.
Assume that the number of AMI pulses is Odd before the first violation.
d. What is multiplexing? With the aid of graph, describe the FDM and TDM multiplexing
methods.

146
 SOLUTIONS TO EEF 304: BASIC TELECOMMUNCATION (2013/2014)

QUESTION 1:
1- The main components of the transmission line are shown in the figure below:

- TRANSMITTER: The transmitter processes the input signal and produces a

transmitted signal suitable to the characteristics of a transmission channel. The
signal processing for transmission often involves encoding and modulation.
- TRANSMISSION CHANNEL:The transmission channel is an electrical medium that
bridges the distance from the source to the destination. It may be a pair of wires, a
coaxial cable, a radio path, or an optical fiber.
- RECEIVER:The receiver operates on an output signal from the channel in preparation
for delivery to the transducer at the destination
- NOISE, DISTORTION AND INTEFRENCE:These are various unwanted factors that have an
impact on the transmission line. These often cause alterations of the signal shape at the
receiver.
2- a. PCM is Pulse coded modulation , it is a standardized method that is used in the telephone
network to change an analog signal to a digital signal for transmission through the digital
telecommunication network.
The Nyquisttheoremstates that the sampling frequency f s should be higher than two times
the highest frequency component of the analog message; W.
i.e f s  2W
by so doing spectral overlapping would be avoided since most analog messages have many
frequency components(the human speech or voice).
b
1- x  t   2cos  600 t   4cos 1600 t   2cos  2  300t   4cos  2  800t 

f 0  800 Hz

So, for overlapping to occur, f s  2 fo .

Bit rate, Rb  200 oct/sec  200  8bits/sec  1600 bits/sec.

147
 Number of bits, n  16 bits.
Rb 1600
sampling frquency, f s    100Hz .
n 16
f s  2 f o so there is spectral overlapping .
Hence,
1 1 1
2- Generally, Resolution  n   16 .
2 q 2
Instead of coding in n-bits, we code in n-1 bits because the converter does not consider
1
the least significant biti.e resolution is  LSB.
2
1
ro  , r1  2ro .
2n
2 2 1
 r1   n  n 1 .
ro 2 2
1 1
 resolution of the converter; r1  n 1
 15 .
2 2
2V max 2  5  10
The quantization step =  n 1  15 .
2n 1 2 2
3-
x  t   2cos  600 t   4cos 1600 t   2cos wt  4cos w0t.
x 2  t    2cos wt  4cos w0t   4cos 2 wt  16cos wt cos w0t  16cos 2 w0t.
2

 T
Power of signal, Px   x  t  dt
2

T 0

 T

T
 4 cos 2
wt  16 cos wt cos wot  16 cos 2 wot dt
0


  2T  8T   10  W  10W, where   1.
T
 T
Prms   x  t  dt  10 W  10 W
2

T 0

Prms  3.162W Ueff  3.162W

OR
 q q
4- We that note it can be shown that in the interval   ,  ,
 2 2
 q2
Noise power, PN  , where  =1 and q  quantization steps.
12
q step 10
 PN    15  3.052 104 W.
12 12  2  12

And Also;

148
 2
 U   12  U2 3.162
 S / N q  12   eff    2   U 2eff  eff  4
 1.036 104.
 q  q  PN 3.052 10
  S / N q  1.036 104.

QUESTION 2:
i- x  t   cos  200 t 
 T
 T
x 2  t  dt  cos  200 t dt
T T
P 2

0 0

  sin 400 t   
T

  t   T   .
2T  400  0 2T 2

Therefore, power of the signal: Px  Ac2 .
2
ii- s  t   Ac 1  m  u  t   cos wct  Ac 1  m  cos  200 t  cos wct.
 A  t   Ac 1  m  cos  200 t  
 A  t   Ac 1  mmax  cos  200 t    Ac 1  mmax  .
T T
A2  t  dt  A 1  m  dt ; since A  t   Ac 1  m  .
T T
Pevelope  2 2
iii- c
0 0

 2 T
Pevelope  Ac 1  m  t    Ac2 1  m  .
2 2

T 0

Power of the signal, Px  Ac2 .
2
The relationship between the peak envelope and power of the signal
 Ac2 1  m 
2
Penvelope
  2 1  m  .
2

Px  2
Ac
2
The power of double sideband modulation,
 m2   m2 Ac2
PDSB  Pc    .
 2  4
The relationship between the peak envelope power and PDSB

Penvelope  1  m 2 
 4 .
PDSB  m2 
 
iv- Now for Peve  4k W; PT  1k W  Penv  4 PT .

149
  m2 
PT  Pc 1   , where Pc is power of the carrier wave.
 2 
A2 A2
Pc   c  c , where  =1.
2 2
A  m2 
2
4 PT
 PT  c 1    Ac 
2
.
2  2   2  m2 
4 PT 4P
Penv  Ac2 1  m   1  m   T 2 1  2m  m2  .
2 2

2  m 
2
2m
1  2m  m 2
Now, For Penv  4 PT ;  1
2  m2
1
 1  2m  m 2  2  m 2  m  or m  50%
2
v- A  t   Ac 1  m  u  t    Ac 1  m cos  200 t 
U M  Ac 1  m  ; i.e when cos  200 t   1.
U m  Ac 1  m  1   Ac 1  m  ; when cos  200 t   1.
Expressing m as a function of U M and U m , we obtain
UM Um
m .
UM Um
Um  4 Um 2
if U M  U m  4,  m  
Um  4 Um Um  2
2 1
hence,  U m   2  2; i.e when m 
m 2

Question 3
1. We can increase the data rate without increasing the bandwidth by:
- Using the QSPK(Quadrature phase shift keying) in which four carrier signals of different
phases are generated and each carrier modulates two bits at a time thereby increasing the
bit rate with same Bandwidth.
- Using the 8-SPK in which eight carrier signals of different phases are generated and each
carrier modulates three bits at a time thereby increasing the bit rate with same Bandwidth.
The negative consequence of this increase in data rate is that there is noise and interference
that can cause errors at the receiver.
2. BPSK(Binary Phase Shift Keying ) generates two carrier waves which are different in phase
shift of  , each modulates a single bit until the data bits are finished.

3.

150
 i. The combination of the Amplitude modulation (AM) and Phase modulation(PM)
gives Quadrature amplitude modulation (QAM). 16-QAM uses three amplitudes and
12 phases to create 16 different carrier waveforms, each representing one
combination of four bits.

4. The energy of the square wave with amplitude A over a period T is given by
T
T T
2
A2T
E   x t  dt   A dt   0dt 
2 2
.
0 0 T 2
2
2
AT 4
E  2 T  2 .
2 A

QUESTION4

151
 EEF 304: BASIC TELECOMMUNICATIONS (2014/2015)
QUESTION 1(18 MARKS)
1- With the help of a schematic diagram, state the difference between FM and PM modulations
2- You are given the following FM modulated signal:
v  t   vo cos  w1t  0.5cos  w2t   , where v0  1V , w1  107 rad / s and w2  104 rad / s
a. Determine the frequency f c and f m of the carrier and modulating waves respectively.
b. Determine the frequency deviation(excursion), the modulating index and the spectral
bandwidth.
c. Deduce the expression of the PM modulated signal.

QUESTION 2(16 MARKS)

You are given the following signals: x1  t   5cos  200 t  , x2  t   5sin  200 t 
a. Calculate the message power Px of x1  t 

b. Determine the Fourier transform of x1  t  and x2  t  .

c. Compare the amplitudes and phases of x1  f  and x2  f  .

d. Represent x1  t  and x2  t  . in the frequency domain.

QUESTION 3( 18 MARKS)
1- Define and give the usefulness of compounding (10 lines maximum).
2- a. Define PCM and the state the Nyquist theorem.
b. A signal is sampled at 60kHz and an encoded using 16 bits words. For how long can we
store the information in 1Moct.

3- Consider the following analog signal:

   
xa  t   2cos 100 t   5cos  250 t    4cos  300 t   16sin  600 t  
 6  4
a. According to the sampling theorem, what minimum value should be chosen as sampling
frequency f s ,min .

b. For f s  3 f s ,min represent the amplitude and phase spectrum of the sampled signal xs  t  .

QUESTION 4( 18 MARKS)
5. Explain how PSK could be used to increase the bit rate without increasing the bandwidth.
Give one negative consequence of this increased data rate.
6. How would you transmit a bit sequence 0111 0101 0010 1011 using BPSK signaling
 
technique? Sketch the modulated signal if the carrier signal is c  t   sin  2 f ct  .
 2
7. i. Describe the 16-QAM frame in terms of amplitude and phase.

152
 0
ii. Draw the constellation diagram of a 16-QAM signal where a carrier with 45 phase shift
and high amplitude corresponding to a bit combination of 1000.

153
 SOLUTION TO EEF 304: BASIC TELECOMMUNICATIONS (2014/2015)
QUESTION 1.
1. See question 3b of the CA 2014.

2.  a  v  t   v0 cos  w1t  0.5sin  w2t   ; v0  1V , w1  107 rad / s, w2  104 rad / s

 2 
comparing this with s  t   Ac cos  wct  Am sin wmt  ,
 wm 
107
we have wc  w1  107 rad / s  f c   1.6 107 Hz.
2
104
we have wm  w2  104 rad / s  f m   1.6 104 Hz.
2
b. the frequency excursion  f s   Am
2 Am 0.5w2
 0.5  f s   Am   795.77Hz
wm 2
2 Am
the modulation index ,  =  0.5
wm
the spectral bandwidth:
c The PM modulated signal
s  t   Ac cos  w1t   cos w2t   1cos  w1t  0.5cos  w2t  
 s  t   cos  w1t  0.5cos w2t 
 T
 T
2.  a  Px 
T
x t 
T
 5cos  200 t   dt  12.5W; where   1.
2 2
1 dt 
0 0

 b We know that F  e   2  w  w0  .

jw0t

let x1  t   5cos  200 t   A cos  w1t 

Also, we know that A cos  w1t    e  e  jw1t  .

A jw1t
2
A  A
 F   e jw1t  e  jw1t     2   w  w1     w  w1  
2  2
 A   w  w1     w  w1  
 F 5cos w1t  5   w  w1     w  w1   .

154
 we also let x2  t   5sin  200 t   A sin  w2t   A sin  w2t  
2j
e  e .
A jw2t  jwt

A  A
 F   e jw2t  e  jwt     2   w  w2     w  w2  
2 j  2j
  jA   w  w2     w  w2  
 F  5sin w2t    j 5   w  w2     w  w2   .
c the amplitudes of X 1  f  is equal to the aplitude of X 2  f 
ie X 1  f   X 2  f   5 .
the phase of X 1  f  is given by
 0 
tan 1  0
 5   w  w1     w  w1   
  
the phase of X 2  f  is given by
 5   w  w1     w  w1    
tan 1     .
 0  2
 
d
QUESTION 3
1. Companding is a non-uniform signal quantizing process in which a signal is
compressed in an encoder and expanded in a decoder. It is useful becausein the end the
quantizing noise is low and the S/N is high since we have a shorter distance between
quantum levels for low level signal and for high level signal, we allow a little wide
distance between quantum levels.
2. a. See question 2(i) of 2014 EXAM.
b. f s  60kHz, n  16bits
the data rate , D  60 103 16  96 104 bps
96 104  1s
1Moct  t
1Moct 1 220  8
t    8.74s
96 104 96 104

155
    
3. xa  t   2 cos 100 t   5cos  250 t    4 cos  380 t   16sin  600 t  
 6  4
600
a. f m   300 Hz.  f s ,min  2 f m  600 Hz.
2
b. we have that f s  3 f s ,min  1800 Hz.
 ws  2 f s  3600 .
  
xa  t   2 cos  3600 t  100 t   2 cos  3600 t  100 t   5cos  3600 t  250 t    5cos  3600 t  250 t 
 6 
  
 4 cos  3600 t  380 t   4 cos  3600 t  380 t   16sin  3600 t  600 t    16sin  3600 t  600
 4 
   
xa  t   2 cos  3600 t  100 t   2 cos  3500 t   5cos  3850    5cos  3350  
 6  6
   
 4 cos  3980 t   4 cos  3220 t   16sin  4200 t    16sin  3000 t   .
 4  4

QUESTION 4
See question 3 of 2014 EXAM.

156
 EEF 310: COMPUTER ARCHITECTURE (2014/2015)
1
What is your understanding of the following words/phrase?
I) ILP
II) Von Neumann architecture
III) Bench marking
IV) Convert 0.430410 to base 5
V) Convert 31214 to base 3
VI) RAID
VII) Flynn’s taxonomy
VIII) Superscalar architecture
IX) Super pipelining
X) Harmonic mean

2 Classify instructions according to the number of operand and give the various address modes

3 a) How is the CPU organized?

b) Discuss the cache and how the CPU move information into and out of it
4 Discuss I/O architecture of a computer and the I/O protocols and control methods

5 a) Discuss the RISC and CISC architectures

b) Discuss MIMD architecture and networking

157
 SOLUTION TO EEF 310: COMPUTER ARCHITECTURE (2014/2015)
1)
a)

i) ILP : Instruction-level parallelism (ILP) is based on multiple issue processors

(MIP). processors use pipelining to overlap the execution of
instructions and improve performance. This potential overlap among
instructions is called instruction-level parallelism (ILP), since the instructions
can be evaluated in parallel
ii) The von Neumann model consists of five major components: Input Unit,
provides instructions and data to the system, which are subsequently stored in
the Memory Unit. The instructions and data are processed by the Arithmetic and
Logic Unit (ALU) under the direction of the Control Unit. The results are sent to
the Output Unit. The ALU and control unit are frequently referred to collectively
as the central processing unit (CPU). Most commercial computers can be
decomposed into these five basic units. The stored program is the most
important aspect of the von Neumann model. A program is stored in the
computer’s memory along with the data to be processed.
iii) Standard tests that are used to compare the performance of computers,
processors, circuits, or algorithms.
iv) 0.430410 𝑡𝑜 𝑏𝑎𝑠𝑒 5
0.4304 ∗ 5 = 2.152 ,2
0.152 ∗ 5 = 0.76 ,0
0.76 ∗ 5 = 3.8 ,3
0.8 ∗ 5 = 4 ,4
0.430410 =. 20345

v) 31214 𝑡𝑜 𝑏𝑎𝑠𝑒 10 𝑤𝑒 𝑕𝑎𝑣𝑒 21710

21710 𝑡𝑜 𝑏𝑎𝑠𝑒 3 𝑤𝑒 𝑕𝑎𝑣𝑒 220013

vi) RAID : redundant array of inexpensive disks (RAID) standardized scheme for
multiple disk data base systems viewed by the operating system as a single
logical drive. Data is distributed across the physical drives allowing
simultaneous access to data from multiple drives, thereby reducing the gap
between processor speeds and relatively slow electromechanical disks.
Redundant disk capacity can also be used to store additional information to
guarantee data recoverability in case of disk failure (such as parity or data
duplication).
vii) Flynn’s taxonomy: is based on identifying two orthogonal stream s in a
computer. These are the instruction and the data stream s. The instruction
stream
is defined as the sequence of instructions performed by the compute r. The data
stream is defined as the data traffic exchanged between the memory and the

158
 processing unit. According to Flynn’ s classification, either of the instruction or
data streams can be single or multiple.
viii) Superscalar Architectures: A scalar machine is able to perform only one
arithmetic operation at once. A superscalar architecture (SPA) is able to fetch,
decode, execute, and store results of several instructions at the same time. It
does so by transforming a static and sequential instruction stream into a
dynamic and parallel one, in order to execute a number of instructions
simultaneously

ix) Pipelining is the division of an instruction into a number of subunits (stages),

and each executed serially. The units are connected in a serial fashion and all of
them operated simultaneously in an overlapping manner. Since cache access is
particularly time critical there may be extra pipeline stages due to decomposing
memory access, this type of deeper pipelining is called superpipelining
x) Harmonic mean:

2)

Instructions can be classified according to the number of operands contained as:

1. three-address
2. two-address
3. one-and-half-address
4. one-address
5. zero-address

using the convention operation, source, destination to express an instruction. In that convention,
operation represents the operation to be performed, for example, add, subtract, write, or read. The
source field represents the source operand(s). The source operand can be a constant, a value stored
in a register, or a value stored in the memory. The destination field represents the place where the
result of the operation is to be stored, for example, a register or a memory location.

For a three-address instruction the address field is made up of 3 addresses. It takes the form
operation add-1, add-2, add-3. In this form, each of add-1, add-2, and add-3 refers to registers or
memory locations. Consider, for example, the instruction ADD R1, R2, R3. This instruction indicates
that the operation to be performed is addition. It also indicates that the values to be added are
those stored in registers R1 and R2 that the results should be stored in register R3. An example of a
three-address instruction that refers to memory locations may take the form ADD A, B, C. The
instruction adds the contents of memory location A to the contents of memory location B and stores
the result in memory location C.

A two-address instruction has two addresses in the address field. It takes the form operation add-1,
add-2. In this form, each of add-1 and add-2 refers to a register or to a memory location. Consider,
for example, the instruction ADD R1, R2. This instruction adds the contents of register R1 to the
contents of register R2 and stores the results in register R2. The original contents of register R2 are

159
lost due to this operation while the original contents of register R1 remain intact. This instruction is
equivalent to a three-address instruction of the form ADD R1, R2, R2. A similar instruction that uses
memory locations instead of registers can take the form ADD A, B. In this case, the contents of
memory location A are added to the contents of memory location B and the result is used to
override the original contents of memory location B.

The operation performed by the three-address instruction ADD A, B, C can be performed by the two
two-address instructions MOVE B, C and ADD A, C. This is because the first instruction moves the
contents of location B into location C and the second instruction adds the contents of location A to
those of location C (the contents of location B) and stores the result in location C.

A one-address instruction takes the form ADD R1. In this case the instruction implicitly refers to a
register, called the Accumulator Racc, such that the contents of the accumulator is added to the
contents of the register R1 and the results are stored back into the accumulator Racc. If a memory
location is used instead of a register then an instruction of the form ADD B is used. In this case, the
instruction adds the content of the accumulator Racc to the content of memory location B and stores
the result back into the accumulator Racc. The instruction ADD R1 is equivalent to the three-address
instruction ADD R1,Racc, Racc or to the two-address instruction ADD R1,Racc.

Between the two- and the one-address instruction, there can be a one-and-half address instruction.
The address field here contains two items, one from memory and the other from a register.
Consider, for example, the instruction ADD B, R1. In this case, the instruction adds the contents of
register R1 to the contents of memory location B and stores the result in register R1. Owing to the
fact that the instruction uses two types of memories, that is, a register and a memory location, it is
called a one-and-half-address instruction. This is because register addressing needs a smaller
number of bits than those needed by memory addressing.

There exist zero-address instructions. These are the instructions that involve stack operations. A
stack is a data organization mechanism in which the last data item stored is the first data item
retrieved. Two specific operations can be performed on a stack. These are the push and the pop
operations.

The different ways in which operands can be addressed are called the
addressing modes. Addressing modes differ in the way the address information of operands is
specified. The simplest addressing mode is to include the operand itself in the
instruction, that is, no address information is needed. This is called immediate
addressing
According to this addressing mode , the value of the operand is (immediately) available in the
instruction itself. Consider, for example, the case of loading the decimal
value 1000 into a register Ri. This operation can be performed using an instruction
such as the following: LOAD #1000, Ri. In this instruction, the operation to be performed is to load a
value into a register. The source operand is (immediately) given
as 1000, and the destination is the register Ri. It should be noted that in order to indicate that the
value 1000 mentioned in the instruction is the operand itself and not
its address (immediate mode), it is customary to prefix the operand by the special
character #
Direct (absolute mode)
According to this addressing mode, the address of the memory location that holds
the operand is included in the instruction. Consider, for example, the case of loading

160
the value of the operand stored in memory location 1000 into register Ri. This operation can be
performed using an instruction such as LOAD 1000, Ri. In this instruction, the source operand is the
value stored in the memory location whose address is
1000, and the destination is the register Ri. Note that the value 1000 is not prefixed
with any special characters, indicating that it is the (direct or absolute) address of the
source operand
Indirect Mode
In the indirect mode, what is included in the instruction is not the address of the
operand, but rather a name of a register or a memory location that holds the (effective) address of
the operand. In order to indicate the use of indirection in the instruction, it is customary to include
the name of the register or the memory location in
parentheses. Consider, for example, the instruction LOAD (1000), Ri. This instruction has the
memory location 1000 enclosed in parentheses, thus indicating indirection
Indexed Mode
In this addressing mode , the address of the operand is obtained by adding a constant to the content
of a register, called the index register. Consider, for example,
the instruction LOAD X(Rind), Ri. This instruction loads register Ri with the contents
of the memory location whose address is the sum of the contents of register
Rind and the value X. Index addressing is indicated in the instruction by including
the name of the index register in parentheses and using the symbol X to indicate
the constant to be added
Other modes include ;
Relative Mode: in indexed addressing, an index register, Rind, is used.
Relative addressing is the same as indexed addressing except that the program
counter (PC) replaces the index register. For example, the instruction LOAD X(PC),
Ri loads register Ri with the contents of the memory location whose address
is the sum of the contents of the program counter (PC) and the value X
Autoincrement Mode :with autoincrement, the content of the autoincrement register is automatical
ly incremented after accessing the operand. As before, indirection is indicated by including the
autoincrementregister in parentheses. The automatic increment of the
register’s content after accessing the operand is indicated by including a (þ ) after
the parentheses. Consider, for example, the instruction LOAD (Rauto)þ, Ri. This
instruction loads register Ri with the operand whose address is the content of register
R auto. After loading the operand into register Ri, the content of register Rauto is
incremented, pointing for example to the next item in a list of items
Autodecrement Mode Similar to the autoincrement, the autodecrement mode
uses a register to hold the address of the operand. However, in this case the
content of the autodecrement register is first decremented and the new content
is used as the effective address of the operand. In order to reflect the fact that the
content of the autodecrement register is decremented before accessing the operand,
a (2 ) is included before the indirection parentheses. Consider, for example, the
instruction LOAD (Rauto), Ri. This instruction decrements the content of the
register Rauto and then uses the new content as the effective address of the operand
that is to be loaded into register Ri

3)
a) A typical CPU has three major components: (1) register set, (2) arithmetic logic
un it (ALU), and (3) cont rol unit (C U). The register set differs from one computer

161
 architecture to another. It is usually a combination of general-purpose and special
purpose
registers. General-purpose registers are used for any purpose, hence the
name general purpose. Special-purpose registers have specific functions within
the CPU. For example, the program counter (PC) is a special-purpose register
that is used to hold the address of the instruction to be executed next . Another
example of special -purpose registers is the instruction register (IR), which is
used to ho ld the instruction that is currently executed . The ALU provides the circuitry
needed to perform the arithmetic, logical and shift operations demanded of
the instruction set. In Chapter 4, we have covered a number of arithmetic operations
and circuits used to support computation in an ALU. The control unit is
the entity responsible for fetching the instruction to be executed from the main
memory and decoding and then executing it

b) After registers the cache memory is the fastest in the computer.

The idea behind using a cache as the first level of the memory hierarchy is to keep the
information expected to be used more frequently by the CPU in the cache (a small high-
speed memory that is near the CPU). The end result is that at any given time some active
portion of the main memory is duplicated in the cache. Therefore, when the processor
makes a request for a memory reference, the request is first sought in the cache . If the
request corresponds to an element that is currently residing in the cache , we cal l that a
cache hit. On the other h and, if the request corresponds to an element that is not
currently in the cache , we call that a cache miss.
The CPU organizes and moves information in and out of the cache using the following
methods

Direct Mapping

This is the simplest. Its simplicity stems from the fact that it places an incoming main memory block
into a specific fixed cache block location. The placement is done based on a fixed relation between

162
the incoming memory block number, i, the cache block number, j, and the number of cache blocks,
N:

According to the direct-mapping technique the MMU(memory management unit)

interprets the address issued by the processor by dividing it into three fields as shown below. The
lengths, in bits, of each of the fields are:

Word field = log 2 B, where B is the size of a cache block in words.

Block field = log 2 N, where N is the size of the cache in blocks.
Tag field = log 2 (M/N), where M is the size of the main memory in blocks.
The number of bits in a main memory address = log 2 (B X M)
The steps of the protocol are:

1. Use the Cache Block field to determine the cache block that should contain the element
requested by the processor. The Block field is used directly to determine the cache block
sought, hence the name of the technique, direct-mapping.
2. Check the corresponding Tag memory to see whether there is a match between its content
and that of the Tag field. A match between the two indicates that the targeted cache block
determined in step 1 is currently holding the main memory element requested by the
processor, that is, a cache hit.
3. Among the elements contained in the cache block, the targeted element can be selected
using the Word field.
4. If in step 2, no match is found, i.e. a cache miss, the required block has to be brought from
the main memory, deposited in the cache, and the targeted element is made available to the
processor. The cache Tag memory and the cache block memory have to be updated
accordingly.

(advantages of this method and its equivalent replacement technique could be discussed based on
the mark allocation )

Fully Associative Mapping

According to this technique, an incoming main memory block can be placed in any available cache
block. Therefore, the address issued by the processor need only have two fields. These are the Tag
and Word fields. The first uniquely identifies the block while residing in the cache. The second field
identifies the element within the block that is requested by the processor. The two fields as
interpreted by MMU are shown below. The length, in bits, of each of the fields are given by

163
The steps of the protocol are:

1. Use the Tag field to search in the Tag memory for a match with any of the tags stored.
2. A match in the tag memory indicates that the corresponding targeted cache block
determined in step 1 is currently holding the main memory element requested by the
processor, that is, a cache hit.
3. Among the elements contained in the cache block, the targeted element can be selected
using the Word field.
4. If in step 2, no match is found, then it is a cache miss and the required block has to be
brought from the main memory, deposited in the first available cache block, and the
targeted element (word) is made available to the processor. The cache Tag memory and the
cache block memory have to be updated accordingly.

Set-Associative Mapping

In the set-associative mapping technique, the cache is divided into a number of sets. Each set
consists of a number of blocks. A given main memory block maps to a specific cache set based on
the equation s = i mod S, where S is the number of sets in the cache, i is the main memory block
number, and s is the specific cache set to which block i maps. However, an incoming block maps to
any block in the assigned cache set. Therefore, the address issued by the processor is divided into
three distinct fields. These are the Tag, Set, and Word fields. The Set field is used to uniquely
identify the specific cache set that ideally should hold the targeted block. The Tag field uniquely
identifies the targeted block within the determined set. The Word field identifies the element
(word) within the block that is requested by the processor. The MMU interprets the address issued
by the processor by dividing it into three fields as shown below. The length, in bits, of each of the
fields of that figure is given by

The steps of the protocol are:

164
 1. Use the Set field (5 bits) to determine (directly) the specified set (1 of the 32 sets)
2. Use the Tag field to find a match with any of the (four) blocks in the determined set. A
match in the tag memory indicates that the specified set determined in step 1 is currently
holding the targeted block, that is, a cache hit.
3. Among the 16 words (elements) contained in hit cache block, the requested word is
selected using a select or with the help of the Word field.
4. If in step 2, no match is found, i.e. a cache miss, the required block has to be brought from
the main memory, deposited in the specified set first, and the targeted element (word) is
made available to the processor. The cache Tag memory and the cache block memory have
to be updated accordingly.

4)
Input – output (I/ O) devices vary substantially in their characteristics. One distinguishing
factor among input devices (and also among output devices) is their
data processing rate, defined as the average number of characters that can be processed by
a device per second. For example, while the data processing rate of an
input device such as the keyboard is about 10 characters (bytes)/ second, a scanner
can send data at a rate of about 200,000 characters/ second. Similarly, while a laser
printer can output data at a rat e of about 100,000 characters/ second, a graphic
display can output data at a rate of about 30,0 00,000 characters/ second
There exists a big difference in the rate at which a processor can process information and
those of input and output devices. One simple way to accommodate this
speed difference is to have the input device, for example, a keyboard, deposit the
character struck by the user in a register (input register), which indicates the availability of
that character to the processor. When the input character has been taken by
the processor, this will be indicated to the input device in order to proceed and input
the next character, and so on. Similarly, when the processor has a character to output
(display), it deposits it in a specific register dedicated for communication with the
graphic display (output register). When the character has been taken by the graphic
display, this will be indicated to the processor such that it can proceed and output the
next character, and so on. This simple way of communication between the processor
and I/O devices, called I/O protocol, requires the availability of the input and
output registers
The I/O protocols include two basic types ;
In the first arrangement, I/ O devices are assigned particular addresses, isolated from the address space
assigned to the memory. The execution of an input instruction at an input device address will cause the
character stored in the input register of that device to be transferred to a specific register in the CPU.
Similarly, the execution of an output instruction at an output device address will cause the character stored in
a specific register in the CPU to be transferred to the output register of that output device. This arrangement,
called shared I/O .In this case, the address and data lines from the CPU can be shared between the memory
and the I/O devices. A separate control line will have to be used. This is because of the need for executing
input and output instructions..
The second possible I/O arrangement is to deal with input and output registers as if they are regular memory
locations. In this case, a read operation from the address corresponding to the input register of an input
device, for example, Read Device 6, is equivalent to performing an input operation from the input register in
Device #6.
Similarly, a write operation to the address corresponding to the output register of an output device, for
example, Write Device 9, is equivalent to performing an output operation into the output register in Device
#9. This arrangement is called memory-mapped I/O. The main advantage of the memory-mapped I/O is the
use of the read and write instructions of the processor to perform the input and output operations,

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respectively. It eliminates the need for introducing special I/O instructions. The main disadvantage of the
memory-mapped I/O is the need to reserve a certain part of the memory address space for addressing I/O
devices, that is, a reduction in the available memory address space. The memory-mapped I/O has been mostly
adopted by Motorola
PROGRAMMED I/O
Consider reading a block of data from a disk. In programmed I/O, the CPU polls each device to see if it needs
servicing. In a restaurant analogy, the host would approach the patron and ask if the patron is ready. The
operations that take place for programmed I/O are shown in the flowchart in Figure 8-8. The CPU first checks
the status of the disk by reading a special register that can be accessed in the memory space, or by issuing a
special I/O instruction if this is how the architecture implements I/O. If the disk is not ready to be read or
written, then the process loops back and checks the status continuously until the disk is ready. This is
referred to as a busy-wait. When the disk is finally ready, then a transfer of data is made between the disk and
the CPU. After the transfer is completed, the CPU checks to see if there is another communication request for
the disk. If there is, then the process repeats, otherwise the CPU continues with another task. In programmed
I/O the CPU wastes time polling devices. Another problem is that high priority devices are not checked until
the CPU is finished with its current I/O task, which may have a low priority. Programmed I/O is simple to
implement
INTERRUPT-DRIVEN I/O
With interrupt driven I/O, the CPU does not access a device until it needs servicing, and so it does not get
caught up in busy-waits. In interrupt-driven I/O, the device requests service through a special interrupt
request line that goes directly to the CPU. The restaurant analogy would have the patron politely tapping
silverware on a water glass, thus interrupting the waiter when service is required. request to the disk for
reading or for writing, and then immediately resumes execution of another process. At some later time, when
the disk is ready, it interrupts the CPU. The CPU then invokes an interrupt service routine (ISR) for the disk,
and returns to normal execution when the interrupt service routine completes its task

DIRECT MEMORY ACCESS (DMA)

The main idea of direct memory access (DMA) is to enable peripheral devices to cut out the “middle
man” role of the CPU in data transfer. It allows peripheral devices to transfer data directly to and
from memory without the intervention of the CPU. Having peripheral devices access memory
directly would allow the CPU to do other work, which would lead to improved performance,
especially in the cases of large transfers.
The DMA controller is a piece of hardware that controls one or more peripheral devices. It allows
devices to transfer data to or from the system’s memory without the help of the processor. In a
typical DMA transfer, some event notifies the DMA controller that data needs to be transferred to or
from memory. Both the DMA and CPU use memory bus and only one or the other can use the
memory at a time. The DMA controller then sends a request to the CPU asking its permission to use
the bus. The CPU returns an acknowledgment to the DMA controller granting it bus access. The
DMA controller now takes control of the bus to independently conduct memory transfer. When the
transfer is complete the DMA relinquishes its control of the bus to the CPU.
Processors that support DMA provide one or more input signals that the bus requester can claim to
gain control of the bus and one or more output signals that the CPU claims to indicate it has
relinquished the bus. The figure below shows how the DMA controller shares the CPU’s memory
bus. A DMA controller may have multiple channels. Each channel has associated with it an address
register and a count register. To initiate a data transfer the device driver sets up the DMA channel’s
address and count registers together with the direction of the data transfer, i.e. either read or write.
While the transfer is taking place, the CPU is free to do other things. When the transfer is complete,
the CPU is interrupted.
DMA channels cannot be shared between device drivers. A device driver must be able to determine
which DMA channel to use. Some devices have a fixed DMA channel, while others are more flexible,
where the device driver can simply pick a free DMA channel to use.

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5)
a) The term RISCs stands for Reduced Instruction Set Computers. It was originally
introduced as a notion to mean architecture s that can execute as fast as one instruction
per clock cycle .This paradigm promotes simplicity in computer
architecture design. In particular, it calls for going back to basics rather than providing
extra hardware support for high-level languages. This paradigm shift relates to
what is know n as the semantic gap, a measure of the difference between the operations
provided in the high-level languages (HLLs) and those provided in computer
architectures.
It is recognized that the wider the semantic gap, the larger the number of undesirable
consequences. These include (a) execution inefficiency, (b) excessive machine program
size, and (c) increased compiler complexity .Because of these expected consequences,
the conventional response of computer architects has been to add layers of
complexity to newer architectures. These include increasing the number and complexity
of instructions together with increasing the number of addressing modes. The
architectures resulting from the adoption of this “add more complexity” are now known
as Complex Instruction Set Computers (CISCs). However, it soon became apparent that a
complex instruction set has a number of disadvantages. These include a complex
instruction decoding scheme, an increased size of the control unit, and increased
logic delays. These drawbacks prompted a team of computer architects to adopt the
principle of “less is actually more.” Hence the birth of the RISC architecture
The choice of RISC versus CISC depends totally on the factors that must be considered by a
computer designer. These factors include size, complexity, and
speed. A RISC architecture has to execute more instructions to perform the same
function performed by a CISC architecture. To compensate for this drawback,
RISC architectures must use the chip area saved by not using complex instruction
decoders in providing a large number of CPU registers, additional execution
units, and instruction caches. The use of these resources leads to a reduction in
the traffic between the processor and the memory. On the other hand, a CISC architecture
with a richer and more complex instructions, will require a smaller number of
instructions than its RISC counterpart. However, a CISC architecture requires a
complex decoding scheme and hence is subject to logic delays. It is therefore reasonable to
consider that the RISC and CISC paradigms differ primarily in the strategy
used to trade off different design factor
There is very little reason to believe that an idea that improves performance for a
RISC architecture will fail to do the same thing in a CISC architecture and vice
versa. For example, one key issue in RISC development is the use of optimizing
the compiler to reduce the complexity of the hardware and to optimize the use of
CPU registers. These same ideas should be applicable to CISC compilers. Increasing

b) Multiple-instruction multiple-data stream s (MI MD): In a multiple instruction stream,

multiple data stream (MIMD) processor, several processors perform different
operations on different data sets, but are all coordinated to execute a single parallel
program
In general, MIMD systems can be categorized based on their memory organization into
shared-memory and message-passing architectures. The choice between the two
categories depends on the cost of communication (relative to that of the computation)

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and the degree of load imbalance in the application. An example of a MIMD processor is
the Sega home video entertainment system,
which has four processors for (1) sound synthesis (a Yamaha synthesis processor);
(2) sound filtering (a Texas Instruments programmable sound generator); (3)
program execution (a 68000); and (4) background processing (a Z80)
(also discuss on networking)

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 EEF 308: SYSTEM SIMULATION
SECTION A

Question 1
Using suitable examples, give the meaning of the following terms in Matlab
a. A command b. A statement c. A variable d. A Script e. workspace f. command History
g. An Expression i. An Operator.
4 x2  2 x  3
j. For x  2, solve p  x  
x3  1

Question 2
a. In simPowerSystems, in which conditions can we use the AC voltage source block as a DC
voltage source block ?
b. How can you invoke Simulink and simPowerSystems?
c. What can you say about the matlab and Simulink environments?
d. On the Simulink library browser, where can you the gain block ?
e. How many integrators do you need to model the following equation in Simulink?
d 2 vc dv
2
 4 c  3vc  3u  t   0
dt dt
f. What is the best choice between the state-space and integrators, when you to display the
output waveform of three variables? justify your answer.

SECTION B

Question 1
Given an R-L circuit, the voltage v  t  and current i  t  are given as v  t   10cos  377t  and
i  t   5cos  377t  600  . For 0  t  25  t is milliseconds  , sketch v  t  and i  t  .

Question 2
For the circuit below, use Simulink to find the nodal voltages V1 , V2 and V3 .

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 SOLUTION TO EEF 308: SYSTEM SIMULATION
SECTION A

QUESTION 1:
a. A Command: This is an instruct ion that tells MATLAB what to do during the execution of a
given task.
b. A Statement: it is a command to be executed when the program runs.
c. A Variable: A Variable is the name given to a storage area that MATLAB can understand
and manipulate.
d. A Script: A Script permits us to create ,save and execute commands in an M-file.
e. Workspace: The workspace keeps track of the variables you have defined as you execute
commands in the command window.
f. Command History : The command history records the commands you issued in the
command window.
g. An Operator: An operator is a symbol that tells MATLAB to perform specific mathematical
or logical operation.
h. An Expression is a variable or constant with or without operators used on MATLAB.
i. The code below permits you solve the given problem in MATLAB.
>> x=sqrt(2); %defining the square root of 2
>>num=4*x^2-2*x+3;%splitting the function into two parts
>>denom=x^3+1;
>> p=num/denom

p=

2.1344

QUESTIO 2:
a. Check
b. Simulink can be invoke either by typing Simulink on the command window or by clicking on
the Simulink icon show on the MATLAB desktop
SimPowerSystems can be invoked in the Simulink environment by searching in options in
Simulink after clicking on the start button.
c. The MATLAB and Simulink environments are integrated into one entity, and thus we can
analyze, simulate and revise our models in either environment.
d. In Simulink library in commonly used Blocks
e. We need two integrators
f. The state-space,

SECTION B

QUESTION 1
clear,clc

170
% this program is aimed at sketching the graph v(t)and i(t)
t=0:.00000001:0.25; %defining the increment in time
theta1=377.*t;
rad1=(theta1.*(pi/180)); %converting from degrees to radians
v=10.*cos(rad1); %expression of voltage
subplot(2,1,1)
plot(t,v)
xlabel('time/ms')
ylabel('voltage/volts')
title(' A Sketch of the voltage in R-L CIRCUIT')
gridon
theta2=377.*t+60;
rad2=((pi/180).*theta2);%converting from degrees to rads
i=5.*cos(rad2);
subplot(2,1,2)
plot(t,i)
xlabel('time/ms')
ylabel('current/A')
title('a Sketch of current in R-L CIRCUIT')
grid on

QUESTION 2
The nodal equations are:
3v1  2v2  v3  100  0........................ 1
20v1  29v2  5v3  0............................  2 
 2v1  v2  3v3  80  0..........................  3

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 EEF 308: SYSTEMS SIMULATION (2014/2015)
QUESTION 1
a) How can you invoke Simulink?
b) On the Simulink library browser, where can you get the gain block?
c) How many integrators do you need to model the following equation in Simulink?
𝑑2 𝑣𝑐 𝑑𝑣𝑐
2
+4 + +3𝑣𝑐 − 3𝑢0 (𝑡) = 0.
𝑑𝑡 𝑑𝑡
d) What is the best choice between the state – space block and the integrators, when you need
to display the output waveform or more variables?
Justify your answer
e) How do you generate cell in an m-file?

QUESTION 2
Using the for loop, create a table that convert angle values from degrees to radians, from 0 to 360
degrees, in increments of 10 degrees. Make sure to develop a flow chart that helps to plan your
code.

QUESTION 3
The voltage, V, across a resistance is given as (Ohm’s Law), 𝑉 = 𝐼𝑅, where 𝐼 is the current and 𝑅 the
resistance. If 𝑅 = 10Ω and the current is increased from 0 to 20A with increments of 2A, use a
script m-file and a function m-file to:
a) Generate a table of current, voltage and power dissipation in 𝑅.
b) Plot the I-P and I-V curves.

QUESTION 4
Create a function called facto that uses a while loop to find𝑁!. Include an if statement to check for
negative numbers and to confirm that the input is a scalar.

QUESTION 5
Consider an object falling towards the ground. A widely reported equation describing the resulting
velocity is the differential equation:
𝑑𝑣 𝑐
= 𝑔 − 𝑣2
𝑑𝑡 𝑚
Where:
g is the acceleration due to gravity; v is the velocity; m is the mass; c is the second-order drag
coefficient.
Using Simulink, solve this equation by find velocity as a function of time, for 𝑔 = 9.81 𝑚/𝑠 2 ,
𝑚 = 720 𝑘𝑔, 𝑐 = 0.3 𝑘𝑔/𝑚, 𝑣(0) = 0 𝑚/𝑠.

QUESTION 6
For the circuit shown below, use Simulink to model and to find the nodal voltages𝑉1 , 𝑉2 , 𝑎𝑛𝑑 𝑉3 .

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 SOLUTION TO EEF 308: SYSTEM SIMULATION
See previous solution.

173