Micro-ohmmeter Design and Simulation

Daniel Alejandro Vergara Escalona - T7173177

Teesside University. December 2017

Abstract
Lock-In Amplifiers are devices used to recover signals with low signal-noise ratios by the
principle of the phase sensitive detection. The scope of the present analysis is the design of
a Micro-Ohmmeter using said principle to measure low resistances in circuit by using the
software Proteus R
8. Simulations of the circuit were run and the main features of the phase
sensitive detection were exposed with results of the effects of different phase shifts for the
demodulation process. The simulation results were in accordance with the mathematical
model obtaining low relative errors between them.

Keywords: Lock-in amplifier, Voltage-Controlled-Oscillator, Micro-Ohmmeter, Phase

Sensitive Demodulation, PSD.

1 Introduction
In order to apply the theoretical principles of
Signal Conditioning, a Lock-In Amplifier based
Micro-Ohmmeter circuit was designed with the
objective to select correct values of different
electrical components in order to generate an
audible tone from a buzzer when a small resis-
2 Overview
The required task was to design and test,
stage by stage, a micro-ohmmeter based on
a lock-in amplifier in able to measure small
resistances without applying large currents, an
application useful for measuring short circuits
in printed circuit boards. The electronic
design software Proteus 8 was used for the
R

tor value was measured. To accomplish this design and simulation of each of the circuit
task, a circuit outline with connections was stages.
available for its reproduction using the soft-
ware Proteus R
8. The objective of the exposed A proposed block diagram for the circuit is
document is to understand the operating prin- shown in Figure 1 in which the circuit main
ciple of the Phase Sensitive Detection and the elements are shown:
importance of the different elements in a signal
conditioning circuit. • Signal Source (Modulation)

The signal is conditioned through a Modu- • Instrumentation Amplifier

lation/Demodulation process in order to im-
prove the signal to noise ratio. Once the signal • Analogue Switch (Demodulation)
is modulated it is amplified through an Instru- • Virtual earth
mentation Amplifier, where the this noise is
further reduced. Then the signal is DC av- • Low-Pass Filter
eraged through a low pass filter to obtain a
smooth DC signal. Finally this DC signal is • Voltage-Controlled Oscillator
converted into audible frequency for a buzzer
• Mute
through a Voltage Controlled Oscillator to in-
dicate that the measured signal is the instru- • Buzzer
ment range.
1
 Figure 1: Block-diagram scheme for the micro-ohmmeter.

3 Metodology extract signal out of the noise at a specific

reference signal. When there noise that is
In order to achieve the required task, each of not in the reference frequency range it is re-
the necessary stages of the Micro-Ohmmeter jected, greatly increasing the signal-noise ratio.
were designed and tested one-by-one to avoid
convergence problems during the simulation. The Lock-In Amplifier, provides a DC out-
put proportional to the AC signal under inves-
In each of the circuit stages a brief ex- tigation. The PSD rectifies only the signal of
planation of the circuit is given. Then the interest while suppressing the effect of noise or
mathematical principles are explained by interfering components which may accompany
derivation of the governing equations, when the signal.
necessary. Finally, the required calculations There are some steps in the PSD process:
for that given stage are shown and the circuit
electronic components and connections are 4.1 Modulation
indicated.
In this step the signal is multiplied by a carrier
Starting in Section 4, the operating princi- signal with higher frequency. The result is a
ple of the Lock-In Amplifier is shown and the signal with higher frequency, usually in a less
full mathematical derivation is proved. In Sec- energetic noise zone.
tion 5, the circuit stages are explained. The
results are shown mostly through graphs fol- Suppose a signal V (t) the signal to modulate
lowed by an explanation of their main features. and a carrier signal Vcarr (t) = A · sin(2πfc t)
In Section 6 a synthesis table is shown with then the modulated signal is given by:
all the circuit missing values in addition to a
Vmod (t) = V (t)·Vcarr = V (t)·Asin(2πfc t) (1)
comparison between the simulation and theo-
retical results for different values of the mea- Now lets suppose V (t) = Vo · Sin(2πfs t) to
sured magnitude. be AC. Then assuming the magnitude of the
carrier signal equal to 1 for simplicity. Without
loss generality its possible to write:
4 Operating Principle Vmod (t) = Vo · Sin(2πfs t) · Sin(2πfc t)
The Micro-Ohmmeter circuit is based on a Then by the trigonometrical identity
Lock-In Amplifier or Phase-Sensitive Detector
cos(a ± b) = cos(a)cos(b) ∓ sin(a)sin(b) (2)
circuit.
A Lock-In Amplifier is an electronic de- The modulated AC signal can be written as:
vice able to measure very small AC signals
accurately even when the signal is deeply 1
Vmod (t) = Cos(2π(fc − fs )t)
obscured by noise. They use a technique 2 
known as Phase-Sensitive Detection (PSD) to − Cos(2π(fc + fs )t) (3)

2
 If the condition fs << fc is satisfied, the without loss of generality the demodulated sig-
original signal is carried from its original nal is given by:
frequency fs to a higher value of fc ± fs .
Vdem = Vm (t) · Vref (t)
= V (t) · Sin(2πfc t) · Sin(2πfref t + φ)
(4)
Again by equation 2, it can be re-written as:
1 
Vdem = V (t) Cos(2π(fref − f c)t − φ)
2 
− Cos(2π(fref + f c)t + φ) (5)

Now setting fref = fc and letting φ as a pa-

rameter:
1  
Vdem = V (t) Cos(φ) − Cos(2φ(2fc )t + φ)
2
(6)
Notice how by equating those frequencies
the signal Vdem has now been decomposed
in two parts: 1/2V (t)Cos(φ) who car-
ries the original signal information and
−1/2V (t)Cos(2π(2fc )t + φ) which has a
higher frequency. Therefore by choosing a
correct value for φ and connecting in cascade a
low-pass filter the signal V (t) can be recovered.
Figure 2: Signal modulation. (Source: Own)

Figure 2 shows a comparison between the

signal V (t) the carrier Vc and the modulated
signal Vmod with fs = 1Hz and fc = 10Hz.

The advantage of modulating a signal with

fc is the fact that it is moved from a
’noise/interference’-sensitive bandwidth to a
less affected one, thus this way the noise can
be greatly suppressed while also increasing the
signal to noise ratio. Its important to chose a
high value for fc in order to distinguish it from
fs .
Figure 3: Influence of the phase angle φ in the
phase sensitive demodulation. (Source: Own)
4.2 Demodulation
Figure 3 shows the waveform of Vdem for
In this step the modulated signal is then different values of the phase angle φ (0o , 90o ,
multiplied by a reference signal with a phase 180o and 270o ). Notice how the average value
shift. The carried signal can be amplified prior for both 90o and 270o is equal to zero in the
to this stage without any loss of information. domain [0,T/2] while the graph for 0o and
180o has an average different from zero in the
Suppose a modulated signal Vm (t) = V (t) · same domain while also describing a similar
Sin(2πfc t). Lets Vref (t) = B · Sin(2πfref t + φ) curve to V (t).
be the reference signal. Suppose B = 1, then

3
 An important remark to both modulation equal to +3V with different phase delays (0o ,
and demodulation is the fact that both carrier 90o , 180o , 270o ).
and reference signal are not necessarily to
be sinusoidal and the presented derivation The 555-timer has two different config-
remains valid because any signal can be urations, mono-stable (or single shot) and
expressed as its equivalent Fourier Series a-stable (continuous/free-run). As a contin-
transformation. uous supply-signal was required the a-stable
configuration was adopted. Figure 4 shows
the 555 circuit outline as it is shown in the
4.3 Filtering Proteus work-space. The resistor R2 value had
to be chosen to guarantee a 1700Hz frequency
As seen before Vdem has two main components: for the 555-Timer pin 3 output.
1
Vdem1 = · V (t) · Cos(φ)
2 (7)
1
Vdem2 = − · V (t) · Cos(2πfc t + φ)
2
And trough the implementation of a
low pass filter in cascade to remove the
2πfc components of Vdem the output signal
has all the characteristics of V (t), is clean
of noise (ideally), and has half of its amplitude.

In the required circuit the modulation oc-

curs through a quadrature divider connected
in series with the interested resistor, the de-
modulation process is occurs through an ana-
log switch in between the stages 1 and 2 of
the Instrumentation Amplifier, and finally the
amplified demodulated signal goes through a Figure 4: 555-Timer (Proteus)
Salen-Key Equal Value Low-pass filter obtain-
ing a DC signal with information regarding to In the A-Stable mode the 555-Timer Capacitor
the status of the measured magnitude. C3 starts its charge through the resistors R1
and R2 . The charge-discharge equation of a
capacitor is given by:
5 Circuit Design  
t
As a required supply of Vcc = 6V was required Vc = V∞ − (V∞ − V0 ) · Exp − (8)
RC
the first step was to configure the power-lines
in Proteus. Then using the software electronic The capacitor C3 during its charge alternates
components library each single stage of the cir- between V∞ /3 and 2V∞ /3, being Vcc = V∞ the
cuit was build and tested separately in order to supplied tension . Therefore by equation 8:
guarantee its correct functionality.

Vch = Vcc − 2Vcc /3 · Exp − t1 /(R1 + R2 )C3
5.1 Signal Source t1 = (R1 + R2 )C3 Ln(2)
(9)
The first stage of the circuit is the Signal
Generation (Source). It is composed by a During its discharge time the capacitor C3
555-timer and a 4013 Quadrature divider alternates between 2Vcc /3 and Vcc /3, being
in order to generate an AC square-wave signal V∞ = 0 the supplied tension and discharges
with frequency equal to 1700Hz and amplitude only through R1 . Therefore again by Equation

4
8:


Vdis = 2Vcc /3 · Exp − t2 /R1 C3
(10)
t2 = R1 C3 Ln(2)
As the total period of the ’charge-discharge’
cycle is equal to the inverse of the required fre-
quency (1700Hz) the value of the resistor R2
was found as:
T = t2 + t1 = (2 · R1 + R2 )C3 Ln(2) = 1/f
R2 = 1/(C3 · f · Ln(2)) − 2R1 = 82.864kΩ
R2 = 82kΩ
(11)
Choosing the value of 82kΩ in order to use one Figure 6: 4013 Quadrature Divider’s Circuit
standard resistor and because the frequency (Proteus)
output using R = 82kΩ was closer to 1700Hz.
The instrument input in this case is repre-
The designed circuit for the 555-Timer was sented by the resistor R5 whose range must be
made by selecting the following components between 0 and 0.22Ω. The outputs V1 and V2
from the Proteus component library: from this stage have both a mean value of 3V
and also a 180o phase shift. Theoretically the
• 555-Timer tension in the middle of the resistor R5 is equal
• Resistor (Generic) x2. to 3V. Therefore a 3-resistors tension divider
can be written as:
• Capacitor (Generic) x2.
Vcc R5
While the schematics for the connection are ∆V = · (12)
R3 + R4 + R5 2
shown in Figure 4.

Figure 5: Output from the 555-Timer

The signal output is shown in Figure 5.
This is a DC continuous square pulse with
amplitude 6V and frequency 1700Hz. An AC
Square-wave signal is required, therefore an
4013-Quadrature Divider was connected in
cascade using as the input the output from
the 555-timer’s pin 3. The circuit for the
Quadrature Divider is shown in Figure 6. Figure 7: 4013 Quadrature Divider’s outputs V1
and V2 their differences is 2∆V

5
With Vcc = 6V the value of ∆V is then
defined for any given value of R5 . As
R5 << R3 + R4 it can be neglected in the
denominator of equation 12. In practice there
is also a tension drop inside the quadrature
divider so the effective value for Vcc is ap-
proximately 5.5V. Equation 12 represents
the modulated version of R5 as this resistor
change is the measured value and therefore
it is equivalent to V (t) from 4.1 Modulation.

Selecting R5 = R5max = 0.22 for design pur-

poses, the value ∆V is determined by:

∆V = 5.5/(R3 + R4 ) · R5 /2
(13)
∆V = 5.5/(R3 + R4 ) · R5 /2 = 275µV Figure 8: Input Stage (Proteus)

In consequence the outputs from pins V1 Although the amplification can be done by
and V2 are equal to 3 ± ∆V valid for any value using only one Operational Amplifier in either
of ∆V . As the maximum values are required inverting/non-inverting configuration it is not
for design and because ∆V grows with R5 recommended as it is possible to saturate the
the value of ∆V = 275µV was chosen as the OP-amp and lose some of the information.
design value. Another problem is that any common mode
noise in the input signal is also amplified.
The proves V0 , V90 , V180 and V270 are dif- Therefore an Instrumentation Amplifier is
ferent values of the carrier signal that can be required.
used as reference for the signal demodulation
(see 4.3 Analogue Switch). An Instrumentation Amplifier is a circuit
The outputs from these stages (V1 , V2 ) are composed by three operational amplifiers in
shown in Figure 7. two amplification stages as shown in Figures
In the design case V1 = 3 + ∆V and 8 & 9.
V2 = 3 − ∆V but simulations shown a slightly
difference form the ideal case. The Instrumentation Amplifier has the
advantage to not load the input signal due to
In order to design this circuit some compo- its high impedance and also does not affect the
nents were selected from the Proteus compo- output signal due to its high common-mode
nent library: rejection rate. It is able to amplify the
differential mode input without amplifying
• 4013 Flip Flop x2 the common mode input.

• Resistor (Generic) x2. In the designed circuit the Instrumentation

The schematics for the connection are shown
in Figure 6.
5.2 Instrumentation Amplifier
As the signal output from the previous stage is
in the OM(µV ) it has to be amplified in order
obtain a nice DC output with the measured
information in a later stage without losing it.
amplifier is divided in two sections: The input
stage (Figure 8), in which the inputs are V1
and V2 modulated from the ’Signal Source
Circuit’ and with outputs Vo1 and Vo2 ,and the
output stage (Figure 9), with inputs Vo1 and
Vo2 and an output VRF . In between both of
them there is a two-pole change over switch
to compute the phase sensitive demodulation
(See: 4.3 Analogue Switch).

6
 By superposition, grounding V2 and connect-
ing V1 the ouputs from the pins VA0 and VB0 are
equal to:
VA0 = (1 + R10 /R9 ) · V1
(14) The connection scheme is again shown in
VB0 = −R10 /R9 · V1
Similarly, by grounding V1 and connecting
V2 , the outputs from VA00 and VB00 are:
VA00 = −R10 /R9 · V2
(15) a Analogue Switch with unit gain. The task
VB00 = (1 + R10 /R9 ) · V2
Then as VA = VA0 + VA00 and VB = VB0 + VB00 ,
from witch the gain for VA − VB is equal to:
VA = (1 + R10 /R9 ) · V1 − R10 /R9 · V2
(16)
VB = (1 + R12 /R9 ) · V2 − R12 /R9 · V1
The output from this stage is given by:
Vo1 − Vo2 = (1 + 2R10 /R9 ) · 2∆V
(17) are single supplied, the information related
GIA1 = (1 + 2R10 /R9 )
The components required in this stage were:
• MC33172P Operational Amplifier x2
• Resistor (Generic) x7
• Capacitor (Generic) x2
The connection scheme is shown in Figure 8.
• MC33172P Operational Amplifier x1
• Resistor (Generic) x4
• Capacitor (Generic) x4
Figure 9.
In between those stages, as said before, the
Phase Sensitive Demodulation occurs through
was to determine a value for R9 . VRF for R5 =
0.22 had to be set at 1.5V (from ground) or
4.5V from Virtual Earth as a design constrain.
VRF = GIA1 · GIA2 · 2∆V + VV G
(20)
R9 = 73.6Ω
Given V1 = Vcom + ∆V and V2 = Vcom − ∆V
notice how the common mode input is lost
after this stage. As the Operational Amplifiers
to the negative semi-cycle of this difference is
going to be lost. Therefore the signal reference
must be lifted by Vcom = 3V therefore VV G
must be equal to Vcom to compensate the loss
of the common mode input and being this
one of the reasons of why a Virtual Earth
(VV G = 3V See 4.5 Virtual Earth) was
necessary.

5.3 Analogue Switch

The phase sensitive demodulation occurs in
this step. It is a 2-pole change-over switch
that also has the task of rectifying the output
from the first stage of the Instrumentation
Amplifier. It acts as a multiplier.

The 4053 is a CMOS Analog Switch that

Figure 9: Output Stage (Proteus)
The gain from this section is given by:
GIA2 = R22 /R21 = 10
Therefore:
VRF = (1 + 2R10 /R9 )(R22 /R21 ) · 2∆V + VV G differential amplifier by limiting its bandwidth
And the components required to build it:
contains three single-pole change-over switches
that are pairs of transmission gates operating
simultaneously. In this design two out of three
gates are being used. They operate on sig-
nals of opposite polarity. However the switch is
(18)
not perfect and some spikes are going to pass
through it. Those spikes are common mode
and most of them can be rejected through the
(19) with the capacitors C9 and C10 from Figure
10.

7
 5.4 Virtual Earth

As the circuit is using MC33172P Single Sup-

Figure 10: Analogue Switch (Proteus)
The reference signal for demodulation come
from the proves V0 to V270 of the Quadrature
Divider (see 4.1 Signal Source). The results
of connecting different phase angle reference
signals are shown in Figure 11.
ply Operational Amplifiers with theoretical
saturation limits of Vsatmax = 6V and Vsatmin =
0V the signal output from the Instrumentation
Amplifier second stag is going to be clamped
due to the output from the first stage being an
AC-squared wave centered at 0V hence losing
the information of each negative half-cycle due
to saturation. In simulations the upper and
lower saturation limits were around 5.2V and
0.2V respectively.

Figure 12: Saturation Curve of an Operational

Amplifier (Texas Instruments, Application Report
SBOA092B, p29)

Adding the virtual earth to lift the signal of

the Op-Amps increases the accuracy of the in-
strument by guaranteeing that the Op-Amps
Figure 11: Influence of the phase angle for the work in their linear zone (no-saturation) and
study case. as long as (from ground):

The Analogue switch has the task of rectifying

the signal. Notice how for a phase angle
φ of 0o and 180o the output signal (after VRF = GIA1 · GIA2 · 2∆V ≤ VV G (21)
amplification) looks almost rectified except for
a few spikes and its average value is almost
DC. The signal needs to be further filtered to The signal output cannot be driven negative.
get the desired smooth DC output.
The circuit used for Virtual Earth is shown
The components required in this stage were: in Figure 13, it is mainly composed by a high-
value resistors voltage divider to obtain the re-
• 4053 Two-Pole Change-Over Switch x1
quired constant tension and a unit gain buffer.
• Resistor (Generic) x3 It also have two 1µ electrolytic capacitors in
order to have a stable output when working
The connection scheme is shown in Figure 10. with high frequencies.

8
 Figure 14: Salen Key Equal Value LP-Filter
Figure 13: Virtual Earth (Proteus) (Proteus)

For a Sallen-Key Filter LP-Filter the filter

From the system point of view after the cut-off frequency is given by:
implementation of Virtual Earth, the system p
works on a +3V 0 -3V logic level values, F 0 = 1/(2π · R23 R24 C11 C12 ) (22)
corresponding to +6V +3V 0V power val- And as R24 = R23 , C12 = C11 .
ues. Therefore the OP-Amp can be seen
as split supply amplifiers sourced by +3V F0 = 1/(2π · R23 C11 ) (23)
and -3V. In consequence the saturation
tensions from a system logic point of view The quality factor of the filter Q is given by:
are going to be Vsmax = 5.2 − 3 = 2.2V and 1
Vsmin = 0.2 − 3 = −2.8V . Q= = 0.578 (24)
3 − GF

The components required in this stage With GF = 1.27 the filter’s gain.
were:
In particular for this design the filter cut-off
frequency was chosen to be F0 = 10Hz. There-
• MC33172P Operational Amplifier x1
fore as C11 = 0.1µF the value of the resistor
R23 is determined as:
• Resistor (Generic) x3
F0 = 1/(2πR23 C11 ) = 10Hz
• Capacitor (Generic) x2 (25)
R23 = 159kΩ
• Capacitor (Electrolytic) x2

And the connection scheme is shown in Figure

13.

5.5 LP-Filter
From Figure 11 the output VRF from the
Instrumentation Amplifier + Analogue Switch
is almost DC but has some spikes. In order
to remove those spikes and obtain a smooth
DC averaged signal output the rectified signal
from the previous stage VRF had to be passed
through a Sallen-Key Equal Value Low-Pass
Filter. Figure 15: Filtered output for different values of
φ

9
From Figure 15 notice how the filter removes Figure 16: Voltage Controlled Oscillator (Pro-
all the spikes from VRF (Figure 11) averages teus)
and amplifies its value by GF as time grows.
The transistor Q1 can be seen ideally as a
For φ = 0 and φ = 180 the filtered signal
switch. When Q1 is open, i.e. when the ouput
final VDC ≈ 4.75 value still has some energy
from U7:B is negative the capacitor C13 starts
content. However for φ = 90 and φ = 270 the
charging at constant current I1 = VF /R31 .
filter averages to ’earth’ at a value of VV G , or
a system ’zero’.
At every moment ideally the positive input
to U7:A is hold at VF /2 due to the voltage
In theory the filter amplifies the signal by
divider between R32 and R33 , therefore the
GF respect to ’earth’. Therefore:
negative input is also at VF /2 and the current
VF = GF · VRF + VV G (26) flow R31 is equal to I = VF /R31 .

For R5 = 0.22 it drives to VF = 4.91V . When Q1 is closed, i.e. when the output
from U7:B is positive R34 is grounded and a
For the filter, the required components were: current flow I2 = VF /R34 flows through R34 .

• MC33172P Operational Amplifier x1 As R31 = 2 · R34 when Q1 is closed the

• Resistor (Generic) x4
• Capacitor (Generic) x2
And the circuit configuration is shown in Fig- the inverting amplifier configuration of U7:B
ure 14.
5.6 VCO
At this point the signal was filtered and fully
conditioned and just the frequency conversion
is missing.
When the measured resistance was in the
range [0, 0.22Ω] it indicates through a sound
that there is a fault. Therefore the DC signal
from the filter VF had to be converted again
into AC signal with a frequency between 20-
20kHZ (human hearing frequency range). The
conditioning circuit for this part was a Volt-
age Controlled Oscillator (VCO) as shown in
Figure 16.
current flow I2 = 2 · I1 . This means that C13 is
discharging a constant current flow equal to I1 .
The output tension to the buzzer is given by
with a tension input equal to the instantaneous
tension of the capacitor C13 . Therefore:
VBU ZZ = (1 + R36 /R35 )VC1 3
(27)
VC1 3 = (R36 /(R35 + R36 )) · VBU ZZ
At this point, due to saturation of U7:B the
values of VBU ZZ are oscillating between 0.2 and
5.2V , from ground, but from the system point
of view −2.8V to 2.2V . Hence (with R36 =
47kΩ and R35 = 100kΩ):
VC1 3min = −900mV
VC1 3max = 703mV
The charge/discharge rate for the capacitor
in an integrator circuit is given by:
dVc I
= (28)
dt C
And being T the period of the charge-
discharge, an integration during a semi-cycle
(T /2) of Vc results in:
I T
∆(Vc ) = · (29)
C 2
Where the value of ∆(Vc ) = ±1.603mV during
the charge/discharge time.

10
 5.7 Buzzer/Mute
The final elements of the Micro-Ohmmeter
were the sounding element (Buzzer) and a con-
trol element for when R5 were out of the work-
ing range [0, 0.22Ω].

Figure 17: Charge-discharge cycle in the inte-

Figure 19: Mute (Proteus)
grating circuit.
For the Mute element a resistor R27 was
Setting by setting f = 1/T to any value in the unknown. However a design constrain was
range 20-20kHz the value of the capacitor C13 that the Buzzer should not receive any signal
is determined as: when R5 > 0.22Ω, i.e. VF > 4.75V (as VF
grows with R5 ). The mute circuit is basically
I1
C= (30) a comparator. Its task is to bypass the signal
2∆(Vc )f going to the transistor in the VCO when the
circuit is out of the measurement range.
Choosing a frequency of 4000Hz gives
C13 = 292.42pF . With VF = 1.75V from As a reference signal of V+ = 4.75V is re-
ground (+3V ). This VCO was designed alone quired to compare at any moment with VF in
using the single input OP-Amp but using a order to mute the buzzer when R5 > 0.22Ω.
dual supply to simulate the effects of virtual V+ is given by the voltage divider compressed
ground. by R27 and R28 :
V+ = R27 /(R27 + R28 ) · Vcc = 4.75V (31)
With Vcc = 6V the tension from a power sup-
ply. Therefore the value for R27 = 38kΩ was
found.
However an higher value of R27 = 40kΩ was
selected to add some tolerance to the circuit
and to guarantee it measured correctly the
The connections are shown in Figure 19
and the required components were:
• MC33172P Operational Amplifier x1
• Resistor (Generic) x 4
• Diode (Generic) x1

Figure 18: Output Signal VBU ZZ with frequency

4000Hz.

The output from Vc and VBU ZZ are shown in

Figure 17 and Figure 18 respectively. Figure 20: Buzzer (Proteus)

11
The buzzer elements is just shown as there The circuit model equations are given by:
were no calculations related to it, but its con- 2 · GA1 · GA2 · Vcc0
nections are shown in Figure 20 and the re- VRF = · R5 + VV G (32)
R4 + R3
quired components were:
• Buzzer x1 2 · GF · GA1 · GA2 · Vcc0
VF = · R5 + VV G (33)
• Resistor (Generic) x 1 R4 + R3

It was connected to the output from the VCO. VF − VV G

f= (34)
2∆(Vc )C
The coefficients for equations 32, 33 and 34
are shown in table 3.
0
GA1 GA2 GF Vcc
214.74 10 1.27 5.5V
R3 /4 C13 R32 VVG
1.1kΩ 282pF 100kΩ 3V
Figure 21: VBU ZZ Frequency Table 3: Constant coefficients for the circuit
mathematical model.
The obtained frequency was 4005Hz as seen
in Figure 21. An evaluation of the circuit model equation for
the same values of R5 is shown in table 5.
6 Results R5 [Ω] VRF [V ] VF [V ] f [Hz]
0 3 3 0
A summary of the components values found for 0.0275 3.19 3.24 500
the design task is show in table 1: 0.055 3.38 3.48 1000
R2 82kΩ 0.0825 3.56 3.71 1500
R9 73.6Ω 0.11 3.75 3.95 2000
R23 159kΩ 0.1375 3.94 4.19 2500
R24 159kΩ 0.165 4.13 4.43 3000
C13 282pF 0.1925 4.31 4.67 3500
R27 40kΩ 0.22 4.5 4.91 4000
Table 4: Theoretical Results for four different
Table 1: Summary of the required circuit com-
values of R5
ponents.

A comparison graph between the theoretical

The circuit was tested for diverse values of
values and the simulation for VRF , VF and f
R5 the results for those simulations are shown
are shown in Figures 22-24.
in table 2.
R5 [Ω] VRF [V ] VF [V ] f [Hz]
0 3 3 0
0.0275 3.18 3.22 541
0.055 3.36 3.44 1075
0.0825 3.54 3.66 1595
0.11 3.72 3.88 2100
0.1375 3.90 4.09 2595
0.165 4.08 4.31 3080
0.1925 4.26 4.53 3553
0.22 4.44 4.75 4005
Table 2: Simulation Results
Figure 22: VRF Theory vs Simulation

12
 And plot of those errors is shown in Figure
25.

Figure 23: VF Theory vs Simulation

As expected the simulation results show a lin-

ear dependency with R5 for both VRF and VF . Figure 25: VBU ZZ Frequency

Notice how the error for both VRF and VF

tend to increase with R5 in the measurement
range while for the frequency this error instead
decreases. The reason behind this discrepancy
lies perhaps in numerical approximation errors
or in the fact that the circuit was designed for
R5 = 0.22Ω and therefore it tends to do a bet-
ter voltage-frequency conversion the closer R5
to 0.22Ω.

7 Conclusions
Figure 24: f Theory vs Simulation

In the other hand the results from frequency A computational simulation of a Micro-
the simulation show a lesser linearity in Ohmmeter
was realized through the software
comparison to the theoretical model. Proteus 8 and it showed a good compro-
R

mise with the theoretical model for a Lock-In

The relative error between theory and simu- Amplifier.
lation is given by:
The Operating Principle of a Lock-In
|Xth − Xsim | Amplifier (Phase Sensitive Detection) was
%errorX = · 100 (35)
Xth demonstrated analytically and verified through
simulations.
R5 [Ω] %errorVRF %errorVF %errorf
0 0 0 0 Simulation results were in accordance with
0.0275 0.31 0.62 8.2 the mathematical model for each stage of the
0.055 0.59 1.15 7.5 circuit.
0.0825 0.56 1.35 6.33
0.11 0.80 1.77 5.00 Proteus R
8 tends to be unstable for big
0.1375 1.02 2.39 3.40 circuits simulations.
0.165 1.21 2.71 2.67
0.1925 1.16 3.00 1.51
0.22 1.33 3.26 0.13
Table 5: Theoretical Results

13
8 References
1. Texas Instruments (2016), Handbook of
Operational Amplifier Operations. Appli-
cation Report SBOA092B, pp.29.

2. Intersil (2009) Instrumentation Amplifier

Application Note AN1298.2”, pp.2-6.

3. PerkinElmer Instruments (2000), What is

a Lock-In Amplifier? Technical Note TN
1000, pp.1-4.

4. Standford Research Systems (1999) About

Lock In Amplifiers, Data Sheet, pp.1-2.

5. Maxim Integrated (2013) Application

Note 5299, Selecting the Right CMOS
Analog Switch, pp.1-3.

14