Paper Title
Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance
Authors
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao
Abstract
Data compression is one of the major fields of research in the present world. In this regard image compression is also having its own significance, so many algorithms for DFT, DCT, DWT, etc. have been developed and among them DWT is most likely used there are two plans are existing for generating 2-DWT and are lifting and flipping plans. The above two plans architecture are having its own fixed scaling constants, multipliers and adders. In my project work I am proposing a lifting plan and flipping plan such that the modification is done in its internal architecture of S.M.B.Multiplier and radix-4 booth multiplier with replacing adder in it with spanning tree parallel prefix adder. This modification has improved Power Delay Product (PDP) by 7% in lifting plan and 5% in flipping plan.
Keywords
Lifting and Flipping , Discrete Wavelet Transform, Spanning Tree Adder
Citation/Export
MLA
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao, “Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance”, November 17 Volume 3 Issue 11 , International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 578 – 582
APA
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao, November 17 Volume 3 Issue 11, “Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance”, International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 578 – 582

© All Rights Reserved

2 visualizações

Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance.

Paper Title
Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance
Authors
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao
Abstract
Data compression is one of the major fields of research in the present world. In this regard image compression is also having its own significance, so many algorithms for DFT, DCT, DWT, etc. have been developed and among them DWT is most likely used there are two plans are existing for generating 2-DWT and are lifting and flipping plans. The above two plans architecture are having its own fixed scaling constants, multipliers and adders. In my project work I am proposing a lifting plan and flipping plan such that the modification is done in its internal architecture of S.M.B.Multiplier and radix-4 booth multiplier with replacing adder in it with spanning tree parallel prefix adder. This modification has improved Power Delay Product (PDP) by 7% in lifting plan and 5% in flipping plan.
Keywords
Lifting and Flipping , Discrete Wavelet Transform, Spanning Tree Adder
Citation/Export
MLA
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao, “Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance”, November 17 Volume 3 Issue 11 , International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 578 – 582
APA
G. Ashok Jeevan, Y. V. A. Prasad, Dr. B. Subrahmanyeswara Rao, November 17 Volume 3 Issue 11, “Implementation of Modified Lifting and Flipping Plans in D.W.T Architecture for Better Performance”, International Journal on Future Revolution in Computer Science & Communication Engineering (IJFRSCE), PP: 578 – 582

© All Rights Reserved

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_______________________________________________________________________________________________

for Better Performance

1

Student, M.Tech , VLSISD,Dept. of ECE, Swarnandhra College of Engg. &Tec, twentycraze@gmail.com

2

Associate Professor, Dept. of ECE Swarnandhra College of Engg. &Tec, yaralagaddavap@gmail.com

2

Professor, Dept. of ECE, Swarnandhra College of Engg. &Tec, boyina-a@yahoo.com

ABSTRACT: Data compression is one of the major fields of research in the present world. In this regard image compression is also having its

own significance, so many algorithms for DFT, DCT, DWT, etc. have been developed and among them DWT is most likely used there are two

plans are existing for generating 2-DWT and are lifting and flipping plans. The above two plans architecture are having its own fixed scaling

constants, multipliers and adders. In my project work I am proposing a lifting plan and flipping plan such that the modification is done in its

internal architecture of S.M.B.Multiplier and radix-4 booth multiplier with replacing adder in it with spanning tree parallel prefix adder. This

modification has improved Power Delay Product (PDP) by 7% in lifting plan and 5% in flipping plan.

Keywords: Lifting and Flipping , Discrete Wavelet Transform, Spanning Tree Adder

__________________________________________________*****_________________________________________________

𝑢𝑙’ (𝑛) = 𝑠2(𝑛) + 𝛿(𝑢ℎ(𝑛) + 𝑢ℎ(𝑛 − 1)) (1d)

I. INTRODUCTION

𝑢ℎ(𝑛) = 1/k 𝑢ℎ’ (𝑛) (1e)

Discrete wavelet transform (DWT) is famously utilized as a 𝑢𝑙(𝑛) = 𝐾.𝑢𝑙(𝑛) (1f)

part of speech and picture compression [1]. There are two

principle computational plans for the DWT calculation, to be Where x (n) is the input sequence, u1(n ) and uℎ(n ), are

specific the lifting plan [1], and the convolution-based plans. respectively the low-pass and the high-pass components of

The lifting plan is prevalently utilized since it includes 1-level DWT. α, β, γ, δ are the lifting constants for 9/7 bi-

altogether less number of augmentations than convolution- orthogonal wavelet filter. K and K-1 are respectively, the

based plans Flipping plan is an altered variant of lifting plans scale normalization constants of the low-pass and the high-

which is all the more prevalently utilized because of its lower pass lifting DWT coefficients. Interestingly, scaling

basic way [2]. The match of scaling constants of lifting plans constants K and K−1 are perfect inverse of each other. This is

are ideal converse of each other while those of flipping plans an important feature of lifting scheme which could be

are not ideal opposite of each other. In spite of this exploited to save several multipliers in a 2-D DWT

component, lifting plans isn't prominent like the flipping structure.

plans because of its more drawn out basic way. In this paper,

we introduce basic way examination of lifting and flipping Based on the flipping plan coefficients of 9/7 wavelet filter

plans and propose a plan to diminish the basic way of lifting can be computed as

structure. Likewise we propose productive pipeline models

for the usage of the DWT in view of lifting and additionally 𝑟1(𝑛)=1/𝛼𝑥(2𝑛−1)+𝑥(2𝑛)+𝑥(2𝑛−2) (2a)

flipping plans. Since, the lifting plans offers sparing of a few 𝑟2(𝑛)=1/𝛼𝛽𝑥(2𝑛)+𝑟1(𝑛)+𝑟1(𝑛−1) (2b)

multipliers when scaling operations are coordinated and 𝑢ℎ’ (𝑛)=1/𝛽𝛾𝑟1(𝑛)+𝑟2(𝑛)+𝑟2(𝑛−1) (2c)

performed in one stage, and it has possibly higher CPD than 𝑢𝑙’ (𝑛)=1/𝛾𝛿𝑟2(𝑛)+𝑢ℎ’ (𝑛)+𝑢ℎ’ (𝑛−1) (2d)

the flipping structure, lifting plan gives a superior region 𝑢ℎ(𝑛)=𝛼/𝛽𝛾𝐾𝑢ℎ’ (𝑛) (2e)

defer effective structure than flipping structure. 𝑢𝑙(𝑛) = 𝐾𝛼𝛽𝛾𝛿𝑢𝑙’ (𝑛) (2f)

II. EFFICIENT DATA-PATH FOR DWT where, 1/𝛼, 1/( αβ ), 1/( αβγ ), and 1/( αβγδ) are the flipping

COMPUTATION BY LIFTING AND FLIPPING PLAN constants of 9/7 bi-orthogonal wavelet filter. (kαβγ ) and

A. Lifting and Flipping plans for 1-D DWT ((αβγ )/k) are respectively, the scale normalization constants

The coefficients of 9/7 bi orthogonal wavelet filter can be of the low-pass and the high-pass flipping DWT. Note that

computed by the lifting scheme as the scaling constants of flipping DWT are not perfect

𝑠1(𝑛) = 𝑥(2𝑛 − 1) + 𝛼(𝑥(2𝑛) + 𝑥(2𝑛 − 2)) (1a) inverse of each other {i.e., determined a productive pipeline

𝑠2(𝑛) = 𝑥(2𝑛) + 𝛽(𝑠1(𝑛) + 𝑠1(𝑛 − 1)) (1b) structure utilizing (1) for the calculation of 1-level lifting

𝑢ℎ’ (𝑛) = 𝑠1(𝑛) + 𝛾(𝑠2(𝑛) + 𝑠2(𝑛 − 1)) (1c) DWT. The structure is appeared in Fi(kαβγδ ) × (αβγ /k) ≠1}

not at all like those of the lifting DWT. We have g.1(a). The

578

IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 578 – 582

_______________________________________________________________________________________________

internal structure of each lifting cell (LC) is appeared in Similarly, the scale normalization of row-wise and column-

Fig.1(b) and the lifting scaling unit (LSU) is appeared in wise computation of flipping 2-D DWT are integrated and

Fig.1(c).The proposed lifting DWT structure includes 6 performed at the end of column-wise DWT computation

multipliers, 8 adders and 12 registers, and it computes two using the following equation

DWT parts in each cycle. The length of cycle period is T=

TM+ 2TA where TM and TA are the time required for 𝑎(𝑚,𝑛)=𝐾2𝛼2𝛽2𝛾2𝛿2𝑎’ (𝑚,𝑛) (4a)

multiplication and an addition 𝑏(𝑚,𝑛)= 𝛼2𝛽2𝛾2𝛿𝑏’ (𝑚,𝑛) (4b)

𝑐(𝑚,𝑛)= 𝛼2𝛽2𝛾2𝛿𝑐’ (𝑚,𝑛) (4c)

𝑑(𝑚, 𝑛) = 𝐾−2 𝛼2𝛽2𝛾2𝑑’ (𝑚, 𝑛) (4d)

of 2-D DWT are with the identical except of the integrated

scaling operation given in (3) and (4). Out of four sub-band

parts, two sub-band segments [low-low { a(m ,n )} and

Fig. 1. (a) Pipeline structure of lifting 1-D DWT. (b) Internal

high-high {b ( m, n)}] just need scaling operation in lifting

structure of lifting cell (LC).(c)Internal structure lifting scaling unit 2-D DWT whereas in case of flipping 2-D DWT all the four

(LSU) subali-band segments should be scaled. Consequently, the

scaling unit of flipping 2-D DWT includes two more

multipliers over the lifting 2-D DWT structure with a

specific end goal to process all the four sub-band parts in

parallel. To show this we have considered the square based

lifting 2-D DWT structure of [6] for piece estimate p= 4. A

flipping-based 2-D DWT structure is acquired from the

lifting 2-D DWT structure by supplanting all the LCs with

FC and the scaling unit by FSU (appeared in Fig2(c)). As

appeared in Fig.3(a) and Fig.3(b), the SU of lifting 2-D

Fig. 2. (a)Pipeline structure of flipping 1-D DWT. (b) Internal DWT structure includes 2 multipliers for square size 4 while

structure of flipping cell (FC). the SU of flipping 2-D DWT structure includes 4

multipliers. By and large, a piece based lifting 2-D DWT

The proposed pipeline structure for the calculation of 1-

structure includes p/2 less multipliers than those of flipping-

level flipping DWT is appeared in Fig.2(a). The inner

based structure for block-size p. This offers a significant

structure of each flipping cell (FC) is appeared in Fig.2(b)

saving of area when the structure is implemented for large

and the flipping scaling unit (FSU) is appeared in Fig.2(b).

block size.

The proposed flipping DWT structure includes 6 multipliers,

8 adders and 12 registers. It ascertains two DWT segments III. CRITICAL-PATH ESTIMATE OF LIFTING AND

in each clock cycle. The span of cycle period T= T M+ TA . FLIPPINGCELLS FOR THE COMPUTATION OF 2-D

The lifting and flipping based structures of 1-D DWT have a DWT

similar equipment unpredictability, however the flipping- We have considered radix-4 Booth algorithm for the

based structure has less CPD than the lifting-based structure multiplications. The Booth-multiplier has three units, (i)

Booth encoder (BE), (ii) partial product generator (PPG) and

B. Integrated Scaling for Lifting and Flipping 2-D DWT

(iii) adder unit (AU). The AU uses carry-save data-path to

Utilizing distinct approach, row-wise and column-wise

compress the partial products. The delay of AU is 𝑇𝐴𝑈 =

computation of 1-D DWT are performed on the input data

𝑇𝐴+(𝑞 −2)𝑇𝐹 𝐴, where 𝑞 = 𝑤/2 and 𝑇𝐹 𝐴 is the FA delay and

matrix to acquire four coefficients l matrices of 2-D DWT in

𝑇𝐴 is thedelayof2𝑤-bit final ripple carry adder (RCA). The

particular low-low (A), low-high (B), high-low (C), and

data-path of flipping cell (using radix-4 Booth multiplier is

high-high (D). The scale normalization of row-wise and

shown in Fig.4(a)). The critical-path delay of FC is 𝑇𝐹 𝐶 =

column-wise lifting 2-D DWT can be integrated and

performed toward the finish of the stage-2 utilizing the 𝑇𝐵𝐸 +𝑇𝑃+𝑇𝐴+(𝑞 − 1)𝐹 𝐴, where 𝑇𝐵𝐸, 𝑇𝑃 are, respectively the

accompanying condition delay of BE and PPG units. The data-path of lifting cell

𝑎(𝑚,𝑛)=𝐾2𝑎’ (𝑚,𝑛) (3a) using radix-4 Booth multiplier is shown in Fig.4(b). In order

𝑏(𝑚,𝑛)=𝑏’ (𝑚,𝑛) (3b) to perform an addition operation prior to the multiplication

operation, we have followed the

𝑐(𝑚,𝑛)=𝑐’ (𝑚,𝑛) (3c)

𝑑(𝑚, 𝑛) = 𝐾−2𝑑’ (𝑚, 𝑛) (3d)

579

IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 578 – 582

_______________________________________________________________________________________________

V. PROPOSED ARCHITECTURE LIFTING PLAN:

(b) Parallel structure of flipping 2-D DWT for block-size TABLE I

multiplier. (b)Existing Data-path of lifting-cell using radix-4 Booth

multiplier well as the existing lifting and flipping 1-D DWT

structures for comparison since they have the same hardware and

the same time complexity.

have the same adder and memory complexity for a given

block-size; however they have different multiplier and

register complexity. The proposed flipping-based 2-D DWT

structure includes 2 less CPD than the proposed lifting-

based structure, yet it includes/2 a more number of

multipliers and registers than the lifting-based structure for a

block size. Since, 2 is small compared with , and the

multiplier and register saving in lifting-based structure is

significant, ADP of lifting structure is expected to be less

than the flipping-based structure for higher block-sizes .The

structure of [5] is the best amongst the existing flipping

based structures while the structure of [6] is the best

amongst.

580

IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 578 – 582

_______________________________________________________________________________________________

High Speed Spanning Adder:- This project presents a flipping plan using booth encoder

which consists of high speed spanning tree adder in the

adder blocks. It is simulated by using Xilinx ISE tool and

results are verified by using Modelsim SE 6.3f .

Experimental results showed that P.D.P. is reduced in the

proposed method compare to existing method

LUTS,CRITICALDELAY,GATECOUNT,POWER

speed of the digital processor depends heavily on the speed

of the adders used is the system. Also, it serves as a building

block for synthesis of all other arithmetic operations. Adders

are most commonly used in various electronic applications

e.g. Digital signal processing in which adders are used to

perform various algorithms like FIR, IIR etc. In past, the

major challenge for VLSI designer is to reduce area of chip

by using efficient optimization techniques. Then the next

phase is to increase the speed of operation to achieve fast

calculations like, in today’s microprocessors millions of

instructions are performed per second. Speed of operation is

one of the major constraints in designing DSP processors.

The redundancy associated with signed-digit numbers offers

the possibility of carry free addition. The redundancy

provided in signed-digit representation allows for fast

addition and subtraction because the sum or difference digit

is a function of only the digits in two adjacent digit positions

of the operands for a radix greater than 2, and 3 adjacent

digit positions for a radix of 2. Thus, the add time for two

redundant signed-digit numbers is a constant independent of

the word length of the operands, which is the key to high

speed computation. Quaternary half adders are designed

using binary logic gates and radix converters. This design is

appropriate to be applied for construction of a high

performance adder like spanning tree which consists of

many full adder components and this can be reduced by

using quaternary full adders in place of normal full adders.

VII. RESULTS

S.No B.E P.BE SMB P SMB

1. Gate count 1113 1185 1236 1314

LUTs

3. Critical 31.524 30.142 32.877 31.495

Delay(ns)

4. Estimated 595 575 1145 1128

power

581

IJFRCSCE | November 2017, Available @ http://www.ijfrcsce.org

_______________________________________________________________________________________

International Journal on Future Revolution in Computer Science & Communication Engineering ISSN: 2454-4248

Volume: 3 Issue: 11 578 – 582

_______________________________________________________________________________________________

Fig-9: Comparison of SMBE AND MODIFIED SMBE VII. Conclusion

LUTS,CRITICALDELAY,GATECOUNT,POWER This project presents a flipping plan using booth encoder

which consists of high speed spanning tree adder in the

adder blocks. It is simulated by using Xilinx ISE tool and

results are verified by using Modelsim SE 6.3f .

Experimental results showed that P.D.P is 5% reduced in the

proposed method compare to existing method.

This project presents a Lifting plan using sum to booth

encoder which consists of high speed spanning tree adder in

the adder blocks. It is simulated by using Xilinx ISE tool

and results are verified by using Modelsim SE 6.3f .

Experimental results showed that P.D.P is 7%reduced in the

proposed method compare to existing method.

REFERENCES

[1] Daubechies and W. Sweldens, Factoring wavelet change

into lifting steps, Journal of Fourier Analysis and

Applications, vol. 4, no. 3, pp. 245– 267, Mar. 1998.

[2] C.- T. Huang, P.- C. Tseng, and L.- G. Chen, Flipping

structure: An effective VLSI engineering for lifting-based

discrete wavelet change, IEEE Trans. Flag Process., vol.

52, no. 4, pp. 10801089, Apr. 2004.

[3] G. Shi, W. Liu, and L. Zhang, An effective collapsed

design for lifting based discrete wavelet change, IEEE

Transaction on Circuit and System-II, Express Brief, vol.

56, no. 4, pp. 290– 294, Apr. 2009.

[4] Y.- K. Lai, L.- F..Chen and Y.- C.Shih, "An elite and

memory-effective VLSI engineering with parallel

examining technique for 2-D lifting-based discrete wavelet

change," IEEE Trans. on Consumer Electronics, vol. 55,

no. 2, pp. 400-407, May. 2009.

[5] W. Zhang, Z. Jiang, Z. Gao, and Y. Liu, "An effective

VLSI design for lifting-based discrete wavelet change",

IEEE Transaction on Circuit and System-II, Express Brief,

vol.59, no.3, pp.158– 162, Mar. 2012.

[6] B. K. Mohanty, A. Mohajan, and P. K. Meher, "Region

control effective high-throughput usage of lifting 2-D

DWT", IEEE Transaction on Circuit and System-II,

Express Brief, vol.59, no.7, pp.434– 438, July 2012.

[7] A. Darji, S. Agrawal, A. Oza, V. Sinha, A. Verma, S. N.

Shipper, and A.N. Chandorkar, "Dua-examine parallle

flipping engineering for a lifting-based 2-D discretee

wavelet change", IEEE Transaction on Circuit and System-

II, Express Brief, vol.61, no.6, pp.433– 437, June. 2014.

[8] K. Tsoumanis, S. Xydis, C. Efstathiou, N. Moschopoulos,

and K.Pekmestzi, "An advanced modifed Booth recorder

for proficient outline of the include increase administrator",

IEEE Transaction on Circuit and System-I: Regular Papers,

vol.61, no.4, pp.1133– 1143, Apr. 2014.

[9] Critical-Path Optimization for Efﬁcient Hardware

This project presents a Lifting plan using sum to booth

Realization of Lifting and Flipping DWTs 978-1-4799-

encoder which consists of high speed spanning tree adder in

8391-9/15/$31.00©2015 IEEE

the adder blocks. It is simulated by using Xilinx ISE tool

and results are verified by using Modelsim SE 6.3f .

Experimental results showed that P.D.P. is reduced in the

proposed method compare to existing method.

582

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_______________________________________________________________________________________

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