Phase Locked Loop Version 1.

0 Topology

by

Ryan Christopher Norris

Presented to the UW ASIC Group

Waterloo, Ontario, Canada, 2005

c 2005
Contents

1 Introduction 4

2 Phase Locked Loop Topology 5

3 Phase Frequency Detector 7

3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 Charge Pump 12
4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Low Pass Filter 15

6 Voltage Controlled Oscillator 17

6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Level Shifter (Down: 3.3V to 1.8V) 22

8 5-bit fixed divider 24

8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Level Shifter (Up: 1.8V to 3.3V) 32

1
10 Band Gap Circuit 34
10.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2
List of Figures

2.1 Phase Locked Loop Version 1 Topology. . . . . . . . . . . . . . 6

3.1 Phase Frequency Detector Topology [pdf]. . . . . . . . . . . . 8

3.2 3.3V Inverter [inverter 3p3 A]. . . . . . . . . . . . . . . . . . . 9
3.3 Phase Frequency Detector Flip-Flip [pdf flop]. . . . . . . . . . 10
3.4 3.3V NAND gate [nand2 3p3 A]. . . . . . . . . . . . . . . . . 11

4.1 Charge Pump [QP1]. . . . . . . . . . . . . . . . . . . . . . . . 13

4.2 Charge Pump Amplifier [amp QP]. . . . . . . . . . . . . . . . 14

5.1 Low Pass Filter [LPF]. . . . . . . . . . . . . . . . . . . . . . . 16

6.1 Voltage Controlled Oscillator [VCO]. . . . . . . . . . . . . . . 18

6.2 3.3V Delay Cell with Mirrored Load [Delay Cell 3.3 practice]. 19
6.3 V2I [V2I]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 V2I Amplifier [amp V2I]. . . . . . . . . . . . . . . . . . . . . . 21

7.1 Level Shift Down [level shift down]. . . . . . . . . . . . . . . . 23

8.1 5-Bit Divider [5b div]. . . . . . . . . . . . . . . . . . . . . . . 25

8.2 PDF Divider [div flop]. . . . . . . . . . . . . . . . . . . . . . . 26
8.3 3.3V Inverter (Revision C) [inverter 3p3 C]. . . . . . . . . . . 27
8.4 XOR (Revision A) [xor a]. . . . . . . . . . . . . . . . . . . . . 29
8.5 NOR (Revision A) [nor2 A]. . . . . . . . . . . . . . . . . . . . 30
8.6 1.8V NAND (Revision A) [nand2 1p8 A]. . . . . . . . . . . . . 31

9.1 Level Shift Up [level shift up v2]. . . . . . . . . . . . . . . . . 33

10.1 Band Gap Circuit [Bandgap]. . . . . . . . . . . . . . . . . . . 35

10.2 Band Gap Circuit’s Amplifier [amp BG]. . . . . . . . . . . . . 36
10.3 Band Gap Circuit’s Kick Circuit [Bandgap kick]. . . . . . . . . 37

3
Chapter 1

Introduction

In 2004 Octavian Florescu created the UW ASIC group. At that time, the
analog subgroup of the UW ASIC group was involved in the design of a PLL.
The topology of that PLL, which is now referred to as Phase Locked Loop
Version 1, is documented herein.

4
Chapter 2

Phase Locked Loop Topology

The PLL consists of 8 blocks:

• pfd

• QP1

• LPF

• VCO

• level shift down

• 5b div

• level shift up v2

• Bandgap

5
Figure 2.1: Phase Locked Loop Version 1 Topology.
6
Chapter 3

Phase Frequency Detector

The pdf consists of 13 blocks:

• 10 inverter 3p3 A blocks

• 2 pdf flop blocks

• 1 nand2 3p3 A blocks

3.1

3.2

3.3

7
Figure 3.1: Phase Frequency Detector Topology [pdf].
8
Figure 3.2: 3.3V Inverter [inverter 3p3 A].
9
Figure 3.3: Phase Frequency Detector Flip-Flip [pdf flop].
10
Figure 3.4: 3.3V NAND gate [nand2 3p3 A].
11
Chapter 4

Charge Pump

The QP1 consists of 1 block and 15 transistors (”pch3” model):

• 1 amp QP block

4.1

12
Figure 4.1: Charge Pump [QP1].
13
Figure 4.2: Charge Pump Amplifier [amp QP].
14
Chapter 5

Low Pass Filter

The LPF consists of:

• two resistors

• two capacitors

and thus is a second order LPF.

15
Figure 5.1: Low Pass Filter [LPF].
16
Chapter 6

Voltage Controlled Oscillator

The VCO consists of 4 blocks and three transistors:

• three Delay Cell 3.3 practice blocks

• V2I block (which contains amp V2I)

6.1

6.2

6.3

17
Figure 6.1: Voltage Controlled Oscillator [VCO].
18
Figure 6.2: 3.3V Delay Cell with Mirrored Load [Delay Cell 3.3 practice].
19
 20
Figure 6.3: V2I [V2I].
Figure 6.4: V2I Amplifier [amp V2I].
21
Chapter 7

Level Shifter (Down: 3.3V to

1.8V)

The level shift down block consists of 14 transistors.

22
Figure 7.1: Level Shift Down [level shift down].
23
Chapter 8

5-bit fixed divider

The 5b div block consists of 17 blocks:

• 6 div flop blocks

• 2 inverter 3p3 C blocks

• 5 xor a blocks

• 3 nor2 A blocks

• 1 nand2 A block

24
Figure 8.1: 5-Bit Divider [5b div].
25
Figure 8.2: PDF Divider [div flop].
26
Figure 8.3: 3.3V Inverter (Revision C) [inverter 3p3 C].
27
8.1

8.2

8.3

8.4

8.5

28
Figure 8.4: XOR (Revision A) [xor a].
29
Figure 8.5: NOR (Revision A) [nor2 A].
30
Figure 8.6: 1.8V NAND (Revision A) [nand2 1p8 A].
31
Chapter 9

Level Shifter (Up: 1.8V to

3.3V)

The level shift up v2 consists of 10 transistors.

32
Figure 9.1: Level Shift Up [level shift up v2].
33
Chapter 10

Band Gap Circuit

The Bandgap consists of:

• 1 amb BG block

• 1 Bandgap kick block

• 6 transistors (”pch3” and ”nch3” models)

• 3 resistors (cmosp18/resistor ”resistor” model)

• 2 diodes (cmosp18/diode ”ndio” model)

10.1

10.2

34
Figure 10.1: Band Gap Circuit [Bandgap].
35
Figure 10.2: Band Gap Circuit’s Amplifier [amp BG].
36
Figure 10.3: Band Gap Circuit’s Kick Circuit [Bandgap kick].
37