3442 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO.

12, DECEMBER 2008

Analytical Model of Subthreshold Current and Slope

for Asymmetric 4-T and 3-T Double-Gate MOSFETs
Aritra Dey, Anjan Chakravorty, Nandita DasGupta, Member, IEEE, and Amitava DasGupta, Member, IEEE

Abstract—In this paper, analytical models of subthreshold cur-

rent and slope for asymmetric four-terminal double-gate (DG)
MOSFETs are presented. The models are used to study the sub-
threshold characteristics with asymmetry in gate oxide thickness,
gate material work function, and gate voltage. A model for the
subthreshold behavior of three-terminal DG MOSFETs is also
presented. The results of the models show excellent match with
simulations using MEDICI. The analytical models provide physi-
cal insight which is helpful for device design.
Index Terms—Analytical model, double gate (DG), drain-
induced barrier lowering (DIBL), silicon-on-insulator (SOI), sub-
threshold current, subthreshold slope.
I. INTRODUCTION
T HE double-gate (DG) MOS technology has emerged as
one of the most promising candidates to extend the CMOS
beyond the scaling limit of conventional technology due to
excellent control of short-channel effects (SCEs) [1], [2]. The
DG MOSFET can either have a three-terminal (3-T) config-
uration, where both the gates are shorted, or a four-terminal
(4-T) configuration, where the back-gate bias is fixed and the
front gate acts as the control electrode. Symmetric 3-T DG
MOSFETs have unacceptably low threshold voltage, leading
to large leakage current (Ioff ). Asymmetric 3-T [3], [4] and
4-T DG MOSFETs [5] with different front and back-gate
work functions and oxide thicknesses have been proposed and
investigated in detail to reduce Ioff . However, it has been found
that 4-T devices have a worse subthreshold slope (S) compared
to 3-T devices and S increases with increasing back-gate bias
(VGB ) [5]. Further studies [6] have shown that a thicker back
insulator results in a lower S than the symmetric structure.
A 4-T DG MOSFET model [5], which calculates the vari-
ation of subthreshold slope in a heuristic manner, has been
reported. Not only is this model unable to predict the variation
of the S with VGB but it is also discontinuous at the point
where VGB equals the front-gate bias (VGF ). Two-dimensional
(2-D) potential variation based on parabolic approximation [7]
has been employed in a subthreshold-current model for fully
depleted silicon-on-insulator (FDSOI) MOSFET [8]. However,
the evanescent method of solution of 2-D Poisson’s equation
Manuscript received May 13, 2008; revised August 15, 2008. Current version
published November 26, 2008. The review of this paper was arranged by
Editor C. Jungemann.
A. Dey is with the Department of Electrical Engineering, Indian Institute
of Technology Madras, Chennai 600 036, India, and also with Arizona State
University, Tempe, AZ 85287 USA.
A. Chakravorty, N. DasGupta, and A. DasGupta are with the Department
of Electrical Engineering, Indian Institute of Technology Madras, Chennai
600 036, India (e-mail address: adg@ee.iitm.ac.in).
Digital Object Identifier 10.1109/TED.2008.2006109
Fig. 1. 4-T DG MOSFET structure considered in our model.
[9] has been shown to be superior [10]. This is because, in the
parabolic case, the characteristic length λ depends on the trans-
verse curvature of the potential along the silicon film which is
not consistent with simulation studies. A model for subthresh-
old slope based on evanescent method has been reported [11].
However, this model is unable to predict the variation of S with
VGB and is only applicable to 3-T symmetric DG MOSFET.
Very recently, an analytical model for threshold voltage has
been developed [12] for symmetric/asymmetric 3-T and 4-T
DG MOSFETs based on cubic-potential approximation. How-
ever, the problem of λ depending on the transverse curvature
remains. Furthermore, this paper does not lead to models for
subthreshold current and slope. To the best of our knowledge,
no analytical model has so far been developed for subthreshold
current as well as slope for the generic 4-T DG structure.
In this paper, we present for the first time a simple analytical
model of the subthreshold current and slope of asymmetric 4-T
DG MOSFET based on 2-D solution of Poisson’s equation us-
ing the evanescent method. The model is then used to study the
dependence of S on back insulator thickness, back-gate bias,
as well as back-gate work function. The subthreshold current
of the 3-T DG MOSFET can be obtained from the 4-T DG
MOSFET model as a special case where both the gate biases
are equal. However, a separate model is required for the sub-
threshold swing in 3-T DG MOSFETs, since in this case, both
the gate voltages change synchronously to control the channel
charge. A model for subthreshold swing in 3-T DG MOSFETs
is presented, which can also take into account asymmetry in
these devices. The models are extensively tested using MEDICI
[13] simulations to confirm their validity and accuracy.
II. ANALYTICAL MODEL
The device structure considered for our analysis is shown in
Fig. 1. As shown in the figure, tsi is the silicon film thickness,
L is the channel length, and tox1 and tox2 are the front and back

0018-9383/$25.00 © 2008 IEEE

DEY et al.: ANALYTICAL MODEL OF SUBTHRESHOLD CURRENT AND SLOPE FOR 4- AND 3-T DG MOSFETs 3443

oxide thicknesses, respectively. In addition, y = 0 at the center Substituting (7) and (8) in (4), we obtain ψL (y) in terms of VGF ,
of the silicon film, and x = 0 at the source end of the channel. VGB and other material parameters of the device.
At first, the 2-D Poisson’s equation is solved under depletion Now, a general solution of (3) can be represented in Fourier
approximation to obtain the potential variation in the silicon series as [9]
film. This leads to an analytical expression for the minimum ∞     
channel potential as a function of depth (ψmin (y)), which is  ny ny
ψ2D (x, y) = cos + An sin
then used to develop analytical expressions for subthreshold λn λn
current and slope.
n=1 ⎡ ⎤
Un sinh λxn + Vn sinh L−x
×⎣
λn ⎦
. (9)
A. Expression for Minimum Channel Potential sinh λLn
As mentioned earlier, to solve the 2-D Poisson’s equation, we
Since the higher order terms decay fast, we can approximate (9)
follow the evanescent method [10]. In this method, the channel
by taking the first mode only and can rewrite (9) as
potential (ψ(x, y)) is decoupled into two parts, i.e.,
 
cos(y/λ) + A sin(y/λ)
ψ(x, y) = ψL (y) + ψ2D (x, y) (1) ψ2D (x, y) =
sinh(L/λ)
 
where ψL (y) is the long-channel approximation of the channel x L−x
× U sinh + V sinh . (10)
potential which satisfies the 1-D Poisson’s equation along the λ λ
channel thickness (y) given by
It may be noted that A = 0 for r1 = r2 to meet the symmetrical
∂ 2 ψL qNA requirement (ψ2D |−tsi /2 = ψ2D |tsi /2 ). To obtain the values of
2
= (2) the constants A, U , V , and λ in (10), we use the four boundary
∂y εsi
conditions at the front and back surfaces and also at drain and
where NA is the doping concentration in the silicon film. On source ends. The boundary conditions are as follows:
the other hand, ψ2D (x, y) takes into account the 2-D variation
of the channel potential and satisfies the 2-D Laplace equation ∂ψ2D
ψ2D (x, y = − tsi /2) = r1 tsi |y=−tsi /2 (11)
given by ∂y
∂ψ2D
∂ 2 ψ2D ∂ 2 ψ2D ψ2D (x, y = tsi /2) = −r2 tsi |y=tsi /2 (12)
2
+ = 0. (3) ∂y
∂x ∂y 2
ψ2D (x = 0, y) = Vbi − ψL (y) (13)
The solution of (2) can be comprehensively written as
ψ2D (x = L, y) = Vbi + VDS − ψL (y) (14)
qNA y 2 ψs2 − ψs1 ψs1 + ψs2 qNA t2si
ψL (y) = + y+ − where Vbi is the built-in voltage of the source and drain junc-
2εsi tsi 2 8εsi
(4) tions and VDS is the applied drain-source voltage. The boundary
conditions (11) and (12) along with (5) and (6) ensure that the
where ψs1 and ψs2 are the potentials at the front and back
front (back) gate voltage is equal to the sum of the front (back)
silicon surfaces, respectively. These surface potentials satisfy
surface potential and the voltage across the front (back) gate
the equations [14]
insulator all along the channel, while (13) and (14) ensure that
qNA tsi the potential at the source and drain ends of the channel are Vbi
VGFS = ψs1 (1 + r1 ) − ψs2 r1 + (5) and Vbi + VDS , respectively.
2Cox1
qNA tsi From the boundary conditions (11) and (12), we get
VGBS = ψs2 (1 + r2 ) − ψs1 r2 + (6)
2Cox2
1 − r1 tsi /λ tan(tsi /2λ) r2 tsi /λ tan(tsi /2λ) − 1
=
where VGFS = VGF − VFBF , VGBS = VGB − VFBB , r1 = tan(tsi /2λ) + r1 tsi /λ tan(tsi /2λ) + r2 tsi /λ
εsi tox1 /εox tsi , r2 = εsi tox2 /εox tsi , Cox1 = εox /tox1 , Cox2 = (15)
εox /tox2 , and VFBF and VFBB denote the flatband voltages at 1 − r1 tsi /λ tan(tsi /2λ)
A= .
the front and back interfaces, respectively. From (5) and (6), tan(tsi /2λ) + r1 tsi /λ
solving for ψs1 and ψs2 , we have (16)

(1 + r2 )VGFS + r1 VGBS The solution of (15) gives us the value of λ, which is then sub-
ψs1 =
1 + r1 + r2  stituted in (16) to obtain the value of A. Now, using boundary

qNA tsi 1 + r2 r1 conditions (13) and (14), we have
− + (7)
2(1 + r1 + r2 ) Cox1 Cox2
V = Vbi − ψL (0) (17)
r2 VGFS + (1 + r1 )VGBS
ψs2 = U = Vbi + VDS − ψL (0). (18)
1 + r1 + r2  
qNA tsi r2 1 + r1 Substituting the values of A, U , V , and λ in (10), we get
− + . (8)
2(1 + r1 + r2 ) Cox1 Cox2 ψ2D in terms of the bias and material parameters. Using the
3444 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008

Fig. 3. Variation of electron concentration at xmin along the silicon film for
different back-gate bias in 4-T MOSFET.

Fig. 2. Variation of ψmin (y) along the silicon film for different bias condi- virtual cathode (nmin (y)), and hence, the current density can
tions in 4-T symmetric DG MOSFET obtained from the present model as well
as from MEDICI.
be expressed as
nmin (y)
Jn (y) ∼
= qDn (1 − e−VDS /Vt ) (20)
solutions for ψL (y) and ψ2D (x, y), the potential at any point in Le
the channel can be obtained from (1). where Dn is the diffusion constant, Le is the effective channel
To evaluate the subthreshold current, we need to find the length, q is the electron charge, and Vt is the thermal voltage.
carrier concentration at the point along the channel where Using Boltzmann approximation, we have
the potential is minimum, i.e., at the virtual source. Since the 
minimum potential ψmin (y) varies with distance from the two nmin (y) = n2i /NA eψmin (y)/Vt (21)
gates, we at first solve ∂ψ2D (x, y)/∂x|x=xmin = 0 to obtain
xmin and then substitute the value of xmin in (1) to get ψmin (y). where ni is the intrinsic carrier concentration. Fig. 3 shows
Using the condition e−L/λ  1 [15], which is valid for practi- the variation of nmin (y) for a 4-T DG MOSFET with different
cal cases, gives back-gate bias. The excellent match with values obtained from
MEDICI shows that the evaluation of ψmin (y) from our model
y y
√ is sufficiently accurate. Otherwise, it would have resulted in
ψmin (y) = ψL (y) + 2 cos + A sin UVe−L/2λ .
λ λ a large error in nmin (y) due to the exponential dependence.
(19) This also validates the omission of the mobile charge term in
Fig. 2 shows the variation of ψmin (y) in symmetric 3-T solution of Poisson’s equation. The effective channel length
and 4-T DG MOSFETs obtained from our model as well as is obtained considering the lateral penetration of the depletion
MEDICI simulations. Our model shows excellent match with region associated with the source (Ls ) and drain (Ld ) as [8]
MEDICI simulations with maximum deviation of only about Le = L − Ls − Ld + 2LD (22)
5 mV at y = ym , where ψmin (y) is minimum. As expected,
the plot for the symmetric 3-T device is also symmetric with where LD is the extrinsic Debye length. In our model, we
ym = 0, while for the 4-T device, it is asymmetric with ym = express Ls and Ld as
0. When VGB is made increasingly negative, the position of
2(Vbi − ψm )
minima shifts toward the back interface, and for large negative Ls = (23)
values of VGB , the back interface may be in accumulation with |∂ψ/∂x|x=0
the ψmin (y) plot, showing a minima at y = −tsi /2, i.e., at the 2(Vbi + VDS − ψm )
Ld = (24)
back interface. It may be mentioned here that, for a symmetric |∂ψ/∂x|x=L
3-T DG MOSFET, the earlier equations reduce to a much
simplified form as reported in [11]. where ψm = ψmin (ym ). The value of ym is obtained by solving
∂ψmin (y)/∂y|y=ym = 0, and ψm is obtained by substituting
the value of ym in (19).
B. Subthreshold-Current Model The drain–current (IDS ) can be obtained by integrating (20)
The earlier 2-D potential model can be used to derive along the silicon film, i.e., from −tsi /2 to tsi /2. Thus, from (20)
an explicit analytical current equation in the subthreshold and (21), we have
regime. For this, we follow the procedure proposed for FDSOI t
si /2
MOSFETs [8] and later used even for FinFETs [16]. In the ψmin (y)

weak inversion region, the current is mainly diffusion dom- IDS = K e Vt dy (25)
inated and proportional to the electron concentration at the −tsi /2
DEY et al.: ANALYTICAL MODEL OF SUBTHRESHOLD CURRENT AND SLOPE FOR 4- AND 3-T DG MOSFETs 3445

where K = (qμn W Vt n2i /Le NA )(1 − e−VDS /Vt ), with W as

the width of the MOSFET. In order to evaluate the integral
in (25) analytically, we partition the channel into two sections:
1) the front section (−tsi /2 ≤ y < ym ) giving rise to the front
component of current (If ) and 2) the back section (ym <
y ≤ tsi /2) giving rise to the back component of current (Ib ).
In addition, we consider that ψmin (y) varies linearly in both
the front and back sections, i.e., ψmin (y) varies linearly from
f
ψm = ψmin (−tsi /2) to ψm , corresponding to a constant elec-
tric field Ef = (ψm f
− ψm )/(ym + tsi /2) in the front section,
b
and from ψm to ψm = ψmin (tsi /2), corresponding to a con-
stant electric field Eb = (ψm b
− ψm )/(ym − tsi /2) in the back
section. Thus, the subthreshold current can now be expressed as

IDS = If + Ib (26)

where
ym  f  Fig. 4. Comparison of the variation in position of charge centroid with
ψmin (y) KVt ψVm ψm difference in front- and back-gate biases, obtained from the analytical model
If = K e Vt dy = e t −e t
V (27) and numerical integration for 4-T symmetric DG MOSFET.
Ef
−tsi /2
Now, assuming a linear variation of ψmin (y) in the two sections,
t
si /2  b
 we get a simple expression for the charge centroid as
ψmin (y) KVt ψVm ψm
Ib = K e Vt dy = e t −e Vt . (28)
Eb deff
ym
ψm
 

ym+tsi /2
KVt e Vt
Ef + tsi /2−y
Eb
m
+If EVft +t2si +Ib Eb
−2
Vt tsi

= .
C. Subthreshold-Slope Model IDS
(32)
The subthreshold slope in a 4-T DG MOSFET can be ex-
pressed as The comparison of this deff obtained from the earlier analytical
 −1 expression and that obtained from numerical integration with-
∂VGF ∂(If + Ib ) out assuming linear variation in potential is shown in Fig. 4
S = ln 10 = IDS ln 10 . (29)
∂ ln(IDS ) ∂VGF for variation in VGF − VGB for a symmetric 4-T DG MOSFET.
From the figure, it is evident that the value of deff calculated
However, it is difficult to obtain a simple expression for S from (32) matches very well with numerical simulations. In
using the relations for If and Ib derived earlier due to the addition, for VGF = VGB , it is observed that deff = 0. This is
f b
complicated dependence of ψm , ym , ψm , and ψm on VGF . also evident from (32) since, for VGFS = VGBS , If = Ib , Ef =
In a simpler approach [11], the subthreshold current is −Eb , and ym = 0. Fig. 4 also shows that, as VGF − VGB is
assumed to be proportional to nmin (y), and (29) can be increased, the charge centroid shifts toward the front interface.
rewritten as This is also evident from Fig. 3 which shows that, when the
 
∂VGF  Vt ln(10)  back-gate bias is reduced, the electrons are mostly concentrated
S ≈ ln 10 = (30)
∂ ln(nmin ) y=deff ∂ψmin /∂VGF y=deff
near the front interface.
Now, substituting (19) in (30), we have an expression of S as
where deff is the charge centroid, which in our model is ob- V ln(10)
tained from S= 2deff
t d d
 .
1+2r2 − (1+2r2 ) cos eff
+A sin eff (U +V )
2(1+r2 +r1 )
tsi
− λ
√
(1+r2 +r1 ) U V
λ
e−L/2λ
/2
tsi
(33)
ynmin (y)dy
−tsi /2
deff = From (33), it is clear that S approaches its ideal value when
/2
tsi
L 2λ, deff ≈ (−tsi /2), and r2 r1 . While the first con-
nmin (y)dy
−tsi /2
dition implies a long channel MOSFET, the second condition
indicates that a higher charge concentration near the front
ym /2
tsi
ψmin (y) ψmin (y) interface will result in better control of the front gate. From the
ye Vt dy + ye Vt dy
−tsi /2 ym
previous discussion, it is clear that the second condition will
= ym . (31) be satisfied when VGB is much less than VGF . Interestingly,
 ψmin (y) ym ψmin (y)
e Vt dy + e Vt dy this condition can also be satisfied for VGF = VGB , provided
−tsi /2 −tsi /2 that the work function of the back-gate material is much greater
3446 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008

than the front-gate material, e.g., when the front and back gates
are n+ and p+ polysilicon, respectively. The third condition
r2 r1 implies that tox1  tox2 , resulting in greater control
of the front gate.
For a MOSFET with structural symmetry, i.e., r1 = r2 = r,
since A = 0, (33) reduces to

  −1
1 deff (U +V ) cos dλeff −L/2λ
S = Vt ln(10) − − √ e .
2 (1+2r)tsi UV
(34)

Here, for ideal subthreshold slope, in addition to L 2λ and

deff ≈ (−tsi /2), we require r  1/2, or the effective oxide
thickness to be much less than the silicon film thickness.
For a 3-T DG MOSFET where both the gates are
shorted, substituting VGB = VGF in (7) and (8), we get Fig. 5. Comparison of the subthreshold drain–current variation for 4-T sym-
∂ψL /∂VGF = 1 from (4). Now, differentiating (19) and metric DG MOS using the present model and MEDICI simulations for different
back-gate bias.
substituting ∂ψL /∂VGF = 1, we obtain an expression of
∂ψmin /∂VGF , which, when substituted in (30), gives where
ym
 ynmin (y)dy
(U + V )
S = Vt ln(10) 1 − √ −tsi /2
UV deff1 = ym

     −1 nmin (y)dy
deff deff −L/2λ −tsi /2
× cos + A sin e
λ λ ψm
 

ym +tsi /2 Vt tsi
KVt e Vt
Ef + If Ef + 2
(35) = (38)
If

which for the symmetric structure (r1 = r2 = r), since A = 0, /2

tsi
ynmin (y)dy
reduces to ym
deff2 =
/2
tsi
   −1 nmin (y)dy
(U + V ) deff
S = Vt ln(10) 1 − √ cos e−L/2λ . ym
UV λ ψm
 

This shows that, for 3-T symmetric DG MOSFETs, S will
approach the ideal value for long-channel devices, while for
shorter channel devices, S will depend on the position of charge
centroid with the minimum slope when deff = ±tsi /2. However,
it must be mentioned that the procedure for calculating deff in
the case of 3-T MOSFETs should be different from that used
for 4-T devices, since, in this case, both the gates are operated
synchronously and have equal control over the channel. Thus,
while a symmetric charge profile with peak concentrations
near the two oxide interfaces is not desirable for 4-T devices
(deff = 0), it is the ideal situation for 3-T MOSFETs and should
be reflected with deff = ±tsi /2. In our model, we consider the
charge from the front interface to ym to be controlled by the
front gate and from ym to the back interface to be controlled by
the back gate. This is justified since the electric field changes
direction at y = ym . Now, defining separate charge centroids
corresponding to front and back gates as deff1 and deff2 , respec-
tively, the overall charge centroid can be expressed as
deff = (If |deff1 | + Ib |deff2 |) /IDS
tsi /2−ym
(36) KVt e Vt
Eb + Ib Vt
Eb − tsi
2
= . (39)
Ib
In (37), a weighted approach is taken into account for
any asymmetries that may be present. For a symmetric DG
MOSFET, since (38) and (39) yield the same results and with
If = Ib , it suffices to take only one deff as has been done
in [11]. But instead of computing deff as in the present case,
in [11], deff has been chosen heuristically as tsi /4. However,
such an approach does not give the variation of S with back
insulator thickness and back-gate work function.
III. RESULTS AND DISCUSSION
Figs. 5 and 6 show the subthreshold current variation in 4-T
DG MOSFETs obtained from our model as well as MEDICI for
various back biases and back insulator thicknesses, respectively.
Both these plots show that the results from the analytical model
match very well with simulations. While Fig. 5 considers a DG
MOSFET with L = 36 nm, tox = 1.6 nm, and tsi = 16 nm,
Fig. 6 considers devices with L = 50 nm, tox = 2 nm, and
tsi = 20 nm. This shows that our model is valid for a wide
(37) range of device parameters and is also applicable for very short
DEY et al.: ANALYTICAL MODEL OF SUBTHRESHOLD CURRENT AND SLOPE FOR 4- AND 3-T DG MOSFETs
Fig. 6. Comparison of the subthreshold drain–current variation using the
present model and MEDICI simulation for different back oxide thicknesses.
Fig. 7. Comparison of subthreshold drain–current variation with VGS for
3-T symmetric (n+ ) and asymmetric (n+ /p+ ) DG MOSFET obtained from
analytical model and MEDICI simulation.
channel MOSFETs in the sub-50-nm regime. Fig. 5 clearly
shows that the subthreshold characteristics degrade as the back
bias is increased. For high back bias, the OFF-state current is no
longer negligible and contributes to standby power. However,
lowering the bias also lowers the ON-state current. Fig. 6 shows
that the subthreshold characteristics improve with increase in
back insulator thickness as with such a strategy the influence of
back gate decreases.
Fig. 7 shows the IDS versus VGS characteristics for
3-T DG MOSFETs with symmetric n+ poly and asymmetric
n+ /p+ poly gates. Here, again, excellent match is obtained with
simulation results. It is quite evident that both characteristics
show a near ideal S close to 60 mV/dec. However, because
of the higher threshold voltage, the asymmetric structure has
lower Ioff .
Fig. 8 shows the variation in subthreshold slope with back-
gate bias in 4-T devices with different back oxide thicknesses
obtained from our model as well as MEDICI simulations. The
excellent match with simulation results validates our model. It
3447
Fig. 8. Comparison of subthreshold-slope variation with back-gate bias for
4-T DG MOSFET with different back oxide thickness obtained from analytical
model and MEDICI simulation.
Fig. 9. Comparison of the variation in subthreshold slope (S) and position
of charge centroid with back-gate metal–silicon work-function difference for
3-T DG MOS obtained from analytical model and MEDICI simulation.
can be seen that, with reduction in VGB , the subthreshold slope
reduces. This is expected, since the charge centroid is closer
to the front interface for lower VGB . In addition, S reduces
with increase in tox2 . Here, again, with higher tox2 , the back-
gate bias has less control over channel charge, and the charge
centroid is closer to front gate. However, when VGB is much
less than VGF , variation in tox2 does not have much effect, since
deff is already quite close to −tsi /2.
Fig. 9 shows the variation in subthreshold slope with back-
gate-to-silicon work-function difference (φBS ) for 3-T DG
MOSFETs with n+ polysilicon front gate. For the substrate
doping concentration of NA = 1016 /cm3 , the front-gate-to-
silicon work-function difference (φFS ) is fixed at φFS =
−EG /2q − φB = −0.9 V, where EG = 1.1 eV is the sili-
con bandgap and φB = Vt ln(NA /ni ) is the Fermi potential.
In addition, when n+ polysilicon is used as the back-gate
material, φBS will similarly be equal to −0.9 V. On the other
hand, if p+ polysilicon is used as the back-gate material
3448
Fig. 10. Comparison of subthreshold-slope variation with drain voltage in
symmetric and asymmetric 3-T DG MOSFET obtained from analytical model
and MEDICI simulation.
φBS = EG /2q − φB = 0.2 V. Thus, in Fig. 9, φBS = −0.9 V
refers to an n+ polysilicon back gate resulting in a sym-
metric device, while φBS = 0.2 V refers to a p+ polysili-
con back gate resulting in an asymmetric n+ /p+ device. As
shown in the figure, the n+ /p+ device shows a reduced sub-
threshold slope as compared to the symmetric device. This
is because, in the asymmetric device, the charge is mostly
concentrated near the front gate, and deff is higher than
the symmetric case. The variation in deff is also shown in
Fig. 9. As shown in the figure, for the symmetric device
deff ≈ 5 nm, which corresponds to tsi /4, as reported ear-
lier [11]. For the asymmetric device, deff increases, resulting
in reduced S. The greater gate control results in reduced
SCEs in the asymmetric device as noted earlier [4]. This also
results in less drain-induced barrier lowering (DIBL) in the
n+ /p+ device. Fig. 10 shows the variation of S with VDS and
shows that the subthreshold slope worsens with VDS much more
for the symmetric case due to greater DIBL. The subthreshold
slope for the asymmetric device is about 66 mV/dec, which
matches well with experimental results [3]. The excellent match
between the results from our model and MEDICI shown in
Figs. 9 and 10 underlines the accuracy of our simple model for
subthreshold slope in 3-T DG MOSFETs.
IV. CONCLUSION
In this paper, simple analytical models for the subthreshold
current and slope for 4-T and 3-T DG MOSFETs are pre-
sented. In the subthreshold-slope models, the idea of shifting
of charge centroid is used to account for the back-gate work
function, back-gate bias, and back insulator dependence of S.
The analytical models have been thoroughly tested and give
accurate results as confirmed by comparison with MEDICI
simulations. The models are also able to predict correctly
the previously reported experimental and simulation results
[3]–[6]. The analytical expressions give sufficient insight into
the design choice of the external parameters.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008
ACKNOWLEDGMENT
The authors would like to thank Prof. C. K. Maiti, Depart-
ment of E&ECE, IIT Kharagpur, for timely help in providing
facilities for some of the MEDICI simulations.
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Aritra Dey received the B.Tech. degree in elec-
tronics and communication engineering from the
Institute of Engineering and Management, Calcutta,
India, in 2006 and the M.S. degree in micro-
electronics and VLSI design with a thesis on
“Potential Based Analytical Modelling of Single and
Double-Gate MOSFETs” from the Indian Institute of
Technology Madras, Chennai, India, in 2008. He
is currently working toward the Ph.D. degree at
Arizona State University, Tempe.
DEY et al.: ANALYTICAL MODEL OF SUBTHRESHOLD CURRENT AND SLOPE FOR 4- AND 3-T DG MOSFETs 3449

Anjan Chakravorty received the B.Tech. degree
from Kalyani Government Engineering College,
University of Kalyani, Kalyani, India, in 1999, the
M.Tech. degree from the Institute of Radiophysics
and Electronics, University of Calcutta, Calcutta,
India, in 2001, and the Ph.D. degree from the
Indian Institute of Technology (IIT), Kharagpur,
India, in 2005.
A few months between 2003 and 2004, he was a
Guest Scientist in a modeling group with Innovations
for High Performance Microelectronics, IHP GmbH,
Germany. From 2005 to 2006, he was a Postdoctorate Fellow with Dresden
University of Technology, Dresden, Germany, where he worked on bipolar
transistor compact modeling. Since January 2007, he has been an Assistant
Professor with the Electrical Engineering Department, IIT Madras, Chennai.
He published few papers in reputed international journals, mainly in the area of
compact modeling. His current research interests include compact modeling of
bipolar and MOS transistors and circuit design for RF applications.
Amitava DasGupta (S’85–M’88) received the B.E.
degree in electronics and telecommunication engi-
neering from Jadavpur University, Calcutta, India,
in 1982, the M.Tech. degree in electrical engineer-
ing from the Indian Institute of Technology (IIT)
Madras, Chennai, India, in 1984, and the Ph.D.
degree from IIT, Kharagpur, India, in 1988, with
a Ph.D. degree dissertation on analytical modeling
of small-geometry MOSFETs with nonuniformly
doped channels.
In 1988, he was a Lecturer with IIT, Kharagpur.
From 1991 to 1992 and in 1997, as a DAAD Fellow, he was with the Institut für
Hochfrequenztechnik, Darmstadt, Germany. Since 1993, he has been a Faculty
Member with the Department of Electrical Engineering, IIT Madras, where he
is currently a Professor. His research interests are in the areas of semiconductor-
device modeling and technology as well as microelectromechanical system. He
has more than 80 research publications in international journals and proceed-
ings of international conferences and has coauthored a book on semiconductor
devices—modeling and technology.

Nandita DasGupta (M’08) received the B.E. degree

in electronics and telecommunication engineering
from Jadavpur University, Calcutta, India, in 1982
and the M.Tech. degree in electrical engineering and
the Ph.D. degree from the Indian Institute of Tech-
nology (IIT) Madras, Chennai, India, in 1984 and
1988, respectively, with a Ph.D. degree dissertation
on high-pressure oxidation of silicon and GaAs.
Since 1993, she has been a Faculty Member
with the Department of Electrical Engineering, IIT
Madras, where she is currently a Professor. She spent
one year in Technische Hochschule Darmstadt, Germany. Her research interest
is in the area of semiconductor-device technology and modeling as well as
microelectromechanical systems. She has about 80 research publications in
international journals and proceedings of international conferences and has
coauthored a book on semiconductor devices—modeling and technology.
Prof. DasGupta was the recipient of the Alexander von Humboldt Fellowship
in 1991.