Q1. Why metal density rules are important?

(Qualcomm)
Ans. Metal Density rules take care of metal over-etching and metal lift off
issues encountered durinf manufacturing process.

Q2. Why power stripes routed in the top metal layers? (Qualcomm)
Ans. Power routes generally conduct a lot of current. In order to reduce effect of
IR drop, we need to make these routes less resistive. Top metal layers are
thicker and offer lesser resistance. This helps to reduce IR drop.

Q3. Types of checks that can be done in PrimeTime ? (Synapse)

Ans. Timing (setup, hold, transition), design constraints, nets, noise, clock skew
and analysis coverage.

Q4. How do you validate your floorplan and what analysis you do
during floorplan? (Synapse)
Ans. 1) Overlapping of macros.
2) Global route congestion -> in order to finalize Min. Channel
spacing.
3) Allowable IR drop.
4) Physical information of the design (report_design_physical)
Q5. How many clocks you had in your designs? How did you do CTS for
the same? (Tessolve/ Synapse)
Ans. I had 5 clocks in my designs, sys_clk, sys_rclk, uart_clk, g_clk and
scan_clk, where sys_clk, g_clk and uart_clk logically exclusive to scan_clk.

Q6. Did you get Antenna problem in your project for all the metal
layers? How did you fix them? (Tessolve/ Synapse)

Ans. Metal Jumper and Antenna diode are two methods to resolve Antenna
violations. But Metal Jumper is preferred approach as it does not need change
to the Netlist and placement. This methodology works for antenna violations on
all metal layers except for the top most layer. In this methodology, we will
switch the small portion of routing to higher level metal close to the location
of failing gate. This will make sure that accumulated charges on metal layer
does not affect the gate as gate will not be connected to the charge carrying
metal route until higher level metal is manufactured.

Antenna Violation in Metal M2

 Metal jumper from Metal M2 to Metal
M3

For example, lets say antenna violation is in M2. This means that M2 has
enough area to accumulate large charge that induces high electron voltage to
destroy the gate. To solve this problem, we cut a portion of M2 close to failing
gate and move the routing to M3. This makes sure that when M2 is being
manufactured, it does not get connected to gate. Connection happens only
when M3 gets manufactured which is much later in time. By then charges on
Metal M2 would have leaked away.

Antenna Violation on Metal M3

Insertion of Antenna Diode

When metal jumper is not possible to implement (probably due to routing

congestion or violation happening in top most layer) we try to fix it by inserting
antenna diode closed to gate failing antenna. Antenna diode provide electrical
path for safe conduction of accumulated charges to the substrate. Antenna
diode is a reversed biased diode but acts like resistor during manufactured
process (CMP) due to high temperature environment.
 Q7. How do you reduce power dissipation using High Vt and Low Vt on
your design? (Broadcomm)
Ans.
1) Use HVT cells for timing paths having +ve slacks.
2) Use LVT cells for timing paths having -ve slacks.
HVT cells have a larger delay but less leakage. +ve slack in a design is not
useful as having only some paths working faster will not help overall design.
We are good if the slack is 0. In such cases give up the slack by using HVT cells
but gain on power dissipation.
LVT cells are very fast but very leaky. Limit the use of LVT cells to only those
paths that have difficulty in closing time.

Q8. What is Electromigration and how to fix it? (Virage)

Ans. Electromigration (EM) refer to the phenomenon of movement of metal
atoms due to momentum transfer from conducting electrons to metal atoms.
Current conduction over a period of time in a metal route causes opens or
shorts due to EM effect. EM effect cannot be avoided.
In order to minimize its effect, we use wider wires so that even with EM effect
wire stays wide enough to conduct over the lifetime of the IC.

Q9. What are the various statistics available in IR drop reports?

(Qualcomm)
Ans. 1) IR drop info for VDD/ VSS.
2) Maximum current through VDD/VSS.
3) Number of current sources for VDD/VSS.
4) Utilization of metal layers used.
5) EM information for signal and via.

Q10. What is the importance of IR drop analysis? (Qualcomm)

Ans. IR drop determines the level of voltage at the pins of standard cells. Value
of acceptable IR drop will be decided at the start of the project and it is one of
the factors used to determine the derate value.
If the value of IR drop is more than the acceptable value, it calls to change the
derate value. Without this change, timing calculation becomes optimistic. For
example setup slack calculated by the tool is less than the reality.

Q1. Explain the flow of physical design and inputs and outputs for each step in
flow?

Q2. Why higher metal layers are preferred for Vdd and Vss?

Q3. Why clock is not synthesized in DC?

Q4. Which layer is used for clock routing and why?

Q5. Which is more complicated when you have a 32 MHz and 512 MHz clock
design?

Q6. Whether congestion is related to placement or routing?

Q7. What parameters (or aspects) differentiate Chip Design & Block level
design?

Q8. What is wire load model?

Q9. What is transition? What if transition time is more?

Q10. What is track assignment?

Q11. What is tie-high and tie-low cells and where it is used?

Q12. What is threshold voltage? How it affect timing?

Q13. What is the significance of negative slack?

Q14. What is the difference between synthesis and simulation?

Q15. What is the difference between core filler cells and metal fillers?

Q16. What is signal integrity? How it affects Timing?

Q17. What is SDC constraint file contains?

Q18. What is scan chain? What if scan chain not detached and reordered? Is it
compulsory?

Q19. What is partial floor plan?

Q20. What is OPC, PSM?

Q21. What is negative slack ? How it affects timing?

Q22. What is metal density, metal slotting rule?

Q23. What is meant by 9 track, 12 track standard cells?

Q24. What corner cells contains?

Q25. What are types of routing?

Q26. What are the steps that you have done in the design flow?

Q27. What are the steps involved in designing an optimal pad ring?

Q28. What are the problems faced related to timing?

Q29. What are the common issues in floor plan?

Q30. What is logic optimization and give some methods of logic optimization.

Q31. What is LEF?

Q32. What is latency? Give the various latency types?

Q33. What is IR drop? How to avoid .how it affects timing?

Q34. What is hold problem? How can you avoid it?

Q35. What is grided and gridless routing?

Q36. What is floor plan and power plan?

Q37. What is ESD?

Q38. What is EM and it’s effect?

Q39. What is effective utilization and chip utilization?

Q40. What is each macro size and no. of standard cell count?

Q41. What is difference between normal buffer and clock buffer?

Q42. What is difference between HFN synthesis and CTS?

Q43. What is DEF?

Q44. What is cross talk? How can you avoid?

Q45. What is core and how you will decide w/h ratio for core?

Q46. What is content of lib, lef, sdc?

Q47. What is congestion?

Q48. What is cloning and buffering?

Q49. What is cell delay and net delay?

Q50. What is antenna effect? How it can be avoided?

Q51. What is a macro and standard cell?

Q52. What is a grid? Why we need different types of grids?

Q53. What is .lib, LEF, DEF, .tf?

Q54. What if hot spot found in some area of block? How you tackle this?
Q55. What are the Input needs for your design?

Q56. What are the input files will you give for primetime correlation?

Q57. What are the algorithms used while routing? Will it optimize wire length?

Q58. What are placement blockages?

Q59. What are high-Vt and low-Vt cells?

Q60. What are the common DFM issues?

Q61. What are delay models and what is the difference between them?

Q62. What are clock trees?

Q63. What are clock tree types?

Q64. Name few tools which you used for physical verification?

Q65. In your project what is die size, number of metal layers, technology,
foundry, number of clocks?

Q66. In which layer do you prefer for clock routing and why?

Q67. If the routing congestion exists between two macros, then what will you
do?

Q68. If lengthy metal layer is connected to diffusion and poly, then which one
will affect by antenna problem?

Q69. If in your design has reset pin, then it’ll affect input pin or output pin or
both?

Q70. How will you place the macros?

Q71. How will you decide the Pin location in block level design?

Q72. How will you decide the die size?

Q73. How to find total chip power?

Q74. How to find number of power pad and IO power pads?

Q75. How to decide number of pads in chip level design?

Q76. How to calculate core ring width, macro ring width and strap or trunk
width?

Q77. How to calculate core ring and stripe widths?

Q78. How the width of metal and number of straps calculated for power and
ground?

Q79. How slow and fast transition at inputs effect timing for gates?

Q80. How R and C values are affecting time?

Q81. How ohm (R), farad (C) is related to second (T)?

Q82. How much aspect ratio should be kept (or have you kept) and what is the
utilization?

Q83. How many macros in your previous design?

Q84. How double spacing will avoid cross talk?

Q85. How do you place macros in a full chip design?

Q86. How did you do power planning?

Q87. How do you resolve the setup and hold time violation problem?

Q88. How did you handle the Clock in your design?

Q89. How delays vary with different PVT conditions? Show the graph.

Q90. How can you estimate area of block?

Q91. During power analysis, if you are facing IR drop problem, then how did
you avoid?

Q92. Differentiate between a Hierarchical Design and flat design?

Q93. Define antenna problem and how did you resolve these problem?

Q94. After adding stripes also if you have hot spot, what do you do?

Q95. What is meant by scaling in VLSI design? Describe various effects of

scaling.

Q96. What is meant by 90nm technology?

Q97. What is a transmission gate, and what is its typical use in VLSI?

Q98. What are the differences between gate array ASIC and cell based ASIC?

Q99. When you want the production in bulk amount which design style you
prefer? Justify?

Q100. Power Optimization Techniques for deep sub micron?

1.what all inputs to the design ?

Ans.
Logical library SDC Gate level Netlist Physical library
Technology file Tlu+ files

2.What is in logical libraries timing & functional information.

3. How are values coming into logical libraries?

4. What are SDC, how do u decide that a path is a false path?

5. What is max transition? how you decide that value?

Wherever the slew is worst. Based on top level guys experience i.e 20% for
data and 10% for clock.

6. How do u set max output load (based on what factors?)

The max_capacitance value can vary with the operating frequency of a cell.
(Because the capacitive load vary as per relationship of Xc=1/ωC .)

7. What are the inputs to PrimeTime?

Gate-level netlist Constraints Exceptions

Technology libraries
Setup file Timing models SDF

8. How did u do power planning?

9. How did u decide metal 5 straps?

Based on IR drop.

10. Are there in vias between metal 5 and metal 1?

11. Given two configuration of Vdd and Vss;

1. VDD VDD VSS VSS
2. VDD VSS VDD VSS..........
which configuration you have used and what does the tool prefer?

Vdd vss because alternative (VDD VSS) will offer better routing resources.

12. Why you require uncertainity before cts with ideal clock?

At pre CTS stage uncertainty is combination of skew, jitter and margin. To get
the better timing at pre CTS.

13. I said -for presenting worst case for setup analysis : then he said
he can increase the operating frequency, then Why uncertainity
is required?

14. What are NDR rules, clock shielding, which metal layer?
Shielding
Double space
double width
top metal layers after power distribution layers.
Because after power clock is the main power hungry.

15. What does u do for low power design?

We apply low power techniques.
Clock gating
Multiple Vt libraries
Multi voltage design
Power gating.

16. What are retention registers?

Retention flops are used in power gating. To retain the position of the off block
when it is turned in.

17. what are HVT cells, how area increases with HVT cells?
For HVT cells the oxide thickness under gate is very high. Such that it can
reduces the leakage current. (as oxide thickness increases little area
increases).

18. What does CTS do for routing clocks? Global routing..?

19. How global routing is different from detailed routing?

Global routing is first stage of routing which checks for routing congestion of
the device.
In track assignment real metal traces are connected to std cells.

20. How GR will handle congested paths, what is its impact on delay?

21. What is single case, worst case and best case and OCV analysis?

22. How can one library have many values for same input slew and
output load?

23. What is CRPR? Explain?

24. Logic Design - Difference between flip flops n latch?

25. Convert D flipflop into T flip flop.

26. Get inverter using XOR.

Tie one of the input to vdd(logic one).

Now it will work as a inverter.

27. Will you give constraints for via in CTS or not. How vias will effect
the clock routing?

1) Latch Up

Q. What is latch up in CMOS design and ways to prevent it?

Latch-up is a condition in which the parasitic components give rise to the Establishment of
low resistance conducting path between VDD and VSS . Latch-up may be induced by glitches
on the supply rails or by incident radiation.
A byproduct of the Bulk CMOS structure is a pair of parasitic bipolar transistors. The collector
of each BJT is connected to the base of the other transistor in a positive feedback structure. A
phenomenon called latchup can occur when
(1) both BJT's conduct, creating a low resistance path between Vdd and GND and
(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is
greater than one.
The result of latchup is at the minimum a circuit malfunction, and in the worst case, the
destruction of the device due to electrical overstress (EOS).

Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2).

If sufficient current flows through Rsub to turn on Q2 (I Rsub > 0.7 V ), this will draw current
through Rwell. If the voltage drop across Rwell is high enough, Q1 will also turn on, and a self-
sustaining low resistance path between the power rails is formed. If the gains are such that b1
 x b2 > 1, latchup may occur. Once latchup has begun, the only way to stop it is to reduce the
current below a critical level, usually by removing power from the circuit.
The most likely place for latchup to occur is in pad drivers, where large voltage transients and
large currents are present.

Prevention for latch Up

Latch Up effects can be minimized either by reducing well and substrate resistances or reduce
the gain product b1 x b2.
So, former method reduce the well and substrate resistances, producing lower voltage drops.
a) higher substrate doping level reduces Rsub.
b) reduce Rwell by making low resistance contact to GND.
c) guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic
resistances.
Later method reduce the gain product b1 x b2.
a) move n-well and n+ source/drain farther apart increases width of the base of Q2 and
reduces gain b2 > also reduces circuit density.
b) buried n+ layer in well reduces gain of Q1.

Sanity Checks

• Library Checks

1. All Cells have timing data.(.libs for all cells)

2. All cells have physical data(.lef for all cells)
• Netlist Checks

1. Floating nets/Pins.
2. Multi driven nets
3. Combinational loops.
• SDC Checks

1. Clocks reaching all clock pins of flops.

2. Ports missing input/output delays.
3. Ports missing slew/load constraints.
4. Multiple clocks driving same register.
• Netlist vs SDC Checks

1. Pre layout timing.

 Inputs to Physical Design :
• Library models
• Technology Data
• Design Netlist
• Timing constraints
• Power Network (Pushdown from top level/ Build from bottom-up).

Input and Output of Automatic Place and Route

Design Setup

The first stage in physical design flow is reading in the netlist and the design constraints to your
tool of choice. Let us see what kinds of files we are dealing with here. I have used Synopsys IC
Compiler extensively, so those are what I will base my examples on. However, every tool uses
pretty much the same flow and even the same format files.

1. Gate Level Netlist

Once you choose a process and a library, a synthesis tool will translate your RTL into a
collection of interconnected logic gates that define the logic. The most common format is
verilog.
2. Standard Cell Library
In digital design, you have a ready made standard cell library which will be used for
synthesis and subsequent layouts. Your netlist will have instantiation of these cells. For
digital layout, you need layout and timing abstracts for these cells.
• Layout Model – An abstract model of the standard cell layout is used instead of the
complete layout. This will have PINs defined, so as to facilitate automatic routing by the
tool as per your netlist. Synopsys tool ICCompiler use “FRAM” views as a PnR abstract.
FRAM view is a cell view that has only the PINs and metal and via blockages defined. This
makes sure that the interconnection between the PINs can be routed automatically and
that the routing tool will not route over existing metal/via areas thus ruling out any shorts.
• Timing Model – Tools also need a timing model in the form of a .lib file. ICC takes a .db
file, which is generated from a .lib. This liberty format file will have timing numbers for the
 various arcs in a cell, generally in a look up model. Please note that .libs may also have
cell power information.
3. Technology File
The rules pertaining to the process you have selected should also be given to the PnR tool.
This includes metal widths, spacing, via definitions etc. ICC takes a milkyway techfile
format, while EDI tools take a technology LEF file.
4. Timing Constraints
SDC files define the timing constraints of your design. You will have the clock definitions,
false paths, any input and output delay constraints etc.
Apart from these some general setup are done at this stage includes search path setting timing and
optimization setup , scenario files etc.

Design Constraints used:

1. Create clock period
2. Create generated clock
3. set asynchronous clocks
4. set logical exclusive
5. set clock uncertainty
6. set input delay
7. set output delay
8. set max transition
9. set load
10. set driving cell
11. set false path
12. set multi-cycle path
13 Scenarios (Func_max, Func_min, CTS mode)
Three types of group paths are created during data set up are REGIN, REGOUT, FEEDTHROUGH.
Generally during timing optimization critical paths are given priority and sub critical paths are
neglected. The group paths helps to optimize all kind of paths independently by considering one
group at a time.