Written Test :

1. If A.B = 0, prove that A xor B = A or B

2. CMOS inverter with P and N devices interchanged. Draw the o/p waveform for
square wave i/p with Vtn =Vtp = 1 V. Vdd = 5V.
3. Given a logic function. Realize with static CMOS. Do sizing for equal worst case
rise and fall time. Given un = 2up.
4. FIFO : sender => 200Megasamples/sec. Receiver => 10 Megasamples/sec. Sender
sends a burst of 10usec in every 1 sec. Find the depth of FIFO.
5. A simple ques on karnaugh map simplification.
6. A question on optical sensors: A and B are placed at 90degrees around the optical
disk that is painted black on 40% of its area. Design a logic to detect the direction
of rotation. (Ans: Give A to clk & B to input or vice versa of D FF)
7. A question on 3 flip- flops cascaded..2 & 3 f/f have closk skew..draw output
waveforms..hold time =0 .One case was when Tcq was less than clock skew
& when it is greater
8. Simple booelan function to be implemented using ex-or , nand , nor gates.
9. Given sheet resistance of metal, and some metal later layout( dimensions were
given ), metal contact……find the power dissipation

Interview :
1. Draw CMOS inverter and explain the transfer char qualitatively with different region
of operations.
2. Realize shift registers in VHDL using signals / variables.
3. Pipelining hazards and possible solutions.
4. Cache design.
5. Prove qualitatively that product of 3 conseq integers is divisible by 6.
6. Sum of digits of a no is div by 3 then prove that no will also be.
7. 5 teams participating in league tournament. How many matches total ?
8. Assume a processor has „S‟ stages of pipeline, and each instruction requires 1 clock
cycle for execution. If a code is written such that a fraction “b” of the total number of
instructions are branch instructions, then what is the average number of clock cyc les
required per instruction (CPI of the processor)?
9. Assume two tristate buffers with inputs A and B, and control C and D, which are
independent of each other. The outputs of both buffers are shorte, what is probability
of bus contention?

** Fundamentals about set up time, hold time, VHDL syntax for simple circuits, timing
analysis of given circuits, are asked.