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Pre-silicon validation is generally performed at a While it may be relatively easy to generate activity or
chip, multi-chip or system level. The objective of stimulate the different ports or interfaces of a chip, the
pre-silicon validation is to verify the correctness difficult part is to implement an automated results or
and sufficiency of the design before sending the data checking strategy. A system-level pre-silicon
design for fabrication. This approach typically validation environment should relieve test writers
requires modeling the complete system, where from maintaining or keeping track of the data in test
the model of the design under test may be RTL,
code to make the task easily manageable for a
and other components of the system may be
multi-ported system. Keeping track of the data
behavioral or bus functional models. By subjecting
becomes arduous when different agents in a system
the design under test (DUT) to real-world-like input
interact on the same address segments.
stimuli, pre-silicon validation aims to:
Whether the design team builds or buys the An Architecture for Pre-silicon Validation
verification IP, they must ensure that the models can
fit into the test generation and checking strategy that We present here a case study of a pre-silicon validation
is adopted. Also, the models need to operate in a mode
environment set up to verify several versions of a
that fits into a pseudo-random test methodology.
Models that load and execute a pre-compiled test bridge device connecting CPU with memory and I/O
sequence do not work in an environment where one interfaces.
can dynamically generate and check tests.
Simulation Enviornment
CPU
Model
Communication Layer
Test
Controller CPU I/F
& Coverage
Test Templates
Data Checker Memory Metrics
Custom Mem
Logic I/F Model
PCI AGP
Model Model
Verification components * Automated Test Generation: The intelligent test
controller and data checker can handle user specified
The major components of this pre-silicon
directed tests with automated data checking and/or
validation environment are:
automatically generate pseudo-random sequences of
* Bus Functional Models: The intelligent transactions with automated data checking. Being a
BFMs provide a transaction-level API, and are dynamic test generator it can handle reactive test
designed to handle concurrency and parallelism. generation as well.
This makes it suitable to be used in an automated * Robust, High-quality Verification IP: The intelligent
test generation environment. It provides a models and monitors provide appropriate level of
consistent programmer’s view. It also offers a abstraction and controllability for effective system
high degree of controllability for the model level pre-silicon validation.
behavior to emulate a real device with real * Ease of Use: It is easy to use and intuitive without
operating characteristics through programmable
requiring the learning of a new language or
delay registers and configuration registers.
* Bus Protocol Monitors: The intelligent bus methodology.
protocol monitors provide dynamic protocol * Leveraging Design and Application Knowledge: It
checking and can be used in automated test leverages application-specific knowledge so that only
generation environments. They provide dynamic the pertinent application space is tested.
bus state information, which can be used to provide * Configurable and Extensible: It is easily
dynamic feedback to user tests or automated test configurable and extensible allowing pre-silicon
controllers. They are extensible to accommodate validation of multiple different configurations.
user-defined sequences. * Reusing the Test Environment: This architecture
* Test Controller and Data Checker: The
allows easy test and environment reuse. Replacing the
intelligent test controller utilizes BFMs and
appropriate models and monitors easily validated
transaction generators to create constraint-based
concurrent sequences of transactions at the subsequent generations of the DUT.
different interfaces of the DUT. The controller can
generate transactions pseudo-randomly, for a user Conclusion
specified sequence, or a mix of both. It can also
perform specific tasks or dynamically reload input Pre-silicon validation requires a well thought out and
constraints upon a certain event occurring during proven strategy and helps achieve shippable first-pass
simulation. In addition to test stimuli generation, silicon. The key features to consider about a
the controller provides for automated and dynamic system-level pre-silicon validation environment
data checking.
are concurrency, automated test generation and results
checking and, intelligent models and monitors
Salient Features
comprising proven, high-quality verification IP. An
Some of the major features and characteristics of this example application outlined the pre-silicon validation
environment are as follows: of a bridge device noting the use of BFMs, monitors
and an intelligent test controller and data checker.
* Concurrency: It handles multiple concurrent,
asynchronous and independent generation of
transaction sequences at the different interfaces of the
DUT.
* Results Checking: It has a built-in shadow memory
system to handle automatic results checking. The test
writer does not need to write code to do data checking.
It is done automatically and transparently.