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Coordinated control design of the voltage and current loop of a

Current Flow Controller for meshed HVDC grids

J. Sau-Bassols*, R. Ferrer-San-José*, E. Prieto-Araujo*, O. Gomis-Bellmunt* †

* CITCEA-UPC Av. Diagonal, 647, Planta 2, 08028 Barcelona, Spain (joan.sau@citcea.upc.edu)

IREC Jardins de les Dones de Negre 1, pl. 2 08930 Sant Adrià de Besòs, Spain

circulating through the cables. Among the CFCs, the devices

Keywords: VSC-HVDC, HVDC grids, Current Flow based on DC/DC converters connected between lines without
Controllers, Power Flow Control AC connections offer several advantages, for instance, they
do not require an isolation transformer [6]. These devices are
Abstract based on one or several passive elements (such as inductances
and capacitors) that are used to exchange energy between
This paper is focused in the control design of a DC/DC lines. [6] uses a single capacitor and an inductance and two
Current Flow Controller (CFC) for meshed HVDC grids. It capacitors are considered in [7]. The control design of the
proposes a control design methodology based on an outer current loop of the CFC is addressed in [8]. Two cascaded
current loop to regulate DC grid currents and an inner voltage controllers, one for controlling DC current and an inner one to
loop to keep under control the CFC voltage. This approach is regulate CFC voltage are presented in other works [9,10], but
able to limit the CFC voltage to avoid exceeding the device without detailing control design methodology.
limitations. A linear model of the HVDC grid including the
CFC is obtained to apply linear control techniques to design The present paper addresses the coordinated control design of
the regulator. The system performance is validated by means the inner loop (voltage loop) and the outer loop (current loop)
of simulations considering different case studies. of the CFC introduced in [6]. A 5-terminal DC grid and the
CFC are linearized to obtain a linear state space model of the
1 Introduction whole system. Considering the linearized model, the voltage
loop is able to be operated with or without outer loop. Then,
The number of commissioned offshore wind turbines is the outer loop is designed co-ordinately, considering the
increasing and the strong build-up of this emerging industry physical restrictions of the system. Both controllers are tested
has reached 10 GW of installed power in 2015 [1]. When in the detailed simulation model using Matlab Simulink and
these Offshore Wind Power Plants (OWPP) are located far compared with a single current loop. Different operations
from the coast, High Voltage Direct Current based on Voltage conditions are considered: reference step change, maximum
Source Converters (VSC) is an interesting option for energy CFC voltage and converter outage.
grid integration [2]. VSC-HVDC can be used as an alternative
to High Voltage Alternating Current (HVAC) due to its 2 System description
advantages when long distances and undersea cables are
considered [2]. The increasing number of built VSC-HVDC The layout of the meshed HVDC grid that is going to be used
corridors makes the idea of interconnecting them into a is depicted in Fig.1.
multiterminal DC grid (MTDC) or a meshed DC grid
attractive [3].

A meshed DC grid concept can bring several advantages such

as enhanced reliability of supply and operation flexibility [4].
Nevertheless, it poses challenges regarding its control and
operation [4]. One important challenge is the power flow
control within this kind of DC grids. In a meshed DC grid, the
power injected in each node is controlled by the VSC.
However, the power within the grid depends on node voltages
and cable resistances. A poor power flow management can
result in transmission cable overrating and transmission
bottlenecks [5]. Additional devices based on power
electronics can be introduced in the meshed DC grid to face
Fig. 1: 5-terminal meshed HVDC grid with a CFC.
the aforementioned challenges [5]. These Current Flow
Controllers (CFCs) or Power Flow Controllers (PFCs) tend to The meshed grid is a symmetrical monopole HVDC grid
be series-connected devices that insert a variable voltage based on VSC. It has 5 nodes interconnected with DC cables.
source into the DC lines, thus, changing the current Each node consists on a VSC in charge of absorbing or

supplying power to the DC grid. The CFC is located in node 2.1 Linearized model of the HVDC grid and CFC
1, interconnecting it with node 4 and 5. The CFC considered
for this study is the dual H-bridge presented in [6]. It is a For control design purposes the model of the HVDC grid,
series-connected device made of 6 IGBTs and their anti- including the CFC is linearized. The average model derived in
parallel diodes. The element that is exchanging energy [8] is used to develop the linearized model of the complete
between different cables is the capacitor. This capacitor is HVDC system. The average model of the CFC consists of
inserted in one line using its current to charge it and two voltage sources applied to the lines with the following
afterwards is placed in the other line where it is discharged. expressions:
Using this power exchange the CFC is able to apply variable ଵ ൌ ሺͳ െ ሻଶ ൌ െ ሺͳሻ
voltage sources into the lines, thus, modifying the current where, E is the average voltage of the CFC capacitor and D is
flow. The CFC layout is depicted in Fig. 2. the duty cycle of the switching IGBTs of the CFC.
The current of the nodes that inject constant power and the
ones that are operating with droop control, respectively, are
described as:
୧ ൌ  ୧ ൌ  ୧ ሺ୧‫ כ‬െ ୧ ሻ ሺʹሻ
The linearized equations describing the DC grid with the CFC
†οଵ ͳ
ൌ ሺെଵ οଵ ൅ ο ଶଵ ൅ ο ଷଵ ൅ ο ସଵ ൅ ο ହଵ ሻ (3)
†– ଵ
†οଶ ͳ οଶ ଶ଴ െ οଶ ଶ଴
ൌ ቆ ଶ െ ο ଶଷ െ ο ଶଵ ቇ (4)
†– ଶ ଶ଴
Fig. 2. Dual H-bridge CFC layout. †οଷ ͳ
ൌ ሺെ ଷ οଷ ൅ ο ଶଷ െ ο ଷଵ െ ο ଷସ ሻ (5)
†– ଷ
3 Meshed HVDC grid and CFC modelling †οସ ͳ οସ ସ଴ െ οସ ସ଴
ൌ ቆ ଶ ൅ ο ଷସ െ ο ସଵ െ ο ସହ ቇ (6)
For this study, the meshed HVDC grid is modelled only as the †– ସ ସ଴
half of the symmetrical monopole. As a result, only one CFC †οହ ͳ οହ ହ଴ െ οହ ହ଴
is needed to be placed in the positive monopole. The cables in ൌ ቆ ଶ ൅ ο ସହ െ ο ହଵ ቇ (7)
†– ହ ହ଴
the DC grid are modelled considering the PI equivalent. The †ο ଶଷ ͳ
resistance, inductance and capacitance are extracted from ൌ ሺοଶ െ οଷ െ  ଶଷ ο ଶଷ ሻ (8)
†– ଶଷ
CIGRÉ benchmark for DC grid studies [11]. VSCs are †ο ଶଵ ͳ
operating either injecting or absorbing constant power or as ൌ ሺοଶ െ οଵ െ  ଶଵ ο ଶଵ ሻ (9)
voltage regulators based on droop control [12]. Nodes 2, 4 †– ଶଵ
†ο ଷଵ ͳ
and 5 inject or absorb constant power and nodes 1 and 3 ൌ ሺοଷ െ οଵ െ  ଷଵ ο ଷଵ ሻ (10)
perform droop control. The CFC is modelled as a dual H- †– ଷଵ
bridge made of IGBTs with the corresponding anti-parallel †ο ଷସ ͳ
ൌ ሺοଷ െ οସ െ  ଷସ ο ଷସ ሻ (11)
diodes removing the two redundant switches [6]. It consists of †– ଷସ
a single capacitor as energy exchange element. The cable, †ο ସଵ ͳ
ൌ ሺοସ െ οଵ െ  ସଵ ο ସଵ ൅ ሺ଴ െ ͳሻο
VSC and CFC parameters can be seen in Table 1. †– ସଵ (12)
൅ ଴ οሻ
DC cable parameters †ο ସହ ͳ
ൌ ሺοସ െ οହ െ  ସହ ο ସହ ሻ (13)
Lines 23 21 31 34 41 45 51 †– ସହ
Distance †ο ହଵ ͳ
100 80 120 100 100 120 80 ൌ ሺοହ െ οଵ െ  ହଵ ο ହଵ ൅ ଴ ο ൅ ଴ οሻ (14)
[km] †– ହଵ
VSC parameters †ο ͳ
Nodes 1 2 3 4 5 ൌ ሺሺͳ െ ଴ ሻο ସଵ െ ଴ ο ହଵ െ ሺ ସଵ଴ ൅ ହଵ଴ ሻοሻ (15)
Capacitance [—F] 300 300 150 150 450
Power [MW] - 800 - -200 -1200 where, Ei, Ii, Pi are the DC voltage, current and power,
Ei* [kV] 200 - 200 - - respectively, of node i, ki is the droop constant for the VSC
Droop constant ki converter in node i, Ci is the VSC capacitance in node i, and it
0.05 - 0.05 - -
[A/V] includes also the half of cable capacitance. Iij is the current
CFC parameters from node i to j. Lij and Rij are the inductance and resistance
Nominal voltage [kV] 4 of the cable from node i to j. C is the capacitance of the CFC.
Switching frequency [kHz] 2 The variables with ¨ are the increments over the linearization
Capacitor [mF] 10 point, and the variables with a 0 subscript are the linearization
Table 1: DC cable, VSC and CFC parameters. points. Then, the linearized state-space of the DC grid
including the CFC is presented below:

† The tuning goal is obtaining a first order time response, IJ c, as
οš ൌ ‫ۯ‬οš ൅ ۰ο— ሺͳ͸ሻ
†– well, without overshoot. The relation between time constants
where, ¨x is the vector of linearized state variables, ¨u is the is given by:
vector of linearized inputs: ߬௖ ൌ ‫߬ܨ‬௩ ሺʹͳሻ
ο‫ ܠ‬ൌ ሺοଵ ǡ οଶ ǡ οଷ ǡ οସ ǡ οହ ǡ ο ଶଷ ǡ where F is a factor > 1.
ο ଶଵ ǡ ο ଷଵ ǡ ο ଷସ ǡ ο ସଵ ǡ ο ସହ ǡ ο ହଵ ǡ οሻ ሺͳ͹ሻ Before obtaining the final controllers design, there are several
ο‫ ܝ‬ൌ ሺοଶ ǡ οସ ǡ οହ ǡ οሻ ሺͳͺሻ considerations regarding system limitations that must be
And A is a 13x13 matrix and B is a 13x4 matrix. taken into account. First, the inner loop time response must be
slower than the switching frequency of the CFC (2 kHz) due
3 Control design methodology to the modulation effect. Secondly, the control action that the
CFC is able to apply (duty cycle D) ranges from 0 to 1.
An enhanced control design methodology is presented in this Therefore, although the linearized model can impose duty
section, compared to the one introduced in [8]. In [8] a cycles higher than 1, they are not feasible in the real system.
current loop is considered to regulate line currents, but the For this reason, the control action (D) must be limited
CFC voltage is not controlled. This issue can lead the voltage between 0 and 1 during transients. In steady-state the D will
of the capacitor to achieve values over its rating and the rating be always between 0 and 1 as they mean nulling one DC
of the switches both during transients and in steady state. current or the other. Moreover, when considering the two
Therefore, here, a coordinated control design of the CFC cascaded controllers, the designed first order time response of
voltage loop and the current loop is presented. The voltage the inner controller cannot be ensured, as it will be affected
controller is designed to be operated independently or as an by the output of the outer loop, the voltage reference (E*). In
inner controller. The control scheme is depicted in Fig. 3. order to tackle these issues, the following transfer functions
are obtained from the linearized model. Tv(s) is the closed
loop transfer function of the CFC voltage relating the
reference, E*, with the measured voltage, E. KSv(s) is the
transfer function relating the reference, E*, with the duty
cycle, D. Both expressions are shown below:

୴  ୴ ୴
୴ ሺ•ሻ ൌ ୴ ሺ•ሻ ൌ ሺʹʹሻ
ͳ ൅
୴  ୴ ͳ ൅
୴  ୴
Fig. 3. Proposed control scheme. The open loop transfer function that relates the duty cycle, D,
with the current reference, I*, is Gc(s). Then, the closed loop
The defined controlled current is I41. The first step consists on transfer function relating I* with the measured current, I, is
designing the inner loop, which is the voltage loop. Tc(s), which expression is:
Consequently, the transfer function Gv(s) relating the CFC  ୡ  ୴ ୡ
voltage E and the duty cycle D is obtained using the ୡ ሺ•ሻ ൌ  ୡ ୴
ୡ ൌ  ሺʹ͵ሻ
ͳ ൅
୴  ୴
linearized model of the system. The transfer function of the The input of the final control system is the current reference,
voltage controller (Kv(s)) is composed of a Proportional- I*, as the voltage controller is part of the inner loop. In order
Integral (PI) controller and a Second Order Compensator to perform a proper design, the transfer functions relating I*
(SOC) to damp the system oscillations in closed loop, as with the measured voltage of the CFC (Govershoot(s)) and the
presented in [8]. The transfer function of the voltage duty cycle (Gaction(s)) must be obtained.
controller has the following expression: Fig. 4 depicts the scheme to obtain these transfer functions.
 ୮୴ • ൅  ୧୴ ƒ ଶ • ଶ ൅ ƒଵ • ൅ ƒ଴
 ୴ ሺ•ሻ ൌ  ቆ ቇቆ ଶ ቇ ሺͳͻሻ
• „ଶ • ൅ „ଵ • ൅ „଴
Kv (s) is designed to be able to control the voltage
independently from the current loop and to achieve a closed
loop first order response of time constant IJv without
overshoot. Then, an outer controller is added in cascade to
regulate the line current I41, whose output or control action is
the reference voltage of the CFC, E*. This outer controller
must be slower than the inner voltage controller to avoid
interactions between them. A single PI controller for the outer
loop is considered for simplicity. It is designed considering
the addition of the previous inner controller into the system.
Equation (20) shows the Kc(s) controller of the current loop. Fig. 4. Block diagram of the transfer functions Govershoot(s) and
 ୮ୡ • ൅  ୧ୡ Gaction(s).
 ୡ ሺ•ሻ ൌ  ቆ ቇ ሺʹͲሻ
Govershoot(s) can be seen in (24) and Gaction(s) is presented in

 ୡ ୴  ୡ  ୴

୭୴ୣ୰ୱ୦୭୭୲ ሺ•ሻ ൌ  ൌ

ୡ  ୡ ୴ ͳ ൅  ୡ  ୴
ୡ ൅  ୴
୴ ሺʹͶሻ

 ୡ ୴
୴ିଵ ୡ ୴

ୟୡ୲୧୭୬ ሺ•ሻ ൌ ିଵ
ൌ  ሺʹͷሻ
ͳ ൅  ୡ ୴

ୡ ͳ ൅  ୡ  ୴
ୡ ൅  ୴

After deriving the previous transfer functions, the effect of

using different time constants IJv and IJc is analysed. The first
value chosen for IJc is 0.15 ms, the same as the current loop
designed in [8]. Then, 0.20 and 0.25 ms are also considered to
see the effect of increasing IJc. For each IJc, four different IJv are
considered with factors F of: 5,7,10 and 15. Fig. 5 and Fig. 6
depict the results of this analysis. Figs. 5a, 5c and 5e illustrate
the frequency response of the closed loop transfer function
Tc(s) and Fig. 5b, 5d and 5f depict the frequency response of
Gaction(s) for the IJv and IJc presented before. In dashed grey line
is shown the system response of the design considered in [8]
without voltage loop. The rest of the lines depict the
behaviour considering different time constants, IJ v, for the
voltage loop. It can be seen that the gain of Tc(s) at 0 Hz is 0
dB, which means that is capable of following DC references.
The bandwidth of Tc(s) is decreasing if IJc increases.
Regarding the frequency response of Gaction(s), increasing IJc,
reduces the gain at higher frequencies and the same happens
for IJv. The duty cycle cannot get values higher than in steady-
state in order to avoid values lower than 0 and higher than 1,
which is only possible in the average model, but not feasible Fig. 5. Frequency response of Tc(s) for different IJc and IJv.
in the detailed model with switches. For this reason, the
maximum allowed gain of Gaction(s) is the steady-state value,
which is always around -70 dB. This discard the values
considered in Fig. a and b. and sets a lower limit for IJv (0.029
s) considering IJc = 0.2 ms.
Fig. 6a, 6c and 6e show the frequency response of Govershoot(s)
and Fig. 6b, 6d and 6f depict the unitary time step response of
Govershoot(s). For this case, a maximum overshoot of 25% is
allowed. According to Fig. 6a, 6c and 6e, the gain of
Govershoot(s) at 0 Hz is 7.32 dB (2.323 V/A) for any time
constant. Then, the maximum gain is extended to all
frequencies to be more restrictive and can be calculated as:

୫ୟ୶ ൌ ʹͲ Ž‘‰ሺʹǤ͵ʹ͵ ൅ ʹǤ͵ʹ͵ ൉ ͲǤʹͷሻ ൌ ͻǤʹ͸† ሺʹ͸ሻ
The region above this limit is illustrated with a shaded area. It
can be seen that all the values considering IJc = 0.15 ms have a
large overshoot in the range of the design addressed in [8] for
any IJv. With IJc = 0.20 ms the overshoot is considerably
reduced and it is below the limit for values of IJ v lower than
0.029 s. This defines an upper limit for IJv. Any value of IJv
could be chosen with IJc = 0.25 s since the overshoot is much
lower, however, the time constant of the closed loop function
is higher, making current response slower.
Therefore, for this analysis the time constants are set to:
ɒୡ ൌ ͲǤʹ•ɒ୴ ൌ ͲǤͲʹͻ• ൌ ͹ ሺʹ͹ሻ
Besides, saturation after the current controller between 0 pu
and 1 pu is included in order to limit the voltage references,
E*, that are introduced into the voltage loop. A similar
saturation is added after the voltage controller to limit the
duty cycle value between 0 and 1.
Fig. 6. Frequency response and time step response of
Govershoot(s) for different IJc and IJv.

Finally, an Anti-Windup (AW) scheme is included in the
model to avoid windup effects when the voltage reference, E *,
is saturated. The final controllers’ parameters are shown in
Table 2.

Control parameters
kpc kic kpv kiv kaw
2.7807 11.0301 0.0127 0.1625 1.1030
a2 a1 a0 b2 b1 b0
0.0094 0.0420 1.7234 1 17.5232 60.1029
Table 2. Parameters of the voltage and current controllers

4 Case studies
Fig. 8. Comparison of different CFC control schemes.
In this section, three case studies are considered to validate
the proposed control design methodology. Simulations are Finally, the dotted grey line and the solid black line depict the
carried out using the detailed model of the grid and the CFC. controllers designed in Section 3 without and with AW,
respectively. The controller presented in [8] shows a faster
4.1 Comparison of the linearized and the detailed model time response when following current references. However,
the second step implies exceeding the CFC nominal voltage
The linearized and the detailed model are compared in this which could damage the CFC device. The CFC voltage gets a
section considering the controllers designed in Section 3. Fig. value higher than 1.2 pu as it can be seen in Fig. 8b in grey
7a shows how both systems are following the I41 references solid line. The addition of the voltage loop allows to saturate
with a first order time response. The difference between them the maximum voltage reference, E*, that is sent to the voltage
is negligible, still it is increasing the further the system goes controller. Thus, the current reference cannot be followed in
from the linearization point. Fig. 7b depicts the CFC voltage this case (Fig. 8a) but the voltage is kept at 1 pu (Fig. 8b). At
E required to change the current. It can be seen that both instant t = 6 s, a new current reference is received that implies
models have a reduced overshoot. It is important to notice reducing the CFC voltage. Without using the AW scheme, the
that when the system is far from the linearization point, the system has too much error in the integrator, leading to a
voltage overshoot is slightly reduced but the steady state slower response. The addition of the anti-windup allows
value differs from one model to the other. having a faster response as it can be seen in Fig. 8b with the
black solid line.

4.3 CFC performance during VSC outage

In this Section, the behaviour of the designed controllers for

the CFC is tested when there is an outage in a VSC terminal.
The detailed model is considered and the VSC 2 suffers the
terminal outage and it is disconnected from the HVDC grid.
Fig. 9 shows the variables of the system during the VSC
outage. Fig. 9a and 9c show the node powers and node
voltages, respectively. DC line currents are depicted in Fig.
Fig. 7. Comparison between the linearized and detailed 9b and 9e. The duty cycle and voltage of the CFC are
model. illustrated in Fig. 9d and 9f. At instant t = 1 s, in Fig. 9b, the
CFC increases the current through I41 and reduces current I51
4.2 Comparison of different CFC control schemes that is near the maximum rating (1 pu). Fig. 9d shows that the
duty cycle suffers a transient peak with the same gain than the
In this Section the control scheme with a single current loop steady-state value, as designed in Section 3. Fig. 9f depicts a
[8] and the voltage and current loop approach presented in small overshoot in the CFC voltage. At instant t = 3 s, VSC 2
this work are compared. In this case the detailed model is suffers an outage and it is disconnected from the DC grid.
used and the current reference sent to the CFC implies a CFC Power and voltage of node 2 go to 0 (Fig. 9a and 9c). The DC
voltage higher than the ratings (1 pu). Fig. 8a and Fig. 8b currents suffer some oscillations; however, the CFC is able to
show the current of line 41 and the CFC voltage, respectively, maintain I41 to the same level (Fig. 9b). Finally, the duty cycle
for the different control approaches. The reference for the and the CFC voltage experiment important oscillations but
current control is depicted in dashed grey line (I41 ref). The after 1 second approximately, they return to stable operation.
solid grey line shows the control approach considering only
one current loop [8].

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This work has been funded by the Spanish Ministry of

Economy and Competitiveness under Project ENE2013-
47296-C2-2-R and Project ENE2015-67048-C4-1-R. This
research was co-financed by the European Regional
Development Fund (ERDF).